1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
26 *
27 * Contributors:
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
32 *
33 */
34
35 #include <drm/display/drm_dp.h>
36
37 #include "i915_drv.h"
38 #include "i915_reg.h"
39 #include "gvt.h"
40
41 #include "display/bxt_dpio_phy_regs.h"
42 #include "display/i9xx_plane_regs.h"
43 #include "display/intel_crt_regs.h"
44 #include "display/intel_cursor_regs.h"
45 #include "display/intel_display.h"
46 #include "display/intel_dpio_phy.h"
47 #include "display/intel_sprite_regs.h"
48
get_edp_pipe(struct intel_vgpu * vgpu)49 static int get_edp_pipe(struct intel_vgpu *vgpu)
50 {
51 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
52 int pipe = -1;
53
54 switch (data & TRANS_DDI_EDP_INPUT_MASK) {
55 case TRANS_DDI_EDP_INPUT_A_ON:
56 case TRANS_DDI_EDP_INPUT_A_ONOFF:
57 pipe = PIPE_A;
58 break;
59 case TRANS_DDI_EDP_INPUT_B_ONOFF:
60 pipe = PIPE_B;
61 break;
62 case TRANS_DDI_EDP_INPUT_C_ONOFF:
63 pipe = PIPE_C;
64 break;
65 }
66 return pipe;
67 }
68
edp_pipe_is_enabled(struct intel_vgpu * vgpu)69 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
70 {
71 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
72 struct intel_display *display = &dev_priv->display;
73
74 if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE))
75 return 0;
76
77 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
78 return 0;
79 return 1;
80 }
81
pipe_is_enabled(struct intel_vgpu * vgpu,int pipe)82 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
83 {
84 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
85 struct intel_display *display = &dev_priv->display;
86
87 if (drm_WARN_ON(&dev_priv->drm,
88 pipe < PIPE_A || pipe >= I915_MAX_PIPES))
89 return -EINVAL;
90
91 if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE)
92 return 1;
93
94 if (edp_pipe_is_enabled(vgpu) &&
95 get_edp_pipe(vgpu) == pipe)
96 return 1;
97 return 0;
98 }
99
100 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
101 {
102 /* EDID with 1024x768 as its resolution */
103 /*Header*/
104 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
105 /* Vendor & Product Identification */
106 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
107 /* Version & Revision */
108 0x01, 0x04,
109 /* Basic Display Parameters & Features */
110 0xa5, 0x34, 0x20, 0x78, 0x23,
111 /* Color Characteristics */
112 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
113 /* Established Timings: maximum resolution is 1024x768 */
114 0x21, 0x08, 0x00,
115 /* Standard Timings. All invalid */
116 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
117 0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
118 /* 18 Byte Data Blocks 1: invalid */
119 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
120 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
121 /* 18 Byte Data Blocks 2: invalid */
122 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
123 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
124 /* 18 Byte Data Blocks 3: invalid */
125 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
126 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
127 /* 18 Byte Data Blocks 4: invalid */
128 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
129 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
130 /* Extension Block Count */
131 0x00,
132 /* Checksum */
133 0xef,
134 },
135 {
136 /* EDID with 1920x1200 as its resolution */
137 /*Header*/
138 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
139 /* Vendor & Product Identification */
140 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
141 /* Version & Revision */
142 0x01, 0x04,
143 /* Basic Display Parameters & Features */
144 0xa5, 0x34, 0x20, 0x78, 0x23,
145 /* Color Characteristics */
146 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
147 /* Established Timings: maximum resolution is 1024x768 */
148 0x21, 0x08, 0x00,
149 /*
150 * Standard Timings.
151 * below new resolutions can be supported:
152 * 1920x1080, 1280x720, 1280x960, 1280x1024,
153 * 1440x900, 1600x1200, 1680x1050
154 */
155 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
156 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
157 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
158 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
159 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
160 /* 18 Byte Data Blocks 2: invalid */
161 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
162 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
163 /* 18 Byte Data Blocks 3: invalid */
164 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
165 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
166 /* 18 Byte Data Blocks 4: invalid */
167 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
168 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
169 /* Extension Block Count */
170 0x00,
171 /* Checksum */
172 0x45,
173 },
174 };
175
176 #define DPCD_HEADER_SIZE 0xb
177
178 /* let the virtual display supports DP1.2 */
179 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
180 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
181 };
182
emulate_monitor_status_change(struct intel_vgpu * vgpu)183 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
184 {
185 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
186 struct intel_display *display = &dev_priv->display;
187 int pipe;
188
189 if (IS_BROXTON(dev_priv)) {
190 enum transcoder trans;
191 enum port port;
192
193 /* Clear PIPE, DDI, PHY, HPD before setting new */
194 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
195 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
196 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
197 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
198
199 for_each_pipe(display, pipe) {
200 vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &=
201 ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE);
202 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;
203 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
204 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;
205 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;
206 }
207
208 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) {
209 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &=
210 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
211 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE);
212 }
213 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
214 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
215 TRANS_DDI_PORT_MASK);
216
217 for (port = PORT_A; port <= PORT_C; port++) {
218 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=
219 ~BXT_PHY_LANE_ENABLED;
220 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=
221 (BXT_PHY_CMNLANE_POWERDOWN_ACK |
222 BXT_PHY_LANE_POWERDOWN_ACK);
223
224 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
225 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
226 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
227 PORT_PLL_ENABLE);
228
229 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
230 ~(DDI_INIT_DISPLAY_DETECTED |
231 DDI_BUF_CTL_ENABLE);
232 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
233 }
234 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
235 ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);
236 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
237 ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK);
238 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
239 ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK);
240 /* No hpd_invert set in vgpu vbt, need to clear invert mask */
241 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
242 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
243
244 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
245 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
246 ~PHY_POWER_GOOD;
247 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
248 ~PHY_POWER_GOOD;
249 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
250 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
251
252 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;
253 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;
254
255 /*
256 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
257 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
258 * TRANSCODER_A can be enabled. PORT_x depends on the input of
259 * setup_virtual_dp_monitor.
260 */
261 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;
262 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;
263
264 /*
265 * Golden M/N are calculated based on:
266 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
267 * DP link clk 1620 MHz and non-constant_n.
268 * TODO: calculate DP link symbol clk and stream clk m/n.
269 */
270 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);
271 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;
272 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;
273 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;
274 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;
275
276 /* Enable per-DDI/PORT vreg */
277 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
278 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
279 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
280 PHY_POWER_GOOD;
281 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=
282 BIT(30);
283 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
284 BXT_PHY_LANE_ENABLED;
285 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
286 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
287 BXT_PHY_LANE_POWERDOWN_ACK);
288 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
289 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
290 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
291 PORT_PLL_ENABLE);
292 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
293 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED);
294 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
295 ~DDI_BUF_IS_IDLE;
296 vgpu_vreg_t(vgpu,
297 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)) |=
298 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
299 TRANS_DDI_FUNC_ENABLE);
300 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
301 PORTA_HOTPLUG_ENABLE;
302 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
303 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
304 }
305
306 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
307 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
308 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
309 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
310 PHY_POWER_GOOD;
311 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
312 BIT(30);
313 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
314 BXT_PHY_LANE_ENABLED;
315 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
316 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
317 BXT_PHY_LANE_POWERDOWN_ACK);
318 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
319 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
320 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
321 PORT_PLL_ENABLE);
322 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
323 DDI_BUF_CTL_ENABLE;
324 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
325 ~DDI_BUF_IS_IDLE;
326 vgpu_vreg_t(vgpu,
327 TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
328 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
329 (PORT_B << TRANS_DDI_PORT_SHIFT) |
330 TRANS_DDI_FUNC_ENABLE);
331 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
332 PORTB_HOTPLUG_ENABLE;
333 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
334 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
335 }
336
337 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
338 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
339 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
340 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
341 PHY_POWER_GOOD;
342 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
343 BIT(30);
344 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
345 BXT_PHY_LANE_ENABLED;
346 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
347 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
348 BXT_PHY_LANE_POWERDOWN_ACK);
349 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
350 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
351 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
352 PORT_PLL_ENABLE);
353 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
354 DDI_BUF_CTL_ENABLE;
355 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
356 ~DDI_BUF_IS_IDLE;
357 vgpu_vreg_t(vgpu,
358 TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
359 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
360 (PORT_B << TRANS_DDI_PORT_SHIFT) |
361 TRANS_DDI_FUNC_ENABLE);
362 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
363 PORTC_HOTPLUG_ENABLE;
364 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
365 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
366 }
367
368 return;
369 }
370
371 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
372 SDE_PORTC_HOTPLUG_CPT |
373 SDE_PORTD_HOTPLUG_CPT);
374
375 if (IS_SKYLAKE(dev_priv) ||
376 IS_KABYLAKE(dev_priv) ||
377 IS_COFFEELAKE(dev_priv) ||
378 IS_COMETLAKE(dev_priv)) {
379 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
380 SDE_PORTE_HOTPLUG_SPT);
381 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
382 SKL_FUSE_DOWNLOAD_STATUS |
383 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
384 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
385 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
386 /*
387 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
388 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
389 * TRANSCODER_A can be enabled. PORT_x depends on the input of
390 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
391 * so we fixed to DPLL0 here.
392 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
393 */
394 vgpu_vreg_t(vgpu, DPLL_CTRL1) =
395 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);
396 vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
397 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);
398 vgpu_vreg_t(vgpu, LCPLL1_CTL) =
399 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK;
400 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
401 /*
402 * Golden M/N are calculated based on:
403 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
404 * DP link clk 1620 MHz and non-constant_n.
405 * TODO: calculate DP link symbol clk and stream clk m/n.
406 */
407 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);
408 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;
409 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;
410 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;
411 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;
412 }
413
414 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
415 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
416 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);
417 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
418 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);
419 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
420 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
421 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
422 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
423 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
424 TRANS_DDI_PORT_MASK);
425 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
426 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
427 (PORT_B << TRANS_DDI_PORT_SHIFT) |
428 TRANS_DDI_FUNC_ENABLE);
429 if (IS_BROADWELL(dev_priv)) {
430 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
431 ~PORT_CLK_SEL_MASK;
432 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
433 PORT_CLK_SEL_LCPLL_810;
434 }
435 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
436 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
437 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
438 }
439
440 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
441 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
442 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
443 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
444 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
445 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
446 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
447 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
448 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
449 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
450 TRANS_DDI_PORT_MASK);
451 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
452 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
453 (PORT_C << TRANS_DDI_PORT_SHIFT) |
454 TRANS_DDI_FUNC_ENABLE);
455 if (IS_BROADWELL(dev_priv)) {
456 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
457 ~PORT_CLK_SEL_MASK;
458 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
459 PORT_CLK_SEL_LCPLL_810;
460 }
461 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
462 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
463 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
464 }
465
466 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
467 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
468 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
469 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
470 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
471 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
472 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
473 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
474 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
475 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
476 TRANS_DDI_PORT_MASK);
477 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
478 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
479 (PORT_D << TRANS_DDI_PORT_SHIFT) |
480 TRANS_DDI_FUNC_ENABLE);
481 if (IS_BROADWELL(dev_priv)) {
482 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
483 ~PORT_CLK_SEL_MASK;
484 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
485 PORT_CLK_SEL_LCPLL_810;
486 }
487 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
488 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
489 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
490 }
491
492 if ((IS_SKYLAKE(dev_priv) ||
493 IS_KABYLAKE(dev_priv) ||
494 IS_COFFEELAKE(dev_priv) ||
495 IS_COMETLAKE(dev_priv)) &&
496 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
497 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
498 }
499
500 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
501 if (IS_BROADWELL(dev_priv))
502 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
503 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
504 else
505 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
506
507 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
508 }
509
510 /* Clear host CRT status, so guest couldn't detect this host CRT. */
511 if (IS_BROADWELL(dev_priv))
512 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
513
514 /* Disable Primary/Sprite/Cursor plane */
515 for_each_pipe(display, pipe) {
516 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;
517 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
518 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;
519 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;
520 }
521
522 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;
523 }
524
clean_virtual_dp_monitor(struct intel_vgpu * vgpu,int port_num)525 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
526 {
527 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
528
529 kfree(port->edid);
530 port->edid = NULL;
531
532 kfree(port->dpcd);
533 port->dpcd = NULL;
534 }
535
vblank_timer_fn(struct hrtimer * data)536 static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data)
537 {
538 struct intel_vgpu_vblank_timer *vblank_timer;
539 struct intel_vgpu *vgpu;
540
541 vblank_timer = container_of(data, struct intel_vgpu_vblank_timer, timer);
542 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer);
543
544 /* Set vblank emulation request per-vGPU bit */
545 intel_gvt_request_service(vgpu->gvt,
546 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id);
547 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period);
548 return HRTIMER_RESTART;
549 }
550
setup_virtual_dp_monitor(struct intel_vgpu * vgpu,int port_num,int type,unsigned int resolution)551 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
552 int type, unsigned int resolution)
553 {
554 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
555 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
556 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer;
557
558 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))
559 return -EINVAL;
560
561 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
562 if (!port->edid)
563 return -ENOMEM;
564
565 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
566 if (!port->dpcd) {
567 kfree(port->edid);
568 return -ENOMEM;
569 }
570
571 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
572 EDID_SIZE);
573 port->edid->data_valid = true;
574
575 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
576 port->dpcd->data_valid = true;
577 port->dpcd->data[DP_SINK_COUNT] = 0x1;
578 port->type = type;
579 port->id = resolution;
580 port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC;
581 vgpu->display.port_num = port_num;
582
583 /* Init hrtimer based on default refresh rate */
584 hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
585 vblank_timer->timer.function = vblank_timer_fn;
586 vblank_timer->vrefresh_k = port->vrefresh_k;
587 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k);
588
589 emulate_monitor_status_change(vgpu);
590
591 return 0;
592 }
593
594 /**
595 * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer
596 * @vgpu: vGPU operated
597 * @turnon: Turn ON/OFF vblank_timer
598 *
599 * This function is used to turn on/off or update the per-vGPU vblank_timer
600 * when TRANSCONF is enabled or disabled. vblank_timer period is also updated
601 * if guest changed the refresh rate.
602 *
603 */
vgpu_update_vblank_emulation(struct intel_vgpu * vgpu,bool turnon)604 void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon)
605 {
606 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer;
607 struct intel_vgpu_port *port =
608 intel_vgpu_port(vgpu, vgpu->display.port_num);
609
610 if (turnon) {
611 /*
612 * Skip the re-enable if already active and vrefresh unchanged.
613 * Otherwise, stop timer if already active and restart with new
614 * period.
615 */
616 if (vblank_timer->vrefresh_k != port->vrefresh_k ||
617 !hrtimer_active(&vblank_timer->timer)) {
618 /* Stop timer before start with new period if active */
619 if (hrtimer_active(&vblank_timer->timer))
620 hrtimer_cancel(&vblank_timer->timer);
621
622 /* Make sure new refresh rate updated to timer period */
623 vblank_timer->vrefresh_k = port->vrefresh_k;
624 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k);
625 hrtimer_start(&vblank_timer->timer,
626 ktime_add_ns(ktime_get(), vblank_timer->period),
627 HRTIMER_MODE_ABS);
628 }
629 } else {
630 /* Caller request to stop vblank */
631 hrtimer_cancel(&vblank_timer->timer);
632 }
633 }
634
emulate_vblank_on_pipe(struct intel_vgpu * vgpu,int pipe)635 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
636 {
637 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
638 struct intel_display *display = &dev_priv->display;
639 struct intel_vgpu_irq *irq = &vgpu->irq;
640 int vblank_event[] = {
641 [PIPE_A] = PIPE_A_VBLANK,
642 [PIPE_B] = PIPE_B_VBLANK,
643 [PIPE_C] = PIPE_C_VBLANK,
644 };
645 int event;
646
647 if (pipe < PIPE_A || pipe > PIPE_C)
648 return;
649
650 for_each_set_bit(event, irq->flip_done_event[pipe],
651 INTEL_GVT_EVENT_MAX) {
652 clear_bit(event, irq->flip_done_event[pipe]);
653 if (!pipe_is_enabled(vgpu, pipe))
654 continue;
655
656 intel_vgpu_trigger_virtual_event(vgpu, event);
657 }
658
659 if (pipe_is_enabled(vgpu, pipe)) {
660 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++;
661 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
662 }
663 }
664
intel_vgpu_emulate_vblank(struct intel_vgpu * vgpu)665 void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu)
666 {
667 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
668 struct intel_display *display = &i915->display;
669 int pipe;
670
671 mutex_lock(&vgpu->vgpu_lock);
672 for_each_pipe(display, pipe)
673 emulate_vblank_on_pipe(vgpu, pipe);
674 mutex_unlock(&vgpu->vgpu_lock);
675 }
676
677 /**
678 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
679 * @vgpu: a vGPU
680 * @connected: link state
681 *
682 * This function is used to trigger hotplug interrupt for vGPU
683 *
684 */
intel_vgpu_emulate_hotplug(struct intel_vgpu * vgpu,bool connected)685 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
686 {
687 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
688
689 /* TODO: add more platforms support */
690 if (IS_SKYLAKE(i915) ||
691 IS_KABYLAKE(i915) ||
692 IS_COFFEELAKE(i915) ||
693 IS_COMETLAKE(i915)) {
694 if (connected) {
695 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
696 SFUSE_STRAP_DDID_DETECTED;
697 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
698 } else {
699 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
700 ~SFUSE_STRAP_DDID_DETECTED;
701 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
702 }
703 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;
704 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
705 PORTD_HOTPLUG_STATUS_MASK;
706 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
707 } else if (IS_BROXTON(i915)) {
708 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
709 if (connected) {
710 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
711 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
712 } else {
713 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
714 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
715 }
716 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
717 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
718 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
719 ~PORTA_HOTPLUG_STATUS_MASK;
720 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
721 PORTA_HOTPLUG_LONG_DETECT;
722 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG);
723 }
724 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
725 if (connected) {
726 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
727 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
728 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
729 SFUSE_STRAP_DDIB_DETECTED;
730 } else {
731 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
732 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
733 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
734 ~SFUSE_STRAP_DDIB_DETECTED;
735 }
736 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
737 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
738 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
739 ~PORTB_HOTPLUG_STATUS_MASK;
740 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
741 PORTB_HOTPLUG_LONG_DETECT;
742 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);
743 }
744 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
745 if (connected) {
746 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
747 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
748 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
749 SFUSE_STRAP_DDIC_DETECTED;
750 } else {
751 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
752 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
753 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
754 ~SFUSE_STRAP_DDIC_DETECTED;
755 }
756 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
757 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
758 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
759 ~PORTC_HOTPLUG_STATUS_MASK;
760 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
761 PORTC_HOTPLUG_LONG_DETECT;
762 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG);
763 }
764 }
765 }
766
767 /**
768 * intel_vgpu_clean_display - clean vGPU virtual display emulation
769 * @vgpu: a vGPU
770 *
771 * This function is used to clean vGPU virtual display emulation stuffs
772 *
773 */
intel_vgpu_clean_display(struct intel_vgpu * vgpu)774 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
775 {
776 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
777
778 if (IS_SKYLAKE(dev_priv) ||
779 IS_KABYLAKE(dev_priv) ||
780 IS_COFFEELAKE(dev_priv) ||
781 IS_COMETLAKE(dev_priv))
782 clean_virtual_dp_monitor(vgpu, PORT_D);
783 else
784 clean_virtual_dp_monitor(vgpu, PORT_B);
785
786 vgpu_update_vblank_emulation(vgpu, false);
787 }
788
789 /**
790 * intel_vgpu_init_display- initialize vGPU virtual display emulation
791 * @vgpu: a vGPU
792 * @resolution: resolution index for intel_vgpu_edid
793 *
794 * This function is used to initialize vGPU virtual display emulation stuffs
795 *
796 * Returns:
797 * Zero on success, negative error code if failed.
798 *
799 */
intel_vgpu_init_display(struct intel_vgpu * vgpu,u64 resolution)800 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
801 {
802 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
803
804 intel_vgpu_init_i2c_edid(vgpu);
805
806 if (IS_SKYLAKE(dev_priv) ||
807 IS_KABYLAKE(dev_priv) ||
808 IS_COFFEELAKE(dev_priv) ||
809 IS_COMETLAKE(dev_priv))
810 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
811 resolution);
812 else
813 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
814 resolution);
815 }
816
817 /**
818 * intel_vgpu_reset_display- reset vGPU virtual display emulation
819 * @vgpu: a vGPU
820 *
821 * This function is used to reset vGPU virtual display emulation stuffs
822 *
823 */
intel_vgpu_reset_display(struct intel_vgpu * vgpu)824 void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
825 {
826 emulate_monitor_status_change(vgpu);
827 }
828