1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "resource.h"
29 #include "include/irq_service_interface.h"
30 #include "link_encoder.h"
31 #include "stream_encoder.h"
32 #include "opp.h"
33 #include "timing_generator.h"
34 #include "transform.h"
35 #include "dccg.h"
36 #include "dchubbub.h"
37 #include "dpp.h"
38 #include "core_types.h"
39 #include "set_mode_types.h"
40 #include "virtual/virtual_stream_encoder.h"
41 #include "dpcd_defs.h"
42 #include "link_enc_cfg.h"
43 #include "link.h"
44 #include "clk_mgr.h"
45 #include "dc_state_priv.h"
46 #include "dc_stream_priv.h"
47
48 #include "virtual/virtual_link_hwss.h"
49 #include "link/hwss/link_hwss_dio.h"
50 #include "link/hwss/link_hwss_dpia.h"
51 #include "link/hwss/link_hwss_hpo_dp.h"
52 #include "link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h"
53 #include "link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h"
54
55 #if defined(CONFIG_DRM_AMD_DC_SI)
56 #include "dce60/dce60_resource.h"
57 #endif
58 #include "dce80/dce80_resource.h"
59 #include "dce100/dce100_resource.h"
60 #include "dce110/dce110_resource.h"
61 #include "dce112/dce112_resource.h"
62 #include "dce120/dce120_resource.h"
63 #include "dcn10/dcn10_resource.h"
64 #include "dcn20/dcn20_resource.h"
65 #include "dcn21/dcn21_resource.h"
66 #include "dcn201/dcn201_resource.h"
67 #include "dcn30/dcn30_resource.h"
68 #include "dcn301/dcn301_resource.h"
69 #include "dcn302/dcn302_resource.h"
70 #include "dcn303/dcn303_resource.h"
71 #include "dcn31/dcn31_resource.h"
72 #include "dcn314/dcn314_resource.h"
73 #include "dcn315/dcn315_resource.h"
74 #include "dcn316/dcn316_resource.h"
75 #include "dcn32/dcn32_resource.h"
76 #include "dcn321/dcn321_resource.h"
77 #include "dcn35/dcn35_resource.h"
78 #include "dcn351/dcn351_resource.h"
79 #include "dcn401/dcn401_resource.h"
80 #if defined(CONFIG_DRM_AMD_DC_FP)
81 #include "dc_spl_translate.h"
82 #endif
83
84 #define VISUAL_CONFIRM_BASE_DEFAULT 3
85 #define VISUAL_CONFIRM_BASE_MIN 1
86 #define VISUAL_CONFIRM_BASE_MAX 10
87 /* we choose 240 because it is a common denominator of common v addressable
88 * such as 2160, 1440, 1200, 960. So we take 1/240 portion of v addressable as
89 * the visual confirm dpp offset height. So visual confirm height can stay
90 * relatively the same independent from timing used.
91 */
92 #define VISUAL_CONFIRM_DPP_OFFSET_DENO 240
93
94 #define DC_LOGGER \
95 dc->ctx->logger
96 #define DC_LOGGER_INIT(logger)
97
98 #include "dml2/dml2_wrapper.h"
99
100 #define UNABLE_TO_SPLIT -1
101
resource_parse_asic_id(struct hw_asic_id asic_id)102 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
103 {
104 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
105
106 switch (asic_id.chip_family) {
107
108 #if defined(CONFIG_DRM_AMD_DC_SI)
109 case FAMILY_SI:
110 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
111 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
112 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
113 dc_version = DCE_VERSION_6_0;
114 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
115 dc_version = DCE_VERSION_6_4;
116 else
117 dc_version = DCE_VERSION_6_1;
118 break;
119 #endif
120 case FAMILY_CI:
121 dc_version = DCE_VERSION_8_0;
122 break;
123 case FAMILY_KV:
124 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
125 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
126 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
127 dc_version = DCE_VERSION_8_3;
128 else
129 dc_version = DCE_VERSION_8_1;
130 break;
131 case FAMILY_CZ:
132 dc_version = DCE_VERSION_11_0;
133 break;
134
135 case FAMILY_VI:
136 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
137 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
138 dc_version = DCE_VERSION_10_0;
139 break;
140 }
141 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
142 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
143 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
144 dc_version = DCE_VERSION_11_2;
145 }
146 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
147 dc_version = DCE_VERSION_11_22;
148 break;
149 case FAMILY_AI:
150 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
151 dc_version = DCE_VERSION_12_1;
152 else
153 dc_version = DCE_VERSION_12_0;
154 break;
155 case FAMILY_RV:
156 dc_version = DCN_VERSION_1_0;
157 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
158 dc_version = DCN_VERSION_1_01;
159 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
160 dc_version = DCN_VERSION_2_1;
161 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
162 dc_version = DCN_VERSION_2_1;
163 break;
164
165 case FAMILY_NV:
166 dc_version = DCN_VERSION_2_0;
167 if (asic_id.chip_id == DEVICE_ID_NV_13FE || asic_id.chip_id == DEVICE_ID_NV_143F) {
168 dc_version = DCN_VERSION_2_01;
169 break;
170 }
171 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
172 dc_version = DCN_VERSION_3_0;
173 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))
174 dc_version = DCN_VERSION_3_02;
175 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev))
176 dc_version = DCN_VERSION_3_03;
177 break;
178
179 case FAMILY_VGH:
180 dc_version = DCN_VERSION_3_01;
181 break;
182
183 case FAMILY_YELLOW_CARP:
184 if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev))
185 dc_version = DCN_VERSION_3_1;
186 break;
187 case AMDGPU_FAMILY_GC_10_3_6:
188 if (ASICREV_IS_GC_10_3_6(asic_id.hw_internal_rev))
189 dc_version = DCN_VERSION_3_15;
190 break;
191 case AMDGPU_FAMILY_GC_10_3_7:
192 if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
193 dc_version = DCN_VERSION_3_16;
194 break;
195 case AMDGPU_FAMILY_GC_11_0_0:
196 dc_version = DCN_VERSION_3_2;
197 if (ASICREV_IS_GC_11_0_2(asic_id.hw_internal_rev))
198 dc_version = DCN_VERSION_3_21;
199 break;
200 case AMDGPU_FAMILY_GC_11_0_1:
201 dc_version = DCN_VERSION_3_14;
202 break;
203 case AMDGPU_FAMILY_GC_11_5_0:
204 dc_version = DCN_VERSION_3_5;
205 if (ASICREV_IS_GC_11_0_4(asic_id.hw_internal_rev))
206 dc_version = DCN_VERSION_3_51;
207 break;
208 case AMDGPU_FAMILY_GC_12_0_0:
209 if (ASICREV_IS_GC_12_0_1_A0(asic_id.hw_internal_rev) ||
210 ASICREV_IS_GC_12_0_0_A0(asic_id.hw_internal_rev))
211 dc_version = DCN_VERSION_4_01;
212 break;
213 default:
214 dc_version = DCE_VERSION_UNKNOWN;
215 break;
216 }
217 return dc_version;
218 }
219
dc_create_resource_pool(struct dc * dc,const struct dc_init_data * init_data,enum dce_version dc_version)220 struct resource_pool *dc_create_resource_pool(struct dc *dc,
221 const struct dc_init_data *init_data,
222 enum dce_version dc_version)
223 {
224 struct resource_pool *res_pool = NULL;
225
226 switch (dc_version) {
227 #if defined(CONFIG_DRM_AMD_DC_SI)
228 case DCE_VERSION_6_0:
229 res_pool = dce60_create_resource_pool(
230 init_data->num_virtual_links, dc);
231 break;
232 case DCE_VERSION_6_1:
233 res_pool = dce61_create_resource_pool(
234 init_data->num_virtual_links, dc);
235 break;
236 case DCE_VERSION_6_4:
237 res_pool = dce64_create_resource_pool(
238 init_data->num_virtual_links, dc);
239 break;
240 #endif
241 case DCE_VERSION_8_0:
242 res_pool = dce80_create_resource_pool(
243 init_data->num_virtual_links, dc);
244 break;
245 case DCE_VERSION_8_1:
246 res_pool = dce81_create_resource_pool(
247 init_data->num_virtual_links, dc);
248 break;
249 case DCE_VERSION_8_3:
250 res_pool = dce83_create_resource_pool(
251 init_data->num_virtual_links, dc);
252 break;
253 case DCE_VERSION_10_0:
254 res_pool = dce100_create_resource_pool(
255 init_data->num_virtual_links, dc);
256 break;
257 case DCE_VERSION_11_0:
258 res_pool = dce110_create_resource_pool(
259 init_data->num_virtual_links, dc,
260 init_data->asic_id);
261 break;
262 case DCE_VERSION_11_2:
263 case DCE_VERSION_11_22:
264 res_pool = dce112_create_resource_pool(
265 init_data->num_virtual_links, dc);
266 break;
267 case DCE_VERSION_12_0:
268 case DCE_VERSION_12_1:
269 res_pool = dce120_create_resource_pool(
270 init_data->num_virtual_links, dc);
271 break;
272
273 #if defined(CONFIG_DRM_AMD_DC_FP)
274 case DCN_VERSION_1_0:
275 case DCN_VERSION_1_01:
276 res_pool = dcn10_create_resource_pool(init_data, dc);
277 break;
278 case DCN_VERSION_2_0:
279 res_pool = dcn20_create_resource_pool(init_data, dc);
280 break;
281 case DCN_VERSION_2_1:
282 res_pool = dcn21_create_resource_pool(init_data, dc);
283 break;
284 case DCN_VERSION_2_01:
285 res_pool = dcn201_create_resource_pool(init_data, dc);
286 break;
287 case DCN_VERSION_3_0:
288 res_pool = dcn30_create_resource_pool(init_data, dc);
289 break;
290 case DCN_VERSION_3_01:
291 res_pool = dcn301_create_resource_pool(init_data, dc);
292 break;
293 case DCN_VERSION_3_02:
294 res_pool = dcn302_create_resource_pool(init_data, dc);
295 break;
296 case DCN_VERSION_3_03:
297 res_pool = dcn303_create_resource_pool(init_data, dc);
298 break;
299 case DCN_VERSION_3_1:
300 res_pool = dcn31_create_resource_pool(init_data, dc);
301 break;
302 case DCN_VERSION_3_14:
303 res_pool = dcn314_create_resource_pool(init_data, dc);
304 break;
305 case DCN_VERSION_3_15:
306 res_pool = dcn315_create_resource_pool(init_data, dc);
307 break;
308 case DCN_VERSION_3_16:
309 res_pool = dcn316_create_resource_pool(init_data, dc);
310 break;
311 case DCN_VERSION_3_2:
312 res_pool = dcn32_create_resource_pool(init_data, dc);
313 break;
314 case DCN_VERSION_3_21:
315 res_pool = dcn321_create_resource_pool(init_data, dc);
316 break;
317 case DCN_VERSION_3_5:
318 res_pool = dcn35_create_resource_pool(init_data, dc);
319 break;
320 case DCN_VERSION_3_51:
321 res_pool = dcn351_create_resource_pool(init_data, dc);
322 break;
323 case DCN_VERSION_4_01:
324 res_pool = dcn401_create_resource_pool(init_data, dc);
325 break;
326 #endif /* CONFIG_DRM_AMD_DC_FP */
327 default:
328 break;
329 }
330
331 if (res_pool != NULL) {
332 if (dc->ctx->dc_bios->fw_info_valid) {
333 res_pool->ref_clocks.xtalin_clock_inKhz =
334 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
335 /* initialize with firmware data first, no all
336 * ASIC have DCCG SW component. FPGA or
337 * simulation need initialization of
338 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
339 * with xtalin_clock_inKhz
340 */
341 res_pool->ref_clocks.dccg_ref_clock_inKhz =
342 res_pool->ref_clocks.xtalin_clock_inKhz;
343 res_pool->ref_clocks.dchub_ref_clock_inKhz =
344 res_pool->ref_clocks.xtalin_clock_inKhz;
345 } else
346 ASSERT_CRITICAL(false);
347 }
348
349 return res_pool;
350 }
351
dc_destroy_resource_pool(struct dc * dc)352 void dc_destroy_resource_pool(struct dc *dc)
353 {
354 if (dc) {
355 if (dc->res_pool)
356 dc->res_pool->funcs->destroy(&dc->res_pool);
357
358 kfree(dc->hwseq);
359 }
360 }
361
update_num_audio(const struct resource_straps * straps,unsigned int * num_audio,struct audio_support * aud_support)362 static void update_num_audio(
363 const struct resource_straps *straps,
364 unsigned int *num_audio,
365 struct audio_support *aud_support)
366 {
367 aud_support->dp_audio = true;
368 aud_support->hdmi_audio_native = false;
369 aud_support->hdmi_audio_on_dongle = false;
370
371 if (straps->hdmi_disable == 0) {
372 if (straps->dc_pinstraps_audio & 0x2) {
373 aud_support->hdmi_audio_on_dongle = true;
374 aud_support->hdmi_audio_native = true;
375 }
376 }
377
378 switch (straps->audio_stream_number) {
379 case 0: /* multi streams supported */
380 break;
381 case 1: /* multi streams not supported */
382 *num_audio = 1;
383 break;
384 default:
385 DC_ERR("DC: unexpected audio fuse!\n");
386 }
387 }
388
resource_construct(unsigned int num_virtual_links,struct dc * dc,struct resource_pool * pool,const struct resource_create_funcs * create_funcs)389 bool resource_construct(
390 unsigned int num_virtual_links,
391 struct dc *dc,
392 struct resource_pool *pool,
393 const struct resource_create_funcs *create_funcs)
394 {
395 struct dc_context *ctx = dc->ctx;
396 const struct resource_caps *caps = pool->res_cap;
397 int i;
398 unsigned int num_audio = caps->num_audio;
399 struct resource_straps straps = {0};
400
401 if (create_funcs->read_dce_straps)
402 create_funcs->read_dce_straps(dc->ctx, &straps);
403
404 pool->audio_count = 0;
405 if (create_funcs->create_audio) {
406 /* find the total number of streams available via the
407 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
408 * registers (one for each pin) starting from pin 1
409 * up to the max number of audio pins.
410 * We stop on the first pin where
411 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
412 */
413 update_num_audio(&straps, &num_audio, &pool->audio_support);
414 for (i = 0; i < caps->num_audio; i++) {
415 struct audio *aud = create_funcs->create_audio(ctx, i);
416
417 if (aud == NULL) {
418 DC_ERR("DC: failed to create audio!\n");
419 return false;
420 }
421 if (!aud->funcs->endpoint_valid(aud)) {
422 aud->funcs->destroy(&aud);
423 break;
424 }
425 pool->audios[i] = aud;
426 pool->audio_count++;
427 }
428 }
429
430 pool->stream_enc_count = 0;
431 if (create_funcs->create_stream_encoder) {
432 for (i = 0; i < caps->num_stream_encoder; i++) {
433 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
434 if (pool->stream_enc[i] == NULL)
435 DC_ERR("DC: failed to create stream_encoder!\n");
436 pool->stream_enc_count++;
437 }
438 }
439
440 pool->hpo_dp_stream_enc_count = 0;
441 if (create_funcs->create_hpo_dp_stream_encoder) {
442 for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) {
443 pool->hpo_dp_stream_enc[i] = create_funcs->create_hpo_dp_stream_encoder(i+ENGINE_ID_HPO_DP_0, ctx);
444 if (pool->hpo_dp_stream_enc[i] == NULL)
445 DC_ERR("DC: failed to create HPO DP stream encoder!\n");
446 pool->hpo_dp_stream_enc_count++;
447
448 }
449 }
450
451 pool->hpo_dp_link_enc_count = 0;
452 if (create_funcs->create_hpo_dp_link_encoder) {
453 for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) {
454 pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx);
455 if (pool->hpo_dp_link_enc[i] == NULL)
456 DC_ERR("DC: failed to create HPO DP link encoder!\n");
457 pool->hpo_dp_link_enc_count++;
458 }
459 }
460
461 for (i = 0; i < caps->num_mpc_3dlut; i++) {
462 pool->mpc_lut[i] = dc_create_3dlut_func();
463 if (pool->mpc_lut[i] == NULL)
464 DC_ERR("DC: failed to create MPC 3dlut!\n");
465 pool->mpc_shaper[i] = dc_create_transfer_func();
466 if (pool->mpc_shaper[i] == NULL)
467 DC_ERR("DC: failed to create MPC shaper!\n");
468 }
469
470 dc->caps.dynamic_audio = false;
471 if (pool->audio_count < pool->stream_enc_count) {
472 dc->caps.dynamic_audio = true;
473 }
474 for (i = 0; i < num_virtual_links; i++) {
475 pool->stream_enc[pool->stream_enc_count] =
476 virtual_stream_encoder_create(
477 ctx, ctx->dc_bios);
478 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
479 DC_ERR("DC: failed to create stream_encoder!\n");
480 return false;
481 }
482 pool->stream_enc_count++;
483 }
484
485 dc->hwseq = create_funcs->create_hwseq(ctx);
486
487 return true;
488 }
find_matching_clock_source(const struct resource_pool * pool,struct clock_source * clock_source)489 static int find_matching_clock_source(
490 const struct resource_pool *pool,
491 struct clock_source *clock_source)
492 {
493
494 int i;
495
496 for (i = 0; i < pool->clk_src_count; i++) {
497 if (pool->clock_sources[i] == clock_source)
498 return i;
499 }
500 return -1;
501 }
502
resource_unreference_clock_source(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)503 void resource_unreference_clock_source(
504 struct resource_context *res_ctx,
505 const struct resource_pool *pool,
506 struct clock_source *clock_source)
507 {
508 int i = find_matching_clock_source(pool, clock_source);
509
510 if (i > -1)
511 res_ctx->clock_source_ref_count[i]--;
512
513 if (pool->dp_clock_source == clock_source)
514 res_ctx->dp_clock_source_ref_count--;
515 }
516
resource_reference_clock_source(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)517 void resource_reference_clock_source(
518 struct resource_context *res_ctx,
519 const struct resource_pool *pool,
520 struct clock_source *clock_source)
521 {
522 int i = find_matching_clock_source(pool, clock_source);
523
524 if (i > -1)
525 res_ctx->clock_source_ref_count[i]++;
526
527 if (pool->dp_clock_source == clock_source)
528 res_ctx->dp_clock_source_ref_count++;
529 }
530
resource_get_clock_source_reference(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)531 int resource_get_clock_source_reference(
532 struct resource_context *res_ctx,
533 const struct resource_pool *pool,
534 struct clock_source *clock_source)
535 {
536 int i = find_matching_clock_source(pool, clock_source);
537
538 if (i > -1)
539 return res_ctx->clock_source_ref_count[i];
540
541 if (pool->dp_clock_source == clock_source)
542 return res_ctx->dp_clock_source_ref_count;
543
544 return -1;
545 }
546
resource_are_vblanks_synchronizable(struct dc_stream_state * stream1,struct dc_stream_state * stream2)547 bool resource_are_vblanks_synchronizable(
548 struct dc_stream_state *stream1,
549 struct dc_stream_state *stream2)
550 {
551 uint32_t base60_refresh_rates[] = {10, 20, 5};
552 uint8_t i;
553 uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates);
554 uint64_t frame_time_diff;
555
556 if (stream1->ctx->dc->config.vblank_alignment_dto_params &&
557 stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 &&
558 dc_is_dp_signal(stream1->signal) &&
559 dc_is_dp_signal(stream2->signal) &&
560 false == stream1->has_non_synchronizable_pclk &&
561 false == stream2->has_non_synchronizable_pclk &&
562 stream1->timing.flags.VBLANK_SYNCHRONIZABLE &&
563 stream2->timing.flags.VBLANK_SYNCHRONIZABLE) {
564 /* disable refresh rates higher than 60Hz for now */
565 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/
566 stream1->timing.v_total > 60)
567 return false;
568 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/
569 stream2->timing.v_total > 60)
570 return false;
571 frame_time_diff = (uint64_t)10000 *
572 stream1->timing.h_total *
573 stream1->timing.v_total *
574 stream2->timing.pix_clk_100hz;
575 frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz);
576 frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total);
577 frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total);
578 for (i = 0; i < rr_count; i++) {
579 int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000;
580
581 if (diff < 0)
582 diff = -diff;
583 if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff)
584 return true;
585 }
586 }
587 return false;
588 }
589
resource_are_streams_timing_synchronizable(struct dc_stream_state * stream1,struct dc_stream_state * stream2)590 bool resource_are_streams_timing_synchronizable(
591 struct dc_stream_state *stream1,
592 struct dc_stream_state *stream2)
593 {
594 if (stream1->timing.h_total != stream2->timing.h_total)
595 return false;
596
597 if (stream1->timing.v_total != stream2->timing.v_total)
598 return false;
599
600 if (stream1->timing.h_addressable
601 != stream2->timing.h_addressable)
602 return false;
603
604 if (stream1->timing.v_addressable
605 != stream2->timing.v_addressable)
606 return false;
607
608 if (stream1->timing.v_front_porch
609 != stream2->timing.v_front_porch)
610 return false;
611
612 if (stream1->timing.pix_clk_100hz
613 != stream2->timing.pix_clk_100hz)
614 return false;
615
616 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
617 return false;
618
619 if (stream1->phy_pix_clk != stream2->phy_pix_clk
620 && (!dc_is_dp_signal(stream1->signal)
621 || !dc_is_dp_signal(stream2->signal)))
622 return false;
623
624 if (stream1->view_format != stream2->view_format)
625 return false;
626
627 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
628 return false;
629
630 return true;
631 }
is_dp_and_hdmi_sharable(struct dc_stream_state * stream1,struct dc_stream_state * stream2)632 static bool is_dp_and_hdmi_sharable(
633 struct dc_stream_state *stream1,
634 struct dc_stream_state *stream2)
635 {
636 if (stream1->ctx->dc->caps.disable_dp_clk_share)
637 return false;
638
639 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
640 stream2->clamping.c_depth != COLOR_DEPTH_888)
641 return false;
642
643 return true;
644
645 }
646
is_sharable_clk_src(const struct pipe_ctx * pipe_with_clk_src,const struct pipe_ctx * pipe)647 static bool is_sharable_clk_src(
648 const struct pipe_ctx *pipe_with_clk_src,
649 const struct pipe_ctx *pipe)
650 {
651 if (pipe_with_clk_src->clock_source == NULL)
652 return false;
653
654 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
655 return false;
656
657 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
658 (dc_is_dp_signal(pipe->stream->signal) &&
659 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
660 pipe->stream)))
661 return false;
662
663 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
664 && dc_is_dual_link_signal(pipe->stream->signal))
665 return false;
666
667 if (dc_is_hdmi_signal(pipe->stream->signal)
668 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
669 return false;
670
671 if (!resource_are_streams_timing_synchronizable(
672 pipe_with_clk_src->stream, pipe->stream))
673 return false;
674
675 return true;
676 }
677
resource_find_used_clk_src_for_sharing(struct resource_context * res_ctx,struct pipe_ctx * pipe_ctx)678 struct clock_source *resource_find_used_clk_src_for_sharing(
679 struct resource_context *res_ctx,
680 struct pipe_ctx *pipe_ctx)
681 {
682 int i;
683
684 for (i = 0; i < MAX_PIPES; i++) {
685 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
686 return res_ctx->pipe_ctx[i].clock_source;
687 }
688
689 return NULL;
690 }
691
convert_pixel_format_to_dalsurface(enum surface_pixel_format surface_pixel_format)692 static enum pixel_format convert_pixel_format_to_dalsurface(
693 enum surface_pixel_format surface_pixel_format)
694 {
695 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
696
697 switch (surface_pixel_format) {
698 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
699 dal_pixel_format = PIXEL_FORMAT_INDEX8;
700 break;
701 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
702 dal_pixel_format = PIXEL_FORMAT_RGB565;
703 break;
704 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
705 dal_pixel_format = PIXEL_FORMAT_RGB565;
706 break;
707 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
708 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
709 break;
710 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
711 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
712 break;
713 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
714 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
715 break;
716 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
717 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
718 break;
719 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
720 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
721 break;
722 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
723 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
724 dal_pixel_format = PIXEL_FORMAT_FP16;
725 break;
726 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
727 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
728 dal_pixel_format = PIXEL_FORMAT_420BPP8;
729 break;
730 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
731 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
732 dal_pixel_format = PIXEL_FORMAT_420BPP10;
733 break;
734 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
735 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
736 default:
737 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
738 break;
739 }
740 return dal_pixel_format;
741 }
742
get_vp_scan_direction(enum dc_rotation_angle rotation,bool horizontal_mirror,bool * orthogonal_rotation,bool * flip_vert_scan_dir,bool * flip_horz_scan_dir)743 static inline void get_vp_scan_direction(
744 enum dc_rotation_angle rotation,
745 bool horizontal_mirror,
746 bool *orthogonal_rotation,
747 bool *flip_vert_scan_dir,
748 bool *flip_horz_scan_dir)
749 {
750 *orthogonal_rotation = false;
751 *flip_vert_scan_dir = false;
752 *flip_horz_scan_dir = false;
753 if (rotation == ROTATION_ANGLE_180) {
754 *flip_vert_scan_dir = true;
755 *flip_horz_scan_dir = true;
756 } else if (rotation == ROTATION_ANGLE_90) {
757 *orthogonal_rotation = true;
758 *flip_horz_scan_dir = true;
759 } else if (rotation == ROTATION_ANGLE_270) {
760 *orthogonal_rotation = true;
761 *flip_vert_scan_dir = true;
762 }
763
764 if (horizontal_mirror)
765 *flip_horz_scan_dir = !*flip_horz_scan_dir;
766 }
767
intersect_rec(const struct rect * r0,const struct rect * r1)768 static struct rect intersect_rec(const struct rect *r0, const struct rect *r1)
769 {
770 struct rect rec;
771 int r0_x_end = r0->x + r0->width;
772 int r1_x_end = r1->x + r1->width;
773 int r0_y_end = r0->y + r0->height;
774 int r1_y_end = r1->y + r1->height;
775
776 rec.x = r0->x > r1->x ? r0->x : r1->x;
777 rec.width = r0_x_end > r1_x_end ? r1_x_end - rec.x : r0_x_end - rec.x;
778 rec.y = r0->y > r1->y ? r0->y : r1->y;
779 rec.height = r0_y_end > r1_y_end ? r1_y_end - rec.y : r0_y_end - rec.y;
780
781 /* in case that there is no intersection */
782 if (rec.width < 0 || rec.height < 0)
783 memset(&rec, 0, sizeof(rec));
784
785 return rec;
786 }
787
shift_rec(const struct rect * rec_in,int x,int y)788 static struct rect shift_rec(const struct rect *rec_in, int x, int y)
789 {
790 struct rect rec_out = *rec_in;
791
792 rec_out.x += x;
793 rec_out.y += y;
794
795 return rec_out;
796 }
797
calculate_plane_rec_in_timing_active(struct pipe_ctx * pipe_ctx,const struct rect * rec_in)798 static struct rect calculate_plane_rec_in_timing_active(
799 struct pipe_ctx *pipe_ctx,
800 const struct rect *rec_in)
801 {
802 /*
803 * The following diagram shows an example where we map a 1920x1200
804 * desktop to a 2560x1440 timing with a plane rect in the middle
805 * of the screen. To map a plane rect from Stream Source to Timing
806 * Active space, we first multiply stream scaling ratios (i.e 2304/1920
807 * horizontal and 1440/1200 vertical) to the plane's x and y, then
808 * we add stream destination offsets (i.e 128 horizontal, 0 vertical).
809 * This will give us a plane rect's position in Timing Active. However
810 * we have to remove the fractional. The rule is that we find left/right
811 * and top/bottom positions and round the value to the adjacent integer.
812 *
813 * Stream Source Space
814 * ------------
815 * __________________________________________________
816 * |Stream Source (1920 x 1200) ^ |
817 * | y |
818 * | <------- w --------|> |
819 * | __________________V |
820 * |<-- x -->|Plane//////////////| ^ |
821 * | |(pre scale)////////| | |
822 * | |///////////////////| | |
823 * | |///////////////////| h |
824 * | |///////////////////| | |
825 * | |///////////////////| | |
826 * | |///////////////////| V |
827 * | |
828 * | |
829 * |__________________________________________________|
830 *
831 *
832 * Timing Active Space
833 * ---------------------------------
834 *
835 * Timing Active (2560 x 1440)
836 * __________________________________________________
837 * |*****| Stteam Destination (2304 x 1440) |*****|
838 * |*****| |*****|
839 * |<128>| |*****|
840 * |*****| __________________ |*****|
841 * |*****| |Plane/////////////| |*****|
842 * |*****| |(post scale)//////| |*****|
843 * |*****| |//////////////////| |*****|
844 * |*****| |//////////////////| |*****|
845 * |*****| |//////////////////| |*****|
846 * |*****| |//////////////////| |*****|
847 * |*****| |*****|
848 * |*****| |*****|
849 * |*****| |*****|
850 * |*****|______________________________________|*****|
851 *
852 * So the resulting formulas are shown below:
853 *
854 * recout_x = 128 + round(plane_x * 2304 / 1920)
855 * recout_w = 128 + round((plane_x + plane_w) * 2304 / 1920) - recout_x
856 * recout_y = 0 + round(plane_y * 1440 / 1280)
857 * recout_h = 0 + round((plane_y + plane_h) * 1440 / 1200) - recout_y
858 *
859 * NOTE: fixed point division is not error free. To reduce errors
860 * introduced by fixed point division, we divide only after
861 * multiplication is complete.
862 */
863 const struct dc_stream_state *stream = pipe_ctx->stream;
864 struct rect rec_out = {0};
865 struct fixed31_32 temp;
866
867 temp = dc_fixpt_from_fraction(rec_in->x * (long long)stream->dst.width,
868 stream->src.width);
869 rec_out.x = stream->dst.x + dc_fixpt_round(temp);
870
871 temp = dc_fixpt_from_fraction(
872 (rec_in->x + rec_in->width) * (long long)stream->dst.width,
873 stream->src.width);
874 rec_out.width = stream->dst.x + dc_fixpt_round(temp) - rec_out.x;
875
876 temp = dc_fixpt_from_fraction(rec_in->y * (long long)stream->dst.height,
877 stream->src.height);
878 rec_out.y = stream->dst.y + dc_fixpt_round(temp);
879
880 temp = dc_fixpt_from_fraction(
881 (rec_in->y + rec_in->height) * (long long)stream->dst.height,
882 stream->src.height);
883 rec_out.height = stream->dst.y + dc_fixpt_round(temp) - rec_out.y;
884
885 return rec_out;
886 }
887
calculate_mpc_slice_in_timing_active(struct pipe_ctx * pipe_ctx,struct rect * plane_clip_rec)888 static struct rect calculate_mpc_slice_in_timing_active(
889 struct pipe_ctx *pipe_ctx,
890 struct rect *plane_clip_rec)
891 {
892 const struct dc_stream_state *stream = pipe_ctx->stream;
893 int mpc_slice_count = resource_get_mpc_slice_count(pipe_ctx);
894 int mpc_slice_idx = resource_get_mpc_slice_index(pipe_ctx);
895 int epimo = mpc_slice_count - plane_clip_rec->width % mpc_slice_count - 1;
896 struct rect mpc_rec;
897
898 mpc_rec.width = plane_clip_rec->width / mpc_slice_count;
899 mpc_rec.x = plane_clip_rec->x + mpc_rec.width * mpc_slice_idx;
900 mpc_rec.height = plane_clip_rec->height;
901 mpc_rec.y = plane_clip_rec->y;
902 ASSERT(mpc_slice_count == 1 ||
903 stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE ||
904 mpc_rec.width % 2 == 0);
905
906 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
907 mpc_rec.x -= (mpc_rec.width * mpc_slice_idx);
908
909 /* extra pixels in the division remainder need to go to pipes after
910 * the extra pixel index minus one(epimo) defined here as:
911 */
912 if (mpc_slice_idx > epimo) {
913 mpc_rec.x += mpc_slice_idx - epimo - 1;
914 mpc_rec.width += 1;
915 }
916
917 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
918 ASSERT(mpc_rec.height % 2 == 0);
919 mpc_rec.height /= 2;
920 }
921 return mpc_rec;
922 }
923
calculate_adjust_recout_for_visual_confirm(struct pipe_ctx * pipe_ctx,int * base_offset,int * dpp_offset)924 static void calculate_adjust_recout_for_visual_confirm(struct pipe_ctx *pipe_ctx,
925 int *base_offset, int *dpp_offset)
926 {
927 struct dc *dc = pipe_ctx->stream->ctx->dc;
928 *base_offset = 0;
929 *dpp_offset = 0;
930
931 if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp)
932 return;
933
934 *dpp_offset = pipe_ctx->stream->timing.v_addressable / VISUAL_CONFIRM_DPP_OFFSET_DENO;
935 *dpp_offset *= pipe_ctx->plane_res.dpp->inst;
936
937 if ((dc->debug.visual_confirm_rect_height >= VISUAL_CONFIRM_BASE_MIN) &&
938 dc->debug.visual_confirm_rect_height <= VISUAL_CONFIRM_BASE_MAX)
939 *base_offset = dc->debug.visual_confirm_rect_height;
940 else
941 *base_offset = VISUAL_CONFIRM_BASE_DEFAULT;
942 }
943
adjust_recout_for_visual_confirm(struct rect * recout,struct pipe_ctx * pipe_ctx)944 static void adjust_recout_for_visual_confirm(struct rect *recout,
945 struct pipe_ctx *pipe_ctx)
946 {
947 int dpp_offset, base_offset;
948
949 calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset,
950 &dpp_offset);
951 recout->height -= base_offset;
952 recout->height -= dpp_offset;
953 }
954
955 /*
956 * The function maps a plane clip from Stream Source Space to ODM Slice Space
957 * and calculates the rec of the overlapping area of MPC slice of the plane
958 * clip, ODM slice associated with the pipe context and stream destination rec.
959 */
calculate_recout(struct pipe_ctx * pipe_ctx)960 static void calculate_recout(struct pipe_ctx *pipe_ctx)
961 {
962 /*
963 * A plane clip represents the desired plane size and position in Stream
964 * Source Space. Stream Source is the destination where all planes are
965 * blended (i.e. positioned, scaled and overlaid). It is a canvas where
966 * all planes associated with the current stream are drawn together.
967 * After Stream Source is completed, we will further scale and
968 * reposition the entire canvas of the stream source to Stream
969 * Destination in Timing Active Space. This could be due to display
970 * overscan adjustment where we will need to rescale and reposition all
971 * the planes so they can fit into a TV with overscan or downscale
972 * upscale features such as GPU scaling or VSR.
973 *
974 * This two step blending is a virtual procedure in software. In
975 * hardware there is no such thing as Stream Source. all planes are
976 * blended once in Timing Active Space. Software virtualizes a Stream
977 * Source space to decouple the math complicity so scaling param
978 * calculation focuses on one step at a time.
979 *
980 * In the following two diagrams, user applied 10% overscan adjustment
981 * so the Stream Source needs to be scaled down a little before mapping
982 * to Timing Active Space. As a result the Plane Clip is also scaled
983 * down by the same ratio, Plane Clip position (i.e. x and y) with
984 * respect to Stream Source is also scaled down. To map it in Timing
985 * Active Space additional x and y offsets from Stream Destination are
986 * added to Plane Clip as well.
987 *
988 * Stream Source Space
989 * ------------
990 * __________________________________________________
991 * |Stream Source (3840 x 2160) ^ |
992 * | y |
993 * | | |
994 * | __________________V |
995 * |<-- x -->|Plane Clip/////////| |
996 * | |(pre scale)////////| |
997 * | |///////////////////| |
998 * | |///////////////////| |
999 * | |///////////////////| |
1000 * | |///////////////////| |
1001 * | |///////////////////| |
1002 * | |
1003 * | |
1004 * |__________________________________________________|
1005 *
1006 *
1007 * Timing Active Space (3840 x 2160)
1008 * ---------------------------------
1009 *
1010 * Timing Active
1011 * __________________________________________________
1012 * | y_____________________________________________ |
1013 * |x |Stream Destination (3456 x 1944) | |
1014 * | | | |
1015 * | | __________________ | |
1016 * | | |Plane Clip////////| | |
1017 * | | |(post scale)//////| | |
1018 * | | |//////////////////| | |
1019 * | | |//////////////////| | |
1020 * | | |//////////////////| | |
1021 * | | |//////////////////| | |
1022 * | | | |
1023 * | | | |
1024 * | |____________________________________________| |
1025 * |__________________________________________________|
1026 *
1027 *
1028 * In Timing Active Space a plane clip could be further sliced into
1029 * pieces called MPC slices. Each Pipe Context is responsible for
1030 * processing only one MPC slice so the plane processing workload can be
1031 * distributed to multiple DPP Pipes. MPC slices could be blended
1032 * together to a single ODM slice. Each ODM slice is responsible for
1033 * processing a portion of Timing Active divided horizontally so the
1034 * output pixel processing workload can be distributed to multiple OPP
1035 * pipes. All ODM slices are mapped together in ODM block so all MPC
1036 * slices belong to different ODM slices could be pieced together to
1037 * form a single image in Timing Active. MPC slices must belong to
1038 * single ODM slice. If an MPC slice goes across ODM slice boundary, it
1039 * needs to be divided into two MPC slices one for each ODM slice.
1040 *
1041 * In the following diagram the output pixel processing workload is
1042 * divided horizontally into two ODM slices one for each OPP blend tree.
1043 * OPP0 blend tree is responsible for processing left half of Timing
1044 * Active, while OPP2 blend tree is responsible for processing right
1045 * half.
1046 *
1047 * The plane has two MPC slices. However since the right MPC slice goes
1048 * across ODM boundary, two DPP pipes are needed one for each OPP blend
1049 * tree. (i.e. DPP1 for OPP0 blend tree and DPP2 for OPP2 blend tree).
1050 *
1051 * Assuming that we have a Pipe Context associated with OPP0 and DPP1
1052 * working on processing the plane in the diagram. We want to know the
1053 * width and height of the shaded rectangle and its relative position
1054 * with respect to the ODM slice0. This is called the recout of the pipe
1055 * context.
1056 *
1057 * Planes can be at arbitrary size and position and there could be an
1058 * arbitrary number of MPC and ODM slices. The algorithm needs to take
1059 * all scenarios into account.
1060 *
1061 * Timing Active Space (3840 x 2160)
1062 * ---------------------------------
1063 *
1064 * Timing Active
1065 * __________________________________________________
1066 * |OPP0(ODM slice0)^ |OPP2(ODM slice1) |
1067 * | y | |
1068 * | | <- w -> |
1069 * | _____V________|____ |
1070 * | |DPP0 ^ |DPP1 |DPP2| |
1071 * |<------ x |-----|->|/////| | |
1072 * | | | |/////| | |
1073 * | | h |/////| | |
1074 * | | | |/////| | |
1075 * | |_____V__|/////|____| |
1076 * | | |
1077 * | | |
1078 * | | |
1079 * |_________________________|________________________|
1080 *
1081 *
1082 */
1083 struct rect plane_clip;
1084 struct rect mpc_slice_of_plane_clip;
1085 struct rect odm_slice_src;
1086 struct rect overlapping_area;
1087
1088 plane_clip = calculate_plane_rec_in_timing_active(pipe_ctx,
1089 &pipe_ctx->plane_state->clip_rect);
1090 /* guard plane clip from drawing beyond stream dst here */
1091 plane_clip = intersect_rec(&plane_clip,
1092 &pipe_ctx->stream->dst);
1093 mpc_slice_of_plane_clip = calculate_mpc_slice_in_timing_active(
1094 pipe_ctx, &plane_clip);
1095 odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);
1096 overlapping_area = intersect_rec(&mpc_slice_of_plane_clip, &odm_slice_src);
1097 if (overlapping_area.height > 0 &&
1098 overlapping_area.width > 0) {
1099 /* shift the overlapping area so it is with respect to current
1100 * ODM slice source's position
1101 */
1102 pipe_ctx->plane_res.scl_data.recout = shift_rec(
1103 &overlapping_area,
1104 -odm_slice_src.x, -odm_slice_src.y);
1105 adjust_recout_for_visual_confirm(
1106 &pipe_ctx->plane_res.scl_data.recout,
1107 pipe_ctx);
1108 } else {
1109 /* if there is no overlap, zero recout */
1110 memset(&pipe_ctx->plane_res.scl_data.recout, 0,
1111 sizeof(struct rect));
1112 }
1113
1114 }
1115
calculate_scaling_ratios(struct pipe_ctx * pipe_ctx)1116 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
1117 {
1118 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1119 const struct dc_stream_state *stream = pipe_ctx->stream;
1120 struct rect surf_src = plane_state->src_rect;
1121 const int in_w = stream->src.width;
1122 const int in_h = stream->src.height;
1123 const int out_w = stream->dst.width;
1124 const int out_h = stream->dst.height;
1125
1126 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
1127 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
1128 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
1129 swap(surf_src.height, surf_src.width);
1130
1131 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
1132 surf_src.width,
1133 plane_state->dst_rect.width);
1134 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
1135 surf_src.height,
1136 plane_state->dst_rect.height);
1137
1138 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
1139 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
1140 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
1141 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
1142
1143 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
1144 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
1145 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
1146 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
1147
1148 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
1149 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
1150
1151 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
1152 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
1153 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
1154 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
1155 }
1156 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
1157 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
1158 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
1159 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
1160 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
1161 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
1162 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
1163 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
1164 }
1165
1166
1167 /*
1168 * We completely calculate vp offset, size and inits here based entirely on scaling
1169 * ratios and recout for pixel perfect pipe combine.
1170 */
calculate_init_and_vp(bool flip_scan_dir,int recout_offset_within_recout_full,int recout_size,int src_size,int taps,struct fixed31_32 ratio,struct fixed31_32 * init,int * vp_offset,int * vp_size)1171 static void calculate_init_and_vp(
1172 bool flip_scan_dir,
1173 int recout_offset_within_recout_full,
1174 int recout_size,
1175 int src_size,
1176 int taps,
1177 struct fixed31_32 ratio,
1178 struct fixed31_32 *init,
1179 int *vp_offset,
1180 int *vp_size)
1181 {
1182 struct fixed31_32 temp;
1183 int int_part;
1184
1185 /*
1186 * First of the taps starts sampling pixel number <init_int_part> corresponding to recout
1187 * pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on.
1188 * All following calculations are based on this logic.
1189 *
1190 * Init calculated according to formula:
1191 * init = (scaling_ratio + number_of_taps + 1) / 2
1192 * init_bot = init + scaling_ratio
1193 * to get pixel perfect combine add the fraction from calculating vp offset
1194 */
1195 temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full);
1196 *vp_offset = dc_fixpt_floor(temp);
1197 temp.value &= 0xffffffff;
1198 *init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int(
1199 dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19);
1200 /*
1201 * If viewport has non 0 offset and there are more taps than covered by init then
1202 * we should decrease the offset and increase init so we are never sampling
1203 * outside of viewport.
1204 */
1205 int_part = dc_fixpt_floor(*init);
1206 if (int_part < taps) {
1207 int_part = taps - int_part;
1208 if (int_part > *vp_offset)
1209 int_part = *vp_offset;
1210 *vp_offset -= int_part;
1211 *init = dc_fixpt_add_int(*init, int_part);
1212 }
1213 /*
1214 * If taps are sampling outside of viewport at end of recout and there are more pixels
1215 * available in the surface we should increase the viewport size, regardless set vp to
1216 * only what is used.
1217 */
1218 temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1));
1219 *vp_size = dc_fixpt_floor(temp);
1220 if (*vp_size + *vp_offset > src_size)
1221 *vp_size = src_size - *vp_offset;
1222
1223 /* We did all the math assuming we are scanning same direction as display does,
1224 * however mirror/rotation changes how vp scans vs how it is offset. If scan direction
1225 * is flipped we simply need to calculate offset from the other side of plane.
1226 * Note that outside of viewport all scaling hardware works in recout space.
1227 */
1228 if (flip_scan_dir)
1229 *vp_offset = src_size - *vp_offset - *vp_size;
1230 }
1231
calculate_inits_and_viewports(struct pipe_ctx * pipe_ctx)1232 static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx)
1233 {
1234 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1235 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
1236 struct rect src = plane_state->src_rect;
1237 struct rect recout_dst_in_active_timing;
1238 struct rect recout_clip_in_active_timing;
1239 struct rect recout_clip_in_recout_dst;
1240 struct rect overlap_in_active_timing;
1241 struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);
1242 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
1243 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1244 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
1245
1246 recout_clip_in_active_timing = shift_rec(
1247 &data->recout, odm_slice_src.x, odm_slice_src.y);
1248 recout_dst_in_active_timing = calculate_plane_rec_in_timing_active(
1249 pipe_ctx, &plane_state->dst_rect);
1250 overlap_in_active_timing = intersect_rec(&recout_clip_in_active_timing,
1251 &recout_dst_in_active_timing);
1252 if (overlap_in_active_timing.width > 0 &&
1253 overlap_in_active_timing.height > 0)
1254 recout_clip_in_recout_dst = shift_rec(&overlap_in_active_timing,
1255 -recout_dst_in_active_timing.x,
1256 -recout_dst_in_active_timing.y);
1257 else
1258 memset(&recout_clip_in_recout_dst, 0, sizeof(struct rect));
1259
1260 /*
1261 * Work in recout rotation since that requires less transformations
1262 */
1263 get_vp_scan_direction(
1264 plane_state->rotation,
1265 plane_state->horizontal_mirror,
1266 &orthogonal_rotation,
1267 &flip_vert_scan_dir,
1268 &flip_horz_scan_dir);
1269
1270 if (orthogonal_rotation) {
1271 swap(src.width, src.height);
1272 swap(flip_vert_scan_dir, flip_horz_scan_dir);
1273 }
1274
1275 calculate_init_and_vp(
1276 flip_horz_scan_dir,
1277 recout_clip_in_recout_dst.x,
1278 data->recout.width,
1279 src.width,
1280 data->taps.h_taps,
1281 data->ratios.horz,
1282 &data->inits.h,
1283 &data->viewport.x,
1284 &data->viewport.width);
1285 calculate_init_and_vp(
1286 flip_horz_scan_dir,
1287 recout_clip_in_recout_dst.x,
1288 data->recout.width,
1289 src.width / vpc_div,
1290 data->taps.h_taps_c,
1291 data->ratios.horz_c,
1292 &data->inits.h_c,
1293 &data->viewport_c.x,
1294 &data->viewport_c.width);
1295 calculate_init_and_vp(
1296 flip_vert_scan_dir,
1297 recout_clip_in_recout_dst.y,
1298 data->recout.height,
1299 src.height,
1300 data->taps.v_taps,
1301 data->ratios.vert,
1302 &data->inits.v,
1303 &data->viewport.y,
1304 &data->viewport.height);
1305 calculate_init_and_vp(
1306 flip_vert_scan_dir,
1307 recout_clip_in_recout_dst.y,
1308 data->recout.height,
1309 src.height / vpc_div,
1310 data->taps.v_taps_c,
1311 data->ratios.vert_c,
1312 &data->inits.v_c,
1313 &data->viewport_c.y,
1314 &data->viewport_c.height);
1315 if (orthogonal_rotation) {
1316 swap(data->viewport.x, data->viewport.y);
1317 swap(data->viewport.width, data->viewport.height);
1318 swap(data->viewport_c.x, data->viewport_c.y);
1319 swap(data->viewport_c.width, data->viewport_c.height);
1320 }
1321 data->viewport.x += src.x;
1322 data->viewport.y += src.y;
1323 ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0);
1324 data->viewport_c.x += src.x / vpc_div;
1325 data->viewport_c.y += src.y / vpc_div;
1326 }
1327
is_subvp_high_refresh_candidate(struct dc_stream_state * stream)1328 static bool is_subvp_high_refresh_candidate(struct dc_stream_state *stream)
1329 {
1330 uint32_t refresh_rate;
1331 struct dc *dc = stream->ctx->dc;
1332
1333 refresh_rate = (stream->timing.pix_clk_100hz * (uint64_t)100 +
1334 stream->timing.v_total * stream->timing.h_total - (uint64_t)1);
1335 refresh_rate = div_u64(refresh_rate, stream->timing.v_total);
1336 refresh_rate = div_u64(refresh_rate, stream->timing.h_total);
1337
1338 /* If there's any stream that fits the SubVP high refresh criteria,
1339 * we must return true. This is because cursor updates are asynchronous
1340 * with full updates, so we could transition into a SubVP config and
1341 * remain in HW cursor mode if there's no cursor update which will
1342 * then cause corruption.
1343 */
1344 if ((refresh_rate >= 120 && refresh_rate <= 175 &&
1345 stream->timing.v_addressable >= 1080 &&
1346 stream->timing.v_addressable <= 2160) &&
1347 (dc->current_state->stream_count > 1 ||
1348 (dc->current_state->stream_count == 1 && !stream->allow_freesync)))
1349 return true;
1350
1351 return false;
1352 }
1353
convert_dp_to_controller_test_pattern(enum dp_test_pattern test_pattern)1354 static enum controller_dp_test_pattern convert_dp_to_controller_test_pattern(
1355 enum dp_test_pattern test_pattern)
1356 {
1357 enum controller_dp_test_pattern controller_test_pattern;
1358
1359 switch (test_pattern) {
1360 case DP_TEST_PATTERN_COLOR_SQUARES:
1361 controller_test_pattern =
1362 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
1363 break;
1364 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
1365 controller_test_pattern =
1366 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
1367 break;
1368 case DP_TEST_PATTERN_VERTICAL_BARS:
1369 controller_test_pattern =
1370 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
1371 break;
1372 case DP_TEST_PATTERN_HORIZONTAL_BARS:
1373 controller_test_pattern =
1374 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
1375 break;
1376 case DP_TEST_PATTERN_COLOR_RAMP:
1377 controller_test_pattern =
1378 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
1379 break;
1380 default:
1381 controller_test_pattern =
1382 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
1383 break;
1384 }
1385
1386 return controller_test_pattern;
1387 }
1388
convert_dp_to_controller_color_space(enum dp_test_pattern_color_space color_space)1389 static enum controller_dp_color_space convert_dp_to_controller_color_space(
1390 enum dp_test_pattern_color_space color_space)
1391 {
1392 enum controller_dp_color_space controller_color_space;
1393
1394 switch (color_space) {
1395 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
1396 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
1397 break;
1398 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
1399 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
1400 break;
1401 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
1402 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
1403 break;
1404 case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
1405 default:
1406 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
1407 break;
1408 }
1409
1410 return controller_color_space;
1411 }
1412
resource_build_test_pattern_params(struct resource_context * res_ctx,struct pipe_ctx * otg_master)1413 void resource_build_test_pattern_params(struct resource_context *res_ctx,
1414 struct pipe_ctx *otg_master)
1415 {
1416 struct pipe_ctx *opp_heads[MAX_PIPES];
1417 struct test_pattern_params *params;
1418 int odm_cnt;
1419 enum controller_dp_test_pattern controller_test_pattern;
1420 enum controller_dp_color_space controller_color_space;
1421 enum dc_color_depth color_depth = otg_master->stream->timing.display_color_depth;
1422 struct rect odm_slice_src;
1423 int i;
1424
1425 controller_test_pattern = convert_dp_to_controller_test_pattern(
1426 otg_master->stream->test_pattern.type);
1427 controller_color_space = convert_dp_to_controller_color_space(
1428 otg_master->stream->test_pattern.color_space);
1429
1430 if (controller_test_pattern == CONTROLLER_DP_TEST_PATTERN_VIDEOMODE)
1431 return;
1432
1433 odm_cnt = resource_get_opp_heads_for_otg_master(otg_master, res_ctx, opp_heads);
1434
1435 for (i = 0; i < odm_cnt; i++) {
1436 odm_slice_src = resource_get_odm_slice_src_rect(opp_heads[i]);
1437 params = &opp_heads[i]->stream_res.test_pattern_params;
1438 params->test_pattern = controller_test_pattern;
1439 params->color_space = controller_color_space;
1440 params->color_depth = color_depth;
1441 params->height = odm_slice_src.height;
1442 params->offset = odm_slice_src.x;
1443 params->width = odm_slice_src.width;
1444 }
1445 }
1446
resource_build_scaling_params(struct pipe_ctx * pipe_ctx)1447 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
1448 {
1449 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1450 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
1451 const struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);
1452 struct scaling_taps temp = {0};
1453 bool res = false;
1454
1455 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1456
1457 /* Invalid input */
1458 if (!plane_state ||
1459 !plane_state->dst_rect.width ||
1460 !plane_state->dst_rect.height ||
1461 !plane_state->src_rect.width ||
1462 !plane_state->src_rect.height) {
1463 ASSERT(0);
1464 return false;
1465 }
1466
1467 /* Timing borders are part of vactive that we are also supposed to skip in addition
1468 * to any stream dst offset. Since dm logic assumes dst is in addressable
1469 * space we need to add the left and top borders to dst offsets temporarily.
1470 * TODO: fix in DM, stream dst is supposed to be in vactive
1471 */
1472 pipe_ctx->stream->dst.x += timing->h_border_left;
1473 pipe_ctx->stream->dst.y += timing->v_border_top;
1474
1475 /* Calculate H and V active size */
1476 pipe_ctx->plane_res.scl_data.h_active = odm_slice_src.width;
1477 pipe_ctx->plane_res.scl_data.v_active = odm_slice_src.height;
1478 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
1479 pipe_ctx->plane_state->format);
1480
1481 #if defined(CONFIG_DRM_AMD_DC_FP)
1482 if ((pipe_ctx->stream->ctx->dc->config.use_spl) && (!pipe_ctx->stream->ctx->dc->debug.disable_spl)) {
1483 struct spl_in *spl_in = &pipe_ctx->plane_res.spl_in;
1484 struct spl_out *spl_out = &pipe_ctx->plane_res.spl_out;
1485
1486 if (plane_state->ctx->dce_version > DCE_VERSION_MAX)
1487 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
1488 else
1489 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1490
1491 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
1492
1493 // Convert pipe_ctx to respective input params for SPL
1494 translate_SPL_in_params_from_pipe_ctx(pipe_ctx, spl_in);
1495 /* Pass visual confirm debug information */
1496 calculate_adjust_recout_for_visual_confirm(pipe_ctx,
1497 &spl_in->debug.visual_confirm_base_offset,
1498 &spl_in->debug.visual_confirm_dpp_offset);
1499 // Set SPL output parameters to dscl_prog_data to be used for hw registers
1500 spl_out->dscl_prog_data = resource_get_dscl_prog_data(pipe_ctx);
1501 // Calculate scaler parameters from SPL
1502 res = spl_calculate_scaler_params(spl_in, spl_out);
1503 // Convert respective out params from SPL to scaler data
1504 translate_SPL_out_params_to_pipe_ctx(pipe_ctx, spl_out);
1505
1506 /* Ignore scaler failure if pipe context plane is phantom plane */
1507 if (!res && plane_state->is_phantom)
1508 res = true;
1509 } else {
1510 #endif
1511 /* depends on h_active */
1512 calculate_recout(pipe_ctx);
1513 /* depends on pixel format */
1514 calculate_scaling_ratios(pipe_ctx);
1515
1516 /*
1517 * LB calculations depend on vp size, h/v_active and scaling ratios
1518 * Setting line buffer pixel depth to 24bpp yields banding
1519 * on certain displays, such as the Sharp 4k. 36bpp is needed
1520 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and
1521 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc
1522 * precision on DCN display engines, but apparently not for DCE, as
1523 * far as testing on DCE-11.2 and DCE-8 showed. Various DCE parts have
1524 * problems: Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
1525 * neither do DCE-8 at 4k resolution, or DCE-11.2 (broken identify pixel
1526 * passthrough). Therefore only use 36 bpp on DCN where it is actually needed.
1527 */
1528 if (plane_state->ctx->dce_version > DCE_VERSION_MAX)
1529 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
1530 else
1531 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1532
1533 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
1534
1535 // get TAP value with 100x100 dummy data for max scaling qualify, override
1536 // if a new scaling quality required
1537 pipe_ctx->plane_res.scl_data.viewport.width = 100;
1538 pipe_ctx->plane_res.scl_data.viewport.height = 100;
1539 pipe_ctx->plane_res.scl_data.viewport_c.width = 100;
1540 pipe_ctx->plane_res.scl_data.viewport_c.height = 100;
1541 if (pipe_ctx->plane_res.xfm != NULL)
1542 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1543 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1544
1545 if (pipe_ctx->plane_res.dpp != NULL)
1546 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1547 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1548
1549 temp = pipe_ctx->plane_res.scl_data.taps;
1550
1551 calculate_inits_and_viewports(pipe_ctx);
1552
1553 if (pipe_ctx->plane_res.xfm != NULL)
1554 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1555 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1556
1557 if (pipe_ctx->plane_res.dpp != NULL)
1558 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1559 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1560
1561
1562 if (!res) {
1563 /* Try 24 bpp linebuffer */
1564 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
1565
1566 if (pipe_ctx->plane_res.xfm != NULL)
1567 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1568 pipe_ctx->plane_res.xfm,
1569 &pipe_ctx->plane_res.scl_data,
1570 &plane_state->scaling_quality);
1571
1572 if (pipe_ctx->plane_res.dpp != NULL)
1573 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1574 pipe_ctx->plane_res.dpp,
1575 &pipe_ctx->plane_res.scl_data,
1576 &plane_state->scaling_quality);
1577 }
1578
1579 /* Ignore scaler failure if pipe context plane is phantom plane */
1580 if (!res && plane_state->is_phantom)
1581 res = true;
1582
1583 if (res && (pipe_ctx->plane_res.scl_data.taps.v_taps != temp.v_taps ||
1584 pipe_ctx->plane_res.scl_data.taps.h_taps != temp.h_taps ||
1585 pipe_ctx->plane_res.scl_data.taps.v_taps_c != temp.v_taps_c ||
1586 pipe_ctx->plane_res.scl_data.taps.h_taps_c != temp.h_taps_c))
1587 calculate_inits_and_viewports(pipe_ctx);
1588
1589 /*
1590 * Handle side by side and top bottom 3d recout offsets after vp calculation
1591 * since 3d is special and needs to calculate vp as if there is no recout offset
1592 * This may break with rotation, good thing we aren't mixing hw rotation and 3d
1593 */
1594 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) {
1595 ASSERT(plane_state->rotation == ROTATION_ANGLE_0 ||
1596 (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM &&
1597 pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE));
1598 if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
1599 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;
1600 else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
1601 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;
1602 }
1603
1604 /* Clamp minimum viewport size */
1605 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE)
1606 pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE;
1607 if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
1608 pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;
1609 #ifdef CONFIG_DRM_AMD_DC_FP
1610 }
1611 #endif
1612 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n"
1613 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n",
1614 __func__,
1615 pipe_ctx->pipe_idx,
1616 pipe_ctx->plane_res.scl_data.viewport.height,
1617 pipe_ctx->plane_res.scl_data.viewport.width,
1618 pipe_ctx->plane_res.scl_data.viewport.x,
1619 pipe_ctx->plane_res.scl_data.viewport.y,
1620 pipe_ctx->plane_res.scl_data.recout.height,
1621 pipe_ctx->plane_res.scl_data.recout.width,
1622 pipe_ctx->plane_res.scl_data.recout.x,
1623 pipe_ctx->plane_res.scl_data.recout.y,
1624 pipe_ctx->plane_res.scl_data.h_active,
1625 pipe_ctx->plane_res.scl_data.v_active,
1626 plane_state->src_rect.height,
1627 plane_state->src_rect.width,
1628 plane_state->src_rect.x,
1629 plane_state->src_rect.y,
1630 plane_state->dst_rect.height,
1631 plane_state->dst_rect.width,
1632 plane_state->dst_rect.x,
1633 plane_state->dst_rect.y,
1634 plane_state->clip_rect.height,
1635 plane_state->clip_rect.width,
1636 plane_state->clip_rect.x,
1637 plane_state->clip_rect.y);
1638
1639 pipe_ctx->stream->dst.x -= timing->h_border_left;
1640 pipe_ctx->stream->dst.y -= timing->v_border_top;
1641
1642 return res;
1643 }
1644
1645
resource_build_scaling_params_for_context(const struct dc * dc,struct dc_state * context)1646 enum dc_status resource_build_scaling_params_for_context(
1647 const struct dc *dc,
1648 struct dc_state *context)
1649 {
1650 int i;
1651
1652 for (i = 0; i < MAX_PIPES; i++) {
1653 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
1654 context->res_ctx.pipe_ctx[i].stream != NULL)
1655 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
1656 return DC_FAIL_SCALING;
1657 }
1658
1659 return DC_OK;
1660 }
1661
resource_find_free_secondary_pipe_legacy(struct resource_context * res_ctx,const struct resource_pool * pool,const struct pipe_ctx * primary_pipe)1662 struct pipe_ctx *resource_find_free_secondary_pipe_legacy(
1663 struct resource_context *res_ctx,
1664 const struct resource_pool *pool,
1665 const struct pipe_ctx *primary_pipe)
1666 {
1667 int i;
1668 struct pipe_ctx *secondary_pipe = NULL;
1669
1670 /*
1671 * We add a preferred pipe mapping to avoid the chance that
1672 * MPCCs already in use will need to be reassigned to other trees.
1673 * For example, if we went with the strict, assign backwards logic:
1674 *
1675 * (State 1)
1676 * Display A on, no surface, top pipe = 0
1677 * Display B on, no surface, top pipe = 1
1678 *
1679 * (State 2)
1680 * Display A on, no surface, top pipe = 0
1681 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1682 *
1683 * (State 3)
1684 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1685 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1686 *
1687 * The state 2->3 transition requires remapping MPCC 5 from display B
1688 * to display A.
1689 *
1690 * However, with the preferred pipe logic, state 2 would look like:
1691 *
1692 * (State 2)
1693 * Display A on, no surface, top pipe = 0
1694 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1695 *
1696 * This would then cause 2->3 to not require remapping any MPCCs.
1697 */
1698 if (primary_pipe) {
1699 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1700 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1701 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1702 secondary_pipe->pipe_idx = preferred_pipe_idx;
1703 }
1704 }
1705
1706 /*
1707 * search backwards for the second pipe to keep pipe
1708 * assignment more consistent
1709 */
1710 if (!secondary_pipe)
1711 for (i = pool->pipe_count - 1; i >= 0; i--) {
1712 if (res_ctx->pipe_ctx[i].stream == NULL) {
1713 secondary_pipe = &res_ctx->pipe_ctx[i];
1714 secondary_pipe->pipe_idx = i;
1715 break;
1716 }
1717 }
1718
1719 return secondary_pipe;
1720 }
1721
resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct pipe_ctx * cur_otg_master)1722 int resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(
1723 const struct resource_context *cur_res_ctx,
1724 struct resource_context *new_res_ctx,
1725 const struct pipe_ctx *cur_otg_master)
1726 {
1727 const struct pipe_ctx *cur_sec_opp_head = cur_otg_master->next_odm_pipe;
1728 struct pipe_ctx *new_pipe;
1729 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1730
1731 while (cur_sec_opp_head) {
1732 new_pipe = &new_res_ctx->pipe_ctx[cur_sec_opp_head->pipe_idx];
1733 if (resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1734 free_pipe_idx = cur_sec_opp_head->pipe_idx;
1735 break;
1736 }
1737 cur_sec_opp_head = cur_sec_opp_head->next_odm_pipe;
1738 }
1739
1740 return free_pipe_idx;
1741 }
1742
resource_find_free_pipe_used_in_cur_mpc_blending_tree(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct pipe_ctx * cur_opp_head)1743 int resource_find_free_pipe_used_in_cur_mpc_blending_tree(
1744 const struct resource_context *cur_res_ctx,
1745 struct resource_context *new_res_ctx,
1746 const struct pipe_ctx *cur_opp_head)
1747 {
1748 const struct pipe_ctx *cur_sec_dpp = cur_opp_head->bottom_pipe;
1749 struct pipe_ctx *new_pipe;
1750 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1751
1752 while (cur_sec_dpp) {
1753 /* find a free pipe used in current opp blend tree,
1754 * this is to avoid MPO pipe switching to different opp blending
1755 * tree
1756 */
1757 new_pipe = &new_res_ctx->pipe_ctx[cur_sec_dpp->pipe_idx];
1758 if (resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1759 free_pipe_idx = cur_sec_dpp->pipe_idx;
1760 break;
1761 }
1762 cur_sec_dpp = cur_sec_dpp->bottom_pipe;
1763 }
1764
1765 return free_pipe_idx;
1766 }
1767
recource_find_free_pipe_not_used_in_cur_res_ctx(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool)1768 int recource_find_free_pipe_not_used_in_cur_res_ctx(
1769 const struct resource_context *cur_res_ctx,
1770 struct resource_context *new_res_ctx,
1771 const struct resource_pool *pool)
1772 {
1773 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1774 const struct pipe_ctx *new_pipe, *cur_pipe;
1775 int i;
1776
1777 for (i = 0; i < pool->pipe_count; i++) {
1778 cur_pipe = &cur_res_ctx->pipe_ctx[i];
1779 new_pipe = &new_res_ctx->pipe_ctx[i];
1780
1781 if (resource_is_pipe_type(cur_pipe, FREE_PIPE) &&
1782 resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1783 free_pipe_idx = i;
1784 break;
1785 }
1786 }
1787
1788 return free_pipe_idx;
1789 }
1790
recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool)1791 int recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx(
1792 const struct resource_context *cur_res_ctx,
1793 struct resource_context *new_res_ctx,
1794 const struct resource_pool *pool)
1795 {
1796 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1797 const struct pipe_ctx *new_pipe, *cur_pipe;
1798 int i;
1799
1800 for (i = 0; i < pool->pipe_count; i++) {
1801 cur_pipe = &cur_res_ctx->pipe_ctx[i];
1802 new_pipe = &new_res_ctx->pipe_ctx[i];
1803
1804 if (resource_is_pipe_type(cur_pipe, OTG_MASTER) &&
1805 resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1806 free_pipe_idx = i;
1807 break;
1808 }
1809 }
1810
1811 return free_pipe_idx;
1812 }
1813
resource_find_free_pipe_used_as_cur_sec_dpp(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool)1814 int resource_find_free_pipe_used_as_cur_sec_dpp(
1815 const struct resource_context *cur_res_ctx,
1816 struct resource_context *new_res_ctx,
1817 const struct resource_pool *pool)
1818 {
1819 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1820 const struct pipe_ctx *new_pipe, *cur_pipe;
1821 int i;
1822
1823 for (i = 0; i < pool->pipe_count; i++) {
1824 cur_pipe = &cur_res_ctx->pipe_ctx[i];
1825 new_pipe = &new_res_ctx->pipe_ctx[i];
1826
1827 if (resource_is_pipe_type(cur_pipe, DPP_PIPE) &&
1828 !resource_is_pipe_type(cur_pipe, OPP_HEAD) &&
1829 resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1830 free_pipe_idx = i;
1831 break;
1832 }
1833 }
1834
1835 return free_pipe_idx;
1836 }
1837
resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool)1838 int resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(
1839 const struct resource_context *cur_res_ctx,
1840 struct resource_context *new_res_ctx,
1841 const struct resource_pool *pool)
1842 {
1843 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1844 const struct pipe_ctx *new_pipe, *cur_pipe;
1845 int i;
1846
1847 for (i = 0; i < pool->pipe_count; i++) {
1848 cur_pipe = &cur_res_ctx->pipe_ctx[i];
1849 new_pipe = &new_res_ctx->pipe_ctx[i];
1850
1851 if (resource_is_pipe_type(cur_pipe, DPP_PIPE) &&
1852 !resource_is_pipe_type(cur_pipe, OPP_HEAD) &&
1853 resource_get_mpc_slice_index(cur_pipe) > 0 &&
1854 resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1855 free_pipe_idx = i;
1856 break;
1857 }
1858 }
1859
1860 return free_pipe_idx;
1861 }
1862
resource_find_any_free_pipe(struct resource_context * new_res_ctx,const struct resource_pool * pool)1863 int resource_find_any_free_pipe(struct resource_context *new_res_ctx,
1864 const struct resource_pool *pool)
1865 {
1866 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1867 const struct pipe_ctx *new_pipe;
1868 int i;
1869
1870 for (i = 0; i < pool->pipe_count; i++) {
1871 new_pipe = &new_res_ctx->pipe_ctx[i];
1872
1873 if (resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1874 free_pipe_idx = i;
1875 break;
1876 }
1877 }
1878
1879 return free_pipe_idx;
1880 }
1881
resource_is_pipe_type(const struct pipe_ctx * pipe_ctx,enum pipe_type type)1882 bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type)
1883 {
1884 switch (type) {
1885 case OTG_MASTER:
1886 return !pipe_ctx->prev_odm_pipe &&
1887 !pipe_ctx->top_pipe &&
1888 pipe_ctx->stream;
1889 case OPP_HEAD:
1890 return !pipe_ctx->top_pipe && pipe_ctx->stream;
1891 case DPP_PIPE:
1892 return pipe_ctx->plane_state && pipe_ctx->stream;
1893 case FREE_PIPE:
1894 return !pipe_ctx->plane_state && !pipe_ctx->stream;
1895 default:
1896 return false;
1897 }
1898 }
1899
resource_get_otg_master_for_stream(struct resource_context * res_ctx,const struct dc_stream_state * stream)1900 struct pipe_ctx *resource_get_otg_master_for_stream(
1901 struct resource_context *res_ctx,
1902 const struct dc_stream_state *stream)
1903 {
1904 int i;
1905
1906 for (i = 0; i < MAX_PIPES; i++) {
1907 if (res_ctx->pipe_ctx[i].stream == stream &&
1908 resource_is_pipe_type(&res_ctx->pipe_ctx[i], OTG_MASTER))
1909 return &res_ctx->pipe_ctx[i];
1910 }
1911 return NULL;
1912 }
1913
resource_get_opp_heads_for_otg_master(const struct pipe_ctx * otg_master,struct resource_context * res_ctx,struct pipe_ctx * opp_heads[MAX_PIPES])1914 int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master,
1915 struct resource_context *res_ctx,
1916 struct pipe_ctx *opp_heads[MAX_PIPES])
1917 {
1918 struct pipe_ctx *opp_head = &res_ctx->pipe_ctx[otg_master->pipe_idx];
1919 struct dc *dc = otg_master->stream->ctx->dc;
1920 int i = 0;
1921
1922 DC_LOGGER_INIT(dc->ctx->logger);
1923
1924 if (!resource_is_pipe_type(otg_master, OTG_MASTER)) {
1925 DC_LOG_WARNING("%s called from a non OTG master, something "
1926 "is wrong in the pipe configuration",
1927 __func__);
1928 ASSERT(0);
1929 return 0;
1930 }
1931 while (opp_head) {
1932 ASSERT(i < MAX_PIPES);
1933 opp_heads[i++] = opp_head;
1934 opp_head = opp_head->next_odm_pipe;
1935 }
1936 return i;
1937 }
1938
resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx * opp_head,struct resource_context * res_ctx,struct pipe_ctx * dpp_pipes[MAX_PIPES])1939 int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head,
1940 struct resource_context *res_ctx,
1941 struct pipe_ctx *dpp_pipes[MAX_PIPES])
1942 {
1943 struct pipe_ctx *pipe = &res_ctx->pipe_ctx[opp_head->pipe_idx];
1944 int i = 0;
1945
1946 if (!resource_is_pipe_type(opp_head, OPP_HEAD)) {
1947 ASSERT(0);
1948 return 0;
1949 }
1950 while (pipe && resource_is_pipe_type(pipe, DPP_PIPE)) {
1951 ASSERT(i < MAX_PIPES);
1952 dpp_pipes[i++] = pipe;
1953 pipe = pipe->bottom_pipe;
1954 }
1955 return i;
1956 }
1957
resource_get_dpp_pipes_for_plane(const struct dc_plane_state * plane,struct resource_context * res_ctx,struct pipe_ctx * dpp_pipes[MAX_PIPES])1958 int resource_get_dpp_pipes_for_plane(const struct dc_plane_state *plane,
1959 struct resource_context *res_ctx,
1960 struct pipe_ctx *dpp_pipes[MAX_PIPES])
1961 {
1962 int i = 0, j;
1963 struct pipe_ctx *pipe;
1964
1965 for (j = 0; j < MAX_PIPES; j++) {
1966 pipe = &res_ctx->pipe_ctx[j];
1967 if (pipe->plane_state == plane && pipe->prev_odm_pipe == NULL) {
1968 if (resource_is_pipe_type(pipe, OPP_HEAD) ||
1969 pipe->top_pipe->plane_state != plane)
1970 break;
1971 }
1972 }
1973
1974 if (j < MAX_PIPES) {
1975 if (pipe->next_odm_pipe)
1976 while (pipe) {
1977 dpp_pipes[i++] = pipe;
1978 pipe = pipe->next_odm_pipe;
1979 }
1980 else
1981 while (pipe && pipe->plane_state == plane) {
1982 dpp_pipes[i++] = pipe;
1983 pipe = pipe->bottom_pipe;
1984 }
1985 }
1986 return i;
1987 }
1988
resource_get_otg_master(const struct pipe_ctx * pipe_ctx)1989 struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx)
1990 {
1991 struct pipe_ctx *otg_master = resource_get_opp_head(pipe_ctx);
1992
1993 while (otg_master->prev_odm_pipe)
1994 otg_master = otg_master->prev_odm_pipe;
1995 return otg_master;
1996 }
1997
resource_get_opp_head(const struct pipe_ctx * pipe_ctx)1998 struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx)
1999 {
2000 struct pipe_ctx *opp_head = (struct pipe_ctx *) pipe_ctx;
2001
2002 ASSERT(!resource_is_pipe_type(opp_head, FREE_PIPE));
2003 while (opp_head->top_pipe)
2004 opp_head = opp_head->top_pipe;
2005 return opp_head;
2006 }
2007
resource_get_primary_dpp_pipe(const struct pipe_ctx * dpp_pipe)2008 struct pipe_ctx *resource_get_primary_dpp_pipe(const struct pipe_ctx *dpp_pipe)
2009 {
2010 struct pipe_ctx *pri_dpp_pipe = (struct pipe_ctx *) dpp_pipe;
2011
2012 ASSERT(resource_is_pipe_type(dpp_pipe, DPP_PIPE));
2013 while (pri_dpp_pipe->prev_odm_pipe)
2014 pri_dpp_pipe = pri_dpp_pipe->prev_odm_pipe;
2015 while (pri_dpp_pipe->top_pipe &&
2016 pri_dpp_pipe->top_pipe->plane_state == pri_dpp_pipe->plane_state)
2017 pri_dpp_pipe = pri_dpp_pipe->top_pipe;
2018 return pri_dpp_pipe;
2019 }
2020
2021
resource_get_mpc_slice_index(const struct pipe_ctx * pipe_ctx)2022 int resource_get_mpc_slice_index(const struct pipe_ctx *pipe_ctx)
2023 {
2024 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
2025 int index = 0;
2026
2027 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
2028 index++;
2029 split_pipe = split_pipe->top_pipe;
2030 }
2031
2032 return index;
2033 }
2034
resource_get_mpc_slice_count(const struct pipe_ctx * pipe)2035 int resource_get_mpc_slice_count(const struct pipe_ctx *pipe)
2036 {
2037 int mpc_split_count = 1;
2038 const struct pipe_ctx *other_pipe = pipe->bottom_pipe;
2039
2040 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
2041 mpc_split_count++;
2042 other_pipe = other_pipe->bottom_pipe;
2043 }
2044 other_pipe = pipe->top_pipe;
2045 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
2046 mpc_split_count++;
2047 other_pipe = other_pipe->top_pipe;
2048 }
2049
2050 return mpc_split_count;
2051 }
2052
resource_get_odm_slice_count(const struct pipe_ctx * pipe)2053 int resource_get_odm_slice_count(const struct pipe_ctx *pipe)
2054 {
2055 int odm_split_count = 1;
2056
2057 pipe = resource_get_otg_master(pipe);
2058
2059 while (pipe->next_odm_pipe) {
2060 odm_split_count++;
2061 pipe = pipe->next_odm_pipe;
2062 }
2063 return odm_split_count;
2064 }
2065
resource_get_odm_slice_index(const struct pipe_ctx * pipe_ctx)2066 int resource_get_odm_slice_index(const struct pipe_ctx *pipe_ctx)
2067 {
2068 int index = 0;
2069
2070 pipe_ctx = resource_get_opp_head(pipe_ctx);
2071 if (!pipe_ctx)
2072 return 0;
2073
2074 while (pipe_ctx->prev_odm_pipe) {
2075 index++;
2076 pipe_ctx = pipe_ctx->prev_odm_pipe;
2077 }
2078
2079 return index;
2080 }
2081
resource_get_odm_slice_dst_width(struct pipe_ctx * otg_master,bool is_last_segment)2082 int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master,
2083 bool is_last_segment)
2084 {
2085 const struct dc_crtc_timing *timing;
2086 int count;
2087 int h_active;
2088 int width;
2089 bool two_pixel_alignment_required = false;
2090
2091 if (!otg_master || !otg_master->stream)
2092 return 0;
2093
2094 timing = &otg_master->stream->timing;
2095 count = resource_get_odm_slice_count(otg_master);
2096 h_active = timing->h_addressable +
2097 timing->h_border_left +
2098 timing->h_border_right +
2099 otg_master->hblank_borrow;
2100 width = h_active / count;
2101
2102 if (otg_master->stream_res.tg)
2103 two_pixel_alignment_required =
2104 otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing) ||
2105 /*
2106 * 422 is sub-sampled horizontally. 1 set of chromas
2107 * (Cb/Cr) is shared for 2 lumas (i.e 2 Y values).
2108 * Therefore even if 422 is still 1 pixel per container,
2109 * ODM segment width still needs to be 2 pixel aligned.
2110 */
2111 timing->pixel_encoding == PIXEL_ENCODING_YCBCR422;
2112 if ((width % 2) && two_pixel_alignment_required)
2113 width++;
2114
2115 return is_last_segment ?
2116 h_active - width * (count - 1) :
2117 width;
2118 }
2119
resource_get_odm_slice_dst_rect(struct pipe_ctx * pipe_ctx)2120 struct rect resource_get_odm_slice_dst_rect(struct pipe_ctx *pipe_ctx)
2121 {
2122 const struct dc_stream_state *stream = pipe_ctx->stream;
2123 bool is_last_odm_slice = pipe_ctx->next_odm_pipe == NULL;
2124 struct pipe_ctx *otg_master = resource_get_otg_master(pipe_ctx);
2125 int odm_slice_idx = resource_get_odm_slice_index(pipe_ctx);
2126 int odm_segment_offset = resource_get_odm_slice_dst_width(otg_master, false);
2127 struct rect odm_slice_dst;
2128
2129 odm_slice_dst.x = odm_segment_offset * odm_slice_idx;
2130 odm_slice_dst.width = resource_get_odm_slice_dst_width(otg_master, is_last_odm_slice);
2131 odm_slice_dst.y = 0;
2132 odm_slice_dst.height = stream->timing.v_addressable +
2133 stream->timing.v_border_bottom +
2134 stream->timing.v_border_top;
2135
2136 return odm_slice_dst;
2137 }
2138
resource_get_odm_slice_src_rect(struct pipe_ctx * pipe_ctx)2139 struct rect resource_get_odm_slice_src_rect(struct pipe_ctx *pipe_ctx)
2140 {
2141 struct rect odm_slice_dst;
2142 struct rect odm_slice_src;
2143 struct pipe_ctx *opp_head = resource_get_opp_head(pipe_ctx);
2144 struct output_pixel_processor *opp = opp_head->stream_res.opp;
2145 uint32_t left_edge_extra_pixel_count;
2146
2147 odm_slice_dst = resource_get_odm_slice_dst_rect(opp_head);
2148 odm_slice_src = odm_slice_dst;
2149
2150 if (opp && opp->funcs->opp_get_left_edge_extra_pixel_count)
2151 left_edge_extra_pixel_count =
2152 opp->funcs->opp_get_left_edge_extra_pixel_count(
2153 opp, pipe_ctx->stream->timing.pixel_encoding,
2154 resource_is_pipe_type(opp_head, OTG_MASTER));
2155 else
2156 left_edge_extra_pixel_count = 0;
2157
2158 odm_slice_src.x -= left_edge_extra_pixel_count;
2159 odm_slice_src.width += left_edge_extra_pixel_count;
2160
2161 return odm_slice_src;
2162 }
2163
resource_is_pipe_topology_changed(const struct dc_state * state_a,const struct dc_state * state_b)2164 bool resource_is_pipe_topology_changed(const struct dc_state *state_a,
2165 const struct dc_state *state_b)
2166 {
2167 int i;
2168 const struct pipe_ctx *pipe_a, *pipe_b;
2169
2170 if (state_a->stream_count != state_b->stream_count)
2171 return true;
2172
2173 for (i = 0; i < MAX_PIPES; i++) {
2174 pipe_a = &state_a->res_ctx.pipe_ctx[i];
2175 pipe_b = &state_b->res_ctx.pipe_ctx[i];
2176
2177 if (pipe_a->stream && !pipe_b->stream)
2178 return true;
2179 else if (!pipe_a->stream && pipe_b->stream)
2180 return true;
2181
2182 if (pipe_a->plane_state && !pipe_b->plane_state)
2183 return true;
2184 else if (!pipe_a->plane_state && pipe_b->plane_state)
2185 return true;
2186
2187 if (pipe_a->bottom_pipe && pipe_b->bottom_pipe) {
2188 if (pipe_a->bottom_pipe->pipe_idx != pipe_b->bottom_pipe->pipe_idx)
2189 return true;
2190 if ((pipe_a->bottom_pipe->plane_state == pipe_a->plane_state) &&
2191 (pipe_b->bottom_pipe->plane_state != pipe_b->plane_state))
2192 return true;
2193 else if ((pipe_a->bottom_pipe->plane_state != pipe_a->plane_state) &&
2194 (pipe_b->bottom_pipe->plane_state == pipe_b->plane_state))
2195 return true;
2196 } else if (pipe_a->bottom_pipe || pipe_b->bottom_pipe) {
2197 return true;
2198 }
2199
2200 if (pipe_a->next_odm_pipe && pipe_b->next_odm_pipe) {
2201 if (pipe_a->next_odm_pipe->pipe_idx != pipe_b->next_odm_pipe->pipe_idx)
2202 return true;
2203 } else if (pipe_a->next_odm_pipe || pipe_b->next_odm_pipe) {
2204 return true;
2205 }
2206 }
2207 return false;
2208 }
2209
resource_is_odm_topology_changed(const struct pipe_ctx * otg_master_a,const struct pipe_ctx * otg_master_b)2210 bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a,
2211 const struct pipe_ctx *otg_master_b)
2212 {
2213 const struct pipe_ctx *opp_head_a = otg_master_a;
2214 const struct pipe_ctx *opp_head_b = otg_master_b;
2215
2216 if (!resource_is_pipe_type(otg_master_a, OTG_MASTER) ||
2217 !resource_is_pipe_type(otg_master_b, OTG_MASTER))
2218 return true;
2219
2220 while (opp_head_a && opp_head_b) {
2221 if (opp_head_a->stream_res.opp != opp_head_b->stream_res.opp)
2222 return true;
2223 if ((opp_head_a->next_odm_pipe && !opp_head_b->next_odm_pipe) ||
2224 (!opp_head_a->next_odm_pipe && opp_head_b->next_odm_pipe))
2225 return true;
2226 opp_head_a = opp_head_a->next_odm_pipe;
2227 opp_head_b = opp_head_b->next_odm_pipe;
2228 }
2229
2230 return false;
2231 }
2232
2233 /*
2234 * Sample log:
2235 * pipe topology update
2236 * ________________________
2237 * | plane0 slice0 stream0|
2238 * |DPP0----OPP0----OTG0----| <--- case 0 (OTG master pipe with plane)
2239 * | plane1 | | |
2240 * |DPP1----| | | <--- case 5 (DPP pipe not in last slice)
2241 * | plane0 slice1 | |
2242 * |DPP2----OPP2----| | <--- case 2 (OPP head pipe with plane)
2243 * | plane1 | |
2244 * |DPP3----| | <--- case 4 (DPP pipe in last slice)
2245 * | slice0 stream1|
2246 * |DPG4----OPP4----OTG4----| <--- case 1 (OTG master pipe without plane)
2247 * | slice1 | |
2248 * |DPG5----OPP5----| | <--- case 3 (OPP head pipe without plane)
2249 * |________________________|
2250 */
2251
resource_log_pipe(struct dc * dc,struct pipe_ctx * pipe,int stream_idx,int slice_idx,int plane_idx,int slice_count,bool is_primary)2252 static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,
2253 int stream_idx, int slice_idx, int plane_idx, int slice_count,
2254 bool is_primary)
2255 {
2256 DC_LOGGER_INIT(dc->ctx->logger);
2257
2258 if (slice_idx == 0 && plane_idx == 0 && is_primary) {
2259 /* case 0 (OTG master pipe with plane) */
2260 DC_LOG_DC(" | plane%d slice%d stream%d|",
2261 plane_idx, slice_idx, stream_idx);
2262 DC_LOG_DC(" |DPP%d----OPP%d----OTG%d----|",
2263 pipe->plane_res.dpp->inst,
2264 pipe->stream_res.opp->inst,
2265 pipe->stream_res.tg->inst);
2266 } else if (slice_idx == 0 && plane_idx == -1) {
2267 /* case 1 (OTG master pipe without plane) */
2268 DC_LOG_DC(" | slice%d stream%d|",
2269 slice_idx, stream_idx);
2270 DC_LOG_DC(" |DPG%d----OPP%d----OTG%d----|",
2271 pipe->stream_res.opp->inst,
2272 pipe->stream_res.opp->inst,
2273 pipe->stream_res.tg->inst);
2274 } else if (slice_idx != 0 && plane_idx == 0 && is_primary) {
2275 /* case 2 (OPP head pipe with plane) */
2276 DC_LOG_DC(" | plane%d slice%d | |",
2277 plane_idx, slice_idx);
2278 DC_LOG_DC(" |DPP%d----OPP%d----| |",
2279 pipe->plane_res.dpp->inst,
2280 pipe->stream_res.opp->inst);
2281 } else if (slice_idx != 0 && plane_idx == -1) {
2282 /* case 3 (OPP head pipe without plane) */
2283 DC_LOG_DC(" | slice%d | |", slice_idx);
2284 DC_LOG_DC(" |DPG%d----OPP%d----| |",
2285 pipe->plane_res.dpp->inst,
2286 pipe->stream_res.opp->inst);
2287 } else if (slice_idx == slice_count - 1) {
2288 /* case 4 (DPP pipe in last slice) */
2289 DC_LOG_DC(" | plane%d | |", plane_idx);
2290 DC_LOG_DC(" |DPP%d----| |",
2291 pipe->plane_res.dpp->inst);
2292 } else {
2293 /* case 5 (DPP pipe not in last slice) */
2294 DC_LOG_DC(" | plane%d | | |", plane_idx);
2295 DC_LOG_DC(" |DPP%d----| | |",
2296 pipe->plane_res.dpp->inst);
2297 }
2298 }
2299
resource_log_pipe_for_stream(struct dc * dc,struct dc_state * state,struct pipe_ctx * otg_master,int stream_idx)2300 static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state,
2301 struct pipe_ctx *otg_master, int stream_idx)
2302 {
2303 struct pipe_ctx *opp_heads[MAX_PIPES];
2304 struct pipe_ctx *dpp_pipes[MAX_PIPES];
2305
2306 int slice_idx, dpp_idx, plane_idx, slice_count, dpp_count;
2307 bool is_primary;
2308 DC_LOGGER_INIT(dc->ctx->logger);
2309
2310 slice_count = resource_get_opp_heads_for_otg_master(otg_master,
2311 &state->res_ctx, opp_heads);
2312 for (slice_idx = 0; slice_idx < slice_count; slice_idx++) {
2313 plane_idx = -1;
2314 if (opp_heads[slice_idx]->plane_state) {
2315 dpp_count = resource_get_dpp_pipes_for_opp_head(
2316 opp_heads[slice_idx],
2317 &state->res_ctx,
2318 dpp_pipes);
2319 for (dpp_idx = 0; dpp_idx < dpp_count; dpp_idx++) {
2320 is_primary = !dpp_pipes[dpp_idx]->top_pipe ||
2321 dpp_pipes[dpp_idx]->top_pipe->plane_state != dpp_pipes[dpp_idx]->plane_state;
2322 if (is_primary)
2323 plane_idx++;
2324 resource_log_pipe(dc, dpp_pipes[dpp_idx],
2325 stream_idx, slice_idx,
2326 plane_idx, slice_count,
2327 is_primary);
2328 }
2329 } else {
2330 resource_log_pipe(dc, opp_heads[slice_idx],
2331 stream_idx, slice_idx, plane_idx,
2332 slice_count, true);
2333 }
2334
2335 }
2336 }
2337
resource_stream_to_stream_idx(struct dc_state * state,struct dc_stream_state * stream)2338 static int resource_stream_to_stream_idx(struct dc_state *state,
2339 struct dc_stream_state *stream)
2340 {
2341 int i, stream_idx = -1;
2342
2343 for (i = 0; i < state->stream_count; i++)
2344 if (state->streams[i] == stream) {
2345 stream_idx = i;
2346 break;
2347 }
2348
2349 /* never return negative array index */
2350 if (stream_idx == -1) {
2351 ASSERT(0);
2352 return 0;
2353 }
2354
2355 return stream_idx;
2356 }
2357
resource_log_pipe_topology_update(struct dc * dc,struct dc_state * state)2358 void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)
2359 {
2360 struct pipe_ctx *otg_master;
2361 int stream_idx, phantom_stream_idx;
2362 DC_LOGGER_INIT(dc->ctx->logger);
2363
2364 DC_LOG_DC(" pipe topology update");
2365 DC_LOG_DC(" ________________________");
2366 for (stream_idx = 0; stream_idx < state->stream_count; stream_idx++) {
2367 if (state->streams[stream_idx]->is_phantom)
2368 continue;
2369
2370 otg_master = resource_get_otg_master_for_stream(
2371 &state->res_ctx, state->streams[stream_idx]);
2372
2373 if (!otg_master)
2374 continue;
2375
2376 resource_log_pipe_for_stream(dc, state, otg_master, stream_idx);
2377 }
2378 if (state->phantom_stream_count > 0) {
2379 DC_LOG_DC(" | (phantom pipes) |");
2380 for (stream_idx = 0; stream_idx < state->stream_count; stream_idx++) {
2381 if (state->stream_status[stream_idx].mall_stream_config.type != SUBVP_MAIN)
2382 continue;
2383
2384 phantom_stream_idx = resource_stream_to_stream_idx(state,
2385 state->stream_status[stream_idx].mall_stream_config.paired_stream);
2386 otg_master = resource_get_otg_master_for_stream(
2387 &state->res_ctx, state->streams[phantom_stream_idx]);
2388 if (!otg_master)
2389 continue;
2390
2391 resource_log_pipe_for_stream(dc, state, otg_master, stream_idx);
2392 }
2393 }
2394 DC_LOG_DC(" |________________________|\n");
2395 }
2396
get_tail_pipe(struct pipe_ctx * head_pipe)2397 static struct pipe_ctx *get_tail_pipe(
2398 struct pipe_ctx *head_pipe)
2399 {
2400 struct pipe_ctx *tail_pipe = head_pipe->bottom_pipe;
2401
2402 while (tail_pipe) {
2403 head_pipe = tail_pipe;
2404 tail_pipe = tail_pipe->bottom_pipe;
2405 }
2406
2407 return head_pipe;
2408 }
2409
get_last_opp_head(struct pipe_ctx * opp_head)2410 static struct pipe_ctx *get_last_opp_head(
2411 struct pipe_ctx *opp_head)
2412 {
2413 ASSERT(resource_is_pipe_type(opp_head, OPP_HEAD));
2414 while (opp_head->next_odm_pipe)
2415 opp_head = opp_head->next_odm_pipe;
2416 return opp_head;
2417 }
2418
get_last_dpp_pipe_in_mpcc_combine(struct pipe_ctx * dpp_pipe)2419 static struct pipe_ctx *get_last_dpp_pipe_in_mpcc_combine(
2420 struct pipe_ctx *dpp_pipe)
2421 {
2422 ASSERT(resource_is_pipe_type(dpp_pipe, DPP_PIPE));
2423 while (dpp_pipe->bottom_pipe &&
2424 dpp_pipe->plane_state == dpp_pipe->bottom_pipe->plane_state)
2425 dpp_pipe = dpp_pipe->bottom_pipe;
2426 return dpp_pipe;
2427 }
2428
update_pipe_params_after_odm_slice_count_change(struct pipe_ctx * otg_master,struct dc_state * context,const struct resource_pool * pool)2429 static bool update_pipe_params_after_odm_slice_count_change(
2430 struct pipe_ctx *otg_master,
2431 struct dc_state *context,
2432 const struct resource_pool *pool)
2433 {
2434 int i;
2435 struct pipe_ctx *pipe;
2436 bool result = true;
2437
2438 for (i = 0; i < pool->pipe_count && result; i++) {
2439 pipe = &context->res_ctx.pipe_ctx[i];
2440 if (pipe->stream == otg_master->stream && pipe->plane_state)
2441 result = resource_build_scaling_params(pipe);
2442 }
2443
2444 if (pool->funcs->build_pipe_pix_clk_params)
2445 pool->funcs->build_pipe_pix_clk_params(otg_master);
2446
2447 resource_build_test_pattern_params(&context->res_ctx, otg_master);
2448
2449 return result;
2450 }
2451
update_pipe_params_after_mpc_slice_count_change(const struct dc_plane_state * plane,struct dc_state * context,const struct resource_pool * pool)2452 static bool update_pipe_params_after_mpc_slice_count_change(
2453 const struct dc_plane_state *plane,
2454 struct dc_state *context,
2455 const struct resource_pool *pool)
2456 {
2457 int i;
2458 struct pipe_ctx *pipe;
2459 bool result = true;
2460
2461 for (i = 0; i < pool->pipe_count && result; i++) {
2462 pipe = &context->res_ctx.pipe_ctx[i];
2463 if (pipe->plane_state == plane)
2464 result = resource_build_scaling_params(pipe);
2465 }
2466 return result;
2467 }
2468
acquire_first_split_pipe(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)2469 static int acquire_first_split_pipe(
2470 struct resource_context *res_ctx,
2471 const struct resource_pool *pool,
2472 struct dc_stream_state *stream)
2473 {
2474 int i;
2475
2476 for (i = 0; i < pool->pipe_count; i++) {
2477 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
2478
2479 if (split_pipe->top_pipe &&
2480 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
2481 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
2482 if (split_pipe->bottom_pipe)
2483 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
2484
2485 if (split_pipe->top_pipe->plane_state)
2486 resource_build_scaling_params(split_pipe->top_pipe);
2487
2488 memset(split_pipe, 0, sizeof(*split_pipe));
2489 split_pipe->stream_res.tg = pool->timing_generators[i];
2490 split_pipe->plane_res.hubp = pool->hubps[i];
2491 split_pipe->plane_res.ipp = pool->ipps[i];
2492 split_pipe->plane_res.dpp = pool->dpps[i];
2493 split_pipe->stream_res.opp = pool->opps[i];
2494 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
2495 split_pipe->pipe_idx = i;
2496
2497 split_pipe->stream = stream;
2498 return i;
2499 }
2500 }
2501 return FREE_PIPE_INDEX_NOT_FOUND;
2502 }
2503
update_stream_engine_usage(struct resource_context * res_ctx,const struct resource_pool * pool,struct stream_encoder * stream_enc,bool acquired)2504 static void update_stream_engine_usage(
2505 struct resource_context *res_ctx,
2506 const struct resource_pool *pool,
2507 struct stream_encoder *stream_enc,
2508 bool acquired)
2509 {
2510 int i;
2511
2512 for (i = 0; i < pool->stream_enc_count; i++) {
2513 if (pool->stream_enc[i] == stream_enc)
2514 res_ctx->is_stream_enc_acquired[i] = acquired;
2515 }
2516 }
2517
update_hpo_dp_stream_engine_usage(struct resource_context * res_ctx,const struct resource_pool * pool,struct hpo_dp_stream_encoder * hpo_dp_stream_enc,bool acquired)2518 static void update_hpo_dp_stream_engine_usage(
2519 struct resource_context *res_ctx,
2520 const struct resource_pool *pool,
2521 struct hpo_dp_stream_encoder *hpo_dp_stream_enc,
2522 bool acquired)
2523 {
2524 int i;
2525
2526 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
2527 if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc)
2528 res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired;
2529 }
2530 }
2531
find_acquired_hpo_dp_link_enc_for_link(const struct resource_context * res_ctx,const struct dc_link * link)2532 static inline int find_acquired_hpo_dp_link_enc_for_link(
2533 const struct resource_context *res_ctx,
2534 const struct dc_link *link)
2535 {
2536 int i;
2537
2538 for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++)
2539 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] > 0 &&
2540 res_ctx->hpo_dp_link_enc_to_link_idx[i] == link->link_index)
2541 return i;
2542
2543 return -1;
2544 }
2545
find_free_hpo_dp_link_enc(const struct resource_context * res_ctx,const struct resource_pool * pool)2546 static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx,
2547 const struct resource_pool *pool)
2548 {
2549 int i;
2550
2551 for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++)
2552 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0)
2553 break;
2554
2555 return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) &&
2556 i < pool->hpo_dp_link_enc_count) ? i : -1;
2557 }
2558
acquire_hpo_dp_link_enc(struct resource_context * res_ctx,unsigned int link_index,int enc_index)2559 static inline void acquire_hpo_dp_link_enc(
2560 struct resource_context *res_ctx,
2561 unsigned int link_index,
2562 int enc_index)
2563 {
2564 res_ctx->hpo_dp_link_enc_to_link_idx[enc_index] = link_index;
2565 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] = 1;
2566 }
2567
retain_hpo_dp_link_enc(struct resource_context * res_ctx,int enc_index)2568 static inline void retain_hpo_dp_link_enc(
2569 struct resource_context *res_ctx,
2570 int enc_index)
2571 {
2572 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++;
2573 }
2574
release_hpo_dp_link_enc(struct resource_context * res_ctx,int enc_index)2575 static inline void release_hpo_dp_link_enc(
2576 struct resource_context *res_ctx,
2577 int enc_index)
2578 {
2579 ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0);
2580 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--;
2581 }
2582
add_hpo_dp_link_enc_to_ctx(struct resource_context * res_ctx,const struct resource_pool * pool,struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream)2583 static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
2584 const struct resource_pool *pool,
2585 struct pipe_ctx *pipe_ctx,
2586 struct dc_stream_state *stream)
2587 {
2588 int enc_index;
2589
2590 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
2591
2592 if (enc_index >= 0) {
2593 retain_hpo_dp_link_enc(res_ctx, enc_index);
2594 } else {
2595 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
2596 if (enc_index >= 0)
2597 acquire_hpo_dp_link_enc(res_ctx, stream->link->link_index, enc_index);
2598 }
2599
2600 if (enc_index >= 0)
2601 pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
2602
2603 return pipe_ctx->link_res.hpo_dp_link_enc != NULL;
2604 }
2605
remove_hpo_dp_link_enc_from_ctx(struct resource_context * res_ctx,struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream)2606 static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
2607 struct pipe_ctx *pipe_ctx,
2608 struct dc_stream_state *stream)
2609 {
2610 int enc_index;
2611
2612 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
2613
2614 if (enc_index >= 0) {
2615 release_hpo_dp_link_enc(res_ctx, enc_index);
2616 pipe_ctx->link_res.hpo_dp_link_enc = NULL;
2617 }
2618 }
2619
get_num_of_free_pipes(const struct resource_pool * pool,const struct dc_state * context)2620 static int get_num_of_free_pipes(const struct resource_pool *pool, const struct dc_state *context)
2621 {
2622 int i;
2623 int count = 0;
2624
2625 for (i = 0; i < pool->pipe_count; i++)
2626 if (resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], FREE_PIPE))
2627 count++;
2628 return count;
2629 }
2630
resource_add_otg_master_for_stream_output(struct dc_state * new_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)2631 enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx,
2632 const struct resource_pool *pool,
2633 struct dc_stream_state *stream)
2634 {
2635 struct dc *dc = stream->ctx->dc;
2636
2637 return dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
2638 }
2639
resource_remove_otg_master_for_stream_output(struct dc_state * context,const struct resource_pool * pool,struct dc_stream_state * stream)2640 void resource_remove_otg_master_for_stream_output(struct dc_state *context,
2641 const struct resource_pool *pool,
2642 struct dc_stream_state *stream)
2643 {
2644 struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(
2645 &context->res_ctx, stream);
2646
2647 if (!otg_master)
2648 return;
2649
2650 ASSERT(resource_get_odm_slice_count(otg_master) == 1);
2651 ASSERT(otg_master->plane_state == NULL);
2652 ASSERT(otg_master->stream_res.stream_enc);
2653 update_stream_engine_usage(
2654 &context->res_ctx,
2655 pool,
2656 otg_master->stream_res.stream_enc,
2657 false);
2658
2659 if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master)) {
2660 update_hpo_dp_stream_engine_usage(
2661 &context->res_ctx, pool,
2662 otg_master->stream_res.hpo_dp_stream_enc,
2663 false);
2664 remove_hpo_dp_link_enc_from_ctx(
2665 &context->res_ctx, otg_master, stream);
2666 }
2667 if (otg_master->stream_res.audio)
2668 update_audio_usage(
2669 &context->res_ctx,
2670 pool,
2671 otg_master->stream_res.audio,
2672 false);
2673
2674 resource_unreference_clock_source(&context->res_ctx,
2675 pool,
2676 otg_master->clock_source);
2677
2678 if (pool->funcs->remove_stream_from_ctx)
2679 pool->funcs->remove_stream_from_ctx(
2680 stream->ctx->dc, context, stream);
2681 memset(otg_master, 0, sizeof(*otg_master));
2682 }
2683
2684 /* For each OPP head of an OTG master, add top plane at plane index 0.
2685 *
2686 * In the following example, the stream has 2 ODM slices without a top plane.
2687 * By adding a plane 0 to OPP heads, we are configuring our hardware to render
2688 * plane 0 by using each OPP head's DPP.
2689 *
2690 * Inter-pipe Relation (Before Adding Plane)
2691 * __________________________________________________
2692 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2693 * | | | slice 0 | |
2694 * | 0 | |blank ----ODM----------- |
2695 * | | | slice 1 | | |
2696 * | 1 | |blank ---- | |
2697 * |________|_______________|___________|_____________|
2698 *
2699 * Inter-pipe Relation (After Adding Plane)
2700 * __________________________________________________
2701 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2702 * | | plane 0 | slice 0 | |
2703 * | 0 | -------------------------ODM----------- |
2704 * | | plane 0 | slice 1 | | |
2705 * | 1 | ------------------------- | |
2706 * |________|_______________|___________|_____________|
2707 */
add_plane_to_opp_head_pipes(struct pipe_ctx * otg_master_pipe,struct dc_plane_state * plane_state,struct dc_state * context)2708 static bool add_plane_to_opp_head_pipes(struct pipe_ctx *otg_master_pipe,
2709 struct dc_plane_state *plane_state,
2710 struct dc_state *context)
2711 {
2712 struct pipe_ctx *opp_head_pipe = otg_master_pipe;
2713
2714 while (opp_head_pipe) {
2715 if (opp_head_pipe->plane_state) {
2716 ASSERT(0);
2717 return false;
2718 }
2719 opp_head_pipe->plane_state = plane_state;
2720 opp_head_pipe = opp_head_pipe->next_odm_pipe;
2721 }
2722
2723 return true;
2724 }
2725
2726 /* For each OPP head of an OTG master, acquire a secondary DPP pipe and add
2727 * the plane. So the plane is added to all ODM slices associated with the OTG
2728 * master pipe in the bottom layer.
2729 *
2730 * In the following example, the stream has 2 ODM slices and a top plane 0.
2731 * By acquiring secondary DPP pipes and adding a plane 1, we are configuring our
2732 * hardware to render the plane 1 by acquiring a new pipe for each ODM slice and
2733 * render plane 1 using new pipes' DPP in the Z axis below plane 0.
2734 *
2735 * Inter-pipe Relation (Before Adding Plane)
2736 * __________________________________________________
2737 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2738 * | | plane 0 | slice 0 | |
2739 * | 0 | -------------------------ODM----------- |
2740 * | | plane 0 | slice 1 | | |
2741 * | 1 | ------------------------- | |
2742 * |________|_______________|___________|_____________|
2743 *
2744 * Inter-pipe Relation (After Acquiring and Adding Plane)
2745 * __________________________________________________
2746 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2747 * | | plane 0 | slice 0 | |
2748 * | 0 | -------------MPC---------ODM----------- |
2749 * | | plane 1 | | | | |
2750 * | 2 | ------------- | | | |
2751 * | | plane 0 | slice 1 | | |
2752 * | 1 | -------------MPC--------- | |
2753 * | | plane 1 | | | |
2754 * | 3 | ------------- | | |
2755 * |________|_______________|___________|_____________|
2756 */
acquire_secondary_dpp_pipes_and_add_plane(struct pipe_ctx * otg_master_pipe,struct dc_plane_state * plane_state,struct dc_state * new_ctx,struct dc_state * cur_ctx,struct resource_pool * pool)2757 static bool acquire_secondary_dpp_pipes_and_add_plane(
2758 struct pipe_ctx *otg_master_pipe,
2759 struct dc_plane_state *plane_state,
2760 struct dc_state *new_ctx,
2761 struct dc_state *cur_ctx,
2762 struct resource_pool *pool)
2763 {
2764 struct pipe_ctx *sec_pipe, *tail_pipe;
2765 struct pipe_ctx *opp_heads[MAX_PIPES];
2766 int opp_head_count;
2767 int i;
2768
2769 if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe) {
2770 ASSERT(0);
2771 return false;
2772 }
2773
2774 opp_head_count = resource_get_opp_heads_for_otg_master(otg_master_pipe,
2775 &new_ctx->res_ctx, opp_heads);
2776 if (get_num_of_free_pipes(pool, new_ctx) < opp_head_count)
2777 /* not enough free pipes */
2778 return false;
2779
2780 for (i = 0; i < opp_head_count; i++) {
2781 sec_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
2782 cur_ctx,
2783 new_ctx,
2784 pool,
2785 opp_heads[i]);
2786 ASSERT(sec_pipe);
2787 sec_pipe->plane_state = plane_state;
2788
2789 /* establish pipe relationship */
2790 tail_pipe = get_tail_pipe(opp_heads[i]);
2791 tail_pipe->bottom_pipe = sec_pipe;
2792 sec_pipe->top_pipe = tail_pipe;
2793 sec_pipe->bottom_pipe = NULL;
2794 if (tail_pipe->prev_odm_pipe) {
2795 ASSERT(tail_pipe->prev_odm_pipe->bottom_pipe);
2796 sec_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
2797 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = sec_pipe;
2798 } else {
2799 sec_pipe->prev_odm_pipe = NULL;
2800 }
2801 }
2802 return true;
2803 }
2804
resource_append_dpp_pipes_for_plane_composition(struct dc_state * new_ctx,struct dc_state * cur_ctx,struct resource_pool * pool,struct pipe_ctx * otg_master_pipe,struct dc_plane_state * plane_state)2805 bool resource_append_dpp_pipes_for_plane_composition(
2806 struct dc_state *new_ctx,
2807 struct dc_state *cur_ctx,
2808 struct resource_pool *pool,
2809 struct pipe_ctx *otg_master_pipe,
2810 struct dc_plane_state *plane_state)
2811 {
2812 bool success;
2813
2814 if (otg_master_pipe->plane_state == NULL)
2815 success = add_plane_to_opp_head_pipes(otg_master_pipe,
2816 plane_state, new_ctx);
2817 else
2818 success = acquire_secondary_dpp_pipes_and_add_plane(
2819 otg_master_pipe, plane_state, new_ctx,
2820 cur_ctx, pool);
2821 if (success) {
2822 /* when appending a plane mpc slice count changes from 0 to 1 */
2823 success = update_pipe_params_after_mpc_slice_count_change(
2824 plane_state, new_ctx, pool);
2825 if (!success)
2826 resource_remove_dpp_pipes_for_plane_composition(new_ctx,
2827 pool, plane_state);
2828 }
2829
2830 return success;
2831 }
2832
resource_remove_dpp_pipes_for_plane_composition(struct dc_state * context,const struct resource_pool * pool,const struct dc_plane_state * plane_state)2833 void resource_remove_dpp_pipes_for_plane_composition(
2834 struct dc_state *context,
2835 const struct resource_pool *pool,
2836 const struct dc_plane_state *plane_state)
2837 {
2838 int i;
2839
2840 for (i = pool->pipe_count - 1; i >= 0; i--) {
2841 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2842
2843 if (pipe_ctx->plane_state == plane_state) {
2844 if (pipe_ctx->top_pipe)
2845 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
2846
2847 /* Second condition is to avoid setting NULL to top pipe
2848 * of tail pipe making it look like head pipe in subsequent
2849 * deletes
2850 */
2851 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
2852 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
2853
2854 /*
2855 * For head pipe detach surfaces from pipe for tail
2856 * pipe just zero it out
2857 */
2858 if (!pipe_ctx->top_pipe)
2859 pipe_ctx->plane_state = NULL;
2860 else
2861 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
2862 }
2863 }
2864 }
2865
2866 /*
2867 * Increase ODM slice count by 1 by acquiring pipes and adding a new ODM slice
2868 * at the last index.
2869 * return - true if a new ODM slice is added and required pipes are acquired.
2870 * false if new_ctx is no longer a valid state after new ODM slice is added.
2871 *
2872 * This is achieved by duplicating MPC blending tree from previous ODM slice.
2873 * In the following example, we have a single MPC tree and 1 ODM slice 0. We
2874 * want to add a new odm slice by duplicating the MPC blending tree and add
2875 * ODM slice 1.
2876 *
2877 * Inter-pipe Relation (Before Acquiring and Adding ODM Slice)
2878 * __________________________________________________
2879 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2880 * | | plane 0 | slice 0 | |
2881 * | 0 | -------------MPC---------ODM----------- |
2882 * | | plane 1 | | | |
2883 * | 1 | ------------- | | |
2884 * |________|_______________|___________|_____________|
2885 *
2886 * Inter-pipe Relation (After Acquiring and Adding ODM Slice)
2887 * __________________________________________________
2888 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2889 * | | plane 0 | slice 0 | |
2890 * | 0 | -------------MPC---------ODM----------- |
2891 * | | plane 1 | | | | |
2892 * | 1 | ------------- | | | |
2893 * | | plane 0 | slice 1 | | |
2894 * | 2 | -------------MPC--------- | |
2895 * | | plane 1 | | | |
2896 * | 3 | ------------- | | |
2897 * |________|_______________|___________|_____________|
2898 */
acquire_pipes_and_add_odm_slice(struct pipe_ctx * otg_master_pipe,struct dc_state * new_ctx,const struct dc_state * cur_ctx,const struct resource_pool * pool)2899 static bool acquire_pipes_and_add_odm_slice(
2900 struct pipe_ctx *otg_master_pipe,
2901 struct dc_state *new_ctx,
2902 const struct dc_state *cur_ctx,
2903 const struct resource_pool *pool)
2904 {
2905 struct pipe_ctx *last_opp_head = get_last_opp_head(otg_master_pipe);
2906 struct pipe_ctx *new_opp_head;
2907 struct pipe_ctx *last_top_dpp_pipe, *last_bottom_dpp_pipe,
2908 *new_top_dpp_pipe, *new_bottom_dpp_pipe;
2909
2910 if (!pool->funcs->acquire_free_pipe_as_secondary_opp_head) {
2911 ASSERT(0);
2912 return false;
2913 }
2914 new_opp_head = pool->funcs->acquire_free_pipe_as_secondary_opp_head(
2915 cur_ctx, new_ctx, pool,
2916 otg_master_pipe);
2917 if (!new_opp_head)
2918 return false;
2919
2920 last_opp_head->next_odm_pipe = new_opp_head;
2921 new_opp_head->prev_odm_pipe = last_opp_head;
2922 new_opp_head->next_odm_pipe = NULL;
2923 new_opp_head->plane_state = last_opp_head->plane_state;
2924 last_top_dpp_pipe = last_opp_head;
2925 new_top_dpp_pipe = new_opp_head;
2926
2927 while (last_top_dpp_pipe->bottom_pipe) {
2928 last_bottom_dpp_pipe = last_top_dpp_pipe->bottom_pipe;
2929 new_bottom_dpp_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
2930 cur_ctx, new_ctx, pool,
2931 new_opp_head);
2932 if (!new_bottom_dpp_pipe)
2933 return false;
2934
2935 new_bottom_dpp_pipe->plane_state = last_bottom_dpp_pipe->plane_state;
2936 new_top_dpp_pipe->bottom_pipe = new_bottom_dpp_pipe;
2937 new_bottom_dpp_pipe->top_pipe = new_top_dpp_pipe;
2938 last_bottom_dpp_pipe->next_odm_pipe = new_bottom_dpp_pipe;
2939 new_bottom_dpp_pipe->prev_odm_pipe = last_bottom_dpp_pipe;
2940 new_bottom_dpp_pipe->next_odm_pipe = NULL;
2941 last_top_dpp_pipe = last_bottom_dpp_pipe;
2942 }
2943
2944 return true;
2945 }
2946
2947 /*
2948 * Decrease ODM slice count by 1 by releasing pipes and removing the ODM slice
2949 * at the last index.
2950 * return - true if the last ODM slice is removed and related pipes are
2951 * released. false if there is no removable ODM slice.
2952 *
2953 * In the following example, we have 2 MPC trees and ODM slice 0 and slice 1.
2954 * We want to remove the last ODM i.e slice 1. We are releasing secondary DPP
2955 * pipe 3 and OPP head pipe 2.
2956 *
2957 * Inter-pipe Relation (Before Releasing and Removing ODM Slice)
2958 * __________________________________________________
2959 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2960 * | | plane 0 | slice 0 | |
2961 * | 0 | -------------MPC---------ODM----------- |
2962 * | | plane 1 | | | | |
2963 * | 1 | ------------- | | | |
2964 * | | plane 0 | slice 1 | | |
2965 * | 2 | -------------MPC--------- | |
2966 * | | plane 1 | | | |
2967 * | 3 | ------------- | | |
2968 * |________|_______________|___________|_____________|
2969 *
2970 * Inter-pipe Relation (After Releasing and Removing ODM Slice)
2971 * __________________________________________________
2972 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
2973 * | | plane 0 | slice 0 | |
2974 * | 0 | -------------MPC---------ODM----------- |
2975 * | | plane 1 | | | |
2976 * | 1 | ------------- | | |
2977 * |________|_______________|___________|_____________|
2978 */
release_pipes_and_remove_odm_slice(struct pipe_ctx * otg_master_pipe,struct dc_state * context,const struct resource_pool * pool)2979 static bool release_pipes_and_remove_odm_slice(
2980 struct pipe_ctx *otg_master_pipe,
2981 struct dc_state *context,
2982 const struct resource_pool *pool)
2983 {
2984 struct pipe_ctx *last_opp_head = get_last_opp_head(otg_master_pipe);
2985 struct pipe_ctx *tail_pipe = get_tail_pipe(last_opp_head);
2986
2987 if (!pool->funcs->release_pipe) {
2988 ASSERT(0);
2989 return false;
2990 }
2991
2992 if (resource_is_pipe_type(last_opp_head, OTG_MASTER))
2993 return false;
2994
2995 while (tail_pipe->top_pipe) {
2996 tail_pipe->prev_odm_pipe->next_odm_pipe = NULL;
2997 tail_pipe = tail_pipe->top_pipe;
2998 pool->funcs->release_pipe(context, tail_pipe->bottom_pipe, pool);
2999 tail_pipe->bottom_pipe = NULL;
3000 }
3001 last_opp_head->prev_odm_pipe->next_odm_pipe = NULL;
3002 pool->funcs->release_pipe(context, last_opp_head, pool);
3003
3004 return true;
3005 }
3006
3007 /*
3008 * Increase MPC slice count by 1 by acquiring a new DPP pipe and add it as the
3009 * last MPC slice of the plane associated with dpp_pipe.
3010 *
3011 * return - true if a new MPC slice is added and required pipes are acquired.
3012 * false if new_ctx is no longer a valid state after new MPC slice is added.
3013 *
3014 * In the following example, we add a new MPC slice for plane 0 into the
3015 * new_ctx. To do so we pass pipe 0 as dpp_pipe. The function acquires a new DPP
3016 * pipe 2 for plane 0 as the bottom most pipe for plane 0.
3017 *
3018 * Inter-pipe Relation (Before Acquiring and Adding MPC Slice)
3019 * __________________________________________________
3020 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
3021 * | | plane 0 | | |
3022 * | 0 | -------------MPC----------------------- |
3023 * | | plane 1 | | | |
3024 * | 1 | ------------- | | |
3025 * |________|_______________|___________|_____________|
3026 *
3027 * Inter-pipe Relation (After Acquiring and Adding MPC Slice)
3028 * __________________________________________________
3029 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
3030 * | | plane 0 | | |
3031 * | 0 | -------------MPC----------------------- |
3032 * | | plane 0 | | | |
3033 * | 2 | ------------- | | |
3034 * | | plane 1 | | | |
3035 * | 1 | ------------- | | |
3036 * |________|_______________|___________|_____________|
3037 */
acquire_dpp_pipe_and_add_mpc_slice(struct pipe_ctx * dpp_pipe,struct dc_state * new_ctx,const struct dc_state * cur_ctx,const struct resource_pool * pool)3038 static bool acquire_dpp_pipe_and_add_mpc_slice(
3039 struct pipe_ctx *dpp_pipe,
3040 struct dc_state *new_ctx,
3041 const struct dc_state *cur_ctx,
3042 const struct resource_pool *pool)
3043 {
3044 struct pipe_ctx *last_dpp_pipe =
3045 get_last_dpp_pipe_in_mpcc_combine(dpp_pipe);
3046 struct pipe_ctx *opp_head = resource_get_opp_head(dpp_pipe);
3047 struct pipe_ctx *new_dpp_pipe;
3048
3049 if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe) {
3050 ASSERT(0);
3051 return false;
3052 }
3053 new_dpp_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
3054 cur_ctx, new_ctx, pool, opp_head);
3055 if (!new_dpp_pipe || resource_get_odm_slice_count(dpp_pipe) > 1)
3056 return false;
3057
3058 new_dpp_pipe->bottom_pipe = last_dpp_pipe->bottom_pipe;
3059 if (new_dpp_pipe->bottom_pipe)
3060 new_dpp_pipe->bottom_pipe->top_pipe = new_dpp_pipe;
3061 new_dpp_pipe->top_pipe = last_dpp_pipe;
3062 last_dpp_pipe->bottom_pipe = new_dpp_pipe;
3063 new_dpp_pipe->plane_state = last_dpp_pipe->plane_state;
3064
3065 return true;
3066 }
3067
3068 /*
3069 * Reduce MPC slice count by 1 by releasing the bottom DPP pipe in MPCC combine
3070 * with dpp_pipe and removing last MPC slice of the plane associated with
3071 * dpp_pipe.
3072 *
3073 * return - true if the last MPC slice of the plane associated with dpp_pipe is
3074 * removed and last DPP pipe in MPCC combine with dpp_pipe is released.
3075 * false if there is no removable MPC slice.
3076 *
3077 * In the following example, we remove an MPC slice for plane 0 from the
3078 * context. To do so we pass pipe 0 as dpp_pipe. The function releases pipe 1 as
3079 * it is the last pipe for plane 0.
3080 *
3081 * Inter-pipe Relation (Before Releasing and Removing MPC Slice)
3082 * __________________________________________________
3083 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
3084 * | | plane 0 | | |
3085 * | 0 | -------------MPC----------------------- |
3086 * | | plane 0 | | | |
3087 * | 1 | ------------- | | |
3088 * | | plane 1 | | | |
3089 * | 2 | ------------- | | |
3090 * |________|_______________|___________|_____________|
3091 *
3092 * Inter-pipe Relation (After Releasing and Removing MPC Slice)
3093 * __________________________________________________
3094 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
3095 * | | plane 0 | | |
3096 * | 0 | -------------MPC----------------------- |
3097 * | | plane 1 | | | |
3098 * | 2 | ------------- | | |
3099 * |________|_______________|___________|_____________|
3100 */
release_dpp_pipe_and_remove_mpc_slice(struct pipe_ctx * dpp_pipe,struct dc_state * context,const struct resource_pool * pool)3101 static bool release_dpp_pipe_and_remove_mpc_slice(
3102 struct pipe_ctx *dpp_pipe,
3103 struct dc_state *context,
3104 const struct resource_pool *pool)
3105 {
3106 struct pipe_ctx *last_dpp_pipe =
3107 get_last_dpp_pipe_in_mpcc_combine(dpp_pipe);
3108
3109 if (!pool->funcs->release_pipe) {
3110 ASSERT(0);
3111 return false;
3112 }
3113
3114 if (resource_is_pipe_type(last_dpp_pipe, OPP_HEAD) ||
3115 resource_get_odm_slice_count(dpp_pipe) > 1)
3116 return false;
3117
3118 last_dpp_pipe->top_pipe->bottom_pipe = last_dpp_pipe->bottom_pipe;
3119 if (last_dpp_pipe->bottom_pipe)
3120 last_dpp_pipe->bottom_pipe->top_pipe = last_dpp_pipe->top_pipe;
3121 pool->funcs->release_pipe(context, last_dpp_pipe, pool);
3122
3123 return true;
3124 }
3125
resource_update_pipes_for_stream_with_slice_count(struct dc_state * new_ctx,const struct dc_state * cur_ctx,const struct resource_pool * pool,const struct dc_stream_state * stream,int new_slice_count)3126 bool resource_update_pipes_for_stream_with_slice_count(
3127 struct dc_state *new_ctx,
3128 const struct dc_state *cur_ctx,
3129 const struct resource_pool *pool,
3130 const struct dc_stream_state *stream,
3131 int new_slice_count)
3132 {
3133 int i;
3134 struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(
3135 &new_ctx->res_ctx, stream);
3136 int cur_slice_count;
3137 bool result = true;
3138
3139 if (!otg_master)
3140 return false;
3141
3142 cur_slice_count = resource_get_odm_slice_count(otg_master);
3143
3144 if (new_slice_count == cur_slice_count)
3145 return result;
3146
3147 if (new_slice_count > cur_slice_count)
3148 for (i = 0; i < new_slice_count - cur_slice_count && result; i++)
3149 result = acquire_pipes_and_add_odm_slice(
3150 otg_master, new_ctx, cur_ctx, pool);
3151 else
3152 for (i = 0; i < cur_slice_count - new_slice_count && result; i++)
3153 result = release_pipes_and_remove_odm_slice(
3154 otg_master, new_ctx, pool);
3155 if (result)
3156 result = update_pipe_params_after_odm_slice_count_change(
3157 otg_master, new_ctx, pool);
3158 return result;
3159 }
3160
resource_update_pipes_for_plane_with_slice_count(struct dc_state * new_ctx,const struct dc_state * cur_ctx,const struct resource_pool * pool,const struct dc_plane_state * plane,int new_slice_count)3161 bool resource_update_pipes_for_plane_with_slice_count(
3162 struct dc_state *new_ctx,
3163 const struct dc_state *cur_ctx,
3164 const struct resource_pool *pool,
3165 const struct dc_plane_state *plane,
3166 int new_slice_count)
3167 {
3168 int i;
3169 int dpp_pipe_count;
3170 int cur_slice_count;
3171 struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};
3172 bool result = true;
3173
3174 dpp_pipe_count = resource_get_dpp_pipes_for_plane(plane,
3175 &new_ctx->res_ctx, dpp_pipes);
3176 ASSERT(dpp_pipe_count > 0);
3177 cur_slice_count = resource_get_mpc_slice_count(dpp_pipes[0]);
3178
3179 if (new_slice_count == cur_slice_count)
3180 return result;
3181
3182 if (new_slice_count > cur_slice_count)
3183 for (i = 0; i < new_slice_count - cur_slice_count && result; i++)
3184 result = acquire_dpp_pipe_and_add_mpc_slice(
3185 dpp_pipes[0], new_ctx, cur_ctx, pool);
3186 else
3187 for (i = 0; i < cur_slice_count - new_slice_count && result; i++)
3188 result = release_dpp_pipe_and_remove_mpc_slice(
3189 dpp_pipes[0], new_ctx, pool);
3190 if (result)
3191 result = update_pipe_params_after_mpc_slice_count_change(
3192 dpp_pipes[0]->plane_state, new_ctx, pool);
3193 return result;
3194 }
3195
dc_is_timing_changed(struct dc_stream_state * cur_stream,struct dc_stream_state * new_stream)3196 bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
3197 struct dc_stream_state *new_stream)
3198 {
3199 if (cur_stream == NULL)
3200 return true;
3201
3202 /* If output color space is changed, need to reprogram info frames */
3203 if (cur_stream->output_color_space != new_stream->output_color_space)
3204 return true;
3205
3206 return memcmp(
3207 &cur_stream->timing,
3208 &new_stream->timing,
3209 sizeof(struct dc_crtc_timing)) != 0;
3210 }
3211
are_stream_backends_same(struct dc_stream_state * stream_a,struct dc_stream_state * stream_b)3212 static bool are_stream_backends_same(
3213 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
3214 {
3215 if (stream_a == stream_b)
3216 return true;
3217
3218 if (stream_a == NULL || stream_b == NULL)
3219 return false;
3220
3221 if (dc_is_timing_changed(stream_a, stream_b))
3222 return false;
3223
3224 if (stream_a->signal != stream_b->signal)
3225 return false;
3226
3227 if (stream_a->dpms_off != stream_b->dpms_off)
3228 return false;
3229
3230 return true;
3231 }
3232
3233 /*
3234 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
3235 *
3236 * Checks if there a difference between the two states
3237 * that would require a mode change.
3238 *
3239 * Does not compare cursor position or attributes.
3240 */
dc_is_stream_unchanged(struct dc_stream_state * old_stream,struct dc_stream_state * stream)3241 bool dc_is_stream_unchanged(
3242 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
3243 {
3244 if (!old_stream || !stream)
3245 return false;
3246
3247 if (!are_stream_backends_same(old_stream, stream))
3248 return false;
3249
3250 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
3251 return false;
3252
3253 /*compare audio info*/
3254 if (memcmp(&old_stream->audio_info, &stream->audio_info, sizeof(stream->audio_info)) != 0)
3255 return false;
3256
3257 return true;
3258 }
3259
3260 /*
3261 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
3262 */
dc_is_stream_scaling_unchanged(struct dc_stream_state * old_stream,struct dc_stream_state * stream)3263 bool dc_is_stream_scaling_unchanged(struct dc_stream_state *old_stream,
3264 struct dc_stream_state *stream)
3265 {
3266 if (old_stream == stream)
3267 return true;
3268
3269 if (old_stream == NULL || stream == NULL)
3270 return false;
3271
3272 if (memcmp(&old_stream->src,
3273 &stream->src,
3274 sizeof(struct rect)) != 0)
3275 return false;
3276
3277 if (memcmp(&old_stream->dst,
3278 &stream->dst,
3279 sizeof(struct rect)) != 0)
3280 return false;
3281
3282 return true;
3283 }
3284
3285 /* TODO: release audio object */
update_audio_usage(struct resource_context * res_ctx,const struct resource_pool * pool,struct audio * audio,bool acquired)3286 void update_audio_usage(
3287 struct resource_context *res_ctx,
3288 const struct resource_pool *pool,
3289 struct audio *audio,
3290 bool acquired)
3291 {
3292 int i;
3293 for (i = 0; i < pool->audio_count; i++) {
3294 if (pool->audios[i] == audio)
3295 res_ctx->is_audio_acquired[i] = acquired;
3296 }
3297 }
3298
find_first_free_match_hpo_dp_stream_enc_for_link(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)3299 static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for_link(
3300 struct resource_context *res_ctx,
3301 const struct resource_pool *pool,
3302 struct dc_stream_state *stream)
3303 {
3304 int i;
3305
3306 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
3307 if (!res_ctx->is_hpo_dp_stream_enc_acquired[i] &&
3308 pool->hpo_dp_stream_enc[i]) {
3309
3310 return pool->hpo_dp_stream_enc[i];
3311 }
3312 }
3313
3314 return NULL;
3315 }
3316
find_first_free_audio(struct resource_context * res_ctx,const struct resource_pool * pool,enum engine_id id,enum dce_version dc_version)3317 static struct audio *find_first_free_audio(
3318 struct resource_context *res_ctx,
3319 const struct resource_pool *pool,
3320 enum engine_id id,
3321 enum dce_version dc_version)
3322 {
3323 int i, available_audio_count;
3324
3325 if (id == ENGINE_ID_UNKNOWN)
3326 return NULL;
3327
3328 available_audio_count = pool->audio_count;
3329
3330 for (i = 0; i < available_audio_count; i++) {
3331 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
3332 /*we have enough audio endpoint, find the matching inst*/
3333 if (id != i)
3334 continue;
3335 return pool->audios[i];
3336 }
3337 }
3338
3339 /* use engine id to find free audio */
3340 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
3341 return pool->audios[id];
3342 }
3343 /*not found the matching one, first come first serve*/
3344 for (i = 0; i < available_audio_count; i++) {
3345 if (res_ctx->is_audio_acquired[i] == false) {
3346 return pool->audios[i];
3347 }
3348 }
3349 return NULL;
3350 }
3351
find_pll_sharable_stream(struct dc_stream_state * stream_needs_pll,struct dc_state * context)3352 static struct dc_stream_state *find_pll_sharable_stream(
3353 struct dc_stream_state *stream_needs_pll,
3354 struct dc_state *context)
3355 {
3356 int i;
3357
3358 for (i = 0; i < context->stream_count; i++) {
3359 struct dc_stream_state *stream_has_pll = context->streams[i];
3360
3361 /* We are looking for non dp, non virtual stream */
3362 if (resource_are_streams_timing_synchronizable(
3363 stream_needs_pll, stream_has_pll)
3364 && !dc_is_dp_signal(stream_has_pll->signal)
3365 && stream_has_pll->link->connector_signal
3366 != SIGNAL_TYPE_VIRTUAL)
3367 return stream_has_pll;
3368
3369 }
3370
3371 return NULL;
3372 }
3373
get_norm_pix_clk(const struct dc_crtc_timing * timing)3374 static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
3375 {
3376 uint32_t pix_clk = timing->pix_clk_100hz;
3377 uint32_t normalized_pix_clk = pix_clk;
3378
3379 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3380 pix_clk /= 2;
3381 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
3382 switch (timing->display_color_depth) {
3383 case COLOR_DEPTH_666:
3384 case COLOR_DEPTH_888:
3385 normalized_pix_clk = pix_clk;
3386 break;
3387 case COLOR_DEPTH_101010:
3388 normalized_pix_clk = (pix_clk * 30) / 24;
3389 break;
3390 case COLOR_DEPTH_121212:
3391 normalized_pix_clk = (pix_clk * 36) / 24;
3392 break;
3393 case COLOR_DEPTH_141414:
3394 normalized_pix_clk = (pix_clk * 42) / 24;
3395 break;
3396 case COLOR_DEPTH_161616:
3397 normalized_pix_clk = (pix_clk * 48) / 24;
3398 break;
3399 default:
3400 ASSERT(0);
3401 break;
3402 }
3403 }
3404 return normalized_pix_clk;
3405 }
3406
calculate_phy_pix_clks(struct dc_stream_state * stream)3407 static void calculate_phy_pix_clks(struct dc_stream_state *stream)
3408 {
3409 /* update actual pixel clock on all streams */
3410 if (dc_is_hdmi_signal(stream->signal))
3411 stream->phy_pix_clk = get_norm_pix_clk(
3412 &stream->timing) / 10;
3413 else
3414 stream->phy_pix_clk =
3415 stream->timing.pix_clk_100hz / 10;
3416
3417 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
3418 stream->phy_pix_clk *= 2;
3419 }
3420
acquire_resource_from_hw_enabled_state(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)3421 static int acquire_resource_from_hw_enabled_state(
3422 struct resource_context *res_ctx,
3423 const struct resource_pool *pool,
3424 struct dc_stream_state *stream)
3425 {
3426 struct dc_link *link = stream->link;
3427 unsigned int i, inst, tg_inst = 0;
3428 uint32_t numPipes = 1;
3429 uint32_t id_src[4] = {0};
3430
3431 /* Check for enabled DIG to identify enabled display */
3432 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
3433 return -1;
3434
3435 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
3436
3437 if (inst == ENGINE_ID_UNKNOWN)
3438 return -1;
3439
3440 for (i = 0; i < pool->stream_enc_count; i++) {
3441 if (pool->stream_enc[i]->id == inst) {
3442 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
3443 pool->stream_enc[i]);
3444 break;
3445 }
3446 }
3447
3448 // tg_inst not found
3449 if (i == pool->stream_enc_count)
3450 return -1;
3451
3452 if (tg_inst >= pool->timing_generator_count)
3453 return -1;
3454
3455 if (!res_ctx->pipe_ctx[tg_inst].stream) {
3456 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
3457
3458 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
3459 id_src[0] = tg_inst;
3460
3461 if (pipe_ctx->stream_res.tg->funcs->get_optc_source)
3462 pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,
3463 &numPipes, &id_src[0], &id_src[1]);
3464
3465 if (id_src[0] == 0xf && id_src[1] == 0xf) {
3466 id_src[0] = tg_inst;
3467 numPipes = 1;
3468 }
3469
3470 for (i = 0; i < numPipes; i++) {
3471 //Check if src id invalid
3472 if (id_src[i] == 0xf)
3473 return -1;
3474
3475 pipe_ctx = &res_ctx->pipe_ctx[id_src[i]];
3476
3477 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
3478 pipe_ctx->plane_res.mi = pool->mis[id_src[i]];
3479 pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];
3480 pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]];
3481 pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]];
3482 pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];
3483 pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
3484
3485 if (pool->dpps[id_src[i]]) {
3486 pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;
3487
3488 if (pool->mpc->funcs->read_mpcc_state) {
3489 struct mpcc_state s = {0};
3490
3491 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
3492
3493 if (s.dpp_id < MAX_MPCC)
3494 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =
3495 s.dpp_id;
3496
3497 if (s.bot_mpcc_id < MAX_MPCC)
3498 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
3499 &pool->mpc->mpcc_array[s.bot_mpcc_id];
3500
3501 if (s.opp_id < MAX_OPP)
3502 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
3503 }
3504 }
3505 pipe_ctx->pipe_idx = id_src[i];
3506
3507 if (id_src[i] >= pool->timing_generator_count) {
3508 id_src[i] = pool->timing_generator_count - 1;
3509
3510 pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];
3511 pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
3512 }
3513
3514 pipe_ctx->stream = stream;
3515 }
3516
3517 if (numPipes == 2) {
3518 stream->apply_boot_odm_mode = dm_odm_combine_policy_2to1;
3519 res_ctx->pipe_ctx[id_src[0]].next_odm_pipe = &res_ctx->pipe_ctx[id_src[1]];
3520 res_ctx->pipe_ctx[id_src[0]].prev_odm_pipe = NULL;
3521 res_ctx->pipe_ctx[id_src[1]].next_odm_pipe = NULL;
3522 res_ctx->pipe_ctx[id_src[1]].prev_odm_pipe = &res_ctx->pipe_ctx[id_src[0]];
3523 } else
3524 stream->apply_boot_odm_mode = dm_odm_combine_mode_disabled;
3525
3526 return id_src[0];
3527 }
3528
3529 return -1;
3530 }
3531
mark_seamless_boot_stream(const struct dc * dc,struct dc_stream_state * stream)3532 static void mark_seamless_boot_stream(
3533 const struct dc *dc,
3534 struct dc_stream_state *stream)
3535 {
3536 struct dc_bios *dcb = dc->ctx->dc_bios;
3537
3538 if (dc->config.allow_seamless_boot_optimization &&
3539 !dcb->funcs->is_accelerated_mode(dcb)) {
3540 if (dc_validate_boot_timing(dc, stream->sink, &stream->timing))
3541 stream->apply_seamless_boot_optimization = true;
3542 }
3543 }
3544
3545 /*
3546 * Acquire a pipe as OTG master and assign to the stream in new dc context.
3547 * return - true if OTG master pipe is acquired and new dc context is updated.
3548 * false if it fails to acquire an OTG master pipe for this stream.
3549 *
3550 * In the example below, we acquired pipe 0 as OTG master pipe for the stream.
3551 * After the function its Inter-pipe Relation is represented by the diagram
3552 * below.
3553 *
3554 * Inter-pipe Relation
3555 * __________________________________________________
3556 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
3557 * | | | | |
3558 * | 0 | |blank ------------------ |
3559 * |________|_______________|___________|_____________|
3560 */
acquire_otg_master_pipe_for_stream(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)3561 static bool acquire_otg_master_pipe_for_stream(
3562 const struct dc_state *cur_ctx,
3563 struct dc_state *new_ctx,
3564 const struct resource_pool *pool,
3565 struct dc_stream_state *stream)
3566 {
3567 /* TODO: Move this function to DCN specific resource file and acquire
3568 * DSC resource here. The reason is that the function should have the
3569 * same level of responsibility as when we acquire secondary OPP head.
3570 * We acquire DSC when we acquire secondary OPP head, so we should
3571 * acquire DSC when we acquire OTG master.
3572 */
3573 int pipe_idx;
3574 struct pipe_ctx *pipe_ctx = NULL;
3575
3576 /*
3577 * Upper level code is responsible to optimize unnecessary addition and
3578 * removal for unchanged streams. So unchanged stream will keep the same
3579 * OTG master instance allocated. When current stream is removed and a
3580 * new stream is added, we want to reuse the OTG instance made available
3581 * by the removed stream first. If not found, we try to avoid of using
3582 * any free pipes already used in current context as this could tear
3583 * down exiting ODM/MPC/MPO configuration unnecessarily.
3584 */
3585
3586 /*
3587 * Try to acquire the same OTG master already in use. This is not
3588 * optimal because resetting an enabled OTG master pipe for a new stream
3589 * requires an extra frame of wait. However there are test automation
3590 * and eDP assumptions that rely on reusing the same OTG master pipe
3591 * during mode change. We have to keep this logic as is for now.
3592 */
3593 pipe_idx = recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx(
3594 &cur_ctx->res_ctx, &new_ctx->res_ctx, pool);
3595 /*
3596 * Try to acquire a pipe not used in current resource context to avoid
3597 * pipe swapping.
3598 */
3599 if (pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
3600 pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(
3601 &cur_ctx->res_ctx, &new_ctx->res_ctx, pool);
3602 /*
3603 * If pipe swapping is unavoidable, try to acquire pipe used as
3604 * secondary DPP pipe in current state as we prioritize to support more
3605 * streams over supporting MPO planes.
3606 */
3607 if (pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
3608 pipe_idx = resource_find_free_pipe_used_as_cur_sec_dpp(
3609 &cur_ctx->res_ctx, &new_ctx->res_ctx, pool);
3610 if (pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
3611 pipe_idx = resource_find_any_free_pipe(&new_ctx->res_ctx, pool);
3612 if (pipe_idx != FREE_PIPE_INDEX_NOT_FOUND) {
3613 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[pipe_idx];
3614 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
3615 pipe_ctx->pipe_idx = pipe_idx;
3616 pipe_ctx->stream_res.tg = pool->timing_generators[pipe_idx];
3617 pipe_ctx->plane_res.mi = pool->mis[pipe_idx];
3618 pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];
3619 pipe_ctx->plane_res.ipp = pool->ipps[pipe_idx];
3620 pipe_ctx->plane_res.xfm = pool->transforms[pipe_idx];
3621 pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];
3622 pipe_ctx->stream_res.opp = pool->opps[pipe_idx];
3623 if (pool->dpps[pipe_idx])
3624 pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
3625
3626 if (pipe_idx >= pool->timing_generator_count && pool->timing_generator_count != 0) {
3627 int tg_inst = pool->timing_generator_count - 1;
3628
3629 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
3630 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
3631 }
3632
3633 pipe_ctx->stream = stream;
3634 } else {
3635 pipe_idx = acquire_first_split_pipe(&new_ctx->res_ctx, pool, stream);
3636 }
3637
3638 return pipe_idx != FREE_PIPE_INDEX_NOT_FOUND;
3639 }
3640
resource_map_pool_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)3641 enum dc_status resource_map_pool_resources(
3642 const struct dc *dc,
3643 struct dc_state *context,
3644 struct dc_stream_state *stream)
3645 {
3646 const struct resource_pool *pool = dc->res_pool;
3647 int i;
3648 struct dc_context *dc_ctx = dc->ctx;
3649 struct pipe_ctx *pipe_ctx = NULL;
3650 int pipe_idx = -1;
3651 bool acquired = false;
3652
3653 calculate_phy_pix_clks(stream);
3654
3655 mark_seamless_boot_stream(dc, stream);
3656
3657 if (stream->apply_seamless_boot_optimization) {
3658 pipe_idx = acquire_resource_from_hw_enabled_state(
3659 &context->res_ctx,
3660 pool,
3661 stream);
3662 if (pipe_idx < 0)
3663 /* hw resource was assigned to other stream */
3664 stream->apply_seamless_boot_optimization = false;
3665 else
3666 acquired = true;
3667 }
3668
3669 if (!acquired)
3670 /* acquire new resources */
3671 acquired = acquire_otg_master_pipe_for_stream(dc->current_state,
3672 context, pool, stream);
3673
3674 pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
3675
3676 if (!pipe_ctx || pipe_ctx->stream_res.tg == NULL)
3677 return DC_NO_CONTROLLER_RESOURCE;
3678
3679 pipe_ctx->stream_res.stream_enc =
3680 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
3681 &context->res_ctx, pool, stream);
3682
3683 if (!pipe_ctx->stream_res.stream_enc)
3684 return DC_NO_STREAM_ENC_RESOURCE;
3685
3686 update_stream_engine_usage(
3687 &context->res_ctx, pool,
3688 pipe_ctx->stream_res.stream_enc,
3689 true);
3690
3691 /* Allocate DP HPO Stream Encoder based on signal, hw capabilities
3692 * and link settings
3693 */
3694 if (dc_is_dp_signal(stream->signal) ||
3695 dc_is_virtual_signal(stream->signal)) {
3696 if (!dc->link_srv->dp_decide_link_settings(stream,
3697 &pipe_ctx->link_config.dp_link_settings))
3698 return DC_FAIL_DP_LINK_BANDWIDTH;
3699 if (dc->link_srv->dp_get_encoding_format(
3700 &pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {
3701 pipe_ctx->stream_res.hpo_dp_stream_enc =
3702 find_first_free_match_hpo_dp_stream_enc_for_link(
3703 &context->res_ctx, pool, stream);
3704
3705 if (!pipe_ctx->stream_res.hpo_dp_stream_enc)
3706 return DC_NO_STREAM_ENC_RESOURCE;
3707
3708 update_hpo_dp_stream_engine_usage(
3709 &context->res_ctx, pool,
3710 pipe_ctx->stream_res.hpo_dp_stream_enc,
3711 true);
3712 if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream))
3713 return DC_NO_LINK_ENC_RESOURCE;
3714 }
3715 }
3716
3717 /* TODO: Add check if ASIC support and EDID audio */
3718 if (!stream->converter_disable_audio &&
3719 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
3720 stream->audio_info.mode_count && stream->audio_info.flags.all) {
3721 pipe_ctx->stream_res.audio = find_first_free_audio(
3722 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
3723
3724 /*
3725 * Audio assigned in order first come first get.
3726 * There are asics which has number of audio
3727 * resources less then number of pipes
3728 */
3729 if (pipe_ctx->stream_res.audio)
3730 update_audio_usage(&context->res_ctx, pool,
3731 pipe_ctx->stream_res.audio, true);
3732 }
3733
3734 /* Add ABM to the resource if on EDP */
3735 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {
3736 if (pool->abm)
3737 pipe_ctx->stream_res.abm = pool->abm;
3738 else
3739 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];
3740 }
3741
3742 for (i = 0; i < context->stream_count; i++)
3743 if (context->streams[i] == stream) {
3744 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
3745 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3746 context->stream_status[i].audio_inst =
3747 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
3748
3749 return DC_OK;
3750 }
3751
3752 DC_ERROR("Stream %p not found in new ctx!\n", stream);
3753 return DC_ERROR_UNEXPECTED;
3754 }
3755
dc_resource_is_dsc_encoding_supported(const struct dc * dc)3756 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
3757 {
3758 if (dc->res_pool == NULL)
3759 return false;
3760
3761 return dc->res_pool->res_cap->num_dsc > 0;
3762 }
3763
planes_changed_for_existing_stream(struct dc_state * context,struct dc_stream_state * stream,const struct dc_validation_set set[],int set_count)3764 static bool planes_changed_for_existing_stream(struct dc_state *context,
3765 struct dc_stream_state *stream,
3766 const struct dc_validation_set set[],
3767 int set_count)
3768 {
3769 int i, j;
3770 struct dc_stream_status *stream_status = NULL;
3771
3772 for (i = 0; i < context->stream_count; i++) {
3773 if (context->streams[i] == stream) {
3774 stream_status = &context->stream_status[i];
3775 break;
3776 }
3777 }
3778
3779 if (!stream_status) {
3780 ASSERT(0);
3781 return false;
3782 }
3783
3784 for (i = 0; i < set_count; i++)
3785 if (set[i].stream == stream)
3786 break;
3787
3788 if (i == set_count)
3789 ASSERT(0);
3790
3791 if (set[i].plane_count != stream_status->plane_count)
3792 return true;
3793
3794 for (j = 0; j < set[i].plane_count; j++)
3795 if (set[i].plane_states[j] != stream_status->plane_states[j])
3796 return true;
3797
3798 return false;
3799 }
3800
add_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,const struct dc_validation_set set[],int set_count,struct dc_state * state)3801 static bool add_all_planes_for_stream(
3802 const struct dc *dc,
3803 struct dc_stream_state *stream,
3804 const struct dc_validation_set set[],
3805 int set_count,
3806 struct dc_state *state)
3807 {
3808 int i, j;
3809
3810 for (i = 0; i < set_count; i++)
3811 if (set[i].stream == stream)
3812 break;
3813
3814 if (i == set_count) {
3815 dm_error("Stream %p not found in set!\n", stream);
3816 return false;
3817 }
3818
3819 for (j = 0; j < set[i].plane_count; j++)
3820 if (!dc_state_add_plane(dc, stream, set[i].plane_states[j], state))
3821 return false;
3822
3823 return true;
3824 }
3825
3826 /**
3827 * dc_validate_with_context - Validate and update the potential new stream in the context object
3828 *
3829 * @dc: Used to get the current state status
3830 * @set: An array of dc_validation_set with all the current streams reference
3831 * @set_count: Total of streams
3832 * @context: New context
3833 * @fast_validate: Enable or disable fast validation
3834 *
3835 * This function updates the potential new stream in the context object. It
3836 * creates multiple lists for the add, remove, and unchanged streams. In
3837 * particular, if the unchanged streams have a plane that changed, it is
3838 * necessary to remove all planes from the unchanged streams. In summary, this
3839 * function is responsible for validating the new context.
3840 *
3841 * Return:
3842 * In case of success, return DC_OK (1), otherwise, return a DC error.
3843 */
dc_validate_with_context(struct dc * dc,const struct dc_validation_set set[],int set_count,struct dc_state * context,bool fast_validate)3844 enum dc_status dc_validate_with_context(struct dc *dc,
3845 const struct dc_validation_set set[],
3846 int set_count,
3847 struct dc_state *context,
3848 bool fast_validate)
3849 {
3850 struct dc_stream_state *unchanged_streams[MAX_PIPES] = { 0 };
3851 struct dc_stream_state *del_streams[MAX_PIPES] = { 0 };
3852 struct dc_stream_state *add_streams[MAX_PIPES] = { 0 };
3853 int old_stream_count = context->stream_count;
3854 enum dc_status res = DC_ERROR_UNEXPECTED;
3855 int unchanged_streams_count = 0;
3856 int del_streams_count = 0;
3857 int add_streams_count = 0;
3858 bool found = false;
3859 int i, j, k;
3860
3861 DC_LOGGER_INIT(dc->ctx->logger);
3862
3863 /* First build a list of streams to be remove from current context */
3864 for (i = 0; i < old_stream_count; i++) {
3865 struct dc_stream_state *stream = context->streams[i];
3866
3867 for (j = 0; j < set_count; j++) {
3868 if (stream == set[j].stream) {
3869 found = true;
3870 break;
3871 }
3872 }
3873
3874 if (!found)
3875 del_streams[del_streams_count++] = stream;
3876
3877 found = false;
3878 }
3879
3880 /* Second, build a list of new streams */
3881 for (i = 0; i < set_count; i++) {
3882 struct dc_stream_state *stream = set[i].stream;
3883
3884 for (j = 0; j < old_stream_count; j++) {
3885 if (stream == context->streams[j]) {
3886 found = true;
3887 break;
3888 }
3889 }
3890
3891 if (!found)
3892 add_streams[add_streams_count++] = stream;
3893
3894 found = false;
3895 }
3896
3897 /* Build a list of unchanged streams which is necessary for handling
3898 * planes change such as added, removed, and updated.
3899 */
3900 for (i = 0; i < set_count; i++) {
3901 /* Check if stream is part of the delete list */
3902 for (j = 0; j < del_streams_count; j++) {
3903 if (set[i].stream == del_streams[j]) {
3904 found = true;
3905 break;
3906 }
3907 }
3908
3909 if (!found) {
3910 /* Check if stream is part of the add list */
3911 for (j = 0; j < add_streams_count; j++) {
3912 if (set[i].stream == add_streams[j]) {
3913 found = true;
3914 break;
3915 }
3916 }
3917 }
3918
3919 if (!found)
3920 unchanged_streams[unchanged_streams_count++] = set[i].stream;
3921
3922 found = false;
3923 }
3924
3925 /* Remove all planes for unchanged streams if planes changed */
3926 for (i = 0; i < unchanged_streams_count; i++) {
3927 if (planes_changed_for_existing_stream(context,
3928 unchanged_streams[i],
3929 set,
3930 set_count)) {
3931
3932 if (!dc_state_rem_all_planes_for_stream(dc,
3933 unchanged_streams[i],
3934 context)) {
3935 res = DC_FAIL_DETACH_SURFACES;
3936 goto fail;
3937 }
3938 }
3939 }
3940
3941 /* Remove all planes for removed streams and then remove the streams */
3942 for (i = 0; i < del_streams_count; i++) {
3943 /* Need to cpy the dwb data from the old stream in order to efc to work */
3944 if (del_streams[i]->num_wb_info > 0) {
3945 for (j = 0; j < add_streams_count; j++) {
3946 if (del_streams[i]->sink == add_streams[j]->sink) {
3947 add_streams[j]->num_wb_info = del_streams[i]->num_wb_info;
3948 for (k = 0; k < del_streams[i]->num_wb_info; k++)
3949 add_streams[j]->writeback_info[k] = del_streams[i]->writeback_info[k];
3950 }
3951 }
3952 }
3953
3954 if (dc_state_get_stream_subvp_type(context, del_streams[i]) == SUBVP_PHANTOM) {
3955 /* remove phantoms specifically */
3956 if (!dc_state_rem_all_phantom_planes_for_stream(dc, del_streams[i], context, true)) {
3957 res = DC_FAIL_DETACH_SURFACES;
3958 goto fail;
3959 }
3960
3961 res = dc_state_remove_phantom_stream(dc, context, del_streams[i]);
3962 dc_state_release_phantom_stream(dc, context, del_streams[i]);
3963 } else {
3964 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) {
3965 res = DC_FAIL_DETACH_SURFACES;
3966 goto fail;
3967 }
3968
3969 res = dc_state_remove_stream(dc, context, del_streams[i]);
3970 }
3971
3972 if (res != DC_OK)
3973 goto fail;
3974 }
3975
3976 /* Swap seamless boot stream to pipe 0 (if needed) to ensure pipe_ctx
3977 * matches. This may change in the future if seamless_boot_stream can be
3978 * multiple.
3979 */
3980 for (i = 0; i < add_streams_count; i++) {
3981 mark_seamless_boot_stream(dc, add_streams[i]);
3982 if (add_streams[i]->apply_seamless_boot_optimization && i != 0) {
3983 struct dc_stream_state *temp = add_streams[0];
3984
3985 add_streams[0] = add_streams[i];
3986 add_streams[i] = temp;
3987 break;
3988 }
3989 }
3990
3991 /* Add new streams and then add all planes for the new stream */
3992 for (i = 0; i < add_streams_count; i++) {
3993 calculate_phy_pix_clks(add_streams[i]);
3994 res = dc_state_add_stream(dc, context, add_streams[i]);
3995 if (res != DC_OK)
3996 goto fail;
3997
3998 if (!add_all_planes_for_stream(dc, add_streams[i], set, set_count, context)) {
3999 res = DC_FAIL_ATTACH_SURFACES;
4000 goto fail;
4001 }
4002 }
4003
4004 /* Add all planes for unchanged streams if planes changed */
4005 for (i = 0; i < unchanged_streams_count; i++) {
4006 if (planes_changed_for_existing_stream(context,
4007 unchanged_streams[i],
4008 set,
4009 set_count)) {
4010 if (!add_all_planes_for_stream(dc, unchanged_streams[i], set, set_count, context)) {
4011 res = DC_FAIL_ATTACH_SURFACES;
4012 goto fail;
4013 }
4014 }
4015 }
4016
4017 res = dc_validate_global_state(dc, context, fast_validate);
4018
4019 /* calculate pixel rate divider after deciding pxiel clock & odm combine */
4020 if ((dc->hwss.calculate_pix_rate_divider) && (res == DC_OK)) {
4021 for (i = 0; i < add_streams_count; i++)
4022 dc->hwss.calculate_pix_rate_divider(dc, context, add_streams[i]);
4023 }
4024
4025 fail:
4026 if (res != DC_OK)
4027 DC_LOG_WARNING("%s:resource validation failed, dc_status:%d\n",
4028 __func__,
4029 res);
4030
4031 return res;
4032 }
4033
4034 /**
4035 * decide_hblank_borrow - Decides the horizontal blanking borrow value for a given pipe context.
4036 * @pipe_ctx: Pointer to the pipe context structure.
4037 *
4038 * This function calculates the horizontal blanking borrow value for a given pipe context based on the
4039 * display stream compression (DSC) configuration. If the horizontal active pixels (hactive) are less
4040 * than the total width of the DSC slices, it sets the hblank_borrow value to the difference. If the
4041 * total horizontal timing minus the hblank_borrow value is less than 32, it resets the hblank_borrow
4042 * value to 0.
4043 */
decide_hblank_borrow(struct pipe_ctx * pipe_ctx)4044 static void decide_hblank_borrow(struct pipe_ctx *pipe_ctx)
4045 {
4046 uint32_t hactive;
4047 uint32_t ceil_slice_width;
4048 struct dc_stream_state *stream = NULL;
4049
4050 if (!pipe_ctx)
4051 return;
4052
4053 stream = pipe_ctx->stream;
4054
4055 if (stream->timing.flags.DSC) {
4056 hactive = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
4057
4058 /* Assume if determined slices does not divide Hactive evenly, Hborrow is needed for padding*/
4059 if (hactive % stream->timing.dsc_cfg.num_slices_h != 0) {
4060 ceil_slice_width = (hactive / stream->timing.dsc_cfg.num_slices_h) + 1;
4061 pipe_ctx->hblank_borrow = ceil_slice_width * stream->timing.dsc_cfg.num_slices_h - hactive;
4062
4063 if (stream->timing.h_total - hactive - pipe_ctx->hblank_borrow < 32)
4064 pipe_ctx->hblank_borrow = 0;
4065 }
4066 }
4067 }
4068
4069 /**
4070 * dc_validate_global_state() - Determine if hardware can support a given state
4071 *
4072 * @dc: dc struct for this driver
4073 * @new_ctx: state to be validated
4074 * @fast_validate: set to true if only yes/no to support matters
4075 *
4076 * Checks hardware resource availability and bandwidth requirement.
4077 *
4078 * Return:
4079 * DC_OK if the result can be programmed. Otherwise, an error code.
4080 */
dc_validate_global_state(struct dc * dc,struct dc_state * new_ctx,bool fast_validate)4081 enum dc_status dc_validate_global_state(
4082 struct dc *dc,
4083 struct dc_state *new_ctx,
4084 bool fast_validate)
4085 {
4086 enum dc_status result = DC_ERROR_UNEXPECTED;
4087 int i, j;
4088
4089 if (!new_ctx)
4090 return DC_ERROR_UNEXPECTED;
4091
4092 if (dc->res_pool->funcs->validate_global) {
4093 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
4094 if (result != DC_OK)
4095 return result;
4096 }
4097
4098 for (i = 0; i < new_ctx->stream_count; i++) {
4099 struct dc_stream_state *stream = new_ctx->streams[i];
4100
4101 for (j = 0; j < dc->res_pool->pipe_count; j++) {
4102 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
4103
4104 if (pipe_ctx->stream != stream)
4105 continue;
4106
4107 /* Decide whether hblank borrow is needed and save it in pipe_ctx */
4108 if (dc->debug.enable_hblank_borrow)
4109 decide_hblank_borrow(pipe_ctx);
4110
4111 if (dc->res_pool->funcs->patch_unknown_plane_state &&
4112 pipe_ctx->plane_state &&
4113 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
4114 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);
4115 if (result != DC_OK)
4116 return result;
4117 }
4118
4119 /* Switch to dp clock source only if there is
4120 * no non dp stream that shares the same timing
4121 * with the dp stream.
4122 */
4123 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
4124 !find_pll_sharable_stream(stream, new_ctx)) {
4125
4126 resource_unreference_clock_source(
4127 &new_ctx->res_ctx,
4128 dc->res_pool,
4129 pipe_ctx->clock_source);
4130
4131 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
4132 resource_reference_clock_source(
4133 &new_ctx->res_ctx,
4134 dc->res_pool,
4135 pipe_ctx->clock_source);
4136 }
4137 }
4138 }
4139
4140 result = resource_build_scaling_params_for_context(dc, new_ctx);
4141
4142 if (result == DC_OK)
4143 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
4144 result = DC_FAIL_BANDWIDTH_VALIDATE;
4145
4146 return result;
4147 }
4148
patch_gamut_packet_checksum(struct dc_info_packet * gamut_packet)4149 static void patch_gamut_packet_checksum(
4150 struct dc_info_packet *gamut_packet)
4151 {
4152 /* For gamut we recalc checksum */
4153 if (gamut_packet->valid) {
4154 uint8_t chk_sum = 0;
4155 uint8_t *ptr;
4156 uint8_t i;
4157
4158 /*start of the Gamut data. */
4159 ptr = &gamut_packet->sb[3];
4160
4161 for (i = 0; i <= gamut_packet->sb[1]; i++)
4162 chk_sum += ptr[i];
4163
4164 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
4165 }
4166 }
4167
set_avi_info_frame(struct dc_info_packet * info_packet,struct pipe_ctx * pipe_ctx)4168 static void set_avi_info_frame(
4169 struct dc_info_packet *info_packet,
4170 struct pipe_ctx *pipe_ctx)
4171 {
4172 struct dc_stream_state *stream = pipe_ctx->stream;
4173 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4174 uint32_t pixel_encoding = 0;
4175 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
4176 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
4177 uint8_t *check_sum = NULL;
4178 uint8_t byte_index = 0;
4179 union hdmi_info_packet hdmi_info;
4180 unsigned int vic = pipe_ctx->stream->timing.vic;
4181 unsigned int rid = pipe_ctx->stream->timing.rid;
4182 unsigned int fr_ind = pipe_ctx->stream->timing.fr_index;
4183 enum dc_timing_3d_format format;
4184
4185 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
4186
4187 color_space = pipe_ctx->stream->output_color_space;
4188 if (color_space == COLOR_SPACE_UNKNOWN)
4189 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
4190 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
4191
4192 /* Initialize header */
4193 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
4194 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
4195 * not be used in HDMI 2.0 (Section 10.1) */
4196 hdmi_info.bits.header.version = 2;
4197 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
4198
4199 /*
4200 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
4201 * according to HDMI 2.0 spec (Section 10.1)
4202 */
4203
4204 switch (stream->timing.pixel_encoding) {
4205 case PIXEL_ENCODING_YCBCR422:
4206 pixel_encoding = 1;
4207 break;
4208
4209 case PIXEL_ENCODING_YCBCR444:
4210 pixel_encoding = 2;
4211 break;
4212 case PIXEL_ENCODING_YCBCR420:
4213 pixel_encoding = 3;
4214 break;
4215
4216 case PIXEL_ENCODING_RGB:
4217 default:
4218 pixel_encoding = 0;
4219 }
4220
4221 /* Y0_Y1_Y2 : The pixel encoding */
4222 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
4223 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
4224
4225 /* A0 = 1 Active Format Information valid */
4226 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
4227
4228 /* B0, B1 = 3; Bar info data is valid */
4229 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
4230
4231 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
4232
4233 /* S0, S1 : Underscan / Overscan */
4234 /* TODO: un-hardcode scan type */
4235 scan_type = SCANNING_TYPE_UNDERSCAN;
4236 hdmi_info.bits.S0_S1 = scan_type;
4237
4238 /* C0, C1 : Colorimetry */
4239 switch (color_space) {
4240 case COLOR_SPACE_YCBCR709:
4241 case COLOR_SPACE_YCBCR709_LIMITED:
4242 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
4243 break;
4244 case COLOR_SPACE_YCBCR601:
4245 case COLOR_SPACE_YCBCR601_LIMITED:
4246 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
4247 break;
4248 case COLOR_SPACE_2020_RGB_FULLRANGE:
4249 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
4250 case COLOR_SPACE_2020_YCBCR:
4251 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
4252 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
4253 break;
4254 case COLOR_SPACE_ADOBERGB:
4255 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
4256 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
4257 break;
4258 case COLOR_SPACE_SRGB:
4259 default:
4260 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
4261 break;
4262 }
4263
4264 if (pixel_encoding && color_space == COLOR_SPACE_2020_YCBCR &&
4265 stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
4266 hdmi_info.bits.EC0_EC2 = 0;
4267 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
4268 }
4269
4270 /* TODO: un-hardcode aspect ratio */
4271 aspect = stream->timing.aspect_ratio;
4272
4273 switch (aspect) {
4274 case ASPECT_RATIO_4_3:
4275 case ASPECT_RATIO_16_9:
4276 hdmi_info.bits.M0_M1 = aspect;
4277 break;
4278
4279 case ASPECT_RATIO_NO_DATA:
4280 case ASPECT_RATIO_64_27:
4281 case ASPECT_RATIO_256_135:
4282 default:
4283 hdmi_info.bits.M0_M1 = 0;
4284 }
4285
4286 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
4287 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
4288
4289 switch (stream->content_type) {
4290 case DISPLAY_CONTENT_TYPE_NO_DATA:
4291 hdmi_info.bits.CN0_CN1 = 0;
4292 hdmi_info.bits.ITC = 1;
4293 break;
4294 case DISPLAY_CONTENT_TYPE_GRAPHICS:
4295 hdmi_info.bits.CN0_CN1 = 0;
4296 hdmi_info.bits.ITC = 1;
4297 break;
4298 case DISPLAY_CONTENT_TYPE_PHOTO:
4299 hdmi_info.bits.CN0_CN1 = 1;
4300 hdmi_info.bits.ITC = 1;
4301 break;
4302 case DISPLAY_CONTENT_TYPE_CINEMA:
4303 hdmi_info.bits.CN0_CN1 = 2;
4304 hdmi_info.bits.ITC = 1;
4305 break;
4306 case DISPLAY_CONTENT_TYPE_GAME:
4307 hdmi_info.bits.CN0_CN1 = 3;
4308 hdmi_info.bits.ITC = 1;
4309 break;
4310 }
4311
4312 if (stream->qs_bit == 1) {
4313 if (color_space == COLOR_SPACE_SRGB ||
4314 color_space == COLOR_SPACE_2020_RGB_FULLRANGE)
4315 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
4316 else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
4317 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
4318 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
4319 else
4320 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
4321 } else
4322 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
4323
4324 /* TODO : We should handle YCC quantization */
4325 /* but we do not have matrix calculation */
4326 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
4327
4328 ///VIC
4329 if (pipe_ctx->stream->timing.hdmi_vic != 0)
4330 vic = 0;
4331 format = stream->timing.timing_3d_format;
4332 /*todo, add 3DStereo support*/
4333 if (format != TIMING_3D_FORMAT_NONE) {
4334 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
4335 switch (pipe_ctx->stream->timing.hdmi_vic) {
4336 case 1:
4337 vic = 95;
4338 break;
4339 case 2:
4340 vic = 94;
4341 break;
4342 case 3:
4343 vic = 93;
4344 break;
4345 case 4:
4346 vic = 98;
4347 break;
4348 default:
4349 break;
4350 }
4351 }
4352 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
4353 hdmi_info.bits.VIC0_VIC7 = vic;
4354 if (vic >= 128)
4355 hdmi_info.bits.header.version = 3;
4356 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
4357 * the Source shall use 20 AVI InfoFrame Version 4
4358 */
4359 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
4360 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
4361 hdmi_info.bits.header.version = 4;
4362 hdmi_info.bits.header.length = 14;
4363 }
4364
4365 if (rid != 0 && fr_ind != 0) {
4366 hdmi_info.bits.header.version = 4;
4367 hdmi_info.bits.header.length = 15;
4368
4369 hdmi_info.bits.FR0_FR3 = fr_ind & 0xF;
4370 hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1;
4371 hdmi_info.bits.RID0_RID5 = rid;
4372 }
4373
4374 /* pixel repetition
4375 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
4376 * repetition start from 1 */
4377 hdmi_info.bits.PR0_PR3 = 0;
4378
4379 /* Bar Info
4380 * barTop: Line Number of End of Top Bar.
4381 * barBottom: Line Number of Start of Bottom Bar.
4382 * barLeft: Pixel Number of End of Left Bar.
4383 * barRight: Pixel Number of Start of Right Bar. */
4384 hdmi_info.bits.bar_top = stream->timing.v_border_top;
4385 hdmi_info.bits.bar_bottom = (stream->timing.v_total
4386 - stream->timing.v_border_bottom + 1);
4387 hdmi_info.bits.bar_left = stream->timing.h_border_left;
4388 hdmi_info.bits.bar_right = (stream->timing.h_total
4389 - stream->timing.h_border_right + 1);
4390
4391 /* Additional Colorimetry Extension
4392 * Used in conduction with C0-C1 and EC0-EC2
4393 * 0 = DCI-P3 RGB (D65)
4394 * 1 = DCI-P3 RGB (theater)
4395 */
4396 hdmi_info.bits.ACE0_ACE3 = 0;
4397
4398 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
4399 check_sum = &hdmi_info.packet_raw_data.sb[0];
4400
4401 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
4402
4403 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
4404 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
4405
4406 /* one byte complement */
4407 *check_sum = (uint8_t) (0x100 - *check_sum);
4408
4409 /* Store in hw_path_mode */
4410 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
4411 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
4412 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
4413
4414 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
4415 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
4416
4417 info_packet->valid = true;
4418 }
4419
set_vendor_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)4420 static void set_vendor_info_packet(
4421 struct dc_info_packet *info_packet,
4422 struct dc_stream_state *stream)
4423 {
4424 /* SPD info packet for FreeSync */
4425
4426 /* Check if Freesync is supported. Return if false. If true,
4427 * set the corresponding bit in the info packet
4428 */
4429 if (!stream->vsp_infopacket.valid)
4430 return;
4431
4432 *info_packet = stream->vsp_infopacket;
4433 }
4434
set_spd_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)4435 static void set_spd_info_packet(
4436 struct dc_info_packet *info_packet,
4437 struct dc_stream_state *stream)
4438 {
4439 /* SPD info packet for FreeSync */
4440
4441 /* Check if Freesync is supported. Return if false. If true,
4442 * set the corresponding bit in the info packet
4443 */
4444 if (!stream->vrr_infopacket.valid)
4445 return;
4446
4447 *info_packet = stream->vrr_infopacket;
4448 }
4449
set_hdr_static_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)4450 static void set_hdr_static_info_packet(
4451 struct dc_info_packet *info_packet,
4452 struct dc_stream_state *stream)
4453 {
4454 /* HDR Static Metadata info packet for HDR10 */
4455
4456 if (!stream->hdr_static_metadata.valid ||
4457 stream->use_dynamic_meta)
4458 return;
4459
4460 *info_packet = stream->hdr_static_metadata;
4461 }
4462
set_vsc_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)4463 static void set_vsc_info_packet(
4464 struct dc_info_packet *info_packet,
4465 struct dc_stream_state *stream)
4466 {
4467 if (!stream->vsc_infopacket.valid)
4468 return;
4469
4470 *info_packet = stream->vsc_infopacket;
4471 }
set_hfvs_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)4472 static void set_hfvs_info_packet(
4473 struct dc_info_packet *info_packet,
4474 struct dc_stream_state *stream)
4475 {
4476 if (!stream->hfvsif_infopacket.valid)
4477 return;
4478
4479 *info_packet = stream->hfvsif_infopacket;
4480 }
4481
adaptive_sync_override_dp_info_packets_sdp_line_num(const struct dc_crtc_timing * timing,struct enc_sdp_line_num * sdp_line_num,unsigned int vstartup_start)4482 static void adaptive_sync_override_dp_info_packets_sdp_line_num(
4483 const struct dc_crtc_timing *timing,
4484 struct enc_sdp_line_num *sdp_line_num,
4485 unsigned int vstartup_start)
4486 {
4487 uint32_t asic_blank_start = 0;
4488 uint32_t asic_blank_end = 0;
4489 uint32_t v_update = 0;
4490
4491 const struct dc_crtc_timing *tg = timing;
4492
4493 /* blank_start = frame end - front porch */
4494 asic_blank_start = tg->v_total - tg->v_front_porch;
4495
4496 /* blank_end = blank_start - active */
4497 asic_blank_end = (asic_blank_start - tg->v_border_bottom -
4498 tg->v_addressable - tg->v_border_top);
4499
4500 if (vstartup_start > asic_blank_end) {
4501 v_update = (tg->v_total - (vstartup_start - asic_blank_end));
4502 sdp_line_num->adaptive_sync_line_num_valid = true;
4503 sdp_line_num->adaptive_sync_line_num = (tg->v_total - v_update - 1);
4504 } else {
4505 sdp_line_num->adaptive_sync_line_num_valid = false;
4506 sdp_line_num->adaptive_sync_line_num = 0;
4507 }
4508 }
4509
set_adaptive_sync_info_packet(struct dc_info_packet * info_packet,const struct dc_stream_state * stream,struct encoder_info_frame * info_frame,unsigned int vstartup_start)4510 static void set_adaptive_sync_info_packet(
4511 struct dc_info_packet *info_packet,
4512 const struct dc_stream_state *stream,
4513 struct encoder_info_frame *info_frame,
4514 unsigned int vstartup_start)
4515 {
4516 if (!stream->adaptive_sync_infopacket.valid)
4517 return;
4518
4519 adaptive_sync_override_dp_info_packets_sdp_line_num(
4520 &stream->timing,
4521 &info_frame->sdp_line_num,
4522 vstartup_start);
4523
4524 *info_packet = stream->adaptive_sync_infopacket;
4525 }
4526
set_vtem_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)4527 static void set_vtem_info_packet(
4528 struct dc_info_packet *info_packet,
4529 struct dc_stream_state *stream)
4530 {
4531 if (!stream->vtem_infopacket.valid)
4532 return;
4533
4534 *info_packet = stream->vtem_infopacket;
4535 }
4536
dc_resource_find_first_free_pll(struct resource_context * res_ctx,const struct resource_pool * pool)4537 struct clock_source *dc_resource_find_first_free_pll(
4538 struct resource_context *res_ctx,
4539 const struct resource_pool *pool)
4540 {
4541 int i;
4542
4543 for (i = 0; i < pool->clk_src_count; ++i) {
4544 if (res_ctx->clock_source_ref_count[i] == 0)
4545 return pool->clock_sources[i];
4546 }
4547
4548 return NULL;
4549 }
4550
resource_build_info_frame(struct pipe_ctx * pipe_ctx)4551 void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
4552 {
4553 enum signal_type signal = SIGNAL_TYPE_NONE;
4554 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4555 unsigned int vstartup_start = 0;
4556
4557 /* default all packets to invalid */
4558 info->avi.valid = false;
4559 info->gamut.valid = false;
4560 info->vendor.valid = false;
4561 info->spd.valid = false;
4562 info->hdrsmd.valid = false;
4563 info->vsc.valid = false;
4564 info->hfvsif.valid = false;
4565 info->vtem.valid = false;
4566 info->adaptive_sync.valid = false;
4567 signal = pipe_ctx->stream->signal;
4568
4569 if (pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe)
4570 vstartup_start = pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe(pipe_ctx);
4571
4572 /* HDMi and DP have different info packets*/
4573 if (dc_is_hdmi_signal(signal)) {
4574 set_avi_info_frame(&info->avi, pipe_ctx);
4575
4576 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
4577 set_hfvs_info_packet(&info->hfvsif, pipe_ctx->stream);
4578 set_vtem_info_packet(&info->vtem, pipe_ctx->stream);
4579
4580 set_spd_info_packet(&info->spd, pipe_ctx->stream);
4581
4582 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
4583
4584 } else if (dc_is_dp_signal(signal)) {
4585 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
4586
4587 set_spd_info_packet(&info->spd, pipe_ctx->stream);
4588
4589 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
4590 set_adaptive_sync_info_packet(&info->adaptive_sync,
4591 pipe_ctx->stream,
4592 info,
4593 vstartup_start);
4594 }
4595
4596 patch_gamut_packet_checksum(&info->gamut);
4597 }
4598
resource_map_clock_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)4599 enum dc_status resource_map_clock_resources(
4600 const struct dc *dc,
4601 struct dc_state *context,
4602 struct dc_stream_state *stream)
4603 {
4604 /* acquire new resources */
4605 const struct resource_pool *pool = dc->res_pool;
4606 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(
4607 &context->res_ctx, stream);
4608
4609 if (!pipe_ctx)
4610 return DC_ERROR_UNEXPECTED;
4611
4612 if (dc_is_dp_signal(pipe_ctx->stream->signal)
4613 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
4614 pipe_ctx->clock_source = pool->dp_clock_source;
4615 else {
4616 pipe_ctx->clock_source = NULL;
4617
4618 if (!dc->config.disable_disp_pll_sharing)
4619 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
4620 &context->res_ctx,
4621 pipe_ctx);
4622
4623 if (pipe_ctx->clock_source == NULL)
4624 pipe_ctx->clock_source =
4625 dc_resource_find_first_free_pll(
4626 &context->res_ctx,
4627 pool);
4628 }
4629
4630 if (pipe_ctx->clock_source == NULL)
4631 return DC_NO_CLOCK_SOURCE_RESOURCE;
4632
4633 resource_reference_clock_source(
4634 &context->res_ctx, pool,
4635 pipe_ctx->clock_source);
4636
4637 return DC_OK;
4638 }
4639
4640 /*
4641 * Note: We need to disable output if clock sources change,
4642 * since bios does optimization and doesn't apply if changing
4643 * PHY when not already disabled.
4644 */
pipe_need_reprogram(struct pipe_ctx * pipe_ctx_old,struct pipe_ctx * pipe_ctx)4645 bool pipe_need_reprogram(
4646 struct pipe_ctx *pipe_ctx_old,
4647 struct pipe_ctx *pipe_ctx)
4648 {
4649 if (!pipe_ctx_old->stream)
4650 return false;
4651
4652 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
4653 return true;
4654
4655 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
4656 return true;
4657
4658 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
4659 return true;
4660
4661 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
4662 && pipe_ctx_old->stream != pipe_ctx->stream)
4663 return true;
4664
4665 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
4666 return true;
4667
4668 if (dc_is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
4669 return true;
4670
4671 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
4672 return true;
4673
4674 if (false == pipe_ctx_old->stream->link->link_state_valid &&
4675 false == pipe_ctx_old->stream->dpms_off)
4676 return true;
4677
4678 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)
4679 return true;
4680
4681 if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc)
4682 return true;
4683 if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc)
4684 return true;
4685
4686 /* DIG link encoder resource assignment for stream changed. */
4687 if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) {
4688 bool need_reprogram = false;
4689 struct dc *dc = pipe_ctx_old->stream->ctx->dc;
4690 struct link_encoder *link_enc_prev =
4691 link_enc_cfg_get_link_enc_used_by_stream_current(dc, pipe_ctx_old->stream);
4692
4693 if (link_enc_prev != pipe_ctx->stream->link_enc)
4694 need_reprogram = true;
4695
4696 return need_reprogram;
4697 }
4698
4699 return false;
4700 }
4701
resource_build_bit_depth_reduction_params(struct dc_stream_state * stream,struct bit_depth_reduction_params * fmt_bit_depth)4702 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
4703 struct bit_depth_reduction_params *fmt_bit_depth)
4704 {
4705 enum dc_dither_option option = stream->dither_option;
4706 enum dc_pixel_encoding pixel_encoding =
4707 stream->timing.pixel_encoding;
4708
4709 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
4710
4711 if (option == DITHER_OPTION_DEFAULT) {
4712 switch (stream->timing.display_color_depth) {
4713 case COLOR_DEPTH_666:
4714 option = DITHER_OPTION_SPATIAL6;
4715 break;
4716 case COLOR_DEPTH_888:
4717 option = DITHER_OPTION_SPATIAL8;
4718 break;
4719 case COLOR_DEPTH_101010:
4720 option = DITHER_OPTION_TRUN10;
4721 break;
4722 default:
4723 option = DITHER_OPTION_DISABLE;
4724 }
4725 }
4726
4727 if (option == DITHER_OPTION_DISABLE)
4728 return;
4729
4730 if (option == DITHER_OPTION_TRUN6) {
4731 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
4732 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
4733 } else if (option == DITHER_OPTION_TRUN8 ||
4734 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
4735 option == DITHER_OPTION_TRUN8_FM6) {
4736 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
4737 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
4738 } else if (option == DITHER_OPTION_TRUN10 ||
4739 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
4740 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
4741 option == DITHER_OPTION_TRUN10_FM8 ||
4742 option == DITHER_OPTION_TRUN10_FM6 ||
4743 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
4744 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
4745 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
4746 if (option == DITHER_OPTION_TRUN10)
4747 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
4748 }
4749
4750 /* special case - Formatter can only reduce by 4 bits at most.
4751 * When reducing from 12 to 6 bits,
4752 * HW recommends we use trunc with round mode
4753 * (if we did nothing, trunc to 10 bits would be used)
4754 * note that any 12->10 bit reduction is ignored prior to DCE8,
4755 * as the input was 10 bits.
4756 */
4757 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
4758 option == DITHER_OPTION_SPATIAL6 ||
4759 option == DITHER_OPTION_FM6) {
4760 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
4761 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
4762 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
4763 }
4764
4765 /* spatial dither
4766 * note that spatial modes 1-3 are never used
4767 */
4768 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
4769 option == DITHER_OPTION_SPATIAL6 ||
4770 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
4771 option == DITHER_OPTION_TRUN8_SPATIAL6) {
4772 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
4773 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
4774 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
4775 fmt_bit_depth->flags.RGB_RANDOM =
4776 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
4777 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
4778 option == DITHER_OPTION_SPATIAL8 ||
4779 option == DITHER_OPTION_SPATIAL8_FM6 ||
4780 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
4781 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
4782 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
4783 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
4784 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
4785 fmt_bit_depth->flags.RGB_RANDOM =
4786 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
4787 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
4788 option == DITHER_OPTION_SPATIAL10 ||
4789 option == DITHER_OPTION_SPATIAL10_FM8 ||
4790 option == DITHER_OPTION_SPATIAL10_FM6) {
4791 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
4792 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
4793 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
4794 fmt_bit_depth->flags.RGB_RANDOM =
4795 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
4796 }
4797
4798 if (option == DITHER_OPTION_SPATIAL6 ||
4799 option == DITHER_OPTION_SPATIAL8 ||
4800 option == DITHER_OPTION_SPATIAL10) {
4801 fmt_bit_depth->flags.FRAME_RANDOM = 0;
4802 } else {
4803 fmt_bit_depth->flags.FRAME_RANDOM = 1;
4804 }
4805
4806 //////////////////////
4807 //// temporal dither
4808 //////////////////////
4809 if (option == DITHER_OPTION_FM6 ||
4810 option == DITHER_OPTION_SPATIAL8_FM6 ||
4811 option == DITHER_OPTION_SPATIAL10_FM6 ||
4812 option == DITHER_OPTION_TRUN10_FM6 ||
4813 option == DITHER_OPTION_TRUN8_FM6 ||
4814 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
4815 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
4816 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
4817 } else if (option == DITHER_OPTION_FM8 ||
4818 option == DITHER_OPTION_SPATIAL10_FM8 ||
4819 option == DITHER_OPTION_TRUN10_FM8) {
4820 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
4821 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
4822 } else if (option == DITHER_OPTION_FM10) {
4823 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
4824 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
4825 }
4826
4827 fmt_bit_depth->pixel_encoding = pixel_encoding;
4828 }
4829
dc_validate_stream(struct dc * dc,struct dc_stream_state * stream)4830 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
4831 {
4832 if (dc == NULL || stream == NULL)
4833 return DC_ERROR_UNEXPECTED;
4834
4835 struct dc_link *link = stream->link;
4836 struct timing_generator *tg = dc->res_pool->timing_generators[0];
4837 enum dc_status res = DC_OK;
4838
4839 calculate_phy_pix_clks(stream);
4840
4841 if (!tg->funcs->validate_timing(tg, &stream->timing))
4842 res = DC_FAIL_CONTROLLER_VALIDATE;
4843
4844 if (res == DC_OK) {
4845 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
4846 !link->link_enc->funcs->validate_output_with_stream(
4847 link->link_enc, stream))
4848 res = DC_FAIL_ENC_VALIDATE;
4849 }
4850
4851 /* TODO: validate audio ASIC caps, encoder */
4852
4853 if (res == DC_OK)
4854 res = dc->link_srv->validate_mode_timing(stream,
4855 link,
4856 &stream->timing);
4857
4858 return res;
4859 }
4860
dc_validate_plane(struct dc * dc,const struct dc_plane_state * plane_state)4861 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
4862 {
4863 enum dc_status res = DC_OK;
4864
4865 /* check if surface has invalid dimensions */
4866 if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 0 ||
4867 plane_state->dst_rect.width == 0 || plane_state->dst_rect.height == 0)
4868 return DC_FAIL_SURFACE_VALIDATE;
4869
4870 /* TODO For now validates pixel format only */
4871 if (dc->res_pool->funcs->validate_plane)
4872 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
4873
4874 return res;
4875 }
4876
resource_pixel_format_to_bpp(enum surface_pixel_format format)4877 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
4878 {
4879 switch (format) {
4880 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
4881 return 8;
4882 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
4883 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
4884 return 12;
4885 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
4886 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
4887 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
4888 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
4889 return 16;
4890 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
4891 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
4892 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
4893 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
4894 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
4895 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
4896 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
4897 return 32;
4898 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
4899 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
4900 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
4901 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
4902 return 64;
4903 default:
4904 ASSERT_CRITICAL(false);
4905 return -1;
4906 }
4907 }
get_max_audio_sample_rate(struct audio_mode * modes)4908 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
4909 {
4910 if (modes) {
4911 if (modes->sample_rates.rate.RATE_192)
4912 return 192000;
4913 if (modes->sample_rates.rate.RATE_176_4)
4914 return 176400;
4915 if (modes->sample_rates.rate.RATE_96)
4916 return 96000;
4917 if (modes->sample_rates.rate.RATE_88_2)
4918 return 88200;
4919 if (modes->sample_rates.rate.RATE_48)
4920 return 48000;
4921 if (modes->sample_rates.rate.RATE_44_1)
4922 return 44100;
4923 if (modes->sample_rates.rate.RATE_32)
4924 return 32000;
4925 }
4926 /*original logic when no audio info*/
4927 return 441000;
4928 }
4929
get_audio_check(struct audio_info * aud_modes,struct audio_check * audio_chk)4930 void get_audio_check(struct audio_info *aud_modes,
4931 struct audio_check *audio_chk)
4932 {
4933 unsigned int i;
4934 unsigned int max_sample_rate = 0;
4935
4936 if (aud_modes) {
4937 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
4938
4939 audio_chk->max_audiosample_rate = 0;
4940 for (i = 0; i < aud_modes->mode_count; i++) {
4941 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]);
4942 if (audio_chk->max_audiosample_rate < max_sample_rate)
4943 audio_chk->max_audiosample_rate = max_sample_rate;
4944 /*dts takes the same as type 2: AP = 0.25*/
4945 }
4946 /*check which one take more bandwidth*/
4947 if (audio_chk->max_audiosample_rate > 192000)
4948 audio_chk->audio_packet_type = 0x9;/*AP =1*/
4949 audio_chk->acat = 0;/*not support*/
4950 }
4951 }
4952
get_temp_hpo_dp_link_enc(const struct resource_context * res_ctx,const struct resource_pool * const pool,const struct dc_link * link)4953 static struct hpo_dp_link_encoder *get_temp_hpo_dp_link_enc(
4954 const struct resource_context *res_ctx,
4955 const struct resource_pool *const pool,
4956 const struct dc_link *link)
4957 {
4958 struct hpo_dp_link_encoder *hpo_dp_link_enc = NULL;
4959 int enc_index;
4960
4961 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, link);
4962
4963 if (enc_index < 0)
4964 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
4965
4966 if (enc_index >= 0)
4967 hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
4968
4969 return hpo_dp_link_enc;
4970 }
4971
get_temp_dp_link_res(struct dc_link * link,struct link_resource * link_res,struct dc_link_settings * link_settings)4972 bool get_temp_dp_link_res(struct dc_link *link,
4973 struct link_resource *link_res,
4974 struct dc_link_settings *link_settings)
4975 {
4976 const struct dc *dc = link->dc;
4977 const struct resource_context *res_ctx = &dc->current_state->res_ctx;
4978
4979 memset(link_res, 0, sizeof(*link_res));
4980
4981 if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
4982 link_res->hpo_dp_link_enc = get_temp_hpo_dp_link_enc(res_ctx,
4983 dc->res_pool, link);
4984 if (!link_res->hpo_dp_link_enc)
4985 return false;
4986 }
4987 return true;
4988 }
4989
reset_syncd_pipes_from_disabled_pipes(struct dc * dc,struct dc_state * context)4990 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
4991 struct dc_state *context)
4992 {
4993 int i, j;
4994 struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd;
4995
4996 /* If pipe backend is reset, need to reset pipe syncd status */
4997 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4998 pipe_ctx_old = &dc->current_state->res_ctx.pipe_ctx[i];
4999 pipe_ctx = &context->res_ctx.pipe_ctx[i];
5000
5001 if (!resource_is_pipe_type(pipe_ctx_old, OTG_MASTER))
5002 continue;
5003
5004 if (!pipe_ctx->stream ||
5005 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
5006
5007 /* Reset all the syncd pipes from the disabled pipe */
5008 for (j = 0; j < dc->res_pool->pipe_count; j++) {
5009 pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j];
5010 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_syncd) == pipe_ctx_old->pipe_idx) ||
5011 !IS_PIPE_SYNCD_VALID(pipe_ctx_syncd))
5012 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_syncd, j);
5013 }
5014 }
5015 }
5016 }
5017
check_syncd_pipes_for_disabled_master_pipe(struct dc * dc,struct dc_state * context,uint8_t disabled_master_pipe_idx)5018 void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
5019 struct dc_state *context,
5020 uint8_t disabled_master_pipe_idx)
5021 {
5022 int i;
5023 struct pipe_ctx *pipe_ctx, *pipe_ctx_check;
5024
5025 pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];
5026 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) ||
5027 !IS_PIPE_SYNCD_VALID(pipe_ctx))
5028 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx);
5029
5030 /* for the pipe disabled, check if any slave pipe exists and assert */
5031 for (i = 0; i < dc->res_pool->pipe_count; i++) {
5032 pipe_ctx_check = &context->res_ctx.pipe_ctx[i];
5033
5034 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) &&
5035 IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx)) {
5036 struct pipe_ctx *first_pipe = pipe_ctx_check;
5037
5038 while (first_pipe->prev_odm_pipe)
5039 first_pipe = first_pipe->prev_odm_pipe;
5040 /* When ODM combine is enabled, this case is expected. If the disabled pipe
5041 * is part of the ODM tree, then we should not print an error.
5042 * */
5043 if (first_pipe->pipe_idx == disabled_master_pipe_idx)
5044 continue;
5045
5046 DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n",
5047 i, disabled_master_pipe_idx);
5048 }
5049 }
5050 }
5051
reset_sync_context_for_pipe(const struct dc * dc,struct dc_state * context,uint8_t pipe_idx)5052 void reset_sync_context_for_pipe(const struct dc *dc,
5053 struct dc_state *context,
5054 uint8_t pipe_idx)
5055 {
5056 int i;
5057 struct pipe_ctx *pipe_ctx_reset;
5058
5059 /* reset the otg sync context for the pipe and its slave pipes if any */
5060 for (i = 0; i < dc->res_pool->pipe_count; i++) {
5061 pipe_ctx_reset = &context->res_ctx.pipe_ctx[i];
5062
5063 if (((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_reset) == pipe_idx) &&
5064 IS_PIPE_SYNCD_VALID(pipe_ctx_reset)) || (i == pipe_idx))
5065 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_reset, i);
5066 }
5067 }
5068
resource_transmitter_to_phy_idx(const struct dc * dc,enum transmitter transmitter)5069 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter)
5070 {
5071 /* TODO - get transmitter to phy idx mapping from DMUB */
5072 uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
5073
5074 if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
5075 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
5076 switch (transmitter) {
5077 case TRANSMITTER_UNIPHY_A:
5078 phy_idx = 0;
5079 break;
5080 case TRANSMITTER_UNIPHY_B:
5081 phy_idx = 1;
5082 break;
5083 case TRANSMITTER_UNIPHY_C:
5084 phy_idx = 5;
5085 break;
5086 case TRANSMITTER_UNIPHY_D:
5087 phy_idx = 6;
5088 break;
5089 case TRANSMITTER_UNIPHY_E:
5090 phy_idx = 4;
5091 break;
5092 default:
5093 phy_idx = 0;
5094 break;
5095 }
5096 }
5097
5098 return phy_idx;
5099 }
5100
get_link_hwss(const struct dc_link * link,const struct link_resource * link_res)5101 const struct link_hwss *get_link_hwss(const struct dc_link *link,
5102 const struct link_resource *link_res)
5103 {
5104 /* Link_hwss is only accessible by getter function instead of accessing
5105 * by pointers in dc with the intent to protect against breaking polymorphism.
5106 */
5107 if (can_use_hpo_dp_link_hwss(link, link_res))
5108 /* TODO: some assumes that if decided link settings is 128b/132b
5109 * channel coding format hpo_dp_link_enc should be used.
5110 * Others believe that if hpo_dp_link_enc is available in link
5111 * resource then hpo_dp_link_enc must be used. This bound between
5112 * hpo_dp_link_enc != NULL and decided link settings is loosely coupled
5113 * with a premise that both hpo_dp_link_enc pointer and decided link
5114 * settings are determined based on single policy function like
5115 * "decide_link_settings" from upper layer. This "convention"
5116 * cannot be maintained and enforced at current level.
5117 * Therefore a refactor is due so we can enforce a strong bound
5118 * between those two parameters at this level.
5119 *
5120 * To put it simple, we want to make enforcement at low level so that
5121 * we will not return link hwss if caller plans to do 8b/10b
5122 * with an hpo encoder. Or we can return a very dummy one that doesn't
5123 * do work for all functions
5124 */
5125 return (requires_fixed_vs_pe_retimer_hpo_link_hwss(link) ?
5126 get_hpo_fixed_vs_pe_retimer_dp_link_hwss() : get_hpo_dp_link_hwss());
5127 else if (can_use_dpia_link_hwss(link, link_res))
5128 return get_dpia_link_hwss();
5129 else if (can_use_dio_link_hwss(link, link_res))
5130 return (requires_fixed_vs_pe_retimer_dio_link_hwss(link)) ?
5131 get_dio_fixed_vs_pe_retimer_link_hwss() : get_dio_link_hwss();
5132 else
5133 return get_virtual_link_hwss();
5134 }
5135
is_h_timing_divisible_by_2(struct dc_stream_state * stream)5136 bool is_h_timing_divisible_by_2(struct dc_stream_state *stream)
5137 {
5138 bool divisible = false;
5139 uint16_t h_blank_start = 0;
5140 uint16_t h_blank_end = 0;
5141
5142 if (stream) {
5143 h_blank_start = stream->timing.h_total - stream->timing.h_front_porch;
5144 h_blank_end = h_blank_start - stream->timing.h_addressable;
5145
5146 /* HTOTAL, Hblank start/end, and Hsync start/end all must be
5147 * divisible by 2 in order for the horizontal timing params
5148 * to be considered divisible by 2. Hsync start is always 0.
5149 */
5150 divisible = (stream->timing.h_total % 2 == 0) &&
5151 (h_blank_start % 2 == 0) &&
5152 (h_blank_end % 2 == 0) &&
5153 (stream->timing.h_sync_width % 2 == 0);
5154 }
5155 return divisible;
5156 }
5157
5158 /* This interface is deprecated for new DCNs. It is replaced by the following
5159 * new interfaces. These two interfaces encapsulate pipe selection priority
5160 * with DCN specific minimum hardware transition optimization algorithm. With
5161 * the new interfaces caller no longer needs to know the implementation detail
5162 * of a pipe topology.
5163 *
5164 * resource_update_pipes_with_odm_slice_count
5165 * resource_update_pipes_with_mpc_slice_count
5166 *
5167 */
dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy(const struct dc * dc,struct dc_state * state,struct pipe_ctx * pri_pipe,struct pipe_ctx * sec_pipe,bool odm)5168 bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy(
5169 const struct dc *dc,
5170 struct dc_state *state,
5171 struct pipe_ctx *pri_pipe,
5172 struct pipe_ctx *sec_pipe,
5173 bool odm)
5174 {
5175 int pipe_idx = sec_pipe->pipe_idx;
5176 struct pipe_ctx *sec_top, *sec_bottom, *sec_next, *sec_prev;
5177 const struct resource_pool *pool = dc->res_pool;
5178
5179 sec_top = sec_pipe->top_pipe;
5180 sec_bottom = sec_pipe->bottom_pipe;
5181 sec_next = sec_pipe->next_odm_pipe;
5182 sec_prev = sec_pipe->prev_odm_pipe;
5183
5184 if (pri_pipe == NULL)
5185 return false;
5186
5187 *sec_pipe = *pri_pipe;
5188
5189 sec_pipe->top_pipe = sec_top;
5190 sec_pipe->bottom_pipe = sec_bottom;
5191 sec_pipe->next_odm_pipe = sec_next;
5192 sec_pipe->prev_odm_pipe = sec_prev;
5193
5194 sec_pipe->pipe_idx = pipe_idx;
5195 sec_pipe->plane_res.mi = pool->mis[pipe_idx];
5196 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
5197 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
5198 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
5199 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
5200 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
5201 sec_pipe->stream_res.dsc = NULL;
5202 if (odm) {
5203 if (!sec_pipe->top_pipe)
5204 sec_pipe->stream_res.opp = pool->opps[pipe_idx];
5205 else
5206 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
5207 if (sec_pipe->stream->timing.flags.DSC == 1) {
5208 #if defined(CONFIG_DRM_AMD_DC_FP)
5209 dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, sec_pipe->stream_res.opp->inst);
5210 #endif
5211 ASSERT(sec_pipe->stream_res.dsc);
5212 if (sec_pipe->stream_res.dsc == NULL)
5213 return false;
5214 }
5215 #if defined(CONFIG_DRM_AMD_DC_FP)
5216 dcn20_build_mapped_resource(dc, state, sec_pipe->stream);
5217 #endif
5218 }
5219
5220 return true;
5221 }
5222
update_dp_encoder_resources_for_test_harness(const struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)5223 enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,
5224 struct dc_state *context,
5225 struct pipe_ctx *pipe_ctx)
5226 {
5227 if (dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {
5228 if (pipe_ctx->stream_res.hpo_dp_stream_enc == NULL) {
5229 pipe_ctx->stream_res.hpo_dp_stream_enc =
5230 find_first_free_match_hpo_dp_stream_enc_for_link(
5231 &context->res_ctx, dc->res_pool, pipe_ctx->stream);
5232
5233 if (!pipe_ctx->stream_res.hpo_dp_stream_enc)
5234 return DC_NO_STREAM_ENC_RESOURCE;
5235
5236 update_hpo_dp_stream_engine_usage(
5237 &context->res_ctx, dc->res_pool,
5238 pipe_ctx->stream_res.hpo_dp_stream_enc,
5239 true);
5240 }
5241
5242 if (pipe_ctx->link_res.hpo_dp_link_enc == NULL) {
5243 if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, dc->res_pool, pipe_ctx, pipe_ctx->stream))
5244 return DC_NO_LINK_ENC_RESOURCE;
5245 }
5246 } else {
5247 if (pipe_ctx->stream_res.hpo_dp_stream_enc) {
5248 update_hpo_dp_stream_engine_usage(
5249 &context->res_ctx, dc->res_pool,
5250 pipe_ctx->stream_res.hpo_dp_stream_enc,
5251 false);
5252 pipe_ctx->stream_res.hpo_dp_stream_enc = NULL;
5253 }
5254 if (pipe_ctx->link_res.hpo_dp_link_enc)
5255 remove_hpo_dp_link_enc_from_ctx(&context->res_ctx, pipe_ctx, pipe_ctx->stream);
5256 }
5257
5258 return DC_OK;
5259 }
5260
check_subvp_sw_cursor_fallback_req(const struct dc * dc,struct dc_stream_state * stream)5261 bool check_subvp_sw_cursor_fallback_req(const struct dc *dc, struct dc_stream_state *stream)
5262 {
5263 if (!dc->debug.disable_subvp_high_refresh && is_subvp_high_refresh_candidate(stream))
5264 return true;
5265 if (dc->current_state->stream_count == 1 && stream->timing.v_addressable >= 2880 &&
5266 ((stream->timing.pix_clk_100hz * 100) / stream->timing.v_total / stream->timing.h_total) < 120)
5267 return true;
5268 else if (dc->current_state->stream_count > 1 && stream->timing.v_addressable >= 1080 &&
5269 ((stream->timing.pix_clk_100hz * 100) / stream->timing.v_total / stream->timing.h_total) < 120)
5270 return true;
5271
5272 return false;
5273 }
5274
resource_get_dscl_prog_data(struct pipe_ctx * pipe_ctx)5275 struct dscl_prog_data *resource_get_dscl_prog_data(struct pipe_ctx *pipe_ctx)
5276 {
5277 return &pipe_ctx->plane_res.scl_data.dscl_prog_data;
5278 }
5279
resource_init_common_dml2_callbacks(struct dc * dc,struct dml2_configuration_options * dml2_options)5280 void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuration_options *dml2_options)
5281 {
5282 dml2_options->callbacks.dc = dc;
5283 dml2_options->callbacks.build_scaling_params = &resource_build_scaling_params;
5284 dml2_options->callbacks.build_test_pattern_params = &resource_build_test_pattern_params;
5285 dml2_options->callbacks.acquire_secondary_pipe_for_mpc_odm = &dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;
5286 dml2_options->callbacks.update_pipes_for_stream_with_slice_count = &resource_update_pipes_for_stream_with_slice_count;
5287 dml2_options->callbacks.update_pipes_for_plane_with_slice_count = &resource_update_pipes_for_plane_with_slice_count;
5288 dml2_options->callbacks.get_mpc_slice_index = &resource_get_mpc_slice_index;
5289 dml2_options->callbacks.get_mpc_slice_count = &resource_get_mpc_slice_count;
5290 dml2_options->callbacks.get_odm_slice_index = &resource_get_odm_slice_index;
5291 dml2_options->callbacks.get_odm_slice_count = &resource_get_odm_slice_count;
5292 dml2_options->callbacks.get_opp_head = &resource_get_opp_head;
5293 dml2_options->callbacks.get_otg_master_for_stream = &resource_get_otg_master_for_stream;
5294 dml2_options->callbacks.get_opp_heads_for_otg_master = &resource_get_opp_heads_for_otg_master;
5295 dml2_options->callbacks.get_dpp_pipes_for_plane = &resource_get_dpp_pipes_for_plane;
5296 dml2_options->callbacks.get_stream_status = &dc_state_get_stream_status;
5297 dml2_options->callbacks.get_stream_from_id = &dc_state_get_stream_from_id;
5298 dml2_options->callbacks.get_max_flickerless_instant_vtotal_increase = &dc_stream_get_max_flickerless_instant_vtotal_increase;
5299
5300 dml2_options->svp_pstate.callbacks.dc = dc;
5301 dml2_options->svp_pstate.callbacks.add_phantom_plane = &dc_state_add_phantom_plane;
5302 dml2_options->svp_pstate.callbacks.add_phantom_stream = &dc_state_add_phantom_stream;
5303 dml2_options->svp_pstate.callbacks.build_scaling_params = &resource_build_scaling_params;
5304 dml2_options->svp_pstate.callbacks.create_phantom_plane = &dc_state_create_phantom_plane;
5305 dml2_options->svp_pstate.callbacks.remove_phantom_plane = &dc_state_remove_phantom_plane;
5306 dml2_options->svp_pstate.callbacks.remove_phantom_stream = &dc_state_remove_phantom_stream;
5307 dml2_options->svp_pstate.callbacks.create_phantom_stream = &dc_state_create_phantom_stream;
5308 dml2_options->svp_pstate.callbacks.release_phantom_plane = &dc_state_release_phantom_plane;
5309 dml2_options->svp_pstate.callbacks.release_phantom_stream = &dc_state_release_phantom_stream;
5310 dml2_options->svp_pstate.callbacks.get_pipe_subvp_type = &dc_state_get_pipe_subvp_type;
5311 dml2_options->svp_pstate.callbacks.get_stream_subvp_type = &dc_state_get_stream_subvp_type;
5312 dml2_options->svp_pstate.callbacks.get_paired_subvp_stream = &dc_state_get_paired_subvp_stream;
5313 dml2_options->svp_pstate.callbacks.remove_phantom_streams_and_planes = &dc_state_remove_phantom_streams_and_planes;
5314 dml2_options->svp_pstate.callbacks.release_phantom_streams_and_planes = &dc_state_release_phantom_streams_and_planes;
5315 }
5316
5317 /* Returns number of DET segments allocated for a given OTG_MASTER pipe */
resource_calculate_det_for_stream(struct dc_state * state,struct pipe_ctx * otg_master)5318 int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master)
5319 {
5320 struct pipe_ctx *opp_heads[MAX_PIPES];
5321 struct pipe_ctx *dpp_pipes[MAX_PIPES];
5322
5323 int dpp_count = 0;
5324 int det_segments = 0;
5325
5326 if (!otg_master->stream)
5327 return 0;
5328
5329 int slice_count = resource_get_opp_heads_for_otg_master(otg_master,
5330 &state->res_ctx, opp_heads);
5331
5332 for (int slice_idx = 0; slice_idx < slice_count; slice_idx++) {
5333 if (opp_heads[slice_idx]->plane_state) {
5334 dpp_count = resource_get_dpp_pipes_for_opp_head(
5335 opp_heads[slice_idx],
5336 &state->res_ctx,
5337 dpp_pipes);
5338 for (int dpp_idx = 0; dpp_idx < dpp_count; dpp_idx++)
5339 det_segments += dpp_pipes[dpp_idx]->hubp_regs.det_size;
5340 }
5341 }
5342 return det_segments;
5343 }
5344
resource_is_hpo_acquired(struct dc_state * context)5345 bool resource_is_hpo_acquired(struct dc_state *context)
5346 {
5347 int i;
5348
5349 for (i = 0; i < MAX_HPO_DP2_ENCODERS; i++) {
5350 if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i]) {
5351 return true;
5352 }
5353 }
5354
5355 return false;
5356 }
5357