1 //===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISC-V target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "RISCVBaseInfo.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/Support/raw_ostream.h"
19 #include "llvm/TargetParser/TargetParser.h"
20 #include "llvm/TargetParser/Triple.h"
21
22 namespace llvm {
23
24 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
25
26 namespace RISCVSysReg {
27 #define GET_SysRegsList_IMPL
28 #include "RISCVGenSearchableTables.inc"
29 } // namespace RISCVSysReg
30
31 namespace RISCVInsnOpcode {
32 #define GET_RISCVOpcodesList_IMPL
33 #include "RISCVGenSearchableTables.inc"
34 } // namespace RISCVInsnOpcode
35
36 namespace RISCVVInversePseudosTable {
37 using namespace RISCV;
38 #define GET_RISCVVInversePseudosTable_IMPL
39 #include "RISCVGenSearchableTables.inc"
40 } // namespace RISCVVInversePseudosTable
41
42 namespace RISCV {
43 #define GET_RISCVVSSEGTable_IMPL
44 #define GET_RISCVVLSEGTable_IMPL
45 #define GET_RISCVVLXSEGTable_IMPL
46 #define GET_RISCVVSXSEGTable_IMPL
47 #define GET_RISCVVLETable_IMPL
48 #define GET_RISCVVSETable_IMPL
49 #define GET_RISCVVLXTable_IMPL
50 #define GET_RISCVVSXTable_IMPL
51 #define GET_RISCVNDSVLNTable_IMPL
52 #include "RISCVGenSearchableTables.inc"
53 } // namespace RISCV
54
55 // Report an error but don't ask the user to report a bug.
56 // TODO: Remove these wrappers.
reportError(const char * Reason)57 [[noreturn]] static void reportError(const char *Reason) {
58 reportFatalUsageError(Reason);
59 }
reportError(Error Err)60 [[noreturn]] static void reportError(Error Err) {
61 reportFatalUsageError(std::move(Err));
62 }
63
64 namespace RISCVABI {
computeTargetABI(const Triple & TT,const FeatureBitset & FeatureBits,StringRef ABIName)65 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
66 StringRef ABIName) {
67 auto TargetABI = getTargetABI(ABIName);
68 bool IsRV64 = TT.isArch64Bit();
69 bool IsRVE = FeatureBits[RISCV::FeatureStdExtE];
70
71 if (!ABIName.empty() && TargetABI == ABI_Unknown) {
72 errs()
73 << "'" << ABIName
74 << "' is not a recognized ABI for this target (ignoring target-abi)\n";
75 } else if (ABIName.starts_with("ilp32") && IsRV64) {
76 errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
77 "target-abi)\n";
78 TargetABI = ABI_Unknown;
79 } else if (ABIName.starts_with("lp64") && !IsRV64) {
80 errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
81 "target-abi)\n";
82 TargetABI = ABI_Unknown;
83 } else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E &&
84 TargetABI != ABI_Unknown) {
85 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
86 errs()
87 << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
88 TargetABI = ABI_Unknown;
89 } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E &&
90 TargetABI != ABI_Unknown) {
91 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
92 errs()
93 << "Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n";
94 TargetABI = ABI_Unknown;
95 }
96
97 if ((TargetABI == RISCVABI::ABI::ABI_ILP32E ||
98 (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) &&
99 FeatureBits[RISCV::FeatureStdExtD])
100 reportError("ILP32E cannot be used with the D ISA extension");
101
102 if (TargetABI != ABI_Unknown)
103 return TargetABI;
104
105 // If no explicit ABI is given, try to compute the default ABI.
106 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits);
107 if (!ISAInfo)
108 reportError(ISAInfo.takeError());
109 return getTargetABI((*ISAInfo)->computeDefaultABI());
110 }
111
getTargetABI(StringRef ABIName)112 ABI getTargetABI(StringRef ABIName) {
113 auto TargetABI = StringSwitch<ABI>(ABIName)
114 .Case("ilp32", ABI_ILP32)
115 .Case("ilp32f", ABI_ILP32F)
116 .Case("ilp32d", ABI_ILP32D)
117 .Case("ilp32e", ABI_ILP32E)
118 .Case("lp64", ABI_LP64)
119 .Case("lp64f", ABI_LP64F)
120 .Case("lp64d", ABI_LP64D)
121 .Case("lp64e", ABI_LP64E)
122 .Default(ABI_Unknown);
123 return TargetABI;
124 }
125
126 // To avoid the BP value clobbered by a function call, we need to choose a
127 // callee saved register to save the value. RV32E only has X8 and X9 as callee
128 // saved registers and X8 will be used as fp. So we choose X9 as bp.
getBPReg()129 MCRegister getBPReg() { return RISCV::X9; }
130
131 // Returns the register holding shadow call stack pointer.
getSCSPReg()132 MCRegister getSCSPReg() { return RISCV::X3; }
133
134 } // namespace RISCVABI
135
136 namespace RISCVFeatures {
137
validate(const Triple & TT,const FeatureBitset & FeatureBits)138 void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
139 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
140 reportError("RV64 target requires an RV64 CPU");
141 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
142 reportError("RV32 target requires an RV32 CPU");
143 if (FeatureBits[RISCV::Feature32Bit] &&
144 FeatureBits[RISCV::Feature64Bit])
145 reportError("RV32 and RV64 can't be combined");
146 }
147
148 llvm::Expected<std::unique_ptr<RISCVISAInfo>>
parseFeatureBits(bool IsRV64,const FeatureBitset & FeatureBits)149 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
150 unsigned XLen = IsRV64 ? 64 : 32;
151 std::vector<std::string> FeatureVector;
152 // Convert FeatureBitset to FeatureVector.
153 for (auto Feature : RISCVFeatureKV) {
154 if (FeatureBits[Feature.Value] &&
155 llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
156 FeatureVector.push_back(std::string("+") + Feature.Key);
157 }
158 return llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
159 }
160
161 } // namespace RISCVFeatures
162
163 // Include the auto-generated portion of the compress emitter.
164 #define GEN_UNCOMPRESS_INSTR
165 #define GEN_COMPRESS_INSTR
166 #include "RISCVGenCompressInstEmitter.inc"
167
compress(MCInst & OutInst,const MCInst & MI,const MCSubtargetInfo & STI)168 bool RISCVRVC::compress(MCInst &OutInst, const MCInst &MI,
169 const MCSubtargetInfo &STI) {
170 return compressInst(OutInst, MI, STI);
171 }
172
uncompress(MCInst & OutInst,const MCInst & MI,const MCSubtargetInfo & STI)173 bool RISCVRVC::uncompress(MCInst &OutInst, const MCInst &MI,
174 const MCSubtargetInfo &STI) {
175 return uncompressInst(OutInst, MI, STI);
176 }
177
178 // Lookup table for fli.s for entries 2-31.
179 static constexpr std::pair<uint8_t, uint8_t> LoadFP32ImmArr[] = {
180 {0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00},
181 {0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00},
182 {0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10},
183 {0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01},
184 {0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00},
185 {0b01111111, 0b01}, {0b01111111, 0b10}, {0b01111111, 0b11},
186 {0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10},
187 {0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00},
188 {0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00},
189 {0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10},
190 };
191
getLoadFPImm(APFloat FPImm)192 int RISCVLoadFPImm::getLoadFPImm(APFloat FPImm) {
193 assert((&FPImm.getSemantics() == &APFloat::IEEEsingle() ||
194 &FPImm.getSemantics() == &APFloat::IEEEdouble() ||
195 &FPImm.getSemantics() == &APFloat::IEEEhalf()) &&
196 "Unexpected semantics");
197
198 // Handle the minimum normalized value which is different for each type.
199 if (FPImm.isSmallestNormalized() && !FPImm.isNegative())
200 return 1;
201
202 // Convert to single precision to use its lookup table.
203 bool LosesInfo;
204 APFloat::opStatus Status = FPImm.convert(
205 APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &LosesInfo);
206 if (Status != APFloat::opOK || LosesInfo)
207 return -1;
208
209 APInt Imm = FPImm.bitcastToAPInt();
210
211 if (Imm.extractBitsAsZExtValue(21, 0) != 0)
212 return -1;
213
214 bool Sign = Imm.extractBitsAsZExtValue(1, 31);
215 uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 21);
216 uint8_t Exp = Imm.extractBitsAsZExtValue(8, 23);
217
218 auto EMI = llvm::lower_bound(LoadFP32ImmArr, std::make_pair(Exp, Mantissa));
219 if (EMI == std::end(LoadFP32ImmArr) || EMI->first != Exp ||
220 EMI->second != Mantissa)
221 return -1;
222
223 // Table doesn't have entry 0 or 1.
224 int Entry = std::distance(std::begin(LoadFP32ImmArr), EMI) + 2;
225
226 // The only legal negative value is -1.0(entry 0). 1.0 is entry 16.
227 if (Sign) {
228 if (Entry == 16)
229 return 0;
230 return -1;
231 }
232
233 return Entry;
234 }
235
getFPImm(unsigned Imm)236 float RISCVLoadFPImm::getFPImm(unsigned Imm) {
237 assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate");
238
239 // Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
240 uint32_t Sign = 0;
241 if (Imm == 0) {
242 Sign = 0b1;
243 Imm = 16;
244 }
245
246 uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
247 uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
248
249 uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
250 return bit_cast<float>(I);
251 }
252
printRegList(unsigned RlistEncode,raw_ostream & OS)253 void RISCVZC::printRegList(unsigned RlistEncode, raw_ostream &OS) {
254 assert(RlistEncode >= RLISTENCODE::RA &&
255 RlistEncode <= RLISTENCODE::RA_S0_S11 && "Invalid Rlist");
256 OS << "{ra";
257 if (RlistEncode > RISCVZC::RA) {
258 OS << ", s0";
259 if (RlistEncode == RISCVZC::RA_S0_S11)
260 OS << "-s11";
261 else if (RlistEncode > RISCVZC::RA_S0 && RlistEncode <= RISCVZC::RA_S0_S11)
262 OS << "-s" << (RlistEncode - RISCVZC::RA_S0);
263 }
264 OS << "}";
265 }
266
267 } // namespace llvm
268