1 /*-
2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
3 * Copyright (c) 2014,2016 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * This software was developed by Andrew Turner under
7 * the sponsorship of the FreeBSD Foundation.
8 *
9 * This software was developed by Semihalf under
10 * the sponsorship of the FreeBSD Foundation.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 */
33
34 /* Generic ECAM PCIe driver FDT attachment */
35
36 #include <sys/cdefs.h>
37 #include "opt_platform.h"
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/bus.h>
42 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
45 #include <sys/rman.h>
46
47 #if defined(INTRNG)
48 #include <machine/intr.h>
49 #endif
50
51 #include <dev/ofw/openfirm.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
54 #include <dev/ofw/ofw_pci.h>
55
56 #include <dev/pci/pcivar.h>
57 #include <dev/pci/pcireg.h>
58 #include <dev/pci/pcib_private.h>
59 #include <dev/pci/pci_host_generic.h>
60 #include <dev/pci/pci_host_generic_fdt.h>
61
62 #include <machine/intr.h>
63
64 #include "pcib_if.h"
65
66 #define SPACE_CODE_SHIFT 24
67 #define SPACE_CODE_MASK 0x3
68 #define SPACE_CODE_IO_SPACE 0x1
69 #define PROPS_CELL_SIZE 1
70 #define PCI_ADDR_CELL_SIZE 2
71
72 struct pci_ofw_devinfo {
73 STAILQ_ENTRY(pci_ofw_devinfo) pci_ofw_link;
74 struct ofw_bus_devinfo di_dinfo;
75 uint8_t slot;
76 uint8_t func;
77 uint8_t bus;
78 };
79
80 /* Forward prototypes */
81
82 static int generic_pcie_fdt_probe(device_t dev);
83 static int parse_pci_mem_ranges(device_t, struct generic_pcie_core_softc *);
84 static int generic_pcie_ofw_bus_attach(device_t);
85 static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t,
86 device_t);
87
88 static int
generic_pcie_fdt_probe(device_t dev)89 generic_pcie_fdt_probe(device_t dev)
90 {
91
92 if (!ofw_bus_status_okay(dev))
93 return (ENXIO);
94
95 if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) {
96 device_set_desc(dev, "Generic PCI host controller");
97 return (BUS_PROBE_GENERIC);
98 }
99 if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) {
100 device_set_desc(dev, "GEM5 PCIe host controller");
101 return (BUS_PROBE_DEFAULT);
102 }
103
104 return (ENXIO);
105 }
106
107 int
pci_host_generic_setup_fdt(device_t dev)108 pci_host_generic_setup_fdt(device_t dev)
109 {
110 struct generic_pcie_fdt_softc *sc;
111 phandle_t node;
112 int error;
113
114 sc = device_get_softc(dev);
115
116 STAILQ_INIT(&sc->pci_ofw_devlist);
117
118 /* Retrieve 'ranges' property from FDT */
119 if (bootverbose)
120 device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam);
121 if (parse_pci_mem_ranges(dev, &sc->base))
122 return (ENXIO);
123
124 /* Attach OFW bus */
125 if (generic_pcie_ofw_bus_attach(dev) != 0)
126 return (ENXIO);
127
128 node = ofw_bus_get_node(dev);
129 if (sc->base.coherent == 0) {
130 sc->base.coherent = OF_hasprop(node, "dma-coherent");
131 }
132 if (bootverbose)
133 device_printf(dev, "Bus is%s cache-coherent\n",
134 sc->base.coherent ? "" : " not");
135
136 /* TODO parse FDT bus ranges */
137 sc->base.bus_start = 0;
138 sc->base.bus_end = 0xFF;
139
140 /*
141 * ofw_pcib uses device unit as PCI domain number.
142 * Do the same. Some boards have multiple RCs handled
143 * by different drivers, this ensures that there are
144 * no collisions.
145 */
146 sc->base.ecam = device_get_unit(dev);
147
148 error = pci_host_generic_core_attach(dev);
149 if (error != 0)
150 return (error);
151
152 if (ofw_bus_is_compatible(dev, "marvell,armada8k-pcie-ecam") ||
153 ofw_bus_is_compatible(dev, "socionext,synquacer-pcie-ecam") ||
154 ofw_bus_is_compatible(dev, "snps,dw-pcie-ecam")) {
155 device_set_desc(dev, "Synopsys DesignWare PCIe Controller");
156 sc->base.quirks |= PCIE_ECAM_DESIGNWARE_QUIRK;
157 }
158
159 ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t));
160
161 return (0);
162 }
163
164 int
pci_host_generic_fdt_attach(device_t dev)165 pci_host_generic_fdt_attach(device_t dev)
166 {
167 int error;
168
169 error = pci_host_generic_setup_fdt(dev);
170 if (error != 0)
171 return (error);
172
173 device_add_child(dev, "pci", DEVICE_UNIT_ANY);
174 bus_attach_children(dev);
175 return (0);
176 }
177
178 static int
parse_pci_mem_ranges(device_t dev,struct generic_pcie_core_softc * sc)179 parse_pci_mem_ranges(device_t dev, struct generic_pcie_core_softc *sc)
180 {
181 pcell_t pci_addr_cells, parent_addr_cells;
182 pcell_t attributes, size_cells;
183 cell_t *base_ranges;
184 int nbase_ranges;
185 phandle_t node;
186 int i, j, k;
187
188 node = ofw_bus_get_node(dev);
189
190 OF_getencprop(node, "#address-cells", &pci_addr_cells,
191 sizeof(pci_addr_cells));
192 OF_getencprop(node, "#size-cells", &size_cells,
193 sizeof(size_cells));
194 OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells,
195 sizeof(parent_addr_cells));
196
197 if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) {
198 device_printf(dev,
199 "Unexpected number of address or size cells in FDT\n");
200 return (ENXIO);
201 }
202
203 nbase_ranges = OF_getproplen(node, "ranges");
204 sc->nranges = nbase_ranges / sizeof(cell_t) /
205 (parent_addr_cells + pci_addr_cells + size_cells);
206 base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK);
207 OF_getencprop(node, "ranges", base_ranges, nbase_ranges);
208
209 for (i = 0, j = 0; i < sc->nranges; i++) {
210 attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \
211 SPACE_CODE_MASK;
212 if (attributes == SPACE_CODE_IO_SPACE) {
213 sc->ranges[i].flags |= FLAG_TYPE_IO;
214 } else {
215 sc->ranges[i].flags |= FLAG_TYPE_MEM;
216 }
217
218 sc->ranges[i].rid = -1;
219 sc->ranges[i].pci_base = 0;
220 for (k = 0; k < (pci_addr_cells - 1); k++) {
221 sc->ranges[i].pci_base <<= 32;
222 sc->ranges[i].pci_base |= base_ranges[j++];
223 }
224 sc->ranges[i].phys_base = 0;
225 for (k = 0; k < parent_addr_cells; k++) {
226 sc->ranges[i].phys_base <<= 32;
227 sc->ranges[i].phys_base |= base_ranges[j++];
228 }
229 sc->ranges[i].size = 0;
230 for (k = 0; k < size_cells; k++) {
231 sc->ranges[i].size <<= 32;
232 sc->ranges[i].size |= base_ranges[j++];
233 }
234 }
235
236 for (; i < MAX_RANGES_TUPLES; i++) {
237 /* zero-fill remaining tuples to mark empty elements in array */
238 sc->ranges[i].pci_base = 0;
239 sc->ranges[i].phys_base = 0;
240 sc->ranges[i].size = 0;
241 }
242
243 free(base_ranges, M_DEVBUF);
244 return (0);
245 }
246
247 static int
generic_pcie_fdt_route_interrupt(device_t bus,device_t dev,int pin)248 generic_pcie_fdt_route_interrupt(device_t bus, device_t dev, int pin)
249 {
250 struct generic_pcie_fdt_softc *sc;
251 struct ofw_pci_register reg;
252 uint32_t pintr, mintr[4];
253 phandle_t iparent;
254 int intrcells;
255
256 sc = device_get_softc(bus);
257 pintr = pin;
258
259 bzero(®, sizeof(reg));
260 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
261 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
262 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
263
264 intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev),
265 &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr),
266 mintr, sizeof(mintr), &iparent);
267 if (intrcells) {
268 pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr);
269 return (pintr);
270 }
271
272 device_printf(bus, "could not route pin %d for device %d.%d\n",
273 pin, pci_get_slot(dev), pci_get_function(dev));
274 return (PCI_INVALID_IRQ);
275 }
276
277 static int
generic_pcie_fdt_alloc_msi(device_t pci,device_t child,int count,int maxcount,int * irqs)278 generic_pcie_fdt_alloc_msi(device_t pci, device_t child, int count,
279 int maxcount, int *irqs)
280 {
281 #if defined(INTRNG)
282 phandle_t msi_parent;
283 int err;
284
285 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
286 &msi_parent, NULL);
287 if (err != 0)
288 return (err);
289 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount,
290 irqs));
291 #else
292 return (ENXIO);
293 #endif
294 }
295
296 static int
generic_pcie_fdt_release_msi(device_t pci,device_t child,int count,int * irqs)297 generic_pcie_fdt_release_msi(device_t pci, device_t child, int count, int *irqs)
298 {
299 #if defined(INTRNG)
300 phandle_t msi_parent;
301 int err;
302
303 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
304 &msi_parent, NULL);
305 if (err != 0)
306 return (err);
307 return (intr_release_msi(pci, child, msi_parent, count, irqs));
308 #else
309 return (ENXIO);
310 #endif
311 }
312
313 static int
generic_pcie_fdt_map_msi(device_t pci,device_t child,int irq,uint64_t * addr,uint32_t * data)314 generic_pcie_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
315 uint32_t *data)
316 {
317 #if defined(INTRNG)
318 phandle_t msi_parent;
319 int err;
320
321 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
322 &msi_parent, NULL);
323 if (err != 0)
324 return (err);
325 return (intr_map_msi(pci, child, msi_parent, irq, addr, data));
326 #else
327 return (ENXIO);
328 #endif
329 }
330
331 static int
generic_pcie_fdt_alloc_msix(device_t pci,device_t child,int * irq)332 generic_pcie_fdt_alloc_msix(device_t pci, device_t child, int *irq)
333 {
334 #if defined(INTRNG)
335 phandle_t msi_parent;
336 int err;
337
338 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
339 &msi_parent, NULL);
340 if (err != 0)
341 return (err);
342 return (intr_alloc_msix(pci, child, msi_parent, irq));
343 #else
344 return (ENXIO);
345 #endif
346 }
347
348 static int
generic_pcie_fdt_release_msix(device_t pci,device_t child,int irq)349 generic_pcie_fdt_release_msix(device_t pci, device_t child, int irq)
350 {
351 #if defined(INTRNG)
352 phandle_t msi_parent;
353 int err;
354
355 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
356 &msi_parent, NULL);
357 if (err != 0)
358 return (err);
359 return (intr_release_msix(pci, child, msi_parent, irq));
360 #else
361 return (ENXIO);
362 #endif
363 }
364
365 static int
generic_pcie_get_iommu(device_t pci,device_t child,uintptr_t * id)366 generic_pcie_get_iommu(device_t pci, device_t child, uintptr_t *id)
367 {
368 struct pci_id_ofw_iommu *iommu;
369 uint32_t iommu_rid;
370 uint32_t iommu_xref;
371 uint16_t pci_rid;
372 phandle_t node;
373 int err;
374
375 node = ofw_bus_get_node(pci);
376 pci_rid = pci_get_rid(child);
377
378 iommu = (struct pci_id_ofw_iommu *)id;
379
380 err = ofw_bus_iommu_map(node, pci_rid, &iommu_xref, &iommu_rid);
381 if (err == 0) {
382 iommu->id = iommu_rid;
383 iommu->xref = iommu_xref;
384 }
385
386 return (err);
387 }
388
389 int
generic_pcie_get_id(device_t pci,device_t child,enum pci_id_type type,uintptr_t * id)390 generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type,
391 uintptr_t *id)
392 {
393 phandle_t node;
394 int err;
395 uint32_t rid;
396 uint16_t pci_rid;
397
398 if (type == PCI_ID_OFW_IOMMU)
399 return (generic_pcie_get_iommu(pci, child, id));
400
401 if (type != PCI_ID_MSI)
402 return (pcib_get_id(pci, child, type, id));
403
404 node = ofw_bus_get_node(pci);
405 pci_rid = pci_get_rid(child);
406
407 err = ofw_bus_msimap(node, pci_rid, NULL, &rid);
408 if (err != 0)
409 return (err);
410 *id = rid;
411
412 return (0);
413 }
414
415 static const struct ofw_bus_devinfo *
generic_pcie_ofw_get_devinfo(device_t bus,device_t child)416 generic_pcie_ofw_get_devinfo(device_t bus, device_t child)
417 {
418 struct generic_pcie_fdt_softc *sc;
419 struct pci_ofw_devinfo *di;
420 uint8_t slot, func, busno;
421
422 sc = device_get_softc(bus);
423 slot = pci_get_slot(child);
424 func = pci_get_function(child);
425 busno = pci_get_bus(child);
426
427 STAILQ_FOREACH(di, &sc->pci_ofw_devlist, pci_ofw_link)
428 if (slot == di->slot && func == di->func && busno == di->bus)
429 return (&di->di_dinfo);
430
431 return (NULL);
432 }
433
434 /* Helper functions */
435
436 static int
generic_pcie_ofw_bus_attach(device_t dev)437 generic_pcie_ofw_bus_attach(device_t dev)
438 {
439 struct generic_pcie_fdt_softc *sc;
440 struct pci_ofw_devinfo *di;
441 phandle_t parent, node;
442 pcell_t reg[5];
443 ssize_t len;
444
445 sc = device_get_softc(dev);
446 parent = ofw_bus_get_node(dev);
447 if (parent == 0)
448 return (0);
449
450 /* Iterate through all bus subordinates */
451 for (node = OF_child(parent); node > 0; node = OF_peer(node)) {
452 len = OF_getencprop(node, "reg", reg, sizeof(reg));
453 if (len != 5 * sizeof(pcell_t))
454 continue;
455
456 /* Allocate and populate devinfo. */
457 di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO);
458 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) {
459 free(di, M_DEVBUF);
460 continue;
461 }
462 di->func = OFW_PCI_PHYS_HI_FUNCTION(reg[0]);
463 di->slot = OFW_PCI_PHYS_HI_DEVICE(reg[0]);
464 di->bus = OFW_PCI_PHYS_HI_BUS(reg[0]);
465 STAILQ_INSERT_TAIL(&sc->pci_ofw_devlist, di, pci_ofw_link);
466 }
467
468 return (0);
469 }
470
471 static device_method_t generic_pcie_fdt_methods[] = {
472 DEVMETHOD(device_probe, generic_pcie_fdt_probe),
473 DEVMETHOD(device_attach, pci_host_generic_fdt_attach),
474
475 /* pcib interface */
476 DEVMETHOD(pcib_route_interrupt, generic_pcie_fdt_route_interrupt),
477 DEVMETHOD(pcib_alloc_msi, generic_pcie_fdt_alloc_msi),
478 DEVMETHOD(pcib_release_msi, generic_pcie_fdt_release_msi),
479 DEVMETHOD(pcib_alloc_msix, generic_pcie_fdt_alloc_msix),
480 DEVMETHOD(pcib_release_msix, generic_pcie_fdt_release_msix),
481 DEVMETHOD(pcib_map_msi, generic_pcie_fdt_map_msi),
482 DEVMETHOD(pcib_get_id, generic_pcie_get_id),
483 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
484
485 DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo),
486 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
487 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
488 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
489 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
490 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
491
492 DEVMETHOD_END
493 };
494
495 DEFINE_CLASS_1(pcib, generic_pcie_fdt_driver, generic_pcie_fdt_methods,
496 sizeof(struct generic_pcie_fdt_softc), generic_pcie_core_driver);
497
498 DRIVER_MODULE(pcib, simplebus, generic_pcie_fdt_driver, 0, 0);
499 DRIVER_MODULE(pcib, ofwbus, generic_pcie_fdt_driver, 0, 0);
500