1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/mod_devicetable.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12
13 #include <dt-bindings/clock/qcom,glymur-gcc.h>
14
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
17 #include "clk-pll.h"
18 #include "clk-rcg.h"
19 #include "clk-regmap.h"
20 #include "clk-regmap-divider.h"
21 #include "clk-regmap-mux.h"
22 #include "clk-regmap-phy-mux.h"
23 #include "common.h"
24 #include "gdsc.h"
25 #include "reset.h"
26
27 enum {
28 DT_BI_TCXO,
29 DT_BI_TCXO_AO,
30 DT_SLEEP_CLK,
31 DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
32 DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
33 DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
34 DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
35 DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
36 DT_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC,
37 DT_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC,
38 DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
39 DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
40 DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
41 DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
42 DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
43 DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
44 DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
45 DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
46 DT_PCIE_3A_PIPE_CLK,
47 DT_PCIE_3B_PIPE_CLK,
48 DT_PCIE_4_PIPE_CLK,
49 DT_PCIE_5_PIPE_CLK,
50 DT_PCIE_6_PIPE_CLK,
51 DT_QUSB4PHY_0_GCC_USB4_RX0_CLK,
52 DT_QUSB4PHY_0_GCC_USB4_RX1_CLK,
53 DT_QUSB4PHY_1_GCC_USB4_RX0_CLK,
54 DT_QUSB4PHY_1_GCC_USB4_RX1_CLK,
55 DT_QUSB4PHY_2_GCC_USB4_RX0_CLK,
56 DT_QUSB4PHY_2_GCC_USB4_RX1_CLK,
57 DT_UFS_PHY_RX_SYMBOL_0_CLK,
58 DT_UFS_PHY_RX_SYMBOL_1_CLK,
59 DT_UFS_PHY_TX_SYMBOL_0_CLK,
60 DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,
61 DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,
62 DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,
63 DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK,
64 DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK,
65 DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
66 DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
67 DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
68 DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
69 DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
70 DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
71 };
72
73 enum {
74 P_BI_TCXO,
75 P_GCC_GPLL0_OUT_EVEN,
76 P_GCC_GPLL0_OUT_MAIN,
77 P_GCC_GPLL14_OUT_EVEN,
78 P_GCC_GPLL14_OUT_MAIN,
79 P_GCC_GPLL1_OUT_MAIN,
80 P_GCC_GPLL4_OUT_MAIN,
81 P_GCC_GPLL5_OUT_MAIN,
82 P_GCC_GPLL7_OUT_MAIN,
83 P_GCC_GPLL8_OUT_MAIN,
84 P_GCC_GPLL9_OUT_MAIN,
85 P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC,
86 P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC,
87 P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC,
88 P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
89 P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
90 P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
91 P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
92 P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
93 P_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC,
94 P_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC,
95 P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
96 P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
97 P_GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC,
98 P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
99 P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
100 P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
101 P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
102 P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
103 P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
104 P_PCIE_3A_PIPE_CLK,
105 P_PCIE_3B_PIPE_CLK,
106 P_PCIE_4_PIPE_CLK,
107 P_PCIE_5_PIPE_CLK,
108 P_PCIE_6_PIPE_CLK,
109 P_QUSB4PHY_0_GCC_USB4_RX0_CLK,
110 P_QUSB4PHY_0_GCC_USB4_RX1_CLK,
111 P_QUSB4PHY_1_GCC_USB4_RX0_CLK,
112 P_QUSB4PHY_1_GCC_USB4_RX1_CLK,
113 P_QUSB4PHY_2_GCC_USB4_RX0_CLK,
114 P_QUSB4PHY_2_GCC_USB4_RX1_CLK,
115 P_SLEEP_CLK,
116 P_UFS_PHY_RX_SYMBOL_0_CLK,
117 P_UFS_PHY_RX_SYMBOL_1_CLK,
118 P_UFS_PHY_TX_SYMBOL_0_CLK,
119 P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,
120 P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,
121 P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,
122 P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK,
123 P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK,
124 P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
125 P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
126 P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
127 P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
128 P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
129 P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
130 };
131
132 static struct clk_alpha_pll gcc_gpll0 = {
133 .offset = 0x0,
134 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
135 .clkr = {
136 .enable_reg = 0x62040,
137 .enable_mask = BIT(0),
138 .hw.init = &(const struct clk_init_data) {
139 .name = "gcc_gpll0",
140 .parent_data = &(const struct clk_parent_data) {
141 .index = DT_BI_TCXO,
142 },
143 .num_parents = 1,
144 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
145 },
146 },
147 };
148
149 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
150 { 0x1, 2 },
151 { }
152 };
153
154 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
155 .offset = 0x0,
156 .post_div_shift = 10,
157 .post_div_table = post_div_table_gcc_gpll0_out_even,
158 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
159 .width = 4,
160 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
161 .clkr.hw.init = &(const struct clk_init_data) {
162 .name = "gcc_gpll0_out_even",
163 .parent_hws = (const struct clk_hw*[]) {
164 &gcc_gpll0.clkr.hw,
165 },
166 .num_parents = 1,
167 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops,
168 },
169 };
170
171 static struct clk_alpha_pll gcc_gpll1 = {
172 .offset = 0x1000,
173 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
174 .clkr = {
175 .enable_reg = 0x62040,
176 .enable_mask = BIT(1),
177 .hw.init = &(const struct clk_init_data) {
178 .name = "gcc_gpll1",
179 .parent_data = &(const struct clk_parent_data) {
180 .index = DT_BI_TCXO,
181 },
182 .num_parents = 1,
183 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
184 },
185 },
186 };
187
188 static struct clk_alpha_pll gcc_gpll14 = {
189 .offset = 0xe000,
190 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
191 .clkr = {
192 .enable_reg = 0x62040,
193 .enable_mask = BIT(14),
194 .hw.init = &(const struct clk_init_data) {
195 .name = "gcc_gpll14",
196 .parent_data = &(const struct clk_parent_data) {
197 .index = DT_BI_TCXO,
198 },
199 .num_parents = 1,
200 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
201 },
202 },
203 };
204
205 static const struct clk_div_table post_div_table_gcc_gpll14_out_even[] = {
206 { 0x1, 2 },
207 { }
208 };
209
210 static struct clk_alpha_pll_postdiv gcc_gpll14_out_even = {
211 .offset = 0xe000,
212 .post_div_shift = 10,
213 .post_div_table = post_div_table_gcc_gpll14_out_even,
214 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll14_out_even),
215 .width = 4,
216 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
217 .clkr.hw.init = &(const struct clk_init_data) {
218 .name = "gcc_gpll14_out_even",
219 .parent_hws = (const struct clk_hw*[]) {
220 &gcc_gpll14.clkr.hw,
221 },
222 .num_parents = 1,
223 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops,
224 },
225 };
226
227 static struct clk_alpha_pll gcc_gpll4 = {
228 .offset = 0x4000,
229 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
230 .clkr = {
231 .enable_reg = 0x62040,
232 .enable_mask = BIT(4),
233 .hw.init = &(const struct clk_init_data) {
234 .name = "gcc_gpll4",
235 .parent_data = &(const struct clk_parent_data) {
236 .index = DT_BI_TCXO,
237 },
238 .num_parents = 1,
239 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
240 },
241 },
242 };
243
244 static struct clk_alpha_pll gcc_gpll5 = {
245 .offset = 0x5000,
246 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
247 .clkr = {
248 .enable_reg = 0x62040,
249 .enable_mask = BIT(5),
250 .hw.init = &(const struct clk_init_data) {
251 .name = "gcc_gpll5",
252 .parent_data = &(const struct clk_parent_data) {
253 .index = DT_BI_TCXO,
254 },
255 .num_parents = 1,
256 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
257 },
258 },
259 };
260
261 static struct clk_alpha_pll gcc_gpll7 = {
262 .offset = 0x7000,
263 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
264 .clkr = {
265 .enable_reg = 0x62040,
266 .enable_mask = BIT(7),
267 .hw.init = &(const struct clk_init_data) {
268 .name = "gcc_gpll7",
269 .parent_data = &(const struct clk_parent_data) {
270 .index = DT_BI_TCXO,
271 },
272 .num_parents = 1,
273 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
274 },
275 },
276 };
277
278 static struct clk_alpha_pll gcc_gpll8 = {
279 .offset = 0x8000,
280 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
281 .clkr = {
282 .enable_reg = 0x62040,
283 .enable_mask = BIT(8),
284 .hw.init = &(const struct clk_init_data) {
285 .name = "gcc_gpll8",
286 .parent_data = &(const struct clk_parent_data) {
287 .index = DT_BI_TCXO,
288 },
289 .num_parents = 1,
290 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
291 },
292 },
293 };
294
295 static struct clk_alpha_pll gcc_gpll9 = {
296 .offset = 0x9000,
297 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
298 .clkr = {
299 .enable_reg = 0x62040,
300 .enable_mask = BIT(9),
301 .hw.init = &(const struct clk_init_data) {
302 .name = "gcc_gpll9",
303 .parent_data = &(const struct clk_parent_data) {
304 .index = DT_BI_TCXO,
305 },
306 .num_parents = 1,
307 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
308 },
309 },
310 };
311
312 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src;
313 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src;
314 static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src;
315
316 static struct clk_rcg2 gcc_usb4_1_phy_pll_pipe_clk_src;
317
318 static const struct parent_map gcc_parent_map_0[] = {
319 { P_BI_TCXO, 0 },
320 { P_GCC_GPLL0_OUT_MAIN, 1 },
321 { P_GCC_GPLL0_OUT_EVEN, 6 },
322 };
323
324 static const struct clk_parent_data gcc_parent_data_0[] = {
325 { .index = DT_BI_TCXO },
326 { .hw = &gcc_gpll0.clkr.hw },
327 { .hw = &gcc_gpll0_out_even.clkr.hw },
328 };
329
330 static const struct parent_map gcc_parent_map_1[] = {
331 { P_BI_TCXO, 0 },
332 { P_GCC_GPLL0_OUT_MAIN, 1 },
333 { P_GCC_GPLL1_OUT_MAIN, 4 },
334 { P_GCC_GPLL0_OUT_EVEN, 6 },
335 };
336
337 static const struct clk_parent_data gcc_parent_data_1[] = {
338 { .index = DT_BI_TCXO },
339 { .hw = &gcc_gpll0.clkr.hw },
340 { .hw = &gcc_gpll1.clkr.hw },
341 { .hw = &gcc_gpll0_out_even.clkr.hw },
342 };
343
344 static const struct parent_map gcc_parent_map_2[] = {
345 { P_BI_TCXO, 0 },
346 { P_SLEEP_CLK, 5 },
347 };
348
349 static const struct clk_parent_data gcc_parent_data_2[] = {
350 { .index = DT_BI_TCXO },
351 { .index = DT_SLEEP_CLK },
352 };
353
354 static const struct parent_map gcc_parent_map_3[] = {
355 { P_BI_TCXO, 0 },
356 { P_GCC_GPLL0_OUT_MAIN, 1 },
357 { P_GCC_GPLL1_OUT_MAIN, 4 },
358 { P_GCC_GPLL4_OUT_MAIN, 5 },
359 { P_GCC_GPLL0_OUT_EVEN, 6 },
360 };
361
362 static const struct clk_parent_data gcc_parent_data_3[] = {
363 { .index = DT_BI_TCXO },
364 { .hw = &gcc_gpll0.clkr.hw },
365 { .hw = &gcc_gpll1.clkr.hw },
366 { .hw = &gcc_gpll4.clkr.hw },
367 { .hw = &gcc_gpll0_out_even.clkr.hw },
368 };
369
370 static const struct parent_map gcc_parent_map_4[] = {
371 { P_BI_TCXO, 0 },
372 { P_GCC_GPLL0_OUT_MAIN, 1 },
373 { P_SLEEP_CLK, 5 },
374 { P_GCC_GPLL0_OUT_EVEN, 6 },
375 };
376
377 static const struct clk_parent_data gcc_parent_data_4[] = {
378 { .index = DT_BI_TCXO },
379 { .hw = &gcc_gpll0.clkr.hw },
380 { .index = DT_SLEEP_CLK },
381 { .hw = &gcc_gpll0_out_even.clkr.hw },
382 };
383
384 static const struct parent_map gcc_parent_map_5[] = {
385 { P_BI_TCXO, 0 },
386 };
387
388 static const struct clk_parent_data gcc_parent_data_5[] = {
389 { .index = DT_BI_TCXO },
390 };
391
392 static const struct parent_map gcc_parent_map_6[] = {
393 { P_BI_TCXO, 0 },
394 { P_GCC_GPLL0_OUT_MAIN, 1 },
395 { P_GCC_GPLL4_OUT_MAIN, 5 },
396 { P_GCC_GPLL0_OUT_EVEN, 6 },
397 };
398
399 static const struct clk_parent_data gcc_parent_data_6[] = {
400 { .index = DT_BI_TCXO },
401 { .hw = &gcc_gpll0.clkr.hw },
402 { .hw = &gcc_gpll4.clkr.hw },
403 { .hw = &gcc_gpll0_out_even.clkr.hw },
404 };
405
406 static const struct parent_map gcc_parent_map_7[] = {
407 { P_BI_TCXO, 0 },
408 { P_GCC_GPLL14_OUT_MAIN, 1 },
409 { P_GCC_GPLL14_OUT_EVEN, 6 },
410 };
411
412 static const struct clk_parent_data gcc_parent_data_7[] = {
413 { .index = DT_BI_TCXO },
414 { .hw = &gcc_gpll14.clkr.hw },
415 { .hw = &gcc_gpll14_out_even.clkr.hw },
416 };
417
418 static const struct parent_map gcc_parent_map_8[] = {
419 { P_BI_TCXO, 0 },
420 { P_GCC_GPLL4_OUT_MAIN, 5 },
421 };
422
423 static const struct clk_parent_data gcc_parent_data_8[] = {
424 { .index = DT_BI_TCXO },
425 { .hw = &gcc_gpll4.clkr.hw },
426 };
427
428 static const struct parent_map gcc_parent_map_9[] = {
429 { P_BI_TCXO, 0 },
430 { P_GCC_GPLL0_OUT_MAIN, 1 },
431 { P_GCC_GPLL8_OUT_MAIN, 2 },
432 { P_GCC_GPLL0_OUT_EVEN, 6 },
433 };
434
435 static const struct clk_parent_data gcc_parent_data_9[] = {
436 { .index = DT_BI_TCXO },
437 { .hw = &gcc_gpll0.clkr.hw },
438 { .hw = &gcc_gpll8.clkr.hw },
439 { .hw = &gcc_gpll0_out_even.clkr.hw },
440 };
441
442 static const struct parent_map gcc_parent_map_10[] = {
443 { P_BI_TCXO, 0 },
444 { P_GCC_GPLL0_OUT_MAIN, 1 },
445 { P_GCC_GPLL7_OUT_MAIN, 2 },
446 };
447
448 static const struct clk_parent_data gcc_parent_data_10[] = {
449 { .index = DT_BI_TCXO },
450 { .hw = &gcc_gpll0.clkr.hw },
451 { .hw = &gcc_gpll7.clkr.hw },
452 };
453
454 static const struct parent_map gcc_parent_map_11[] = {
455 { P_BI_TCXO, 0 },
456 { P_GCC_GPLL0_OUT_MAIN, 1 },
457 { P_GCC_GPLL7_OUT_MAIN, 2 },
458 { P_GCC_GPLL8_OUT_MAIN, 3 },
459 { P_SLEEP_CLK, 5 },
460 };
461
462 static const struct clk_parent_data gcc_parent_data_11[] = {
463 { .index = DT_BI_TCXO },
464 { .hw = &gcc_gpll0.clkr.hw },
465 { .hw = &gcc_gpll7.clkr.hw },
466 { .hw = &gcc_gpll8.clkr.hw },
467 { .index = DT_SLEEP_CLK },
468 };
469
470 static const struct parent_map gcc_parent_map_17[] = {
471 { P_BI_TCXO, 0 },
472 { P_GCC_GPLL0_OUT_MAIN, 1 },
473 { P_GCC_GPLL9_OUT_MAIN, 2 },
474 { P_GCC_GPLL4_OUT_MAIN, 5 },
475 { P_GCC_GPLL0_OUT_EVEN, 6 },
476 };
477
478 static const struct clk_parent_data gcc_parent_data_17[] = {
479 { .index = DT_BI_TCXO },
480 { .hw = &gcc_gpll0.clkr.hw },
481 { .hw = &gcc_gpll9.clkr.hw },
482 { .hw = &gcc_gpll4.clkr.hw },
483 { .hw = &gcc_gpll0_out_even.clkr.hw },
484 };
485
486 static const struct parent_map gcc_parent_map_18[] = {
487 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
488 { P_BI_TCXO, 2 },
489 };
490
491 static const struct clk_parent_data gcc_parent_data_18[] = {
492 { .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
493 { .index = DT_BI_TCXO },
494 };
495
496 static const struct parent_map gcc_parent_map_19[] = {
497 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
498 { P_BI_TCXO, 2 },
499 };
500
501 static const struct clk_parent_data gcc_parent_data_19[] = {
502 { .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
503 { .index = DT_BI_TCXO },
504 };
505
506 static const struct parent_map gcc_parent_map_20[] = {
507 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
508 { P_BI_TCXO, 2 },
509 };
510
511 static const struct clk_parent_data gcc_parent_data_20[] = {
512 { .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
513 { .index = DT_BI_TCXO },
514 };
515
516 static const struct parent_map gcc_parent_map_21[] = {
517 { P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },
518 { P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
519 { P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 3 },
520 };
521
522 static const struct clk_parent_data gcc_parent_data_21[] = {
523 { .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw },
524 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
525 { .index = DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC },
526 };
527
528 static const struct parent_map gcc_parent_map_22[] = {
529 { P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 },
530 { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
531 { P_GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC, 2 },
532 { P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 },
533 };
534
535 static const struct clk_parent_data gcc_parent_data_22[] = {
536 { .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw },
537 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
538 { .hw = &gcc_usb4_1_phy_pll_pipe_clk_src.clkr.hw },
539 { .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC },
540 };
541
542 static const struct parent_map gcc_parent_map_23[] = {
543 { P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 0 },
544 { P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
545 { P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 3 },
546 };
547
548 static const struct clk_parent_data gcc_parent_data_23[] = {
549 { .hw = &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw },
550 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
551 { .index = DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC },
552 };
553
554 static const struct parent_map gcc_parent_map_24[] = {
555 { P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 0 },
556 { P_BI_TCXO, 2 },
557 };
558
559 static const struct clk_parent_data gcc_parent_data_24[] = {
560 { .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK },
561 { .index = DT_BI_TCXO },
562 };
563
564 static const struct parent_map gcc_parent_map_25[] = {
565 { P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 0 },
566 { P_BI_TCXO, 2 },
567 };
568
569 static const struct clk_parent_data gcc_parent_data_25[] = {
570 { .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK },
571 { .index = DT_BI_TCXO },
572 };
573
574 static const struct parent_map gcc_parent_map_26[] = {
575 { P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
576 { P_BI_TCXO, 2 },
577 };
578
579 static const struct clk_parent_data gcc_parent_data_26[] = {
580 { .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK },
581 { .index = DT_BI_TCXO },
582 };
583
584 static const struct parent_map gcc_parent_map_27[] = {
585 { P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
586 { P_BI_TCXO, 2 },
587 };
588
589 static const struct clk_parent_data gcc_parent_data_27[] = {
590 { .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK },
591 { .index = DT_BI_TCXO },
592 };
593
594 static const struct parent_map gcc_parent_map_28[] = {
595 { P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
596 { P_BI_TCXO, 2 },
597 };
598
599 static const struct clk_parent_data gcc_parent_data_28[] = {
600 { .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK },
601 { .index = DT_BI_TCXO },
602 };
603
604 static const struct parent_map gcc_parent_map_29[] = {
605 { P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, 0 },
606 { P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
607 };
608
609 static const struct clk_parent_data gcc_parent_data_29[] = {
610 { .index = DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC },
611 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
612 };
613
614 static const struct parent_map gcc_parent_map_30[] = {
615 { P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, 0 },
616 { P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
617 };
618
619 static const struct clk_parent_data gcc_parent_data_30[] = {
620 { .index = DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC },
621 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
622 };
623
624 static const struct parent_map gcc_parent_map_31[] = {
625 { P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
626 { P_BI_TCXO, 2 },
627 };
628
629 static const struct clk_parent_data gcc_parent_data_31[] = {
630 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
631 { .index = DT_BI_TCXO },
632 };
633
634 static const struct parent_map gcc_parent_map_32[] = {
635 { P_BI_TCXO, 0 },
636 { P_GCC_GPLL0_OUT_MAIN, 1 },
637 { P_GCC_GPLL7_OUT_MAIN, 2 },
638 { P_SLEEP_CLK, 5 },
639 };
640
641 static const struct clk_parent_data gcc_parent_data_32[] = {
642 { .index = DT_BI_TCXO },
643 { .hw = &gcc_gpll0.clkr.hw },
644 { .hw = &gcc_gpll7.clkr.hw },
645 { .index = DT_SLEEP_CLK },
646 };
647
648 static const struct parent_map gcc_parent_map_33[] = {
649 { P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
650 { P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
651 };
652
653 static const struct clk_parent_data gcc_parent_data_33[] = {
654 { .index = DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC },
655 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
656 };
657
658 static const struct parent_map gcc_parent_map_34[] = {
659 { P_QUSB4PHY_0_GCC_USB4_RX0_CLK, 0 },
660 { P_BI_TCXO, 2 },
661 };
662
663 static const struct clk_parent_data gcc_parent_data_34[] = {
664 { .index = DT_QUSB4PHY_0_GCC_USB4_RX0_CLK },
665 { .index = DT_BI_TCXO },
666 };
667
668 static const struct parent_map gcc_parent_map_35[] = {
669 { P_QUSB4PHY_0_GCC_USB4_RX1_CLK, 0 },
670 { P_BI_TCXO, 2 },
671 };
672
673 static const struct clk_parent_data gcc_parent_data_35[] = {
674 { .index = DT_QUSB4PHY_0_GCC_USB4_RX1_CLK },
675 { .index = DT_BI_TCXO },
676 };
677
678 static const struct parent_map gcc_parent_map_36[] = {
679 { P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
680 { P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
681 };
682
683 static const struct clk_parent_data gcc_parent_data_36[] = {
684 { .index = DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC },
685 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
686 };
687
688 static const struct parent_map gcc_parent_map_37[] = {
689 { P_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC, 0 },
690 { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
691 };
692
693 static const struct clk_parent_data gcc_parent_data_37[] = {
694 { .index = DT_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC },
695 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
696 };
697
698 static const struct parent_map gcc_parent_map_38[] = {
699 { P_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC, 0 },
700 { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
701 };
702
703 static const struct clk_parent_data gcc_parent_data_38[] = {
704 { .index = DT_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC },
705 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
706 };
707
708 static const struct parent_map gcc_parent_map_39[] = {
709 { P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
710 { P_BI_TCXO, 2 },
711 };
712
713 static const struct clk_parent_data gcc_parent_data_39[] = {
714 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
715 { .index = DT_BI_TCXO },
716 };
717
718 static const struct parent_map gcc_parent_map_40[] = {
719 { P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
720 { P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
721 };
722
723 static const struct clk_parent_data gcc_parent_data_40[] = {
724 { .index = DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC },
725 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
726 };
727
728 static const struct parent_map gcc_parent_map_41[] = {
729 { P_BI_TCXO, 0 },
730 { P_GCC_GPLL0_OUT_MAIN, 1 },
731 { P_GCC_GPLL5_OUT_MAIN, 3 },
732 { P_GCC_GPLL0_OUT_EVEN, 6 },
733 };
734
735 static const struct clk_parent_data gcc_parent_data_41[] = {
736 { .index = DT_BI_TCXO },
737 { .hw = &gcc_gpll0.clkr.hw },
738 { .hw = &gcc_gpll5.clkr.hw },
739 { .hw = &gcc_gpll0_out_even.clkr.hw },
740 };
741
742 static const struct parent_map gcc_parent_map_42[] = {
743 { P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 0 },
744 { P_BI_TCXO, 2 },
745 };
746
747 static const struct clk_parent_data gcc_parent_data_42[] = {
748 { .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK },
749 { .index = DT_BI_TCXO },
750 };
751
752 static const struct parent_map gcc_parent_map_43[] = {
753 { P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 0 },
754 { P_BI_TCXO, 2 },
755 };
756
757 static const struct clk_parent_data gcc_parent_data_43[] = {
758 { .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK },
759 { .index = DT_BI_TCXO },
760 };
761
762 static const struct parent_map gcc_parent_map_44[] = {
763 { P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
764 { P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
765 };
766
767 static const struct clk_parent_data gcc_parent_data_44[] = {
768 { .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },
769 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
770 };
771
772 static const struct parent_map gcc_parent_map_45[] = {
773 { P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, 0 },
774 { P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
775 };
776
777 static const struct clk_parent_data gcc_parent_data_45[] = {
778 { .index = DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC },
779 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
780 };
781
782 static const struct parent_map gcc_parent_map_46[] = {
783 { P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, 0 },
784 { P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
785 };
786
787 static const struct clk_parent_data gcc_parent_data_46[] = {
788 { .index = DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC },
789 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
790 };
791
792 static const struct parent_map gcc_parent_map_47[] = {
793 { P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
794 { P_BI_TCXO, 2 },
795 };
796
797 static const struct clk_parent_data gcc_parent_data_47[] = {
798 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
799 { .index = DT_BI_TCXO },
800 };
801
802 static const struct parent_map gcc_parent_map_48[] = {
803 { P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
804 { P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
805 };
806
807 static const struct clk_parent_data gcc_parent_data_48[] = {
808 { .index = DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC },
809 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
810 };
811
812 static const struct parent_map gcc_parent_map_49[] = {
813 { P_QUSB4PHY_2_GCC_USB4_RX0_CLK, 0 },
814 { P_BI_TCXO, 2 },
815 };
816
817 static const struct clk_parent_data gcc_parent_data_49[] = {
818 { .index = DT_QUSB4PHY_2_GCC_USB4_RX0_CLK },
819 { .index = DT_BI_TCXO },
820 };
821
822 static const struct parent_map gcc_parent_map_50[] = {
823 { P_QUSB4PHY_2_GCC_USB4_RX1_CLK, 0 },
824 { P_BI_TCXO, 2 },
825 };
826
827 static const struct clk_parent_data gcc_parent_data_50[] = {
828 { .index = DT_QUSB4PHY_2_GCC_USB4_RX1_CLK },
829 { .index = DT_BI_TCXO },
830 };
831
832 static const struct parent_map gcc_parent_map_51[] = {
833 { P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
834 { P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
835 };
836
837 static const struct clk_parent_data gcc_parent_data_51[] = {
838 { .index = DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC },
839 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
840 };
841
842 static struct clk_regmap_phy_mux gcc_pcie_3a_pipe_clk_src = {
843 .reg = 0xdc088,
844 .clkr = {
845 .hw.init = &(const struct clk_init_data) {
846 .name = "gcc_pcie_3a_pipe_clk_src",
847 .parent_data = &(const struct clk_parent_data){
848 .index = DT_PCIE_3A_PIPE_CLK,
849 },
850 .num_parents = 1,
851 .ops = &clk_regmap_phy_mux_ops,
852 },
853 },
854 };
855
856 static struct clk_regmap_phy_mux gcc_pcie_3b_pipe_clk_src = {
857 .reg = 0x941b4,
858 .clkr = {
859 .hw.init = &(const struct clk_init_data) {
860 .name = "gcc_pcie_3b_pipe_clk_src",
861 .parent_data = &(const struct clk_parent_data){
862 .index = DT_PCIE_3B_PIPE_CLK,
863 },
864 .num_parents = 1,
865 .ops = &clk_regmap_phy_mux_ops,
866 },
867 },
868 };
869
870 static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = {
871 .reg = 0x881a4,
872 .clkr = {
873 .hw.init = &(const struct clk_init_data) {
874 .name = "gcc_pcie_4_pipe_clk_src",
875 .parent_data = &(const struct clk_parent_data){
876 .index = DT_PCIE_4_PIPE_CLK,
877 },
878 .num_parents = 1,
879 .ops = &clk_regmap_phy_mux_ops,
880 },
881 },
882 };
883
884 static struct clk_regmap_phy_mux gcc_pcie_5_pipe_clk_src = {
885 .reg = 0xc309c,
886 .clkr = {
887 .hw.init = &(const struct clk_init_data) {
888 .name = "gcc_pcie_5_pipe_clk_src",
889 .parent_data = &(const struct clk_parent_data){
890 .index = DT_PCIE_5_PIPE_CLK,
891 },
892 .num_parents = 1,
893 .ops = &clk_regmap_phy_mux_ops,
894 },
895 },
896 };
897
898 static struct clk_regmap_phy_mux gcc_pcie_6_pipe_clk_src = {
899 .reg = 0x8a1a4,
900 .clkr = {
901 .hw.init = &(const struct clk_init_data) {
902 .name = "gcc_pcie_6_pipe_clk_src",
903 .parent_data = &(const struct clk_parent_data){
904 .index = DT_PCIE_6_PIPE_CLK,
905 },
906 .num_parents = 1,
907 .ops = &clk_regmap_phy_mux_ops,
908 },
909 },
910 };
911
912 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
913 .reg = 0x7706c,
914 .shift = 0,
915 .width = 2,
916 .parent_map = gcc_parent_map_18,
917 .clkr = {
918 .hw.init = &(const struct clk_init_data) {
919 .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
920 .parent_data = gcc_parent_data_18,
921 .num_parents = ARRAY_SIZE(gcc_parent_data_18),
922 .ops = &clk_regmap_mux_closest_ops,
923 },
924 },
925 };
926
927 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
928 .reg = 0x770f0,
929 .shift = 0,
930 .width = 2,
931 .parent_map = gcc_parent_map_19,
932 .clkr = {
933 .hw.init = &(const struct clk_init_data) {
934 .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
935 .parent_data = gcc_parent_data_19,
936 .num_parents = ARRAY_SIZE(gcc_parent_data_19),
937 .ops = &clk_regmap_mux_closest_ops,
938 },
939 },
940 };
941
942 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
943 .reg = 0x7705c,
944 .shift = 0,
945 .width = 2,
946 .parent_map = gcc_parent_map_20,
947 .clkr = {
948 .hw.init = &(const struct clk_init_data) {
949 .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
950 .parent_data = gcc_parent_data_20,
951 .num_parents = ARRAY_SIZE(gcc_parent_data_20),
952 .ops = &clk_regmap_mux_closest_ops,
953 },
954 },
955 };
956
957 static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = {
958 .reg = 0x2b0b8,
959 .shift = 0,
960 .width = 2,
961 .parent_map = gcc_parent_map_21,
962 .clkr = {
963 .hw.init = &(const struct clk_init_data) {
964 .name = "gcc_usb34_prim_phy_pipe_clk_src",
965 .parent_data = gcc_parent_data_21,
966 .num_parents = ARRAY_SIZE(gcc_parent_data_21),
967 .ops = &clk_regmap_mux_closest_ops,
968 },
969 },
970 };
971
972 static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = {
973 .reg = 0x2d0c4,
974 .shift = 0,
975 .width = 2,
976 .parent_map = gcc_parent_map_22,
977 .clkr = {
978 .hw.init = &(const struct clk_init_data) {
979 .name = "gcc_usb34_sec_phy_pipe_clk_src",
980 .parent_data = gcc_parent_data_22,
981 .num_parents = ARRAY_SIZE(gcc_parent_data_22),
982 .ops = &clk_regmap_mux_closest_ops,
983 },
984 },
985 };
986
987 static struct clk_regmap_mux gcc_usb34_tert_phy_pipe_clk_src = {
988 .reg = 0xe00bc,
989 .shift = 0,
990 .width = 2,
991 .parent_map = gcc_parent_map_23,
992 .clkr = {
993 .hw.init = &(const struct clk_init_data) {
994 .name = "gcc_usb34_tert_phy_pipe_clk_src",
995 .parent_data = gcc_parent_data_23,
996 .num_parents = ARRAY_SIZE(gcc_parent_data_23),
997 .ops = &clk_regmap_mux_closest_ops,
998 },
999 },
1000 };
1001
1002 static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_0_clk_src = {
1003 .reg = 0x9a07c,
1004 .shift = 0,
1005 .width = 2,
1006 .parent_map = gcc_parent_map_24,
1007 .clkr = {
1008 .hw.init = &(const struct clk_init_data) {
1009 .name = "gcc_usb3_mp_phy_pipe_0_clk_src",
1010 .parent_data = gcc_parent_data_24,
1011 .num_parents = ARRAY_SIZE(gcc_parent_data_24),
1012 .ops = &clk_regmap_mux_closest_ops,
1013 },
1014 },
1015 };
1016
1017 static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_1_clk_src = {
1018 .reg = 0x9a084,
1019 .shift = 0,
1020 .width = 2,
1021 .parent_map = gcc_parent_map_25,
1022 .clkr = {
1023 .hw.init = &(const struct clk_init_data) {
1024 .name = "gcc_usb3_mp_phy_pipe_1_clk_src",
1025 .parent_data = gcc_parent_data_25,
1026 .num_parents = ARRAY_SIZE(gcc_parent_data_25),
1027 .ops = &clk_regmap_mux_closest_ops,
1028 },
1029 },
1030 };
1031
1032 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
1033 .reg = 0x3f08c,
1034 .shift = 0,
1035 .width = 2,
1036 .parent_map = gcc_parent_map_26,
1037 .clkr = {
1038 .hw.init = &(const struct clk_init_data) {
1039 .name = "gcc_usb3_prim_phy_pipe_clk_src",
1040 .parent_data = gcc_parent_data_26,
1041 .num_parents = ARRAY_SIZE(gcc_parent_data_26),
1042 .ops = &clk_regmap_mux_closest_ops,
1043 },
1044 },
1045 };
1046
1047 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
1048 .reg = 0xe207c,
1049 .shift = 0,
1050 .width = 2,
1051 .parent_map = gcc_parent_map_27,
1052 .clkr = {
1053 .hw.init = &(const struct clk_init_data) {
1054 .name = "gcc_usb3_sec_phy_pipe_clk_src",
1055 .parent_data = gcc_parent_data_27,
1056 .num_parents = ARRAY_SIZE(gcc_parent_data_27),
1057 .ops = &clk_regmap_mux_closest_ops,
1058 },
1059 },
1060 };
1061
1062 static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = {
1063 .reg = 0xe107c,
1064 .shift = 0,
1065 .width = 2,
1066 .parent_map = gcc_parent_map_28,
1067 .clkr = {
1068 .hw.init = &(const struct clk_init_data) {
1069 .name = "gcc_usb3_tert_phy_pipe_clk_src",
1070 .parent_data = gcc_parent_data_28,
1071 .num_parents = ARRAY_SIZE(gcc_parent_data_28),
1072 .ops = &clk_regmap_mux_closest_ops,
1073 },
1074 },
1075 };
1076
1077 static struct clk_regmap_mux gcc_usb4_0_phy_dp0_clk_src = {
1078 .reg = 0x2b080,
1079 .shift = 0,
1080 .width = 2,
1081 .parent_map = gcc_parent_map_29,
1082 .clkr = {
1083 .hw.init = &(const struct clk_init_data) {
1084 .name = "gcc_usb4_0_phy_dp0_clk_src",
1085 .parent_data = gcc_parent_data_29,
1086 .num_parents = ARRAY_SIZE(gcc_parent_data_29),
1087 .ops = &clk_regmap_mux_closest_ops,
1088 },
1089 },
1090 };
1091
1092 static struct clk_regmap_mux gcc_usb4_0_phy_dp1_clk_src = {
1093 .reg = 0x2b134,
1094 .shift = 0,
1095 .width = 2,
1096 .parent_map = gcc_parent_map_30,
1097 .clkr = {
1098 .hw.init = &(const struct clk_init_data) {
1099 .name = "gcc_usb4_0_phy_dp1_clk_src",
1100 .parent_data = gcc_parent_data_30,
1101 .num_parents = ARRAY_SIZE(gcc_parent_data_30),
1102 .ops = &clk_regmap_mux_closest_ops,
1103 },
1104 },
1105 };
1106
1107 static struct clk_regmap_mux gcc_usb4_0_phy_p2rr2p_pipe_clk_src = {
1108 .reg = 0x2b0f0,
1109 .shift = 0,
1110 .width = 2,
1111 .parent_map = gcc_parent_map_31,
1112 .clkr = {
1113 .hw.init = &(const struct clk_init_data) {
1114 .name = "gcc_usb4_0_phy_p2rr2p_pipe_clk_src",
1115 .parent_data = gcc_parent_data_31,
1116 .num_parents = ARRAY_SIZE(gcc_parent_data_31),
1117 .ops = &clk_regmap_mux_closest_ops,
1118 },
1119 },
1120 };
1121
1122 static struct clk_regmap_mux gcc_usb4_0_phy_pcie_pipe_mux_clk_src = {
1123 .reg = 0x2b120,
1124 .shift = 0,
1125 .width = 1,
1126 .parent_map = gcc_parent_map_33,
1127 .clkr = {
1128 .hw.init = &(const struct clk_init_data) {
1129 .name = "gcc_usb4_0_phy_pcie_pipe_mux_clk_src",
1130 .parent_data = gcc_parent_data_33,
1131 .num_parents = ARRAY_SIZE(gcc_parent_data_33),
1132 .ops = &clk_regmap_mux_closest_ops,
1133 },
1134 },
1135 };
1136
1137 static struct clk_regmap_mux gcc_usb4_0_phy_rx0_clk_src = {
1138 .reg = 0x2b0c0,
1139 .shift = 0,
1140 .width = 2,
1141 .parent_map = gcc_parent_map_34,
1142 .clkr = {
1143 .hw.init = &(const struct clk_init_data) {
1144 .name = "gcc_usb4_0_phy_rx0_clk_src",
1145 .parent_data = gcc_parent_data_34,
1146 .num_parents = ARRAY_SIZE(gcc_parent_data_34),
1147 .ops = &clk_regmap_mux_closest_ops,
1148 },
1149 },
1150 };
1151
1152 static struct clk_regmap_mux gcc_usb4_0_phy_rx1_clk_src = {
1153 .reg = 0x2b0d4,
1154 .shift = 0,
1155 .width = 2,
1156 .parent_map = gcc_parent_map_35,
1157 .clkr = {
1158 .hw.init = &(const struct clk_init_data) {
1159 .name = "gcc_usb4_0_phy_rx1_clk_src",
1160 .parent_data = gcc_parent_data_35,
1161 .num_parents = ARRAY_SIZE(gcc_parent_data_35),
1162 .ops = &clk_regmap_mux_closest_ops,
1163 },
1164 },
1165 };
1166
1167 static struct clk_regmap_mux gcc_usb4_0_phy_sys_clk_src = {
1168 .reg = 0x2b100,
1169 .shift = 0,
1170 .width = 2,
1171 .parent_map = gcc_parent_map_36,
1172 .clkr = {
1173 .hw.init = &(const struct clk_init_data) {
1174 .name = "gcc_usb4_0_phy_sys_clk_src",
1175 .parent_data = gcc_parent_data_36,
1176 .num_parents = ARRAY_SIZE(gcc_parent_data_36),
1177 .ops = &clk_regmap_mux_closest_ops,
1178 },
1179 },
1180 };
1181
1182 static struct clk_regmap_mux gcc_usb4_1_phy_dp0_clk_src = {
1183 .reg = 0x2d08c,
1184 .shift = 0,
1185 .width = 2,
1186 .parent_map = gcc_parent_map_37,
1187 .clkr = {
1188 .hw.init = &(const struct clk_init_data) {
1189 .name = "gcc_usb4_1_phy_dp0_clk_src",
1190 .parent_data = gcc_parent_data_37,
1191 .num_parents = ARRAY_SIZE(gcc_parent_data_37),
1192 .ops = &clk_regmap_mux_closest_ops,
1193 },
1194 },
1195 };
1196
1197 static struct clk_regmap_mux gcc_usb4_1_phy_dp1_clk_src = {
1198 .reg = 0x2d154,
1199 .shift = 0,
1200 .width = 2,
1201 .parent_map = gcc_parent_map_38,
1202 .clkr = {
1203 .hw.init = &(const struct clk_init_data) {
1204 .name = "gcc_usb4_1_phy_dp1_clk_src",
1205 .parent_data = gcc_parent_data_38,
1206 .num_parents = ARRAY_SIZE(gcc_parent_data_38),
1207 .ops = &clk_regmap_mux_closest_ops,
1208 },
1209 },
1210 };
1211
1212 static struct clk_regmap_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = {
1213 .reg = 0x2d114,
1214 .shift = 0,
1215 .width = 2,
1216 .parent_map = gcc_parent_map_39,
1217 .clkr = {
1218 .hw.init = &(const struct clk_init_data) {
1219 .name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src",
1220 .parent_data = gcc_parent_data_39,
1221 .num_parents = ARRAY_SIZE(gcc_parent_data_39),
1222 .ops = &clk_regmap_mux_closest_ops,
1223 },
1224 },
1225 };
1226
1227 static struct clk_regmap_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = {
1228 .reg = 0x2d140,
1229 .shift = 0,
1230 .width = 1,
1231 .parent_map = gcc_parent_map_40,
1232 .clkr = {
1233 .hw.init = &(const struct clk_init_data) {
1234 .name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src",
1235 .parent_data = gcc_parent_data_40,
1236 .num_parents = ARRAY_SIZE(gcc_parent_data_40),
1237 .ops = &clk_regmap_mux_closest_ops,
1238 },
1239 },
1240 };
1241
1242 static struct clk_regmap_mux gcc_usb4_1_phy_rx0_clk_src = {
1243 .reg = 0x2d0e4,
1244 .shift = 0,
1245 .width = 2,
1246 .parent_map = gcc_parent_map_42,
1247 .clkr = {
1248 .hw.init = &(const struct clk_init_data) {
1249 .name = "gcc_usb4_1_phy_rx0_clk_src",
1250 .parent_data = gcc_parent_data_42,
1251 .num_parents = ARRAY_SIZE(gcc_parent_data_42),
1252 .ops = &clk_regmap_mux_closest_ops,
1253 },
1254 },
1255 };
1256
1257 static struct clk_regmap_mux gcc_usb4_1_phy_rx1_clk_src = {
1258 .reg = 0x2d0f8,
1259 .shift = 0,
1260 .width = 2,
1261 .parent_map = gcc_parent_map_43,
1262 .clkr = {
1263 .hw.init = &(const struct clk_init_data) {
1264 .name = "gcc_usb4_1_phy_rx1_clk_src",
1265 .parent_data = gcc_parent_data_43,
1266 .num_parents = ARRAY_SIZE(gcc_parent_data_43),
1267 .ops = &clk_regmap_mux_closest_ops,
1268 },
1269 },
1270 };
1271
1272 static struct clk_regmap_mux gcc_usb4_1_phy_sys_clk_src = {
1273 .reg = 0x2d124,
1274 .shift = 0,
1275 .width = 2,
1276 .parent_map = gcc_parent_map_44,
1277 .clkr = {
1278 .hw.init = &(const struct clk_init_data) {
1279 .name = "gcc_usb4_1_phy_sys_clk_src",
1280 .parent_data = gcc_parent_data_44,
1281 .num_parents = ARRAY_SIZE(gcc_parent_data_44),
1282 .ops = &clk_regmap_mux_closest_ops,
1283 },
1284 },
1285 };
1286
1287 static struct clk_regmap_mux gcc_usb4_2_phy_dp0_clk_src = {
1288 .reg = 0xe0084,
1289 .shift = 0,
1290 .width = 2,
1291 .parent_map = gcc_parent_map_45,
1292 .clkr = {
1293 .hw.init = &(const struct clk_init_data) {
1294 .name = "gcc_usb4_2_phy_dp0_clk_src",
1295 .parent_data = gcc_parent_data_45,
1296 .num_parents = ARRAY_SIZE(gcc_parent_data_45),
1297 .ops = &clk_regmap_mux_closest_ops,
1298 },
1299 },
1300 };
1301
1302 static struct clk_regmap_mux gcc_usb4_2_phy_dp1_clk_src = {
1303 .reg = 0xe013c,
1304 .shift = 0,
1305 .width = 2,
1306 .parent_map = gcc_parent_map_46,
1307 .clkr = {
1308 .hw.init = &(const struct clk_init_data) {
1309 .name = "gcc_usb4_2_phy_dp1_clk_src",
1310 .parent_data = gcc_parent_data_46,
1311 .num_parents = ARRAY_SIZE(gcc_parent_data_46),
1312 .ops = &clk_regmap_mux_closest_ops,
1313 },
1314 },
1315 };
1316
1317 static struct clk_regmap_mux gcc_usb4_2_phy_p2rr2p_pipe_clk_src = {
1318 .reg = 0xe00f4,
1319 .shift = 0,
1320 .width = 2,
1321 .parent_map = gcc_parent_map_47,
1322 .clkr = {
1323 .hw.init = &(const struct clk_init_data) {
1324 .name = "gcc_usb4_2_phy_p2rr2p_pipe_clk_src",
1325 .parent_data = gcc_parent_data_47,
1326 .num_parents = ARRAY_SIZE(gcc_parent_data_47),
1327 .ops = &clk_regmap_mux_closest_ops,
1328 },
1329 },
1330 };
1331
1332 static struct clk_regmap_mux gcc_usb4_2_phy_pcie_pipe_mux_clk_src = {
1333 .reg = 0xe0124,
1334 .shift = 0,
1335 .width = 1,
1336 .parent_map = gcc_parent_map_48,
1337 .clkr = {
1338 .hw.init = &(const struct clk_init_data) {
1339 .name = "gcc_usb4_2_phy_pcie_pipe_mux_clk_src",
1340 .parent_data = gcc_parent_data_48,
1341 .num_parents = ARRAY_SIZE(gcc_parent_data_48),
1342 .ops = &clk_regmap_mux_closest_ops,
1343 },
1344 },
1345 };
1346
1347 static struct clk_regmap_mux gcc_usb4_2_phy_rx0_clk_src = {
1348 .reg = 0xe00c4,
1349 .shift = 0,
1350 .width = 2,
1351 .parent_map = gcc_parent_map_49,
1352 .clkr = {
1353 .hw.init = &(const struct clk_init_data) {
1354 .name = "gcc_usb4_2_phy_rx0_clk_src",
1355 .parent_data = gcc_parent_data_49,
1356 .num_parents = ARRAY_SIZE(gcc_parent_data_49),
1357 .ops = &clk_regmap_mux_closest_ops,
1358 },
1359 },
1360 };
1361
1362 static struct clk_regmap_mux gcc_usb4_2_phy_rx1_clk_src = {
1363 .reg = 0xe00d8,
1364 .shift = 0,
1365 .width = 2,
1366 .parent_map = gcc_parent_map_50,
1367 .clkr = {
1368 .hw.init = &(const struct clk_init_data) {
1369 .name = "gcc_usb4_2_phy_rx1_clk_src",
1370 .parent_data = gcc_parent_data_50,
1371 .num_parents = ARRAY_SIZE(gcc_parent_data_50),
1372 .ops = &clk_regmap_mux_closest_ops,
1373 },
1374 },
1375 };
1376
1377 static struct clk_regmap_mux gcc_usb4_2_phy_sys_clk_src = {
1378 .reg = 0xe0104,
1379 .shift = 0,
1380 .width = 2,
1381 .parent_map = gcc_parent_map_51,
1382 .clkr = {
1383 .hw.init = &(const struct clk_init_data) {
1384 .name = "gcc_usb4_2_phy_sys_clk_src",
1385 .parent_data = gcc_parent_data_51,
1386 .num_parents = ARRAY_SIZE(gcc_parent_data_51),
1387 .ops = &clk_regmap_mux_closest_ops,
1388 },
1389 },
1390 };
1391
1392 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
1393 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1394 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1395 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1396 { }
1397 };
1398
1399 static struct clk_rcg2 gcc_gp1_clk_src = {
1400 .cmd_rcgr = 0x64004,
1401 .mnd_width = 16,
1402 .hid_width = 5,
1403 .parent_map = gcc_parent_map_4,
1404 .freq_tbl = ftbl_gcc_gp1_clk_src,
1405 .clkr.hw.init = &(const struct clk_init_data) {
1406 .name = "gcc_gp1_clk_src",
1407 .parent_data = gcc_parent_data_4,
1408 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
1409 .flags = CLK_SET_RATE_PARENT,
1410 .ops = &clk_rcg2_shared_no_init_park_ops,
1411 },
1412 };
1413
1414 static struct clk_rcg2 gcc_gp2_clk_src = {
1415 .cmd_rcgr = 0x92004,
1416 .mnd_width = 16,
1417 .hid_width = 5,
1418 .parent_map = gcc_parent_map_4,
1419 .freq_tbl = ftbl_gcc_gp1_clk_src,
1420 .clkr.hw.init = &(const struct clk_init_data) {
1421 .name = "gcc_gp2_clk_src",
1422 .parent_data = gcc_parent_data_4,
1423 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
1424 .flags = CLK_SET_RATE_PARENT,
1425 .ops = &clk_rcg2_shared_no_init_park_ops,
1426 },
1427 };
1428
1429 static struct clk_rcg2 gcc_gp3_clk_src = {
1430 .cmd_rcgr = 0x93004,
1431 .mnd_width = 16,
1432 .hid_width = 5,
1433 .parent_map = gcc_parent_map_4,
1434 .freq_tbl = ftbl_gcc_gp1_clk_src,
1435 .clkr.hw.init = &(const struct clk_init_data) {
1436 .name = "gcc_gp3_clk_src",
1437 .parent_data = gcc_parent_data_4,
1438 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
1439 .flags = CLK_SET_RATE_PARENT,
1440 .ops = &clk_rcg2_shared_no_init_park_ops,
1441 },
1442 };
1443
1444 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
1445 F(19200000, P_BI_TCXO, 1, 0, 0),
1446 { }
1447 };
1448
1449 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
1450 .cmd_rcgr = 0xc8168,
1451 .mnd_width = 16,
1452 .hid_width = 5,
1453 .parent_map = gcc_parent_map_2,
1454 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1455 .clkr.hw.init = &(const struct clk_init_data) {
1456 .name = "gcc_pcie_0_aux_clk_src",
1457 .parent_data = gcc_parent_data_2,
1458 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1459 .flags = CLK_SET_RATE_PARENT,
1460 .ops = &clk_rcg2_shared_no_init_park_ops,
1461 },
1462 };
1463
1464 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
1465 F(19200000, P_BI_TCXO, 1, 0, 0),
1466 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1467 { }
1468 };
1469
1470 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
1471 .cmd_rcgr = 0xc803c,
1472 .mnd_width = 0,
1473 .hid_width = 5,
1474 .parent_map = gcc_parent_map_0,
1475 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1476 .clkr.hw.init = &(const struct clk_init_data) {
1477 .name = "gcc_pcie_0_phy_rchng_clk_src",
1478 .parent_data = gcc_parent_data_0,
1479 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1480 .flags = CLK_SET_RATE_PARENT,
1481 .ops = &clk_rcg2_shared_no_init_park_ops,
1482 },
1483 };
1484
1485 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
1486 .cmd_rcgr = 0x2e168,
1487 .mnd_width = 16,
1488 .hid_width = 5,
1489 .parent_map = gcc_parent_map_2,
1490 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1491 .clkr.hw.init = &(const struct clk_init_data) {
1492 .name = "gcc_pcie_1_aux_clk_src",
1493 .parent_data = gcc_parent_data_2,
1494 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1495 .flags = CLK_SET_RATE_PARENT,
1496 .ops = &clk_rcg2_shared_no_init_park_ops,
1497 },
1498 };
1499
1500 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
1501 .cmd_rcgr = 0x2e03c,
1502 .mnd_width = 0,
1503 .hid_width = 5,
1504 .parent_map = gcc_parent_map_0,
1505 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1506 .clkr.hw.init = &(const struct clk_init_data) {
1507 .name = "gcc_pcie_1_phy_rchng_clk_src",
1508 .parent_data = gcc_parent_data_0,
1509 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1510 .flags = CLK_SET_RATE_PARENT,
1511 .ops = &clk_rcg2_shared_no_init_park_ops,
1512 },
1513 };
1514
1515 static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
1516 .cmd_rcgr = 0xc0168,
1517 .mnd_width = 16,
1518 .hid_width = 5,
1519 .parent_map = gcc_parent_map_2,
1520 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1521 .clkr.hw.init = &(const struct clk_init_data) {
1522 .name = "gcc_pcie_2_aux_clk_src",
1523 .parent_data = gcc_parent_data_2,
1524 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1525 .flags = CLK_SET_RATE_PARENT,
1526 .ops = &clk_rcg2_shared_no_init_park_ops,
1527 },
1528 };
1529
1530 static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = {
1531 .cmd_rcgr = 0xc003c,
1532 .mnd_width = 0,
1533 .hid_width = 5,
1534 .parent_map = gcc_parent_map_0,
1535 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1536 .clkr.hw.init = &(const struct clk_init_data) {
1537 .name = "gcc_pcie_2_phy_rchng_clk_src",
1538 .parent_data = gcc_parent_data_0,
1539 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1540 .flags = CLK_SET_RATE_PARENT,
1541 .ops = &clk_rcg2_shared_no_init_park_ops,
1542 },
1543 };
1544
1545 static struct clk_rcg2 gcc_pcie_3a_aux_clk_src = {
1546 .cmd_rcgr = 0xdc08c,
1547 .mnd_width = 16,
1548 .hid_width = 5,
1549 .parent_map = gcc_parent_map_2,
1550 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1551 .clkr.hw.init = &(const struct clk_init_data) {
1552 .name = "gcc_pcie_3a_aux_clk_src",
1553 .parent_data = gcc_parent_data_2,
1554 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1555 .flags = CLK_SET_RATE_PARENT,
1556 .ops = &clk_rcg2_shared_no_init_park_ops,
1557 },
1558 };
1559
1560 static struct clk_rcg2 gcc_pcie_3a_phy_rchng_clk_src = {
1561 .cmd_rcgr = 0xdc070,
1562 .mnd_width = 0,
1563 .hid_width = 5,
1564 .parent_map = gcc_parent_map_0,
1565 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1566 .clkr.hw.init = &(const struct clk_init_data) {
1567 .name = "gcc_pcie_3a_phy_rchng_clk_src",
1568 .parent_data = gcc_parent_data_0,
1569 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1570 .flags = CLK_SET_RATE_PARENT,
1571 .ops = &clk_rcg2_shared_no_init_park_ops,
1572 },
1573 };
1574
1575 static struct clk_rcg2 gcc_pcie_3b_aux_clk_src = {
1576 .cmd_rcgr = 0x941b8,
1577 .mnd_width = 16,
1578 .hid_width = 5,
1579 .parent_map = gcc_parent_map_2,
1580 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1581 .clkr.hw.init = &(const struct clk_init_data) {
1582 .name = "gcc_pcie_3b_aux_clk_src",
1583 .parent_data = gcc_parent_data_2,
1584 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1585 .flags = CLK_SET_RATE_PARENT,
1586 .ops = &clk_rcg2_shared_no_init_park_ops,
1587 },
1588 };
1589
1590 static struct clk_rcg2 gcc_pcie_3b_phy_rchng_clk_src = {
1591 .cmd_rcgr = 0x94088,
1592 .mnd_width = 0,
1593 .hid_width = 5,
1594 .parent_map = gcc_parent_map_0,
1595 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1596 .clkr.hw.init = &(const struct clk_init_data) {
1597 .name = "gcc_pcie_3b_phy_rchng_clk_src",
1598 .parent_data = gcc_parent_data_0,
1599 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1600 .flags = CLK_SET_RATE_PARENT,
1601 .ops = &clk_rcg2_shared_no_init_park_ops,
1602 },
1603 };
1604
1605 static struct clk_rcg2 gcc_pcie_4_aux_clk_src = {
1606 .cmd_rcgr = 0x881a8,
1607 .mnd_width = 16,
1608 .hid_width = 5,
1609 .parent_map = gcc_parent_map_2,
1610 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1611 .clkr.hw.init = &(const struct clk_init_data) {
1612 .name = "gcc_pcie_4_aux_clk_src",
1613 .parent_data = gcc_parent_data_2,
1614 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1615 .flags = CLK_SET_RATE_PARENT,
1616 .ops = &clk_rcg2_shared_no_init_park_ops,
1617 },
1618 };
1619
1620 static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = {
1621 .cmd_rcgr = 0x88078,
1622 .mnd_width = 0,
1623 .hid_width = 5,
1624 .parent_map = gcc_parent_map_0,
1625 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1626 .clkr.hw.init = &(const struct clk_init_data) {
1627 .name = "gcc_pcie_4_phy_rchng_clk_src",
1628 .parent_data = gcc_parent_data_0,
1629 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1630 .flags = CLK_SET_RATE_PARENT,
1631 .ops = &clk_rcg2_shared_no_init_park_ops,
1632 },
1633 };
1634
1635 static struct clk_rcg2 gcc_pcie_5_aux_clk_src = {
1636 .cmd_rcgr = 0xc30a0,
1637 .mnd_width = 16,
1638 .hid_width = 5,
1639 .parent_map = gcc_parent_map_2,
1640 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1641 .clkr.hw.init = &(const struct clk_init_data) {
1642 .name = "gcc_pcie_5_aux_clk_src",
1643 .parent_data = gcc_parent_data_2,
1644 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1645 .flags = CLK_SET_RATE_PARENT,
1646 .ops = &clk_rcg2_shared_no_init_park_ops,
1647 },
1648 };
1649
1650 static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = {
1651 .cmd_rcgr = 0xc3084,
1652 .mnd_width = 0,
1653 .hid_width = 5,
1654 .parent_map = gcc_parent_map_0,
1655 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1656 .clkr.hw.init = &(const struct clk_init_data) {
1657 .name = "gcc_pcie_5_phy_rchng_clk_src",
1658 .parent_data = gcc_parent_data_0,
1659 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1660 .flags = CLK_SET_RATE_PARENT,
1661 .ops = &clk_rcg2_shared_no_init_park_ops,
1662 },
1663 };
1664
1665 static struct clk_rcg2 gcc_pcie_6_aux_clk_src = {
1666 .cmd_rcgr = 0x8a1a8,
1667 .mnd_width = 16,
1668 .hid_width = 5,
1669 .parent_map = gcc_parent_map_2,
1670 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1671 .clkr.hw.init = &(const struct clk_init_data) {
1672 .name = "gcc_pcie_6_aux_clk_src",
1673 .parent_data = gcc_parent_data_2,
1674 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1675 .flags = CLK_SET_RATE_PARENT,
1676 .ops = &clk_rcg2_shared_no_init_park_ops,
1677 },
1678 };
1679
1680 static struct clk_rcg2 gcc_pcie_6_phy_rchng_clk_src = {
1681 .cmd_rcgr = 0x8a078,
1682 .mnd_width = 0,
1683 .hid_width = 5,
1684 .parent_map = gcc_parent_map_0,
1685 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1686 .clkr.hw.init = &(const struct clk_init_data) {
1687 .name = "gcc_pcie_6_phy_rchng_clk_src",
1688 .parent_data = gcc_parent_data_0,
1689 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1690 .flags = CLK_SET_RATE_PARENT,
1691 .ops = &clk_rcg2_shared_no_init_park_ops,
1692 },
1693 };
1694
1695 static struct clk_rcg2 gcc_pcie_phy_3a_aux_clk_src = {
1696 .cmd_rcgr = 0x6c01c,
1697 .mnd_width = 16,
1698 .hid_width = 5,
1699 .parent_map = gcc_parent_map_2,
1700 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1701 .clkr.hw.init = &(const struct clk_init_data) {
1702 .name = "gcc_pcie_phy_3a_aux_clk_src",
1703 .parent_data = gcc_parent_data_2,
1704 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1705 .flags = CLK_SET_RATE_PARENT,
1706 .ops = &clk_rcg2_shared_no_init_park_ops,
1707 },
1708 };
1709
1710 static struct clk_rcg2 gcc_pcie_phy_3b_aux_clk_src = {
1711 .cmd_rcgr = 0x7501c,
1712 .mnd_width = 16,
1713 .hid_width = 5,
1714 .parent_map = gcc_parent_map_2,
1715 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1716 .clkr.hw.init = &(const struct clk_init_data) {
1717 .name = "gcc_pcie_phy_3b_aux_clk_src",
1718 .parent_data = gcc_parent_data_2,
1719 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1720 .flags = CLK_SET_RATE_PARENT,
1721 .ops = &clk_rcg2_shared_no_init_park_ops,
1722 },
1723 };
1724
1725 static struct clk_rcg2 gcc_pcie_phy_4_aux_clk_src = {
1726 .cmd_rcgr = 0xd3018,
1727 .mnd_width = 16,
1728 .hid_width = 5,
1729 .parent_map = gcc_parent_map_2,
1730 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1731 .clkr.hw.init = &(const struct clk_init_data) {
1732 .name = "gcc_pcie_phy_4_aux_clk_src",
1733 .parent_data = gcc_parent_data_2,
1734 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1735 .flags = CLK_SET_RATE_PARENT,
1736 .ops = &clk_rcg2_shared_no_init_park_ops,
1737 },
1738 };
1739
1740 static struct clk_rcg2 gcc_pcie_phy_5_aux_clk_src = {
1741 .cmd_rcgr = 0xd2018,
1742 .mnd_width = 16,
1743 .hid_width = 5,
1744 .parent_map = gcc_parent_map_2,
1745 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1746 .clkr.hw.init = &(const struct clk_init_data) {
1747 .name = "gcc_pcie_phy_5_aux_clk_src",
1748 .parent_data = gcc_parent_data_2,
1749 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1750 .flags = CLK_SET_RATE_PARENT,
1751 .ops = &clk_rcg2_shared_no_init_park_ops,
1752 },
1753 };
1754
1755 static struct clk_rcg2 gcc_pcie_phy_6_aux_clk_src = {
1756 .cmd_rcgr = 0xd4018,
1757 .mnd_width = 16,
1758 .hid_width = 5,
1759 .parent_map = gcc_parent_map_2,
1760 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1761 .clkr.hw.init = &(const struct clk_init_data) {
1762 .name = "gcc_pcie_phy_6_aux_clk_src",
1763 .parent_data = gcc_parent_data_2,
1764 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1765 .flags = CLK_SET_RATE_PARENT,
1766 .ops = &clk_rcg2_shared_no_init_park_ops,
1767 },
1768 };
1769
1770 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
1771 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
1772 { }
1773 };
1774
1775 static struct clk_rcg2 gcc_pdm2_clk_src = {
1776 .cmd_rcgr = 0x33010,
1777 .mnd_width = 0,
1778 .hid_width = 5,
1779 .parent_map = gcc_parent_map_0,
1780 .freq_tbl = ftbl_gcc_pdm2_clk_src,
1781 .clkr.hw.init = &(const struct clk_init_data) {
1782 .name = "gcc_pdm2_clk_src",
1783 .parent_data = gcc_parent_data_0,
1784 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1785 .flags = CLK_SET_RATE_PARENT,
1786 .ops = &clk_rcg2_shared_no_init_park_ops,
1787 },
1788 };
1789
1790 static const struct freq_tbl ftbl_gcc_qupv3_oob_qspi_s0_clk_src[] = {
1791 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1792 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1793 F(19200000, P_BI_TCXO, 1, 0, 0),
1794 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1795 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1796 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1797 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1798 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1799 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1800 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1801 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1802 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1803 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1804 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1805 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1806 { }
1807 };
1808
1809 static struct clk_init_data gcc_qupv3_oob_qspi_s0_clk_src_init = {
1810 .name = "gcc_qupv3_oob_qspi_s0_clk_src",
1811 .parent_data = gcc_parent_data_3,
1812 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1813 .flags = CLK_SET_RATE_PARENT,
1814 .ops = &clk_rcg2_shared_no_init_park_ops,
1815 };
1816
1817 static struct clk_rcg2 gcc_qupv3_oob_qspi_s0_clk_src = {
1818 .cmd_rcgr = 0xe7044,
1819 .mnd_width = 16,
1820 .hid_width = 5,
1821 .parent_map = gcc_parent_map_3,
1822 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s0_clk_src,
1823 .clkr.hw.init = &gcc_qupv3_oob_qspi_s0_clk_src_init,
1824 };
1825
1826 static const struct freq_tbl ftbl_gcc_qupv3_oob_qspi_s1_clk_src[] = {
1827 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1828 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1829 F(19200000, P_BI_TCXO, 1, 0, 0),
1830 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1831 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1832 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1833 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1834 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1835 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1836 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1837 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1838 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1839 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1840 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1841 { }
1842 };
1843
1844 static struct clk_init_data gcc_qupv3_oob_qspi_s1_clk_src_init = {
1845 .name = "gcc_qupv3_oob_qspi_s1_clk_src",
1846 .parent_data = gcc_parent_data_1,
1847 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1848 .flags = CLK_SET_RATE_PARENT,
1849 .ops = &clk_rcg2_shared_no_init_park_ops,
1850 };
1851
1852 static struct clk_rcg2 gcc_qupv3_oob_qspi_s1_clk_src = {
1853 .cmd_rcgr = 0xe7170,
1854 .mnd_width = 16,
1855 .hid_width = 5,
1856 .parent_map = gcc_parent_map_1,
1857 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
1858 .clkr.hw.init = &gcc_qupv3_oob_qspi_s1_clk_src_init,
1859 };
1860
1861 static struct clk_init_data gcc_qupv3_wrap0_qspi_s2_clk_src_init = {
1862 .name = "gcc_qupv3_wrap0_qspi_s2_clk_src",
1863 .parent_data = gcc_parent_data_1,
1864 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1865 .flags = CLK_SET_RATE_PARENT,
1866 .ops = &clk_rcg2_shared_no_init_park_ops,
1867 };
1868
1869 static struct clk_rcg2 gcc_qupv3_wrap0_qspi_s2_clk_src = {
1870 .cmd_rcgr = 0x287a0,
1871 .mnd_width = 16,
1872 .hid_width = 5,
1873 .parent_map = gcc_parent_map_1,
1874 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
1875 .clkr.hw.init = &gcc_qupv3_wrap0_qspi_s2_clk_src_init,
1876 };
1877
1878 static struct clk_init_data gcc_qupv3_wrap0_qspi_s3_clk_src_init = {
1879 .name = "gcc_qupv3_wrap0_qspi_s3_clk_src",
1880 .parent_data = gcc_parent_data_1,
1881 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1882 .flags = CLK_SET_RATE_PARENT,
1883 .ops = &clk_rcg2_shared_no_init_park_ops,
1884 };
1885
1886 static struct clk_rcg2 gcc_qupv3_wrap0_qspi_s3_clk_src = {
1887 .cmd_rcgr = 0x288d0,
1888 .mnd_width = 16,
1889 .hid_width = 5,
1890 .parent_map = gcc_parent_map_1,
1891 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
1892 .clkr.hw.init = &gcc_qupv3_wrap0_qspi_s3_clk_src_init,
1893 };
1894
1895 static struct clk_init_data gcc_qupv3_wrap0_qspi_s6_clk_src_init = {
1896 .name = "gcc_qupv3_wrap0_qspi_s6_clk_src",
1897 .parent_data = gcc_parent_data_1,
1898 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1899 .flags = CLK_SET_RATE_PARENT,
1900 .ops = &clk_rcg2_shared_no_init_park_ops,
1901 };
1902
1903 static struct clk_rcg2 gcc_qupv3_wrap0_qspi_s6_clk_src = {
1904 .cmd_rcgr = 0x2866c,
1905 .mnd_width = 16,
1906 .hid_width = 5,
1907 .parent_map = gcc_parent_map_1,
1908 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
1909 .clkr.hw.init = &gcc_qupv3_wrap0_qspi_s6_clk_src_init,
1910 };
1911
1912 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
1913 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1914 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1915 F(19200000, P_BI_TCXO, 1, 0, 0),
1916 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1917 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1918 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1919 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1920 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1921 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1922 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1923 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1924 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1925 { }
1926 };
1927
1928 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
1929 .name = "gcc_qupv3_wrap0_s0_clk_src",
1930 .parent_data = gcc_parent_data_1,
1931 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1932 .flags = CLK_SET_RATE_PARENT,
1933 .ops = &clk_rcg2_shared_no_init_park_ops,
1934 };
1935
1936 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
1937 .cmd_rcgr = 0x28014,
1938 .mnd_width = 16,
1939 .hid_width = 5,
1940 .parent_map = gcc_parent_map_1,
1941 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1942 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
1943 };
1944
1945 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
1946 .name = "gcc_qupv3_wrap0_s1_clk_src",
1947 .parent_data = gcc_parent_data_1,
1948 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1949 .flags = CLK_SET_RATE_PARENT,
1950 .ops = &clk_rcg2_shared_no_init_park_ops,
1951 };
1952
1953 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
1954 .cmd_rcgr = 0x28150,
1955 .mnd_width = 16,
1956 .hid_width = 5,
1957 .parent_map = gcc_parent_map_1,
1958 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1959 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
1960 };
1961
1962 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = {
1963 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1964 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1965 F(19200000, P_BI_TCXO, 1, 0, 0),
1966 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1967 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1968 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1969 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1970 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1971 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1972 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1973 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1974 { }
1975 };
1976
1977 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
1978 .name = "gcc_qupv3_wrap0_s4_clk_src",
1979 .parent_data = gcc_parent_data_1,
1980 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1981 .flags = CLK_SET_RATE_PARENT,
1982 .ops = &clk_rcg2_shared_no_init_park_ops,
1983 };
1984
1985 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
1986 .cmd_rcgr = 0x282b4,
1987 .mnd_width = 16,
1988 .hid_width = 5,
1989 .parent_map = gcc_parent_map_1,
1990 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1991 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
1992 };
1993
1994 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
1995 .name = "gcc_qupv3_wrap0_s5_clk_src",
1996 .parent_data = gcc_parent_data_1,
1997 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1998 .flags = CLK_SET_RATE_PARENT,
1999 .ops = &clk_rcg2_shared_no_init_park_ops,
2000 };
2001
2002 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
2003 .cmd_rcgr = 0x283f0,
2004 .mnd_width = 16,
2005 .hid_width = 5,
2006 .parent_map = gcc_parent_map_1,
2007 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2008 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
2009 };
2010
2011 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
2012 .name = "gcc_qupv3_wrap0_s7_clk_src",
2013 .parent_data = gcc_parent_data_1,
2014 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2015 .flags = CLK_SET_RATE_PARENT,
2016 .ops = &clk_rcg2_shared_no_init_park_ops,
2017 };
2018
2019 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
2020 .cmd_rcgr = 0x28540,
2021 .mnd_width = 16,
2022 .hid_width = 5,
2023 .parent_map = gcc_parent_map_1,
2024 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2025 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
2026 };
2027
2028 static struct clk_init_data gcc_qupv3_wrap1_qspi_s2_clk_src_init = {
2029 .name = "gcc_qupv3_wrap1_qspi_s2_clk_src",
2030 .parent_data = gcc_parent_data_1,
2031 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2032 .flags = CLK_SET_RATE_PARENT,
2033 .ops = &clk_rcg2_shared_no_init_park_ops,
2034 };
2035
2036 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_s2_clk_src = {
2037 .cmd_rcgr = 0xb37a0,
2038 .mnd_width = 16,
2039 .hid_width = 5,
2040 .parent_map = gcc_parent_map_1,
2041 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
2042 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_s2_clk_src_init,
2043 };
2044
2045 static struct clk_init_data gcc_qupv3_wrap1_qspi_s3_clk_src_init = {
2046 .name = "gcc_qupv3_wrap1_qspi_s3_clk_src",
2047 .parent_data = gcc_parent_data_1,
2048 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2049 .flags = CLK_SET_RATE_PARENT,
2050 .ops = &clk_rcg2_shared_no_init_park_ops,
2051 };
2052
2053 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_s3_clk_src = {
2054 .cmd_rcgr = 0xb38d0,
2055 .mnd_width = 16,
2056 .hid_width = 5,
2057 .parent_map = gcc_parent_map_1,
2058 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
2059 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_s3_clk_src_init,
2060 };
2061
2062 static struct clk_init_data gcc_qupv3_wrap1_qspi_s6_clk_src_init = {
2063 .name = "gcc_qupv3_wrap1_qspi_s6_clk_src",
2064 .parent_data = gcc_parent_data_1,
2065 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2066 .flags = CLK_SET_RATE_PARENT,
2067 .ops = &clk_rcg2_shared_no_init_park_ops,
2068 };
2069
2070 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_s6_clk_src = {
2071 .cmd_rcgr = 0xb366c,
2072 .mnd_width = 16,
2073 .hid_width = 5,
2074 .parent_map = gcc_parent_map_1,
2075 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
2076 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_s6_clk_src_init,
2077 };
2078
2079 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
2080 .name = "gcc_qupv3_wrap1_s0_clk_src",
2081 .parent_data = gcc_parent_data_1,
2082 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2083 .flags = CLK_SET_RATE_PARENT,
2084 .ops = &clk_rcg2_shared_no_init_park_ops,
2085 };
2086
2087 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
2088 .cmd_rcgr = 0xb3014,
2089 .mnd_width = 16,
2090 .hid_width = 5,
2091 .parent_map = gcc_parent_map_1,
2092 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
2093 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
2094 };
2095
2096 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
2097 .name = "gcc_qupv3_wrap1_s1_clk_src",
2098 .parent_data = gcc_parent_data_1,
2099 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2100 .flags = CLK_SET_RATE_PARENT,
2101 .ops = &clk_rcg2_shared_no_init_park_ops,
2102 };
2103
2104 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
2105 .cmd_rcgr = 0xb3150,
2106 .mnd_width = 16,
2107 .hid_width = 5,
2108 .parent_map = gcc_parent_map_1,
2109 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
2110 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
2111 };
2112
2113 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
2114 .name = "gcc_qupv3_wrap1_s4_clk_src",
2115 .parent_data = gcc_parent_data_1,
2116 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2117 .flags = CLK_SET_RATE_PARENT,
2118 .ops = &clk_rcg2_shared_no_init_park_ops,
2119 };
2120
2121 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
2122 .cmd_rcgr = 0xb32b4,
2123 .mnd_width = 16,
2124 .hid_width = 5,
2125 .parent_map = gcc_parent_map_1,
2126 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2127 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
2128 };
2129
2130 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
2131 .name = "gcc_qupv3_wrap1_s5_clk_src",
2132 .parent_data = gcc_parent_data_1,
2133 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2134 .flags = CLK_SET_RATE_PARENT,
2135 .ops = &clk_rcg2_shared_no_init_park_ops,
2136 };
2137
2138 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
2139 .cmd_rcgr = 0xb33f0,
2140 .mnd_width = 16,
2141 .hid_width = 5,
2142 .parent_map = gcc_parent_map_1,
2143 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2144 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
2145 };
2146
2147 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
2148 .name = "gcc_qupv3_wrap1_s7_clk_src",
2149 .parent_data = gcc_parent_data_1,
2150 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2151 .flags = CLK_SET_RATE_PARENT,
2152 .ops = &clk_rcg2_shared_no_init_park_ops,
2153 };
2154
2155 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
2156 .cmd_rcgr = 0xb3540,
2157 .mnd_width = 16,
2158 .hid_width = 5,
2159 .parent_map = gcc_parent_map_1,
2160 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2161 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
2162 };
2163
2164 static struct clk_init_data gcc_qupv3_wrap2_qspi_s2_clk_src_init = {
2165 .name = "gcc_qupv3_wrap2_qspi_s2_clk_src",
2166 .parent_data = gcc_parent_data_1,
2167 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2168 .flags = CLK_SET_RATE_PARENT,
2169 .ops = &clk_rcg2_shared_no_init_park_ops,
2170 };
2171
2172 static struct clk_rcg2 gcc_qupv3_wrap2_qspi_s2_clk_src = {
2173 .cmd_rcgr = 0xb47a0,
2174 .mnd_width = 16,
2175 .hid_width = 5,
2176 .parent_map = gcc_parent_map_1,
2177 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
2178 .clkr.hw.init = &gcc_qupv3_wrap2_qspi_s2_clk_src_init,
2179 };
2180
2181 static struct clk_init_data gcc_qupv3_wrap2_qspi_s3_clk_src_init = {
2182 .name = "gcc_qupv3_wrap2_qspi_s3_clk_src",
2183 .parent_data = gcc_parent_data_1,
2184 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2185 .flags = CLK_SET_RATE_PARENT,
2186 .ops = &clk_rcg2_shared_no_init_park_ops,
2187 };
2188
2189 static struct clk_rcg2 gcc_qupv3_wrap2_qspi_s3_clk_src = {
2190 .cmd_rcgr = 0xb48d0,
2191 .mnd_width = 16,
2192 .hid_width = 5,
2193 .parent_map = gcc_parent_map_1,
2194 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
2195 .clkr.hw.init = &gcc_qupv3_wrap2_qspi_s3_clk_src_init,
2196 };
2197
2198 static struct clk_init_data gcc_qupv3_wrap2_qspi_s6_clk_src_init = {
2199 .name = "gcc_qupv3_wrap2_qspi_s6_clk_src",
2200 .parent_data = gcc_parent_data_1,
2201 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2202 .flags = CLK_SET_RATE_PARENT,
2203 .ops = &clk_rcg2_shared_no_init_park_ops,
2204 };
2205
2206 static struct clk_rcg2 gcc_qupv3_wrap2_qspi_s6_clk_src = {
2207 .cmd_rcgr = 0xb466c,
2208 .mnd_width = 16,
2209 .hid_width = 5,
2210 .parent_map = gcc_parent_map_1,
2211 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
2212 .clkr.hw.init = &gcc_qupv3_wrap2_qspi_s6_clk_src_init,
2213 };
2214
2215 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
2216 .name = "gcc_qupv3_wrap2_s0_clk_src",
2217 .parent_data = gcc_parent_data_1,
2218 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2219 .flags = CLK_SET_RATE_PARENT,
2220 .ops = &clk_rcg2_shared_no_init_park_ops,
2221 };
2222
2223 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
2224 .cmd_rcgr = 0xb4014,
2225 .mnd_width = 16,
2226 .hid_width = 5,
2227 .parent_map = gcc_parent_map_1,
2228 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
2229 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
2230 };
2231
2232 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
2233 .name = "gcc_qupv3_wrap2_s1_clk_src",
2234 .parent_data = gcc_parent_data_1,
2235 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2236 .flags = CLK_SET_RATE_PARENT,
2237 .ops = &clk_rcg2_shared_no_init_park_ops,
2238 };
2239
2240 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
2241 .cmd_rcgr = 0xb4150,
2242 .mnd_width = 16,
2243 .hid_width = 5,
2244 .parent_map = gcc_parent_map_1,
2245 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
2246 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
2247 };
2248
2249 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
2250 .name = "gcc_qupv3_wrap2_s4_clk_src",
2251 .parent_data = gcc_parent_data_1,
2252 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2253 .flags = CLK_SET_RATE_PARENT,
2254 .ops = &clk_rcg2_shared_no_init_park_ops,
2255 };
2256
2257 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
2258 .cmd_rcgr = 0xb42b4,
2259 .mnd_width = 16,
2260 .hid_width = 5,
2261 .parent_map = gcc_parent_map_1,
2262 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2263 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
2264 };
2265
2266 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
2267 .name = "gcc_qupv3_wrap2_s5_clk_src",
2268 .parent_data = gcc_parent_data_1,
2269 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2270 .flags = CLK_SET_RATE_PARENT,
2271 .ops = &clk_rcg2_shared_no_init_park_ops,
2272 };
2273
2274 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
2275 .cmd_rcgr = 0xb43f0,
2276 .mnd_width = 16,
2277 .hid_width = 5,
2278 .parent_map = gcc_parent_map_1,
2279 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2280 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
2281 };
2282
2283 static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
2284 .name = "gcc_qupv3_wrap2_s7_clk_src",
2285 .parent_data = gcc_parent_data_1,
2286 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
2287 .flags = CLK_SET_RATE_PARENT,
2288 .ops = &clk_rcg2_shared_no_init_park_ops,
2289 };
2290
2291 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
2292 .cmd_rcgr = 0xb4540,
2293 .mnd_width = 16,
2294 .hid_width = 5,
2295 .parent_map = gcc_parent_map_1,
2296 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2297 .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
2298 };
2299
2300 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
2301 F(400000, P_BI_TCXO, 12, 1, 4),
2302 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
2303 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
2304 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
2305 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
2306 { }
2307 };
2308
2309 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
2310 .cmd_rcgr = 0xb001c,
2311 .mnd_width = 8,
2312 .hid_width = 5,
2313 .parent_map = gcc_parent_map_17,
2314 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
2315 .clkr.hw.init = &(const struct clk_init_data) {
2316 .name = "gcc_sdcc2_apps_clk_src",
2317 .parent_data = gcc_parent_data_17,
2318 .num_parents = ARRAY_SIZE(gcc_parent_data_17),
2319 .flags = CLK_SET_RATE_PARENT,
2320 .ops = &clk_rcg2_floor_ops,
2321 },
2322 };
2323
2324 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
2325 F(400000, P_BI_TCXO, 12, 1, 4),
2326 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
2327 F(75000000, P_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
2328 { }
2329 };
2330
2331 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
2332 .cmd_rcgr = 0xdf01c,
2333 .mnd_width = 8,
2334 .hid_width = 5,
2335 .parent_map = gcc_parent_map_3,
2336 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
2337 .clkr.hw.init = &(const struct clk_init_data) {
2338 .name = "gcc_sdcc4_apps_clk_src",
2339 .parent_data = gcc_parent_data_3,
2340 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
2341 .flags = CLK_SET_RATE_PARENT,
2342 .ops = &clk_rcg2_floor_ops,
2343 },
2344 };
2345
2346 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
2347 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
2348 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
2349 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
2350 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
2351 { }
2352 };
2353
2354 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
2355 .cmd_rcgr = 0x77038,
2356 .mnd_width = 8,
2357 .hid_width = 5,
2358 .parent_map = gcc_parent_map_6,
2359 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
2360 .clkr.hw.init = &(const struct clk_init_data) {
2361 .name = "gcc_ufs_phy_axi_clk_src",
2362 .parent_data = gcc_parent_data_6,
2363 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
2364 .flags = CLK_SET_RATE_PARENT,
2365 .ops = &clk_rcg2_shared_no_init_park_ops,
2366 },
2367 };
2368
2369 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
2370 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
2371 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
2372 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
2373 { }
2374 };
2375
2376 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
2377 .cmd_rcgr = 0x77090,
2378 .mnd_width = 0,
2379 .hid_width = 5,
2380 .parent_map = gcc_parent_map_6,
2381 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
2382 .clkr.hw.init = &(const struct clk_init_data) {
2383 .name = "gcc_ufs_phy_ice_core_clk_src",
2384 .parent_data = gcc_parent_data_6,
2385 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
2386 .flags = CLK_SET_RATE_PARENT,
2387 .ops = &clk_rcg2_shared_no_init_park_ops,
2388 },
2389 };
2390
2391 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
2392 .cmd_rcgr = 0x770c4,
2393 .mnd_width = 0,
2394 .hid_width = 5,
2395 .parent_map = gcc_parent_map_5,
2396 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2397 .clkr.hw.init = &(const struct clk_init_data) {
2398 .name = "gcc_ufs_phy_phy_aux_clk_src",
2399 .parent_data = gcc_parent_data_5,
2400 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
2401 .flags = CLK_SET_RATE_PARENT,
2402 .ops = &clk_rcg2_shared_no_init_park_ops,
2403 },
2404 };
2405
2406 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
2407 .cmd_rcgr = 0x770a8,
2408 .mnd_width = 0,
2409 .hid_width = 5,
2410 .parent_map = gcc_parent_map_6,
2411 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
2412 .clkr.hw.init = &(const struct clk_init_data) {
2413 .name = "gcc_ufs_phy_unipro_core_clk_src",
2414 .parent_data = gcc_parent_data_6,
2415 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
2416 .flags = CLK_SET_RATE_PARENT,
2417 .ops = &clk_rcg2_shared_no_init_park_ops,
2418 },
2419 };
2420
2421 static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
2422 F(60000000, P_GCC_GPLL14_OUT_MAIN, 10, 0, 0),
2423 F(120000000, P_GCC_GPLL14_OUT_MAIN, 5, 0, 0),
2424 { }
2425 };
2426
2427 static struct clk_rcg2 gcc_usb20_master_clk_src = {
2428 .cmd_rcgr = 0xbc030,
2429 .mnd_width = 8,
2430 .hid_width = 5,
2431 .parent_map = gcc_parent_map_7,
2432 .freq_tbl = ftbl_gcc_usb20_master_clk_src,
2433 .clkr.hw.init = &(const struct clk_init_data) {
2434 .name = "gcc_usb20_master_clk_src",
2435 .parent_data = gcc_parent_data_7,
2436 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
2437 .flags = CLK_SET_RATE_PARENT,
2438 .ops = &clk_rcg2_shared_no_init_park_ops,
2439 },
2440 };
2441
2442 static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = {
2443 .cmd_rcgr = 0xbc048,
2444 .mnd_width = 0,
2445 .hid_width = 5,
2446 .parent_map = gcc_parent_map_7,
2447 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2448 .clkr.hw.init = &(const struct clk_init_data) {
2449 .name = "gcc_usb20_mock_utmi_clk_src",
2450 .parent_data = gcc_parent_data_7,
2451 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
2452 .flags = CLK_SET_RATE_PARENT,
2453 .ops = &clk_rcg2_shared_no_init_park_ops,
2454 },
2455 };
2456
2457 static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {
2458 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
2459 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
2460 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
2461 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
2462 { }
2463 };
2464
2465 static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {
2466 .cmd_rcgr = 0x9a03c,
2467 .mnd_width = 8,
2468 .hid_width = 5,
2469 .parent_map = gcc_parent_map_0,
2470 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
2471 .clkr.hw.init = &(const struct clk_init_data) {
2472 .name = "gcc_usb30_mp_master_clk_src",
2473 .parent_data = gcc_parent_data_0,
2474 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
2475 .flags = CLK_SET_RATE_PARENT,
2476 .ops = &clk_rcg2_shared_no_init_park_ops,
2477 },
2478 };
2479
2480 static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
2481 .cmd_rcgr = 0x9a054,
2482 .mnd_width = 0,
2483 .hid_width = 5,
2484 .parent_map = gcc_parent_map_0,
2485 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2486 .clkr.hw.init = &(const struct clk_init_data) {
2487 .name = "gcc_usb30_mp_mock_utmi_clk_src",
2488 .parent_data = gcc_parent_data_0,
2489 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
2490 .flags = CLK_SET_RATE_PARENT,
2491 .ops = &clk_rcg2_shared_no_init_park_ops,
2492 },
2493 };
2494
2495 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
2496 .cmd_rcgr = 0x3f04c,
2497 .mnd_width = 8,
2498 .hid_width = 5,
2499 .parent_map = gcc_parent_map_0,
2500 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
2501 .clkr.hw.init = &(const struct clk_init_data) {
2502 .name = "gcc_usb30_prim_master_clk_src",
2503 .parent_data = gcc_parent_data_0,
2504 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
2505 .flags = CLK_SET_RATE_PARENT,
2506 .ops = &clk_rcg2_shared_no_init_park_ops,
2507 },
2508 };
2509
2510 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
2511 .cmd_rcgr = 0x3f064,
2512 .mnd_width = 0,
2513 .hid_width = 5,
2514 .parent_map = gcc_parent_map_0,
2515 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2516 .clkr.hw.init = &(const struct clk_init_data) {
2517 .name = "gcc_usb30_prim_mock_utmi_clk_src",
2518 .parent_data = gcc_parent_data_0,
2519 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
2520 .flags = CLK_SET_RATE_PARENT,
2521 .ops = &clk_rcg2_shared_no_init_park_ops,
2522 },
2523 };
2524
2525 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
2526 .cmd_rcgr = 0xe203c,
2527 .mnd_width = 8,
2528 .hid_width = 5,
2529 .parent_map = gcc_parent_map_0,
2530 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
2531 .clkr.hw.init = &(const struct clk_init_data) {
2532 .name = "gcc_usb30_sec_master_clk_src",
2533 .parent_data = gcc_parent_data_0,
2534 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
2535 .flags = CLK_SET_RATE_PARENT,
2536 .ops = &clk_rcg2_shared_no_init_park_ops,
2537 },
2538 };
2539
2540 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
2541 .cmd_rcgr = 0xe2054,
2542 .mnd_width = 0,
2543 .hid_width = 5,
2544 .parent_map = gcc_parent_map_0,
2545 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2546 .clkr.hw.init = &(const struct clk_init_data) {
2547 .name = "gcc_usb30_sec_mock_utmi_clk_src",
2548 .parent_data = gcc_parent_data_0,
2549 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
2550 .flags = CLK_SET_RATE_PARENT,
2551 .ops = &clk_rcg2_shared_no_init_park_ops,
2552 },
2553 };
2554
2555 static struct clk_rcg2 gcc_usb30_tert_master_clk_src = {
2556 .cmd_rcgr = 0xe103c,
2557 .mnd_width = 8,
2558 .hid_width = 5,
2559 .parent_map = gcc_parent_map_0,
2560 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
2561 .clkr.hw.init = &(const struct clk_init_data) {
2562 .name = "gcc_usb30_tert_master_clk_src",
2563 .parent_data = gcc_parent_data_0,
2564 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
2565 .flags = CLK_SET_RATE_PARENT,
2566 .ops = &clk_rcg2_shared_no_init_park_ops,
2567 },
2568 };
2569
2570 static struct clk_rcg2 gcc_usb30_tert_mock_utmi_clk_src = {
2571 .cmd_rcgr = 0xe1054,
2572 .mnd_width = 0,
2573 .hid_width = 5,
2574 .parent_map = gcc_parent_map_0,
2575 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2576 .clkr.hw.init = &(const struct clk_init_data) {
2577 .name = "gcc_usb30_tert_mock_utmi_clk_src",
2578 .parent_data = gcc_parent_data_0,
2579 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
2580 .flags = CLK_SET_RATE_PARENT,
2581 .ops = &clk_rcg2_shared_no_init_park_ops,
2582 },
2583 };
2584
2585 static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {
2586 .cmd_rcgr = 0x9a088,
2587 .mnd_width = 0,
2588 .hid_width = 5,
2589 .parent_map = gcc_parent_map_8,
2590 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2591 .clkr.hw.init = &(const struct clk_init_data) {
2592 .name = "gcc_usb3_mp_phy_aux_clk_src",
2593 .parent_data = gcc_parent_data_8,
2594 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
2595 .flags = CLK_SET_RATE_PARENT,
2596 .ops = &clk_rcg2_shared_no_init_park_ops,
2597 },
2598 };
2599
2600 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
2601 .cmd_rcgr = 0x3f090,
2602 .mnd_width = 0,
2603 .hid_width = 5,
2604 .parent_map = gcc_parent_map_8,
2605 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2606 .clkr.hw.init = &(const struct clk_init_data) {
2607 .name = "gcc_usb3_prim_phy_aux_clk_src",
2608 .parent_data = gcc_parent_data_8,
2609 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
2610 .flags = CLK_SET_RATE_PARENT,
2611 .ops = &clk_rcg2_shared_no_init_park_ops,
2612 },
2613 };
2614
2615 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
2616 .cmd_rcgr = 0xe2080,
2617 .mnd_width = 0,
2618 .hid_width = 5,
2619 .parent_map = gcc_parent_map_8,
2620 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2621 .clkr.hw.init = &(const struct clk_init_data) {
2622 .name = "gcc_usb3_sec_phy_aux_clk_src",
2623 .parent_data = gcc_parent_data_8,
2624 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
2625 .flags = CLK_SET_RATE_PARENT,
2626 .ops = &clk_rcg2_shared_no_init_park_ops,
2627 },
2628 };
2629
2630 static struct clk_rcg2 gcc_usb3_tert_phy_aux_clk_src = {
2631 .cmd_rcgr = 0xe1080,
2632 .mnd_width = 0,
2633 .hid_width = 5,
2634 .parent_map = gcc_parent_map_8,
2635 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2636 .clkr.hw.init = &(const struct clk_init_data) {
2637 .name = "gcc_usb3_tert_phy_aux_clk_src",
2638 .parent_data = gcc_parent_data_8,
2639 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
2640 .flags = CLK_SET_RATE_PARENT,
2641 .ops = &clk_rcg2_shared_no_init_park_ops,
2642 },
2643 };
2644
2645 static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] = {
2646 F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0),
2647 F(177666750, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
2648 F(355333500, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
2649 { }
2650 };
2651
2652 static struct clk_rcg2 gcc_usb4_0_master_clk_src = {
2653 .cmd_rcgr = 0x2b02c,
2654 .mnd_width = 8,
2655 .hid_width = 5,
2656 .parent_map = gcc_parent_map_9,
2657 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
2658 .clkr.hw.init = &(const struct clk_init_data) {
2659 .name = "gcc_usb4_0_master_clk_src",
2660 .parent_data = gcc_parent_data_9,
2661 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
2662 .flags = CLK_SET_RATE_PARENT,
2663 .ops = &clk_rcg2_shared_no_init_park_ops,
2664 },
2665 };
2666
2667 static const struct freq_tbl ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src[] = {
2668 F(19200000, P_BI_TCXO, 1, 0, 0),
2669 F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
2670 F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
2671 { }
2672 };
2673
2674 static struct clk_rcg2 gcc_usb4_0_phy_pcie_pipe_clk_src = {
2675 .cmd_rcgr = 0x2b104,
2676 .mnd_width = 0,
2677 .hid_width = 5,
2678 .parent_map = gcc_parent_map_32,
2679 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
2680 .clkr.hw.init = &(const struct clk_init_data) {
2681 .name = "gcc_usb4_0_phy_pcie_pipe_clk_src",
2682 .parent_data = gcc_parent_data_32,
2683 .num_parents = ARRAY_SIZE(gcc_parent_data_32),
2684 .flags = CLK_SET_RATE_PARENT,
2685 .ops = &clk_rcg2_shared_no_init_park_ops,
2686 },
2687 };
2688
2689 static struct clk_rcg2 gcc_usb4_0_sb_if_clk_src = {
2690 .cmd_rcgr = 0x2b0a0,
2691 .mnd_width = 0,
2692 .hid_width = 5,
2693 .parent_map = gcc_parent_map_5,
2694 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2695 .clkr.hw.init = &(const struct clk_init_data) {
2696 .name = "gcc_usb4_0_sb_if_clk_src",
2697 .parent_data = gcc_parent_data_5,
2698 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
2699 .flags = CLK_SET_RATE_PARENT,
2700 .ops = &clk_rcg2_shared_no_init_park_ops,
2701 },
2702 };
2703
2704 static struct clk_rcg2 gcc_usb4_0_tmu_clk_src = {
2705 .cmd_rcgr = 0x2b084,
2706 .mnd_width = 0,
2707 .hid_width = 5,
2708 .parent_map = gcc_parent_map_10,
2709 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
2710 .clkr.hw.init = &(const struct clk_init_data) {
2711 .name = "gcc_usb4_0_tmu_clk_src",
2712 .parent_data = gcc_parent_data_10,
2713 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
2714 .flags = CLK_SET_RATE_PARENT,
2715 .ops = &clk_rcg2_shared_no_init_park_ops,
2716 },
2717 };
2718
2719 static struct clk_rcg2 gcc_usb4_1_master_clk_src = {
2720 .cmd_rcgr = 0x2d02c,
2721 .mnd_width = 8,
2722 .hid_width = 5,
2723 .parent_map = gcc_parent_map_9,
2724 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
2725 .clkr.hw.init = &(const struct clk_init_data) {
2726 .name = "gcc_usb4_1_master_clk_src",
2727 .parent_data = gcc_parent_data_9,
2728 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
2729 .flags = CLK_SET_RATE_PARENT,
2730 .ops = &clk_rcg2_shared_no_init_park_ops,
2731 },
2732 };
2733
2734 static const struct freq_tbl ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src[] = {
2735 F(19200000, P_BI_TCXO, 1, 0, 0),
2736 F(177666750, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
2737 F(355333500, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
2738 { }
2739 };
2740
2741 static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = {
2742 .cmd_rcgr = 0x2d128,
2743 .mnd_width = 0,
2744 .hid_width = 5,
2745 .parent_map = gcc_parent_map_11,
2746 .freq_tbl = ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src,
2747 .clkr.hw.init = &(const struct clk_init_data) {
2748 .name = "gcc_usb4_1_phy_pcie_pipe_clk_src",
2749 .parent_data = gcc_parent_data_11,
2750 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
2751 .flags = CLK_SET_RATE_PARENT,
2752 .ops = &clk_rcg2_shared_no_init_park_ops,
2753 },
2754 };
2755
2756 static const struct freq_tbl ftbl_gcc_usb4_1_phy_pll_pipe_clk_src[] = {
2757 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
2758 F(311000000, P_GCC_GPLL5_OUT_MAIN, 3, 0, 0),
2759 { }
2760 };
2761
2762 static struct clk_rcg2 gcc_usb4_1_phy_pll_pipe_clk_src = {
2763 .cmd_rcgr = 0x2d0c8,
2764 .mnd_width = 0,
2765 .hid_width = 5,
2766 .parent_map = gcc_parent_map_41,
2767 .freq_tbl = ftbl_gcc_usb4_1_phy_pll_pipe_clk_src,
2768 .clkr.hw.init = &(const struct clk_init_data) {
2769 .name = "gcc_usb4_1_phy_pll_pipe_clk_src",
2770 .parent_data = gcc_parent_data_41,
2771 .num_parents = ARRAY_SIZE(gcc_parent_data_41),
2772 .flags = CLK_SET_RATE_PARENT,
2773 .ops = &clk_rcg2_shared_no_init_park_ops,
2774 },
2775 };
2776
2777 static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = {
2778 .cmd_rcgr = 0x2d0ac,
2779 .mnd_width = 0,
2780 .hid_width = 5,
2781 .parent_map = gcc_parent_map_5,
2782 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2783 .clkr.hw.init = &(const struct clk_init_data) {
2784 .name = "gcc_usb4_1_sb_if_clk_src",
2785 .parent_data = gcc_parent_data_5,
2786 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
2787 .flags = CLK_SET_RATE_PARENT,
2788 .ops = &clk_rcg2_shared_no_init_park_ops,
2789 },
2790 };
2791
2792 static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = {
2793 .cmd_rcgr = 0x2d090,
2794 .mnd_width = 0,
2795 .hid_width = 5,
2796 .parent_map = gcc_parent_map_10,
2797 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
2798 .clkr.hw.init = &(const struct clk_init_data) {
2799 .name = "gcc_usb4_1_tmu_clk_src",
2800 .parent_data = gcc_parent_data_10,
2801 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
2802 .flags = CLK_SET_RATE_PARENT,
2803 .ops = &clk_rcg2_shared_no_init_park_ops,
2804 },
2805 };
2806
2807 static struct clk_rcg2 gcc_usb4_2_master_clk_src = {
2808 .cmd_rcgr = 0xe002c,
2809 .mnd_width = 8,
2810 .hid_width = 5,
2811 .parent_map = gcc_parent_map_9,
2812 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
2813 .clkr.hw.init = &(const struct clk_init_data) {
2814 .name = "gcc_usb4_2_master_clk_src",
2815 .parent_data = gcc_parent_data_9,
2816 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
2817 .flags = CLK_SET_RATE_PARENT,
2818 .ops = &clk_rcg2_shared_no_init_park_ops,
2819 },
2820 };
2821
2822 static struct clk_rcg2 gcc_usb4_2_phy_pcie_pipe_clk_src = {
2823 .cmd_rcgr = 0xe0108,
2824 .mnd_width = 0,
2825 .hid_width = 5,
2826 .parent_map = gcc_parent_map_11,
2827 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
2828 .clkr.hw.init = &(const struct clk_init_data) {
2829 .name = "gcc_usb4_2_phy_pcie_pipe_clk_src",
2830 .parent_data = gcc_parent_data_11,
2831 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
2832 .flags = CLK_SET_RATE_PARENT,
2833 .ops = &clk_rcg2_shared_no_init_park_ops,
2834 },
2835 };
2836
2837 static struct clk_rcg2 gcc_usb4_2_sb_if_clk_src = {
2838 .cmd_rcgr = 0xe00a4,
2839 .mnd_width = 0,
2840 .hid_width = 5,
2841 .parent_map = gcc_parent_map_5,
2842 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2843 .clkr.hw.init = &(const struct clk_init_data) {
2844 .name = "gcc_usb4_2_sb_if_clk_src",
2845 .parent_data = gcc_parent_data_5,
2846 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
2847 .flags = CLK_SET_RATE_PARENT,
2848 .ops = &clk_rcg2_shared_no_init_park_ops,
2849 },
2850 };
2851
2852 static struct clk_rcg2 gcc_usb4_2_tmu_clk_src = {
2853 .cmd_rcgr = 0xe0088,
2854 .mnd_width = 0,
2855 .hid_width = 5,
2856 .parent_map = gcc_parent_map_10,
2857 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
2858 .clkr.hw.init = &(const struct clk_init_data) {
2859 .name = "gcc_usb4_2_tmu_clk_src",
2860 .parent_data = gcc_parent_data_10,
2861 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
2862 .flags = CLK_SET_RATE_PARENT,
2863 .ops = &clk_rcg2_shared_no_init_park_ops,
2864 },
2865 };
2866
2867 static struct clk_regmap_div gcc_pcie_3b_pipe_div_clk_src = {
2868 .reg = 0x94070,
2869 .shift = 0,
2870 .width = 4,
2871 .clkr.hw.init = &(const struct clk_init_data) {
2872 .name = "gcc_pcie_3b_pipe_div_clk_src",
2873 .parent_hws = (const struct clk_hw*[]) {
2874 &gcc_pcie_3b_pipe_clk_src.clkr.hw,
2875 },
2876 .num_parents = 1,
2877 .flags = CLK_SET_RATE_PARENT,
2878 .ops = &clk_regmap_div_ro_ops,
2879 },
2880 };
2881
2882 static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = {
2883 .reg = 0x88060,
2884 .shift = 0,
2885 .width = 4,
2886 .clkr.hw.init = &(const struct clk_init_data) {
2887 .name = "gcc_pcie_4_pipe_div_clk_src",
2888 .parent_hws = (const struct clk_hw*[]) {
2889 &gcc_pcie_4_pipe_clk_src.clkr.hw,
2890 },
2891 .num_parents = 1,
2892 .flags = CLK_SET_RATE_PARENT,
2893 .ops = &clk_regmap_div_ro_ops,
2894 },
2895 };
2896
2897 static struct clk_regmap_div gcc_pcie_5_pipe_div_clk_src = {
2898 .reg = 0xc306c,
2899 .shift = 0,
2900 .width = 4,
2901 .clkr.hw.init = &(const struct clk_init_data) {
2902 .name = "gcc_pcie_5_pipe_div_clk_src",
2903 .parent_hws = (const struct clk_hw*[]) {
2904 &gcc_pcie_5_pipe_clk_src.clkr.hw,
2905 },
2906 .num_parents = 1,
2907 .flags = CLK_SET_RATE_PARENT,
2908 .ops = &clk_regmap_div_ro_ops,
2909 },
2910 };
2911
2912 static struct clk_regmap_div gcc_pcie_6_pipe_div_clk_src = {
2913 .reg = 0x8a060,
2914 .shift = 0,
2915 .width = 4,
2916 .clkr.hw.init = &(const struct clk_init_data) {
2917 .name = "gcc_pcie_6_pipe_div_clk_src",
2918 .parent_hws = (const struct clk_hw*[]) {
2919 &gcc_pcie_6_pipe_clk_src.clkr.hw,
2920 },
2921 .num_parents = 1,
2922 .flags = CLK_SET_RATE_PARENT,
2923 .ops = &clk_regmap_div_ro_ops,
2924 },
2925 };
2926
2927 static struct clk_regmap_div gcc_qupv3_oob_s0_clk_src = {
2928 .reg = 0xe7024,
2929 .shift = 0,
2930 .width = 4,
2931 .clkr.hw.init = &(const struct clk_init_data) {
2932 .name = "gcc_qupv3_oob_s0_clk_src",
2933 .parent_hws = (const struct clk_hw*[]) {
2934 &gcc_qupv3_oob_qspi_s0_clk_src.clkr.hw,
2935 },
2936 .num_parents = 1,
2937 .flags = CLK_SET_RATE_PARENT,
2938 .ops = &clk_regmap_div_ro_ops,
2939 },
2940 };
2941
2942 static struct clk_regmap_div gcc_qupv3_oob_s1_clk_src = {
2943 .reg = 0xe7038,
2944 .shift = 0,
2945 .width = 4,
2946 .clkr.hw.init = &(const struct clk_init_data) {
2947 .name = "gcc_qupv3_oob_s1_clk_src",
2948 .parent_hws = (const struct clk_hw*[]) {
2949 &gcc_qupv3_oob_qspi_s1_clk_src.clkr.hw,
2950 },
2951 .num_parents = 1,
2952 .flags = CLK_SET_RATE_PARENT,
2953 .ops = &clk_regmap_div_ro_ops,
2954 },
2955 };
2956
2957 static struct clk_regmap_div gcc_qupv3_wrap0_s2_clk_src = {
2958 .reg = 0x2828c,
2959 .shift = 0,
2960 .width = 4,
2961 .clkr.hw.init = &(const struct clk_init_data) {
2962 .name = "gcc_qupv3_wrap0_s2_clk_src",
2963 .parent_hws = (const struct clk_hw*[]) {
2964 &gcc_qupv3_wrap0_qspi_s2_clk_src.clkr.hw,
2965 },
2966 .num_parents = 1,
2967 .flags = CLK_SET_RATE_PARENT,
2968 .ops = &clk_regmap_div_ro_ops,
2969 },
2970 };
2971
2972 static struct clk_regmap_div gcc_qupv3_wrap0_s3_clk_src = {
2973 .reg = 0x282a0,
2974 .shift = 0,
2975 .width = 4,
2976 .clkr.hw.init = &(const struct clk_init_data) {
2977 .name = "gcc_qupv3_wrap0_s3_clk_src",
2978 .parent_hws = (const struct clk_hw*[]) {
2979 &gcc_qupv3_wrap0_qspi_s3_clk_src.clkr.hw,
2980 },
2981 .num_parents = 1,
2982 .flags = CLK_SET_RATE_PARENT,
2983 .ops = &clk_regmap_div_ro_ops,
2984 },
2985 };
2986
2987 static struct clk_regmap_div gcc_qupv3_wrap0_s6_clk_src = {
2988 .reg = 0x2852c,
2989 .shift = 0,
2990 .width = 4,
2991 .clkr.hw.init = &(const struct clk_init_data) {
2992 .name = "gcc_qupv3_wrap0_s6_clk_src",
2993 .parent_hws = (const struct clk_hw*[]) {
2994 &gcc_qupv3_wrap0_qspi_s6_clk_src.clkr.hw,
2995 },
2996 .num_parents = 1,
2997 .flags = CLK_SET_RATE_PARENT,
2998 .ops = &clk_regmap_div_ro_ops,
2999 },
3000 };
3001
3002 static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = {
3003 .reg = 0xb328c,
3004 .shift = 0,
3005 .width = 4,
3006 .clkr.hw.init = &(const struct clk_init_data) {
3007 .name = "gcc_qupv3_wrap1_s2_clk_src",
3008 .parent_hws = (const struct clk_hw*[]) {
3009 &gcc_qupv3_wrap1_qspi_s2_clk_src.clkr.hw,
3010 },
3011 .num_parents = 1,
3012 .flags = CLK_SET_RATE_PARENT,
3013 .ops = &clk_regmap_div_ro_ops,
3014 },
3015 };
3016
3017 static struct clk_regmap_div gcc_qupv3_wrap1_s3_clk_src = {
3018 .reg = 0xb32a0,
3019 .shift = 0,
3020 .width = 4,
3021 .clkr.hw.init = &(const struct clk_init_data) {
3022 .name = "gcc_qupv3_wrap1_s3_clk_src",
3023 .parent_hws = (const struct clk_hw*[]) {
3024 &gcc_qupv3_wrap1_qspi_s3_clk_src.clkr.hw,
3025 },
3026 .num_parents = 1,
3027 .flags = CLK_SET_RATE_PARENT,
3028 .ops = &clk_regmap_div_ro_ops,
3029 },
3030 };
3031
3032 static struct clk_regmap_div gcc_qupv3_wrap1_s6_clk_src = {
3033 .reg = 0xb352c,
3034 .shift = 0,
3035 .width = 4,
3036 .clkr.hw.init = &(const struct clk_init_data) {
3037 .name = "gcc_qupv3_wrap1_s6_clk_src",
3038 .parent_hws = (const struct clk_hw*[]) {
3039 &gcc_qupv3_wrap1_qspi_s6_clk_src.clkr.hw,
3040 },
3041 .num_parents = 1,
3042 .flags = CLK_SET_RATE_PARENT,
3043 .ops = &clk_regmap_div_ro_ops,
3044 },
3045 };
3046
3047 static struct clk_regmap_div gcc_qupv3_wrap2_s2_clk_src = {
3048 .reg = 0xb428c,
3049 .shift = 0,
3050 .width = 4,
3051 .clkr.hw.init = &(const struct clk_init_data) {
3052 .name = "gcc_qupv3_wrap2_s2_clk_src",
3053 .parent_hws = (const struct clk_hw*[]) {
3054 &gcc_qupv3_wrap2_qspi_s2_clk_src.clkr.hw,
3055 },
3056 .num_parents = 1,
3057 .flags = CLK_SET_RATE_PARENT,
3058 .ops = &clk_regmap_div_ro_ops,
3059 },
3060 };
3061
3062 static struct clk_regmap_div gcc_qupv3_wrap2_s3_clk_src = {
3063 .reg = 0xb42a0,
3064 .shift = 0,
3065 .width = 4,
3066 .clkr.hw.init = &(const struct clk_init_data) {
3067 .name = "gcc_qupv3_wrap2_s3_clk_src",
3068 .parent_hws = (const struct clk_hw*[]) {
3069 &gcc_qupv3_wrap2_qspi_s3_clk_src.clkr.hw,
3070 },
3071 .num_parents = 1,
3072 .flags = CLK_SET_RATE_PARENT,
3073 .ops = &clk_regmap_div_ro_ops,
3074 },
3075 };
3076
3077 static struct clk_regmap_div gcc_qupv3_wrap2_s6_clk_src = {
3078 .reg = 0xb452c,
3079 .shift = 0,
3080 .width = 4,
3081 .clkr.hw.init = &(const struct clk_init_data) {
3082 .name = "gcc_qupv3_wrap2_s6_clk_src",
3083 .parent_hws = (const struct clk_hw*[]) {
3084 &gcc_qupv3_wrap2_qspi_s6_clk_src.clkr.hw,
3085 },
3086 .num_parents = 1,
3087 .flags = CLK_SET_RATE_PARENT,
3088 .ops = &clk_regmap_div_ro_ops,
3089 },
3090 };
3091
3092 static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = {
3093 .reg = 0xbc174,
3094 .shift = 0,
3095 .width = 4,
3096 .clkr.hw.init = &(const struct clk_init_data) {
3097 .name = "gcc_usb20_mock_utmi_postdiv_clk_src",
3098 .parent_hws = (const struct clk_hw*[]) {
3099 &gcc_usb20_mock_utmi_clk_src.clkr.hw,
3100 },
3101 .num_parents = 1,
3102 .flags = CLK_SET_RATE_PARENT,
3103 .ops = &clk_regmap_div_ro_ops,
3104 },
3105 };
3106
3107 static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = {
3108 .reg = 0x9a06c,
3109 .shift = 0,
3110 .width = 4,
3111 .clkr.hw.init = &(const struct clk_init_data) {
3112 .name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src",
3113 .parent_hws = (const struct clk_hw*[]) {
3114 &gcc_usb30_mp_mock_utmi_clk_src.clkr.hw,
3115 },
3116 .num_parents = 1,
3117 .flags = CLK_SET_RATE_PARENT,
3118 .ops = &clk_regmap_div_ro_ops,
3119 },
3120 };
3121
3122 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
3123 .reg = 0x3f07c,
3124 .shift = 0,
3125 .width = 4,
3126 .clkr.hw.init = &(const struct clk_init_data) {
3127 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
3128 .parent_hws = (const struct clk_hw*[]) {
3129 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
3130 },
3131 .num_parents = 1,
3132 .flags = CLK_SET_RATE_PARENT,
3133 .ops = &clk_regmap_div_ro_ops,
3134 },
3135 };
3136
3137 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
3138 .reg = 0xe206c,
3139 .shift = 0,
3140 .width = 4,
3141 .clkr.hw.init = &(const struct clk_init_data) {
3142 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
3143 .parent_hws = (const struct clk_hw*[]) {
3144 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
3145 },
3146 .num_parents = 1,
3147 .flags = CLK_SET_RATE_PARENT,
3148 .ops = &clk_regmap_div_ro_ops,
3149 },
3150 };
3151
3152 static struct clk_regmap_div gcc_usb30_tert_mock_utmi_postdiv_clk_src = {
3153 .reg = 0xe106c,
3154 .shift = 0,
3155 .width = 4,
3156 .clkr.hw.init = &(const struct clk_init_data) {
3157 .name = "gcc_usb30_tert_mock_utmi_postdiv_clk_src",
3158 .parent_hws = (const struct clk_hw*[]) {
3159 &gcc_usb30_tert_mock_utmi_clk_src.clkr.hw,
3160 },
3161 .num_parents = 1,
3162 .flags = CLK_SET_RATE_PARENT,
3163 .ops = &clk_regmap_div_ro_ops,
3164 },
3165 };
3166
3167 static struct clk_branch gcc_aggre_noc_pcie_3a_west_sf_axi_clk = {
3168 .halt_reg = 0xdc0bc,
3169 .halt_check = BRANCH_HALT_VOTED,
3170 .clkr = {
3171 .enable_reg = 0x62008,
3172 .enable_mask = BIT(27),
3173 .hw.init = &(const struct clk_init_data) {
3174 .name = "gcc_aggre_noc_pcie_3a_west_sf_axi_clk",
3175 .ops = &clk_branch2_ops,
3176 },
3177 },
3178 };
3179
3180 static struct clk_branch gcc_aggre_noc_pcie_3b_west_sf_axi_clk = {
3181 .halt_reg = 0x941ec,
3182 .halt_check = BRANCH_HALT_VOTED,
3183 .clkr = {
3184 .enable_reg = 0x62008,
3185 .enable_mask = BIT(28),
3186 .hw.init = &(const struct clk_init_data) {
3187 .name = "gcc_aggre_noc_pcie_3b_west_sf_axi_clk",
3188 .ops = &clk_branch2_ops,
3189 },
3190 },
3191 };
3192
3193 static struct clk_branch gcc_aggre_noc_pcie_4_west_sf_axi_clk = {
3194 .halt_reg = 0x881d0,
3195 .halt_check = BRANCH_HALT_VOTED,
3196 .clkr = {
3197 .enable_reg = 0x62008,
3198 .enable_mask = BIT(29),
3199 .hw.init = &(const struct clk_init_data) {
3200 .name = "gcc_aggre_noc_pcie_4_west_sf_axi_clk",
3201 .ops = &clk_branch2_ops,
3202 },
3203 },
3204 };
3205
3206 static struct clk_branch gcc_aggre_noc_pcie_5_east_sf_axi_clk = {
3207 .halt_reg = 0xc30d0,
3208 .halt_check = BRANCH_HALT_VOTED,
3209 .clkr = {
3210 .enable_reg = 0x62008,
3211 .enable_mask = BIT(30),
3212 .hw.init = &(const struct clk_init_data) {
3213 .name = "gcc_aggre_noc_pcie_5_east_sf_axi_clk",
3214 .ops = &clk_branch2_ops,
3215 },
3216 },
3217 };
3218
3219 static struct clk_branch gcc_aggre_noc_pcie_6_west_sf_axi_clk = {
3220 .halt_reg = 0x8a1d0,
3221 .halt_check = BRANCH_HALT_VOTED,
3222 .clkr = {
3223 .enable_reg = 0x62008,
3224 .enable_mask = BIT(31),
3225 .hw.init = &(const struct clk_init_data) {
3226 .name = "gcc_aggre_noc_pcie_6_west_sf_axi_clk",
3227 .ops = &clk_branch2_ops,
3228 },
3229 },
3230 };
3231
3232 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
3233 .halt_reg = 0x77000,
3234 .halt_check = BRANCH_HALT_VOTED,
3235 .hwcg_reg = 0x77000,
3236 .hwcg_bit = 1,
3237 .clkr = {
3238 .enable_reg = 0x77000,
3239 .enable_mask = BIT(0),
3240 .hw.init = &(const struct clk_init_data) {
3241 .name = "gcc_aggre_ufs_phy_axi_clk",
3242 .parent_hws = (const struct clk_hw*[]) {
3243 &gcc_ufs_phy_axi_clk_src.clkr.hw,
3244 },
3245 .num_parents = 1,
3246 .flags = CLK_SET_RATE_PARENT,
3247 .ops = &clk_branch2_ops,
3248 },
3249 },
3250 };
3251
3252 static struct clk_branch gcc_aggre_usb2_prim_axi_clk = {
3253 .halt_reg = 0xbc17c,
3254 .halt_check = BRANCH_HALT_VOTED,
3255 .hwcg_reg = 0xbc17c,
3256 .hwcg_bit = 1,
3257 .clkr = {
3258 .enable_reg = 0xbc17c,
3259 .enable_mask = BIT(0),
3260 .hw.init = &(const struct clk_init_data) {
3261 .name = "gcc_aggre_usb2_prim_axi_clk",
3262 .parent_hws = (const struct clk_hw*[]) {
3263 &gcc_usb20_master_clk_src.clkr.hw,
3264 },
3265 .num_parents = 1,
3266 .flags = CLK_SET_RATE_PARENT,
3267 .ops = &clk_branch2_ops,
3268 },
3269 },
3270 };
3271
3272 static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {
3273 .halt_reg = 0x9a004,
3274 .halt_check = BRANCH_HALT_VOTED,
3275 .hwcg_reg = 0x9a004,
3276 .hwcg_bit = 1,
3277 .clkr = {
3278 .enable_reg = 0x9a004,
3279 .enable_mask = BIT(0),
3280 .hw.init = &(const struct clk_init_data) {
3281 .name = "gcc_aggre_usb3_mp_axi_clk",
3282 .parent_hws = (const struct clk_hw*[]) {
3283 &gcc_usb30_mp_master_clk_src.clkr.hw,
3284 },
3285 .num_parents = 1,
3286 .flags = CLK_SET_RATE_PARENT,
3287 .ops = &clk_branch2_ops,
3288 },
3289 },
3290 };
3291
3292 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
3293 .halt_reg = 0x3f00c,
3294 .halt_check = BRANCH_HALT_VOTED,
3295 .hwcg_reg = 0x3f00c,
3296 .hwcg_bit = 1,
3297 .clkr = {
3298 .enable_reg = 0x3f00c,
3299 .enable_mask = BIT(0),
3300 .hw.init = &(const struct clk_init_data) {
3301 .name = "gcc_aggre_usb3_prim_axi_clk",
3302 .parent_hws = (const struct clk_hw*[]) {
3303 &gcc_usb30_prim_master_clk_src.clkr.hw,
3304 },
3305 .num_parents = 1,
3306 .flags = CLK_SET_RATE_PARENT,
3307 .ops = &clk_branch2_ops,
3308 },
3309 },
3310 };
3311
3312 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
3313 .halt_reg = 0xe2004,
3314 .halt_check = BRANCH_HALT_VOTED,
3315 .hwcg_reg = 0xe2004,
3316 .hwcg_bit = 1,
3317 .clkr = {
3318 .enable_reg = 0xe2004,
3319 .enable_mask = BIT(0),
3320 .hw.init = &(const struct clk_init_data) {
3321 .name = "gcc_aggre_usb3_sec_axi_clk",
3322 .parent_hws = (const struct clk_hw*[]) {
3323 &gcc_usb30_sec_master_clk_src.clkr.hw,
3324 },
3325 .num_parents = 1,
3326 .flags = CLK_SET_RATE_PARENT,
3327 .ops = &clk_branch2_ops,
3328 },
3329 },
3330 };
3331
3332 static struct clk_branch gcc_aggre_usb3_tert_axi_clk = {
3333 .halt_reg = 0xe1004,
3334 .halt_check = BRANCH_HALT_VOTED,
3335 .hwcg_reg = 0xe1004,
3336 .hwcg_bit = 1,
3337 .clkr = {
3338 .enable_reg = 0xe1004,
3339 .enable_mask = BIT(0),
3340 .hw.init = &(const struct clk_init_data) {
3341 .name = "gcc_aggre_usb3_tert_axi_clk",
3342 .parent_hws = (const struct clk_hw*[]) {
3343 &gcc_usb30_tert_master_clk_src.clkr.hw,
3344 },
3345 .num_parents = 1,
3346 .flags = CLK_SET_RATE_PARENT,
3347 .ops = &clk_branch2_ops,
3348 },
3349 },
3350 };
3351
3352 static struct clk_branch gcc_aggre_usb4_0_axi_clk = {
3353 .halt_reg = 0x2b000,
3354 .halt_check = BRANCH_HALT_VOTED,
3355 .hwcg_reg = 0x2b000,
3356 .hwcg_bit = 1,
3357 .clkr = {
3358 .enable_reg = 0x2b000,
3359 .enable_mask = BIT(0),
3360 .hw.init = &(const struct clk_init_data) {
3361 .name = "gcc_aggre_usb4_0_axi_clk",
3362 .parent_hws = (const struct clk_hw*[]) {
3363 &gcc_usb4_0_master_clk_src.clkr.hw,
3364 },
3365 .num_parents = 1,
3366 .flags = CLK_SET_RATE_PARENT,
3367 .ops = &clk_branch2_ops,
3368 },
3369 },
3370 };
3371
3372 static struct clk_branch gcc_aggre_usb4_1_axi_clk = {
3373 .halt_reg = 0x2d000,
3374 .halt_check = BRANCH_HALT_VOTED,
3375 .hwcg_reg = 0x2d000,
3376 .hwcg_bit = 1,
3377 .clkr = {
3378 .enable_reg = 0x2d000,
3379 .enable_mask = BIT(0),
3380 .hw.init = &(const struct clk_init_data) {
3381 .name = "gcc_aggre_usb4_1_axi_clk",
3382 .parent_hws = (const struct clk_hw*[]) {
3383 &gcc_usb4_1_master_clk_src.clkr.hw,
3384 },
3385 .num_parents = 1,
3386 .flags = CLK_SET_RATE_PARENT,
3387 .ops = &clk_branch2_ops,
3388 },
3389 },
3390 };
3391
3392 static struct clk_branch gcc_aggre_usb4_2_axi_clk = {
3393 .halt_reg = 0xe0000,
3394 .halt_check = BRANCH_HALT_VOTED,
3395 .hwcg_reg = 0xe0000,
3396 .hwcg_bit = 1,
3397 .clkr = {
3398 .enable_reg = 0xe0000,
3399 .enable_mask = BIT(0),
3400 .hw.init = &(const struct clk_init_data) {
3401 .name = "gcc_aggre_usb4_2_axi_clk",
3402 .parent_hws = (const struct clk_hw*[]) {
3403 &gcc_usb4_2_master_clk_src.clkr.hw,
3404 },
3405 .num_parents = 1,
3406 .flags = CLK_SET_RATE_PARENT,
3407 .ops = &clk_branch2_ops,
3408 },
3409 },
3410 };
3411
3412 static struct clk_branch gcc_av1e_ahb_clk = {
3413 .halt_reg = 0x9b02c,
3414 .halt_check = BRANCH_HALT_VOTED,
3415 .hwcg_reg = 0x9b02c,
3416 .hwcg_bit = 1,
3417 .clkr = {
3418 .enable_reg = 0x9b02c,
3419 .enable_mask = BIT(0),
3420 .hw.init = &(const struct clk_init_data) {
3421 .name = "gcc_av1e_ahb_clk",
3422 .ops = &clk_branch2_ops,
3423 },
3424 },
3425 };
3426
3427 static struct clk_branch gcc_av1e_axi_clk = {
3428 .halt_reg = 0x9b030,
3429 .halt_check = BRANCH_HALT_SKIP,
3430 .hwcg_reg = 0x9b030,
3431 .hwcg_bit = 1,
3432 .clkr = {
3433 .enable_reg = 0x9b030,
3434 .enable_mask = BIT(0),
3435 .hw.init = &(const struct clk_init_data) {
3436 .name = "gcc_av1e_axi_clk",
3437 .ops = &clk_branch2_ops,
3438 },
3439 },
3440 };
3441
3442 static struct clk_branch gcc_av1e_xo_clk = {
3443 .halt_reg = 0x9b044,
3444 .halt_check = BRANCH_HALT,
3445 .clkr = {
3446 .enable_reg = 0x9b044,
3447 .enable_mask = BIT(0),
3448 .hw.init = &(const struct clk_init_data) {
3449 .name = "gcc_av1e_xo_clk",
3450 .ops = &clk_branch2_ops,
3451 },
3452 },
3453 };
3454
3455 static struct clk_branch gcc_boot_rom_ahb_clk = {
3456 .halt_reg = 0x34038,
3457 .halt_check = BRANCH_HALT_VOTED,
3458 .hwcg_reg = 0x34038,
3459 .hwcg_bit = 1,
3460 .clkr = {
3461 .enable_reg = 0x62020,
3462 .enable_mask = BIT(27),
3463 .hw.init = &(const struct clk_init_data) {
3464 .name = "gcc_boot_rom_ahb_clk",
3465 .ops = &clk_branch2_ops,
3466 },
3467 },
3468 };
3469
3470 static struct clk_branch gcc_camera_hf_axi_clk = {
3471 .halt_reg = 0x26014,
3472 .halt_check = BRANCH_HALT_SKIP,
3473 .hwcg_reg = 0x26014,
3474 .hwcg_bit = 1,
3475 .clkr = {
3476 .enable_reg = 0x26014,
3477 .enable_mask = BIT(0),
3478 .hw.init = &(const struct clk_init_data) {
3479 .name = "gcc_camera_hf_axi_clk",
3480 .ops = &clk_branch2_ops,
3481 },
3482 },
3483 };
3484
3485 static struct clk_branch gcc_camera_sf_axi_clk = {
3486 .halt_reg = 0x26028,
3487 .halt_check = BRANCH_HALT_SKIP,
3488 .hwcg_reg = 0x26028,
3489 .hwcg_bit = 1,
3490 .clkr = {
3491 .enable_reg = 0x26028,
3492 .enable_mask = BIT(0),
3493 .hw.init = &(const struct clk_init_data) {
3494 .name = "gcc_camera_sf_axi_clk",
3495 .ops = &clk_branch2_ops,
3496 },
3497 },
3498 };
3499
3500 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
3501 .halt_reg = 0x82004,
3502 .halt_check = BRANCH_HALT_VOTED,
3503 .hwcg_reg = 0x82004,
3504 .hwcg_bit = 1,
3505 .clkr = {
3506 .enable_reg = 0x62008,
3507 .enable_mask = BIT(19),
3508 .hw.init = &(const struct clk_init_data) {
3509 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
3510 .ops = &clk_branch2_ops,
3511 },
3512 },
3513 };
3514
3515 static struct clk_branch gcc_cfg_noc_pcie_anoc_south_ahb_clk = {
3516 .halt_reg = 0xba2ec,
3517 .halt_check = BRANCH_HALT_VOTED,
3518 .hwcg_reg = 0xba2ec,
3519 .hwcg_bit = 1,
3520 .clkr = {
3521 .enable_reg = 0x62008,
3522 .enable_mask = BIT(16),
3523 .hw.init = &(const struct clk_init_data) {
3524 .name = "gcc_cfg_noc_pcie_anoc_south_ahb_clk",
3525 .ops = &clk_branch2_ops,
3526 },
3527 },
3528 };
3529
3530 static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = {
3531 .halt_reg = 0xbc178,
3532 .halt_check = BRANCH_HALT_VOTED,
3533 .hwcg_reg = 0xbc178,
3534 .hwcg_bit = 1,
3535 .clkr = {
3536 .enable_reg = 0xbc178,
3537 .enable_mask = BIT(0),
3538 .hw.init = &(const struct clk_init_data) {
3539 .name = "gcc_cfg_noc_usb2_prim_axi_clk",
3540 .parent_hws = (const struct clk_hw*[]) {
3541 &gcc_usb20_master_clk_src.clkr.hw,
3542 },
3543 .num_parents = 1,
3544 .flags = CLK_SET_RATE_PARENT,
3545 .ops = &clk_branch2_ops,
3546 },
3547 },
3548 };
3549
3550 static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {
3551 .halt_reg = 0x9a000,
3552 .halt_check = BRANCH_HALT_VOTED,
3553 .hwcg_reg = 0x9a000,
3554 .hwcg_bit = 1,
3555 .clkr = {
3556 .enable_reg = 0x9a000,
3557 .enable_mask = BIT(0),
3558 .hw.init = &(const struct clk_init_data) {
3559 .name = "gcc_cfg_noc_usb3_mp_axi_clk",
3560 .parent_hws = (const struct clk_hw*[]) {
3561 &gcc_usb30_mp_master_clk_src.clkr.hw,
3562 },
3563 .num_parents = 1,
3564 .flags = CLK_SET_RATE_PARENT,
3565 .ops = &clk_branch2_ops,
3566 },
3567 },
3568 };
3569
3570 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
3571 .halt_reg = 0x3f000,
3572 .halt_check = BRANCH_HALT_VOTED,
3573 .hwcg_reg = 0x3f000,
3574 .hwcg_bit = 1,
3575 .clkr = {
3576 .enable_reg = 0x3f000,
3577 .enable_mask = BIT(0),
3578 .hw.init = &(const struct clk_init_data) {
3579 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
3580 .parent_hws = (const struct clk_hw*[]) {
3581 &gcc_usb30_prim_master_clk_src.clkr.hw,
3582 },
3583 .num_parents = 1,
3584 .flags = CLK_SET_RATE_PARENT,
3585 .ops = &clk_branch2_ops,
3586 },
3587 },
3588 };
3589
3590 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
3591 .halt_reg = 0xe2000,
3592 .halt_check = BRANCH_HALT_VOTED,
3593 .hwcg_reg = 0xe2000,
3594 .hwcg_bit = 1,
3595 .clkr = {
3596 .enable_reg = 0xe2000,
3597 .enable_mask = BIT(0),
3598 .hw.init = &(const struct clk_init_data) {
3599 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
3600 .parent_hws = (const struct clk_hw*[]) {
3601 &gcc_usb30_sec_master_clk_src.clkr.hw,
3602 },
3603 .num_parents = 1,
3604 .flags = CLK_SET_RATE_PARENT,
3605 .ops = &clk_branch2_ops,
3606 },
3607 },
3608 };
3609
3610 static struct clk_branch gcc_cfg_noc_usb3_tert_axi_clk = {
3611 .halt_reg = 0xe1000,
3612 .halt_check = BRANCH_HALT_VOTED,
3613 .hwcg_reg = 0xe1000,
3614 .hwcg_bit = 1,
3615 .clkr = {
3616 .enable_reg = 0xe1000,
3617 .enable_mask = BIT(0),
3618 .hw.init = &(const struct clk_init_data) {
3619 .name = "gcc_cfg_noc_usb3_tert_axi_clk",
3620 .parent_hws = (const struct clk_hw*[]) {
3621 &gcc_usb30_tert_master_clk_src.clkr.hw,
3622 },
3623 .num_parents = 1,
3624 .flags = CLK_SET_RATE_PARENT,
3625 .ops = &clk_branch2_ops,
3626 },
3627 },
3628 };
3629
3630 static struct clk_branch gcc_cfg_noc_usb_anoc_ahb_clk = {
3631 .halt_reg = 0x3f004,
3632 .halt_check = BRANCH_HALT_VOTED,
3633 .hwcg_reg = 0x3f004,
3634 .hwcg_bit = 1,
3635 .clkr = {
3636 .enable_reg = 0x62008,
3637 .enable_mask = BIT(17),
3638 .hw.init = &(const struct clk_init_data) {
3639 .name = "gcc_cfg_noc_usb_anoc_ahb_clk",
3640 .ops = &clk_branch2_ops,
3641 },
3642 },
3643 };
3644
3645 static struct clk_branch gcc_cfg_noc_usb_anoc_south_ahb_clk = {
3646 .halt_reg = 0x3f008,
3647 .halt_check = BRANCH_HALT_VOTED,
3648 .hwcg_reg = 0x3f008,
3649 .hwcg_bit = 1,
3650 .clkr = {
3651 .enable_reg = 0x62008,
3652 .enable_mask = BIT(18),
3653 .hw.init = &(const struct clk_init_data) {
3654 .name = "gcc_cfg_noc_usb_anoc_south_ahb_clk",
3655 .ops = &clk_branch2_ops,
3656 },
3657 },
3658 };
3659
3660 static struct clk_branch gcc_disp_hf_axi_clk = {
3661 .halt_reg = 0x27008,
3662 .halt_check = BRANCH_HALT_SKIP,
3663 .clkr = {
3664 .enable_reg = 0x27008,
3665 .enable_mask = BIT(0),
3666 .hw.init = &(const struct clk_init_data) {
3667 .name = "gcc_disp_hf_axi_clk",
3668 .ops = &clk_branch2_ops,
3669 .flags = CLK_IS_CRITICAL,
3670 },
3671 },
3672 };
3673
3674 static struct clk_branch gcc_eva_ahb_clk = {
3675 .halt_reg = 0x9b004,
3676 .halt_check = BRANCH_HALT_VOTED,
3677 .hwcg_reg = 0x9b004,
3678 .hwcg_bit = 1,
3679 .clkr = {
3680 .enable_reg = 0x9b004,
3681 .enable_mask = BIT(0),
3682 .hw.init = &(const struct clk_init_data) {
3683 .name = "gcc_eva_ahb_clk",
3684 .ops = &clk_branch2_ops,
3685 },
3686 },
3687 };
3688
3689 static struct clk_branch gcc_eva_axi0_clk = {
3690 .halt_reg = 0x9b008,
3691 .halt_check = BRANCH_HALT_SKIP,
3692 .hwcg_reg = 0x9b008,
3693 .hwcg_bit = 1,
3694 .clkr = {
3695 .enable_reg = 0x9b008,
3696 .enable_mask = BIT(0),
3697 .hw.init = &(const struct clk_init_data) {
3698 .name = "gcc_eva_axi0_clk",
3699 .ops = &clk_branch2_ops,
3700 },
3701 },
3702 };
3703
3704 static struct clk_branch gcc_eva_axi0c_clk = {
3705 .halt_reg = 0x9b01c,
3706 .halt_check = BRANCH_HALT_VOTED,
3707 .hwcg_reg = 0x9b01c,
3708 .hwcg_bit = 1,
3709 .clkr = {
3710 .enable_reg = 0x9b01c,
3711 .enable_mask = BIT(0),
3712 .hw.init = &(const struct clk_init_data) {
3713 .name = "gcc_eva_axi0c_clk",
3714 .ops = &clk_branch2_ops,
3715 },
3716 },
3717 };
3718
3719 static struct clk_branch gcc_eva_xo_clk = {
3720 .halt_reg = 0x9b024,
3721 .halt_check = BRANCH_HALT,
3722 .clkr = {
3723 .enable_reg = 0x9b024,
3724 .enable_mask = BIT(0),
3725 .hw.init = &(const struct clk_init_data) {
3726 .name = "gcc_eva_xo_clk",
3727 .ops = &clk_branch2_ops,
3728 },
3729 },
3730 };
3731
3732 static struct clk_branch gcc_gp1_clk = {
3733 .halt_reg = 0x64000,
3734 .halt_check = BRANCH_HALT,
3735 .clkr = {
3736 .enable_reg = 0x64000,
3737 .enable_mask = BIT(0),
3738 .hw.init = &(const struct clk_init_data) {
3739 .name = "gcc_gp1_clk",
3740 .parent_hws = (const struct clk_hw*[]) {
3741 &gcc_gp1_clk_src.clkr.hw,
3742 },
3743 .num_parents = 1,
3744 .flags = CLK_SET_RATE_PARENT,
3745 .ops = &clk_branch2_ops,
3746 },
3747 },
3748 };
3749
3750 static struct clk_branch gcc_gp2_clk = {
3751 .halt_reg = 0x92000,
3752 .halt_check = BRANCH_HALT,
3753 .clkr = {
3754 .enable_reg = 0x92000,
3755 .enable_mask = BIT(0),
3756 .hw.init = &(const struct clk_init_data) {
3757 .name = "gcc_gp2_clk",
3758 .parent_hws = (const struct clk_hw*[]) {
3759 &gcc_gp2_clk_src.clkr.hw,
3760 },
3761 .num_parents = 1,
3762 .flags = CLK_SET_RATE_PARENT,
3763 .ops = &clk_branch2_ops,
3764 },
3765 },
3766 };
3767
3768 static struct clk_branch gcc_gp3_clk = {
3769 .halt_reg = 0x93000,
3770 .halt_check = BRANCH_HALT,
3771 .clkr = {
3772 .enable_reg = 0x93000,
3773 .enable_mask = BIT(0),
3774 .hw.init = &(const struct clk_init_data) {
3775 .name = "gcc_gp3_clk",
3776 .parent_hws = (const struct clk_hw*[]) {
3777 &gcc_gp3_clk_src.clkr.hw,
3778 },
3779 .num_parents = 1,
3780 .flags = CLK_SET_RATE_PARENT,
3781 .ops = &clk_branch2_ops,
3782 },
3783 },
3784 };
3785
3786 static struct clk_branch gcc_gpu_gemnoc_gfx_clk = {
3787 .halt_reg = 0x71010,
3788 .halt_check = BRANCH_HALT_VOTED,
3789 .hwcg_reg = 0x71010,
3790 .hwcg_bit = 1,
3791 .clkr = {
3792 .enable_reg = 0x71010,
3793 .enable_mask = BIT(0),
3794 .hw.init = &(const struct clk_init_data) {
3795 .name = "gcc_gpu_gemnoc_gfx_clk",
3796 .ops = &clk_branch2_ops,
3797 },
3798 },
3799 };
3800
3801 static struct clk_branch gcc_gpu_gpll0_clk_src = {
3802 .halt_reg = 0x71024,
3803 .halt_check = BRANCH_HALT_VOTED,
3804 .hwcg_reg = 0x71024,
3805 .hwcg_bit = 1,
3806 .clkr = {
3807 .enable_reg = 0x62038,
3808 .enable_mask = BIT(0),
3809 .hw.init = &(const struct clk_init_data) {
3810 .name = "gcc_gpu_gpll0_clk_src",
3811 .parent_hws = (const struct clk_hw*[]) {
3812 &gcc_gpll0.clkr.hw,
3813 },
3814 .num_parents = 1,
3815 .flags = CLK_SET_RATE_PARENT,
3816 .ops = &clk_branch2_ops,
3817 },
3818 },
3819 };
3820
3821 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
3822 .halt_reg = 0x7102c,
3823 .halt_check = BRANCH_HALT_VOTED,
3824 .hwcg_reg = 0x7102c,
3825 .hwcg_bit = 1,
3826 .clkr = {
3827 .enable_reg = 0x62038,
3828 .enable_mask = BIT(1),
3829 .hw.init = &(const struct clk_init_data) {
3830 .name = "gcc_gpu_gpll0_div_clk_src",
3831 .parent_hws = (const struct clk_hw*[]) {
3832 &gcc_gpll0_out_even.clkr.hw,
3833 },
3834 .num_parents = 1,
3835 .flags = CLK_SET_RATE_PARENT,
3836 .ops = &clk_branch2_ops,
3837 },
3838 },
3839 };
3840
3841 static struct clk_branch gcc_pcie_0_aux_clk = {
3842 .halt_reg = 0xc8018,
3843 .halt_check = BRANCH_HALT_VOTED,
3844 .clkr = {
3845 .enable_reg = 0x62010,
3846 .enable_mask = BIT(25),
3847 .hw.init = &(const struct clk_init_data) {
3848 .name = "gcc_pcie_0_aux_clk",
3849 .parent_hws = (const struct clk_hw*[]) {
3850 &gcc_pcie_0_aux_clk_src.clkr.hw,
3851 },
3852 .num_parents = 1,
3853 .flags = CLK_SET_RATE_PARENT,
3854 .ops = &clk_branch2_ops,
3855 },
3856 },
3857 };
3858
3859 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
3860 .halt_reg = 0xba4a8,
3861 .halt_check = BRANCH_HALT_VOTED,
3862 .hwcg_reg = 0xba4a8,
3863 .hwcg_bit = 1,
3864 .clkr = {
3865 .enable_reg = 0x62010,
3866 .enable_mask = BIT(24),
3867 .hw.init = &(const struct clk_init_data) {
3868 .name = "gcc_pcie_0_cfg_ahb_clk",
3869 .ops = &clk_branch2_ops,
3870 },
3871 },
3872 };
3873
3874 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
3875 .halt_reg = 0xba498,
3876 .halt_check = BRANCH_HALT_SKIP,
3877 .hwcg_reg = 0xba498,
3878 .hwcg_bit = 1,
3879 .clkr = {
3880 .enable_reg = 0x62010,
3881 .enable_mask = BIT(23),
3882 .hw.init = &(const struct clk_init_data) {
3883 .name = "gcc_pcie_0_mstr_axi_clk",
3884 .ops = &clk_branch2_ops,
3885 },
3886 },
3887 };
3888
3889 static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
3890 .halt_reg = 0xc8038,
3891 .halt_check = BRANCH_HALT_VOTED,
3892 .clkr = {
3893 .enable_reg = 0x62010,
3894 .enable_mask = BIT(27),
3895 .hw.init = &(const struct clk_init_data) {
3896 .name = "gcc_pcie_0_phy_rchng_clk",
3897 .parent_hws = (const struct clk_hw*[]) {
3898 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
3899 },
3900 .num_parents = 1,
3901 .flags = CLK_SET_RATE_PARENT,
3902 .ops = &clk_branch2_ops,
3903 },
3904 },
3905 };
3906
3907 static struct clk_branch gcc_pcie_0_pipe_clk = {
3908 .halt_reg = 0xc8028,
3909 .halt_check = BRANCH_HALT_SKIP,
3910 .clkr = {
3911 .enable_reg = 0x62010,
3912 .enable_mask = BIT(26),
3913 .hw.init = &(const struct clk_init_data) {
3914 .name = "gcc_pcie_0_pipe_clk",
3915 .parent_hws = (const struct clk_hw*[]) {
3916 &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
3917 },
3918 .num_parents = 1,
3919 .flags = CLK_SET_RATE_PARENT,
3920 .ops = &clk_branch2_ops,
3921 },
3922 },
3923 };
3924
3925 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
3926 .halt_reg = 0xba488,
3927 .halt_check = BRANCH_HALT_VOTED,
3928 .hwcg_reg = 0xba488,
3929 .hwcg_bit = 1,
3930 .clkr = {
3931 .enable_reg = 0x62010,
3932 .enable_mask = BIT(22),
3933 .hw.init = &(const struct clk_init_data) {
3934 .name = "gcc_pcie_0_slv_axi_clk",
3935 .ops = &clk_branch2_ops,
3936 },
3937 },
3938 };
3939
3940 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
3941 .halt_reg = 0xba484,
3942 .halt_check = BRANCH_HALT_VOTED,
3943 .clkr = {
3944 .enable_reg = 0x62010,
3945 .enable_mask = BIT(21),
3946 .hw.init = &(const struct clk_init_data) {
3947 .name = "gcc_pcie_0_slv_q2a_axi_clk",
3948 .ops = &clk_branch2_ops,
3949 },
3950 },
3951 };
3952
3953 static struct clk_branch gcc_pcie_1_aux_clk = {
3954 .halt_reg = 0x2e018,
3955 .halt_check = BRANCH_HALT_VOTED,
3956 .clkr = {
3957 .enable_reg = 0x62010,
3958 .enable_mask = BIT(18),
3959 .hw.init = &(const struct clk_init_data) {
3960 .name = "gcc_pcie_1_aux_clk",
3961 .parent_hws = (const struct clk_hw*[]) {
3962 &gcc_pcie_1_aux_clk_src.clkr.hw,
3963 },
3964 .num_parents = 1,
3965 .flags = CLK_SET_RATE_PARENT,
3966 .ops = &clk_branch2_ops,
3967 },
3968 },
3969 };
3970
3971 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
3972 .halt_reg = 0xba480,
3973 .halt_check = BRANCH_HALT_VOTED,
3974 .hwcg_reg = 0xba480,
3975 .hwcg_bit = 1,
3976 .clkr = {
3977 .enable_reg = 0x62010,
3978 .enable_mask = BIT(17),
3979 .hw.init = &(const struct clk_init_data) {
3980 .name = "gcc_pcie_1_cfg_ahb_clk",
3981 .ops = &clk_branch2_ops,
3982 },
3983 },
3984 };
3985
3986 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
3987 .halt_reg = 0xba470,
3988 .halt_check = BRANCH_HALT_SKIP,
3989 .hwcg_reg = 0xba470,
3990 .hwcg_bit = 1,
3991 .clkr = {
3992 .enable_reg = 0x62010,
3993 .enable_mask = BIT(16),
3994 .hw.init = &(const struct clk_init_data) {
3995 .name = "gcc_pcie_1_mstr_axi_clk",
3996 .ops = &clk_branch2_ops,
3997 },
3998 },
3999 };
4000
4001 static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
4002 .halt_reg = 0x2e038,
4003 .halt_check = BRANCH_HALT_VOTED,
4004 .clkr = {
4005 .enable_reg = 0x62010,
4006 .enable_mask = BIT(20),
4007 .hw.init = &(const struct clk_init_data) {
4008 .name = "gcc_pcie_1_phy_rchng_clk",
4009 .parent_hws = (const struct clk_hw*[]) {
4010 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
4011 },
4012 .num_parents = 1,
4013 .flags = CLK_SET_RATE_PARENT,
4014 .ops = &clk_branch2_ops,
4015 },
4016 },
4017 };
4018
4019 static struct clk_branch gcc_pcie_1_pipe_clk = {
4020 .halt_reg = 0x2e028,
4021 .halt_check = BRANCH_HALT_SKIP,
4022 .clkr = {
4023 .enable_reg = 0x62010,
4024 .enable_mask = BIT(19),
4025 .hw.init = &(const struct clk_init_data) {
4026 .name = "gcc_pcie_1_pipe_clk",
4027 .parent_hws = (const struct clk_hw*[]) {
4028 &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
4029 },
4030 .num_parents = 1,
4031 .flags = CLK_SET_RATE_PARENT,
4032 .ops = &clk_branch2_ops,
4033 },
4034 },
4035 };
4036
4037 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
4038 .halt_reg = 0xba460,
4039 .halt_check = BRANCH_HALT_VOTED,
4040 .hwcg_reg = 0xba460,
4041 .hwcg_bit = 1,
4042 .clkr = {
4043 .enable_reg = 0x62010,
4044 .enable_mask = BIT(15),
4045 .hw.init = &(const struct clk_init_data) {
4046 .name = "gcc_pcie_1_slv_axi_clk",
4047 .ops = &clk_branch2_ops,
4048 },
4049 },
4050 };
4051
4052 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
4053 .halt_reg = 0xba45c,
4054 .halt_check = BRANCH_HALT_VOTED,
4055 .clkr = {
4056 .enable_reg = 0x62010,
4057 .enable_mask = BIT(14),
4058 .hw.init = &(const struct clk_init_data) {
4059 .name = "gcc_pcie_1_slv_q2a_axi_clk",
4060 .ops = &clk_branch2_ops,
4061 },
4062 },
4063 };
4064
4065 static struct clk_branch gcc_pcie_2_aux_clk = {
4066 .halt_reg = 0xc0018,
4067 .halt_check = BRANCH_HALT_VOTED,
4068 .clkr = {
4069 .enable_reg = 0x62018,
4070 .enable_mask = BIT(0),
4071 .hw.init = &(const struct clk_init_data) {
4072 .name = "gcc_pcie_2_aux_clk",
4073 .parent_hws = (const struct clk_hw*[]) {
4074 &gcc_pcie_2_aux_clk_src.clkr.hw,
4075 },
4076 .num_parents = 1,
4077 .flags = CLK_SET_RATE_PARENT,
4078 .ops = &clk_branch2_ops,
4079 },
4080 },
4081 };
4082
4083 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
4084 .halt_reg = 0xba4d0,
4085 .halt_check = BRANCH_HALT_VOTED,
4086 .hwcg_reg = 0xba4d0,
4087 .hwcg_bit = 1,
4088 .clkr = {
4089 .enable_reg = 0x62010,
4090 .enable_mask = BIT(31),
4091 .hw.init = &(const struct clk_init_data) {
4092 .name = "gcc_pcie_2_cfg_ahb_clk",
4093 .ops = &clk_branch2_ops,
4094 },
4095 },
4096 };
4097
4098 static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
4099 .halt_reg = 0xba4c0,
4100 .halt_check = BRANCH_HALT_SKIP,
4101 .hwcg_reg = 0xba4c0,
4102 .hwcg_bit = 1,
4103 .clkr = {
4104 .enable_reg = 0x62010,
4105 .enable_mask = BIT(30),
4106 .hw.init = &(const struct clk_init_data) {
4107 .name = "gcc_pcie_2_mstr_axi_clk",
4108 .ops = &clk_branch2_ops,
4109 },
4110 },
4111 };
4112
4113 static struct clk_branch gcc_pcie_2_phy_rchng_clk = {
4114 .halt_reg = 0xc0038,
4115 .halt_check = BRANCH_HALT_VOTED,
4116 .clkr = {
4117 .enable_reg = 0x62018,
4118 .enable_mask = BIT(2),
4119 .hw.init = &(const struct clk_init_data) {
4120 .name = "gcc_pcie_2_phy_rchng_clk",
4121 .parent_hws = (const struct clk_hw*[]) {
4122 &gcc_pcie_2_phy_rchng_clk_src.clkr.hw,
4123 },
4124 .num_parents = 1,
4125 .flags = CLK_SET_RATE_PARENT,
4126 .ops = &clk_branch2_ops,
4127 },
4128 },
4129 };
4130
4131 static struct clk_branch gcc_pcie_2_pipe_clk = {
4132 .halt_reg = 0xc0028,
4133 .halt_check = BRANCH_HALT_SKIP,
4134 .clkr = {
4135 .enable_reg = 0x62018,
4136 .enable_mask = BIT(1),
4137 .hw.init = &(const struct clk_init_data) {
4138 .name = "gcc_pcie_2_pipe_clk",
4139 .parent_hws = (const struct clk_hw*[]) {
4140 &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
4141 },
4142 .num_parents = 1,
4143 .flags = CLK_SET_RATE_PARENT,
4144 .ops = &clk_branch2_ops,
4145 },
4146 },
4147 };
4148
4149 static struct clk_branch gcc_pcie_2_slv_axi_clk = {
4150 .halt_reg = 0xba4b0,
4151 .halt_check = BRANCH_HALT_VOTED,
4152 .hwcg_reg = 0xba4b0,
4153 .hwcg_bit = 1,
4154 .clkr = {
4155 .enable_reg = 0x62010,
4156 .enable_mask = BIT(29),
4157 .hw.init = &(const struct clk_init_data) {
4158 .name = "gcc_pcie_2_slv_axi_clk",
4159 .ops = &clk_branch2_ops,
4160 },
4161 },
4162 };
4163
4164 static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
4165 .halt_reg = 0xba4ac,
4166 .halt_check = BRANCH_HALT_VOTED,
4167 .clkr = {
4168 .enable_reg = 0x62010,
4169 .enable_mask = BIT(28),
4170 .hw.init = &(const struct clk_init_data) {
4171 .name = "gcc_pcie_2_slv_q2a_axi_clk",
4172 .ops = &clk_branch2_ops,
4173 },
4174 },
4175 };
4176
4177 static struct clk_branch gcc_pcie_3a_aux_clk = {
4178 .halt_reg = 0xdc04c,
4179 .halt_check = BRANCH_HALT_VOTED,
4180 .hwcg_reg = 0xdc04c,
4181 .hwcg_bit = 1,
4182 .clkr = {
4183 .enable_reg = 0x62028,
4184 .enable_mask = BIT(16),
4185 .hw.init = &(const struct clk_init_data) {
4186 .name = "gcc_pcie_3a_aux_clk",
4187 .parent_hws = (const struct clk_hw*[]) {
4188 &gcc_pcie_3a_aux_clk_src.clkr.hw,
4189 },
4190 .num_parents = 1,
4191 .flags = CLK_SET_RATE_PARENT,
4192 .ops = &clk_branch2_ops,
4193 },
4194 },
4195 };
4196
4197 static struct clk_branch gcc_pcie_3a_cfg_ahb_clk = {
4198 .halt_reg = 0xba4f0,
4199 .halt_check = BRANCH_HALT_VOTED,
4200 .hwcg_reg = 0xba4f0,
4201 .hwcg_bit = 1,
4202 .clkr = {
4203 .enable_reg = 0x62028,
4204 .enable_mask = BIT(15),
4205 .hw.init = &(const struct clk_init_data) {
4206 .name = "gcc_pcie_3a_cfg_ahb_clk",
4207 .ops = &clk_branch2_ops,
4208 },
4209 },
4210 };
4211
4212 static struct clk_branch gcc_pcie_3a_mstr_axi_clk = {
4213 .halt_reg = 0xdc038,
4214 .halt_check = BRANCH_HALT_SKIP,
4215 .hwcg_reg = 0xdc038,
4216 .hwcg_bit = 1,
4217 .clkr = {
4218 .enable_reg = 0x62028,
4219 .enable_mask = BIT(14),
4220 .hw.init = &(const struct clk_init_data) {
4221 .name = "gcc_pcie_3a_mstr_axi_clk",
4222 .ops = &clk_branch2_ops,
4223 },
4224 },
4225 };
4226
4227 static struct clk_branch gcc_pcie_3a_phy_rchng_clk = {
4228 .halt_reg = 0xdc06c,
4229 .halt_check = BRANCH_HALT_VOTED,
4230 .hwcg_reg = 0xdc06c,
4231 .hwcg_bit = 1,
4232 .clkr = {
4233 .enable_reg = 0x62028,
4234 .enable_mask = BIT(18),
4235 .hw.init = &(const struct clk_init_data) {
4236 .name = "gcc_pcie_3a_phy_rchng_clk",
4237 .parent_hws = (const struct clk_hw*[]) {
4238 &gcc_pcie_3a_phy_rchng_clk_src.clkr.hw,
4239 },
4240 .num_parents = 1,
4241 .flags = CLK_SET_RATE_PARENT,
4242 .ops = &clk_branch2_ops,
4243 },
4244 },
4245 };
4246
4247 static struct clk_branch gcc_pcie_3a_pipe_clk = {
4248 .halt_reg = 0xdc05c,
4249 .halt_check = BRANCH_HALT_SKIP,
4250 .hwcg_reg = 0xdc05c,
4251 .hwcg_bit = 1,
4252 .clkr = {
4253 .enable_reg = 0x62028,
4254 .enable_mask = BIT(17),
4255 .hw.init = &(const struct clk_init_data) {
4256 .name = "gcc_pcie_3a_pipe_clk",
4257 .parent_hws = (const struct clk_hw*[]) {
4258 &gcc_pcie_3a_pipe_clk_src.clkr.hw,
4259 },
4260 .num_parents = 1,
4261 .flags = CLK_SET_RATE_PARENT,
4262 .ops = &clk_branch2_ops,
4263 },
4264 },
4265 };
4266
4267 static struct clk_branch gcc_pcie_3a_slv_axi_clk = {
4268 .halt_reg = 0xdc024,
4269 .halt_check = BRANCH_HALT_VOTED,
4270 .hwcg_reg = 0xdc024,
4271 .hwcg_bit = 1,
4272 .clkr = {
4273 .enable_reg = 0x62028,
4274 .enable_mask = BIT(13),
4275 .hw.init = &(const struct clk_init_data) {
4276 .name = "gcc_pcie_3a_slv_axi_clk",
4277 .ops = &clk_branch2_ops,
4278 },
4279 },
4280 };
4281
4282 static struct clk_branch gcc_pcie_3a_slv_q2a_axi_clk = {
4283 .halt_reg = 0xdc01c,
4284 .halt_check = BRANCH_HALT_VOTED,
4285 .hwcg_reg = 0xdc01c,
4286 .hwcg_bit = 1,
4287 .clkr = {
4288 .enable_reg = 0x62028,
4289 .enable_mask = BIT(12),
4290 .hw.init = &(const struct clk_init_data) {
4291 .name = "gcc_pcie_3a_slv_q2a_axi_clk",
4292 .ops = &clk_branch2_ops,
4293 },
4294 },
4295 };
4296
4297 static struct clk_branch gcc_pcie_3b_aux_clk = {
4298 .halt_reg = 0x94050,
4299 .halt_check = BRANCH_HALT_VOTED,
4300 .clkr = {
4301 .enable_reg = 0x62028,
4302 .enable_mask = BIT(25),
4303 .hw.init = &(const struct clk_init_data) {
4304 .name = "gcc_pcie_3b_aux_clk",
4305 .parent_hws = (const struct clk_hw*[]) {
4306 &gcc_pcie_3b_aux_clk_src.clkr.hw,
4307 },
4308 .num_parents = 1,
4309 .flags = CLK_SET_RATE_PARENT,
4310 .ops = &clk_branch2_ops,
4311 },
4312 },
4313 };
4314
4315 static struct clk_branch gcc_pcie_3b_cfg_ahb_clk = {
4316 .halt_reg = 0xba4f4,
4317 .halt_check = BRANCH_HALT_VOTED,
4318 .hwcg_reg = 0xba4f4,
4319 .hwcg_bit = 1,
4320 .clkr = {
4321 .enable_reg = 0x62028,
4322 .enable_mask = BIT(24),
4323 .hw.init = &(const struct clk_init_data) {
4324 .name = "gcc_pcie_3b_cfg_ahb_clk",
4325 .ops = &clk_branch2_ops,
4326 },
4327 },
4328 };
4329
4330 static struct clk_branch gcc_pcie_3b_mstr_axi_clk = {
4331 .halt_reg = 0x94038,
4332 .halt_check = BRANCH_HALT_SKIP,
4333 .hwcg_reg = 0x94038,
4334 .hwcg_bit = 1,
4335 .clkr = {
4336 .enable_reg = 0x62028,
4337 .enable_mask = BIT(23),
4338 .hw.init = &(const struct clk_init_data) {
4339 .name = "gcc_pcie_3b_mstr_axi_clk",
4340 .ops = &clk_branch2_ops,
4341 },
4342 },
4343 };
4344
4345 static struct clk_branch gcc_pcie_3b_phy_rchng_clk = {
4346 .halt_reg = 0x94084,
4347 .halt_check = BRANCH_HALT_VOTED,
4348 .clkr = {
4349 .enable_reg = 0x62028,
4350 .enable_mask = BIT(28),
4351 .hw.init = &(const struct clk_init_data) {
4352 .name = "gcc_pcie_3b_phy_rchng_clk",
4353 .parent_hws = (const struct clk_hw*[]) {
4354 &gcc_pcie_3b_phy_rchng_clk_src.clkr.hw,
4355 },
4356 .num_parents = 1,
4357 .flags = CLK_SET_RATE_PARENT,
4358 .ops = &clk_branch2_ops,
4359 },
4360 },
4361 };
4362
4363 static struct clk_branch gcc_pcie_3b_pipe_clk = {
4364 .halt_reg = 0x94060,
4365 .halt_check = BRANCH_HALT_SKIP,
4366 .clkr = {
4367 .enable_reg = 0x62028,
4368 .enable_mask = BIT(26),
4369 .hw.init = &(const struct clk_init_data) {
4370 .name = "gcc_pcie_3b_pipe_clk",
4371 .parent_hws = (const struct clk_hw*[]) {
4372 &gcc_pcie_3b_pipe_clk_src.clkr.hw,
4373 },
4374 .num_parents = 1,
4375 .flags = CLK_SET_RATE_PARENT,
4376 .ops = &clk_branch2_ops,
4377 },
4378 },
4379 };
4380
4381 static struct clk_branch gcc_pcie_3b_pipe_div2_clk = {
4382 .halt_reg = 0x94074,
4383 .halt_check = BRANCH_HALT_SKIP,
4384 .clkr = {
4385 .enable_reg = 0x62028,
4386 .enable_mask = BIT(27),
4387 .hw.init = &(const struct clk_init_data) {
4388 .name = "gcc_pcie_3b_pipe_div2_clk",
4389 .parent_hws = (const struct clk_hw*[]) {
4390 &gcc_pcie_3b_pipe_div_clk_src.clkr.hw,
4391 },
4392 .num_parents = 1,
4393 .flags = CLK_SET_RATE_PARENT,
4394 .ops = &clk_branch2_ops,
4395 },
4396 },
4397 };
4398
4399 static struct clk_branch gcc_pcie_3b_slv_axi_clk = {
4400 .halt_reg = 0x94024,
4401 .halt_check = BRANCH_HALT_VOTED,
4402 .hwcg_reg = 0x94024,
4403 .hwcg_bit = 1,
4404 .clkr = {
4405 .enable_reg = 0x62028,
4406 .enable_mask = BIT(22),
4407 .hw.init = &(const struct clk_init_data) {
4408 .name = "gcc_pcie_3b_slv_axi_clk",
4409 .ops = &clk_branch2_ops,
4410 },
4411 },
4412 };
4413
4414 static struct clk_branch gcc_pcie_3b_slv_q2a_axi_clk = {
4415 .halt_reg = 0x9401c,
4416 .halt_check = BRANCH_HALT_VOTED,
4417 .clkr = {
4418 .enable_reg = 0x62028,
4419 .enable_mask = BIT(21),
4420 .hw.init = &(const struct clk_init_data) {
4421 .name = "gcc_pcie_3b_slv_q2a_axi_clk",
4422 .ops = &clk_branch2_ops,
4423 },
4424 },
4425 };
4426
4427 static struct clk_branch gcc_pcie_4_aux_clk = {
4428 .halt_reg = 0x88040,
4429 .halt_check = BRANCH_HALT_VOTED,
4430 .clkr = {
4431 .enable_reg = 0x62030,
4432 .enable_mask = BIT(17),
4433 .hw.init = &(const struct clk_init_data) {
4434 .name = "gcc_pcie_4_aux_clk",
4435 .parent_hws = (const struct clk_hw*[]) {
4436 &gcc_pcie_4_aux_clk_src.clkr.hw,
4437 },
4438 .num_parents = 1,
4439 .flags = CLK_SET_RATE_PARENT,
4440 .ops = &clk_branch2_ops,
4441 },
4442 },
4443 };
4444
4445 static struct clk_branch gcc_pcie_4_cfg_ahb_clk = {
4446 .halt_reg = 0xba4fc,
4447 .halt_check = BRANCH_HALT_VOTED,
4448 .hwcg_reg = 0xba4fc,
4449 .hwcg_bit = 1,
4450 .clkr = {
4451 .enable_reg = 0x62030,
4452 .enable_mask = BIT(16),
4453 .hw.init = &(const struct clk_init_data) {
4454 .name = "gcc_pcie_4_cfg_ahb_clk",
4455 .ops = &clk_branch2_ops,
4456 },
4457 },
4458 };
4459
4460 static struct clk_branch gcc_pcie_4_mstr_axi_clk = {
4461 .halt_reg = 0x88030,
4462 .halt_check = BRANCH_HALT_SKIP,
4463 .hwcg_reg = 0x88030,
4464 .hwcg_bit = 1,
4465 .clkr = {
4466 .enable_reg = 0x62030,
4467 .enable_mask = BIT(15),
4468 .hw.init = &(const struct clk_init_data) {
4469 .name = "gcc_pcie_4_mstr_axi_clk",
4470 .ops = &clk_branch2_ops,
4471 },
4472 },
4473 };
4474
4475 static struct clk_branch gcc_pcie_4_phy_rchng_clk = {
4476 .halt_reg = 0x88074,
4477 .halt_check = BRANCH_HALT_VOTED,
4478 .clkr = {
4479 .enable_reg = 0x62030,
4480 .enable_mask = BIT(20),
4481 .hw.init = &(const struct clk_init_data) {
4482 .name = "gcc_pcie_4_phy_rchng_clk",
4483 .parent_hws = (const struct clk_hw*[]) {
4484 &gcc_pcie_4_phy_rchng_clk_src.clkr.hw,
4485 },
4486 .num_parents = 1,
4487 .flags = CLK_SET_RATE_PARENT,
4488 .ops = &clk_branch2_ops,
4489 },
4490 },
4491 };
4492
4493 static struct clk_branch gcc_pcie_4_pipe_clk = {
4494 .halt_reg = 0x88050,
4495 .halt_check = BRANCH_HALT_SKIP,
4496 .clkr = {
4497 .enable_reg = 0x62030,
4498 .enable_mask = BIT(18),
4499 .hw.init = &(const struct clk_init_data) {
4500 .name = "gcc_pcie_4_pipe_clk",
4501 .parent_hws = (const struct clk_hw*[]) {
4502 &gcc_pcie_4_pipe_clk_src.clkr.hw,
4503 },
4504 .num_parents = 1,
4505 .flags = CLK_SET_RATE_PARENT,
4506 .ops = &clk_branch2_ops,
4507 },
4508 },
4509 };
4510
4511 static struct clk_branch gcc_pcie_4_pipe_div2_clk = {
4512 .halt_reg = 0x88064,
4513 .halt_check = BRANCH_HALT_SKIP,
4514 .clkr = {
4515 .enable_reg = 0x62030,
4516 .enable_mask = BIT(19),
4517 .hw.init = &(const struct clk_init_data) {
4518 .name = "gcc_pcie_4_pipe_div2_clk",
4519 .parent_hws = (const struct clk_hw*[]) {
4520 &gcc_pcie_4_pipe_div_clk_src.clkr.hw,
4521 },
4522 .num_parents = 1,
4523 .flags = CLK_SET_RATE_PARENT,
4524 .ops = &clk_branch2_ops,
4525 },
4526 },
4527 };
4528
4529 static struct clk_branch gcc_pcie_4_slv_axi_clk = {
4530 .halt_reg = 0x88020,
4531 .halt_check = BRANCH_HALT_VOTED,
4532 .hwcg_reg = 0x88020,
4533 .hwcg_bit = 1,
4534 .clkr = {
4535 .enable_reg = 0x62030,
4536 .enable_mask = BIT(14),
4537 .hw.init = &(const struct clk_init_data) {
4538 .name = "gcc_pcie_4_slv_axi_clk",
4539 .ops = &clk_branch2_ops,
4540 },
4541 },
4542 };
4543
4544 static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = {
4545 .halt_reg = 0x8801c,
4546 .halt_check = BRANCH_HALT_VOTED,
4547 .clkr = {
4548 .enable_reg = 0x62030,
4549 .enable_mask = BIT(13),
4550 .hw.init = &(const struct clk_init_data) {
4551 .name = "gcc_pcie_4_slv_q2a_axi_clk",
4552 .ops = &clk_branch2_ops,
4553 },
4554 },
4555 };
4556
4557 static struct clk_branch gcc_pcie_5_aux_clk = {
4558 .halt_reg = 0xc304c,
4559 .halt_check = BRANCH_HALT_VOTED,
4560 .clkr = {
4561 .enable_reg = 0x62030,
4562 .enable_mask = BIT(5),
4563 .hw.init = &(const struct clk_init_data) {
4564 .name = "gcc_pcie_5_aux_clk",
4565 .parent_hws = (const struct clk_hw*[]) {
4566 &gcc_pcie_5_aux_clk_src.clkr.hw,
4567 },
4568 .num_parents = 1,
4569 .flags = CLK_SET_RATE_PARENT,
4570 .ops = &clk_branch2_ops,
4571 },
4572 },
4573 };
4574
4575 static struct clk_branch gcc_pcie_5_cfg_ahb_clk = {
4576 .halt_reg = 0xba4f8,
4577 .halt_check = BRANCH_HALT_VOTED,
4578 .hwcg_reg = 0xba4f8,
4579 .hwcg_bit = 1,
4580 .clkr = {
4581 .enable_reg = 0x62030,
4582 .enable_mask = BIT(4),
4583 .hw.init = &(const struct clk_init_data) {
4584 .name = "gcc_pcie_5_cfg_ahb_clk",
4585 .ops = &clk_branch2_ops,
4586 },
4587 },
4588 };
4589
4590 static struct clk_branch gcc_pcie_5_mstr_axi_clk = {
4591 .halt_reg = 0xc3038,
4592 .halt_check = BRANCH_HALT_SKIP,
4593 .hwcg_reg = 0xc3038,
4594 .hwcg_bit = 1,
4595 .clkr = {
4596 .enable_reg = 0x62030,
4597 .enable_mask = BIT(3),
4598 .hw.init = &(const struct clk_init_data) {
4599 .name = "gcc_pcie_5_mstr_axi_clk",
4600 .ops = &clk_branch2_ops,
4601 },
4602 },
4603 };
4604
4605 static struct clk_branch gcc_pcie_5_phy_rchng_clk = {
4606 .halt_reg = 0xc3080,
4607 .halt_check = BRANCH_HALT_VOTED,
4608 .clkr = {
4609 .enable_reg = 0x62030,
4610 .enable_mask = BIT(8),
4611 .hw.init = &(const struct clk_init_data) {
4612 .name = "gcc_pcie_5_phy_rchng_clk",
4613 .parent_hws = (const struct clk_hw*[]) {
4614 &gcc_pcie_5_phy_rchng_clk_src.clkr.hw,
4615 },
4616 .num_parents = 1,
4617 .flags = CLK_SET_RATE_PARENT,
4618 .ops = &clk_branch2_ops,
4619 },
4620 },
4621 };
4622
4623 static struct clk_branch gcc_pcie_5_pipe_clk = {
4624 .halt_reg = 0xc305c,
4625 .halt_check = BRANCH_HALT_SKIP,
4626 .clkr = {
4627 .enable_reg = 0x62030,
4628 .enable_mask = BIT(6),
4629 .hw.init = &(const struct clk_init_data) {
4630 .name = "gcc_pcie_5_pipe_clk",
4631 .parent_hws = (const struct clk_hw*[]) {
4632 &gcc_pcie_5_pipe_clk_src.clkr.hw,
4633 },
4634 .num_parents = 1,
4635 .flags = CLK_SET_RATE_PARENT,
4636 .ops = &clk_branch2_ops,
4637 },
4638 },
4639 };
4640
4641 static struct clk_branch gcc_pcie_5_pipe_div2_clk = {
4642 .halt_reg = 0xc3070,
4643 .halt_check = BRANCH_HALT_SKIP,
4644 .clkr = {
4645 .enable_reg = 0x62030,
4646 .enable_mask = BIT(7),
4647 .hw.init = &(const struct clk_init_data) {
4648 .name = "gcc_pcie_5_pipe_div2_clk",
4649 .parent_hws = (const struct clk_hw*[]) {
4650 &gcc_pcie_5_pipe_div_clk_src.clkr.hw,
4651 },
4652 .num_parents = 1,
4653 .flags = CLK_SET_RATE_PARENT,
4654 .ops = &clk_branch2_ops,
4655 },
4656 },
4657 };
4658
4659 static struct clk_branch gcc_pcie_5_slv_axi_clk = {
4660 .halt_reg = 0xc3024,
4661 .halt_check = BRANCH_HALT_VOTED,
4662 .hwcg_reg = 0xc3024,
4663 .hwcg_bit = 1,
4664 .clkr = {
4665 .enable_reg = 0x62030,
4666 .enable_mask = BIT(2),
4667 .hw.init = &(const struct clk_init_data) {
4668 .name = "gcc_pcie_5_slv_axi_clk",
4669 .ops = &clk_branch2_ops,
4670 },
4671 },
4672 };
4673
4674 static struct clk_branch gcc_pcie_5_slv_q2a_axi_clk = {
4675 .halt_reg = 0xc301c,
4676 .halt_check = BRANCH_HALT_VOTED,
4677 .clkr = {
4678 .enable_reg = 0x62030,
4679 .enable_mask = BIT(1),
4680 .hw.init = &(const struct clk_init_data) {
4681 .name = "gcc_pcie_5_slv_q2a_axi_clk",
4682 .ops = &clk_branch2_ops,
4683 },
4684 },
4685 };
4686
4687 static struct clk_branch gcc_pcie_6_aux_clk = {
4688 .halt_reg = 0x8a040,
4689 .halt_check = BRANCH_HALT_VOTED,
4690 .clkr = {
4691 .enable_reg = 0x62030,
4692 .enable_mask = BIT(27),
4693 .hw.init = &(const struct clk_init_data) {
4694 .name = "gcc_pcie_6_aux_clk",
4695 .parent_hws = (const struct clk_hw*[]) {
4696 &gcc_pcie_6_aux_clk_src.clkr.hw,
4697 },
4698 .num_parents = 1,
4699 .flags = CLK_SET_RATE_PARENT,
4700 .ops = &clk_branch2_ops,
4701 },
4702 },
4703 };
4704
4705 static struct clk_branch gcc_pcie_6_cfg_ahb_clk = {
4706 .halt_reg = 0xba500,
4707 .halt_check = BRANCH_HALT_VOTED,
4708 .hwcg_reg = 0xba500,
4709 .hwcg_bit = 1,
4710 .clkr = {
4711 .enable_reg = 0x62030,
4712 .enable_mask = BIT(26),
4713 .hw.init = &(const struct clk_init_data) {
4714 .name = "gcc_pcie_6_cfg_ahb_clk",
4715 .ops = &clk_branch2_ops,
4716 },
4717 },
4718 };
4719
4720 static struct clk_branch gcc_pcie_6_mstr_axi_clk = {
4721 .halt_reg = 0x8a030,
4722 .halt_check = BRANCH_HALT_SKIP,
4723 .hwcg_reg = 0x8a030,
4724 .hwcg_bit = 1,
4725 .clkr = {
4726 .enable_reg = 0x62030,
4727 .enable_mask = BIT(25),
4728 .hw.init = &(const struct clk_init_data) {
4729 .name = "gcc_pcie_6_mstr_axi_clk",
4730 .ops = &clk_branch2_ops,
4731 },
4732 },
4733 };
4734
4735 static struct clk_branch gcc_pcie_6_phy_rchng_clk = {
4736 .halt_reg = 0x8a074,
4737 .halt_check = BRANCH_HALT_VOTED,
4738 .clkr = {
4739 .enable_reg = 0x62030,
4740 .enable_mask = BIT(30),
4741 .hw.init = &(const struct clk_init_data) {
4742 .name = "gcc_pcie_6_phy_rchng_clk",
4743 .parent_hws = (const struct clk_hw*[]) {
4744 &gcc_pcie_6_phy_rchng_clk_src.clkr.hw,
4745 },
4746 .num_parents = 1,
4747 .flags = CLK_SET_RATE_PARENT,
4748 .ops = &clk_branch2_ops,
4749 },
4750 },
4751 };
4752
4753 static struct clk_branch gcc_pcie_6_pipe_clk = {
4754 .halt_reg = 0x8a050,
4755 .halt_check = BRANCH_HALT_SKIP,
4756 .clkr = {
4757 .enable_reg = 0x62030,
4758 .enable_mask = BIT(28),
4759 .hw.init = &(const struct clk_init_data) {
4760 .name = "gcc_pcie_6_pipe_clk",
4761 .parent_hws = (const struct clk_hw*[]) {
4762 &gcc_pcie_6_pipe_clk_src.clkr.hw,
4763 },
4764 .num_parents = 1,
4765 .flags = CLK_SET_RATE_PARENT,
4766 .ops = &clk_branch2_ops,
4767 },
4768 },
4769 };
4770
4771 static struct clk_branch gcc_pcie_6_pipe_div2_clk = {
4772 .halt_reg = 0x8a064,
4773 .halt_check = BRANCH_HALT_SKIP,
4774 .clkr = {
4775 .enable_reg = 0x62030,
4776 .enable_mask = BIT(29),
4777 .hw.init = &(const struct clk_init_data) {
4778 .name = "gcc_pcie_6_pipe_div2_clk",
4779 .parent_hws = (const struct clk_hw*[]) {
4780 &gcc_pcie_6_pipe_div_clk_src.clkr.hw,
4781 },
4782 .num_parents = 1,
4783 .flags = CLK_SET_RATE_PARENT,
4784 .ops = &clk_branch2_ops,
4785 },
4786 },
4787 };
4788
4789 static struct clk_branch gcc_pcie_6_slv_axi_clk = {
4790 .halt_reg = 0x8a020,
4791 .halt_check = BRANCH_HALT_VOTED,
4792 .hwcg_reg = 0x8a020,
4793 .hwcg_bit = 1,
4794 .clkr = {
4795 .enable_reg = 0x62030,
4796 .enable_mask = BIT(24),
4797 .hw.init = &(const struct clk_init_data) {
4798 .name = "gcc_pcie_6_slv_axi_clk",
4799 .ops = &clk_branch2_ops,
4800 },
4801 },
4802 };
4803
4804 static struct clk_branch gcc_pcie_6_slv_q2a_axi_clk = {
4805 .halt_reg = 0x8a01c,
4806 .halt_check = BRANCH_HALT_VOTED,
4807 .clkr = {
4808 .enable_reg = 0x62030,
4809 .enable_mask = BIT(23),
4810 .hw.init = &(const struct clk_init_data) {
4811 .name = "gcc_pcie_6_slv_q2a_axi_clk",
4812 .ops = &clk_branch2_ops,
4813 },
4814 },
4815 };
4816
4817 static struct clk_branch gcc_pcie_noc_pwrctl_clk = {
4818 .halt_reg = 0xba2ac,
4819 .halt_check = BRANCH_HALT_VOTED,
4820 .clkr = {
4821 .enable_reg = 0x62008,
4822 .enable_mask = BIT(7),
4823 .hw.init = &(const struct clk_init_data) {
4824 .name = "gcc_pcie_noc_pwrctl_clk",
4825 .ops = &clk_branch2_ops,
4826 },
4827 },
4828 };
4829
4830 static struct clk_branch gcc_pcie_noc_qosgen_extref_clk = {
4831 .halt_reg = 0xba2a8,
4832 .halt_check = BRANCH_HALT_VOTED,
4833 .clkr = {
4834 .enable_reg = 0x62008,
4835 .enable_mask = BIT(6),
4836 .hw.init = &(const struct clk_init_data) {
4837 .name = "gcc_pcie_noc_qosgen_extref_clk",
4838 .ops = &clk_branch2_ops,
4839 },
4840 },
4841 };
4842
4843 static struct clk_branch gcc_pcie_noc_sf_center_clk = {
4844 .halt_reg = 0xba2b0,
4845 .halt_check = BRANCH_HALT_VOTED,
4846 .hwcg_reg = 0xba2b0,
4847 .hwcg_bit = 1,
4848 .clkr = {
4849 .enable_reg = 0x62008,
4850 .enable_mask = BIT(8),
4851 .hw.init = &(const struct clk_init_data) {
4852 .name = "gcc_pcie_noc_sf_center_clk",
4853 .ops = &clk_branch2_ops,
4854 },
4855 },
4856 };
4857
4858 static struct clk_branch gcc_pcie_noc_slave_sf_east_clk = {
4859 .halt_reg = 0xba2b8,
4860 .halt_check = BRANCH_HALT_VOTED,
4861 .hwcg_reg = 0xba2b8,
4862 .hwcg_bit = 1,
4863 .clkr = {
4864 .enable_reg = 0x62008,
4865 .enable_mask = BIT(9),
4866 .hw.init = &(const struct clk_init_data) {
4867 .name = "gcc_pcie_noc_slave_sf_east_clk",
4868 .ops = &clk_branch2_ops,
4869 },
4870 },
4871 };
4872
4873 static struct clk_branch gcc_pcie_noc_slave_sf_west_clk = {
4874 .halt_reg = 0xba2c0,
4875 .halt_check = BRANCH_HALT_VOTED,
4876 .hwcg_reg = 0xba2c0,
4877 .hwcg_bit = 1,
4878 .clkr = {
4879 .enable_reg = 0x62008,
4880 .enable_mask = BIT(10),
4881 .hw.init = &(const struct clk_init_data) {
4882 .name = "gcc_pcie_noc_slave_sf_west_clk",
4883 .ops = &clk_branch2_ops,
4884 },
4885 },
4886 };
4887
4888 static struct clk_branch gcc_pcie_noc_tsctr_clk = {
4889 .halt_reg = 0xba2a4,
4890 .halt_check = BRANCH_HALT_VOTED,
4891 .hwcg_reg = 0xba2a4,
4892 .hwcg_bit = 1,
4893 .clkr = {
4894 .enable_reg = 0x62008,
4895 .enable_mask = BIT(5),
4896 .hw.init = &(const struct clk_init_data) {
4897 .name = "gcc_pcie_noc_tsctr_clk",
4898 .ops = &clk_branch2_ops,
4899 },
4900 },
4901 };
4902
4903 static struct clk_branch gcc_pcie_phy_3a_aux_clk = {
4904 .halt_reg = 0x6c038,
4905 .halt_check = BRANCH_HALT_VOTED,
4906 .hwcg_reg = 0x6c038,
4907 .hwcg_bit = 1,
4908 .clkr = {
4909 .enable_reg = 0x62028,
4910 .enable_mask = BIT(19),
4911 .hw.init = &(const struct clk_init_data) {
4912 .name = "gcc_pcie_phy_3a_aux_clk",
4913 .parent_hws = (const struct clk_hw*[]) {
4914 &gcc_pcie_phy_3a_aux_clk_src.clkr.hw,
4915 },
4916 .num_parents = 1,
4917 .flags = CLK_SET_RATE_PARENT,
4918 .ops = &clk_branch2_ops,
4919 },
4920 },
4921 };
4922
4923 static struct clk_branch gcc_pcie_phy_3b_aux_clk = {
4924 .halt_reg = 0x75034,
4925 .halt_check = BRANCH_HALT_VOTED,
4926 .clkr = {
4927 .enable_reg = 0x62028,
4928 .enable_mask = BIT(31),
4929 .hw.init = &(const struct clk_init_data) {
4930 .name = "gcc_pcie_phy_3b_aux_clk",
4931 .parent_hws = (const struct clk_hw*[]) {
4932 &gcc_pcie_phy_3b_aux_clk_src.clkr.hw,
4933 },
4934 .num_parents = 1,
4935 .flags = CLK_SET_RATE_PARENT,
4936 .ops = &clk_branch2_ops,
4937 },
4938 },
4939 };
4940
4941 static struct clk_branch gcc_pcie_phy_4_aux_clk = {
4942 .halt_reg = 0xd3030,
4943 .halt_check = BRANCH_HALT_VOTED,
4944 .clkr = {
4945 .enable_reg = 0x62030,
4946 .enable_mask = BIT(21),
4947 .hw.init = &(const struct clk_init_data) {
4948 .name = "gcc_pcie_phy_4_aux_clk",
4949 .parent_hws = (const struct clk_hw*[]) {
4950 &gcc_pcie_phy_4_aux_clk_src.clkr.hw,
4951 },
4952 .num_parents = 1,
4953 .flags = CLK_SET_RATE_PARENT,
4954 .ops = &clk_branch2_ops,
4955 },
4956 },
4957 };
4958
4959 static struct clk_branch gcc_pcie_phy_5_aux_clk = {
4960 .halt_reg = 0xd2030,
4961 .halt_check = BRANCH_HALT_VOTED,
4962 .clkr = {
4963 .enable_reg = 0x62030,
4964 .enable_mask = BIT(11),
4965 .hw.init = &(const struct clk_init_data) {
4966 .name = "gcc_pcie_phy_5_aux_clk",
4967 .parent_hws = (const struct clk_hw*[]) {
4968 &gcc_pcie_phy_5_aux_clk_src.clkr.hw,
4969 },
4970 .num_parents = 1,
4971 .flags = CLK_SET_RATE_PARENT,
4972 .ops = &clk_branch2_ops,
4973 },
4974 },
4975 };
4976
4977 static struct clk_branch gcc_pcie_phy_6_aux_clk = {
4978 .halt_reg = 0xd4030,
4979 .halt_check = BRANCH_HALT_VOTED,
4980 .clkr = {
4981 .enable_reg = 0x62030,
4982 .enable_mask = BIT(31),
4983 .hw.init = &(const struct clk_init_data) {
4984 .name = "gcc_pcie_phy_6_aux_clk",
4985 .parent_hws = (const struct clk_hw*[]) {
4986 &gcc_pcie_phy_6_aux_clk_src.clkr.hw,
4987 },
4988 .num_parents = 1,
4989 .flags = CLK_SET_RATE_PARENT,
4990 .ops = &clk_branch2_ops,
4991 },
4992 },
4993 };
4994
4995 static struct clk_branch gcc_pcie_rscc_cfg_ahb_clk = {
4996 .halt_reg = 0xb8004,
4997 .halt_check = BRANCH_HALT_VOTED,
4998 .hwcg_reg = 0xb8004,
4999 .hwcg_bit = 1,
5000 .clkr = {
5001 .enable_reg = 0x62038,
5002 .enable_mask = BIT(2),
5003 .hw.init = &(const struct clk_init_data) {
5004 .name = "gcc_pcie_rscc_cfg_ahb_clk",
5005 .ops = &clk_branch2_ops,
5006 },
5007 },
5008 };
5009
5010 static struct clk_branch gcc_pcie_rscc_xo_clk = {
5011 .halt_reg = 0xb8008,
5012 .halt_check = BRANCH_HALT_VOTED,
5013 .clkr = {
5014 .enable_reg = 0x62038,
5015 .enable_mask = BIT(3),
5016 .hw.init = &(const struct clk_init_data) {
5017 .name = "gcc_pcie_rscc_xo_clk",
5018 .ops = &clk_branch2_ops,
5019 },
5020 },
5021 };
5022
5023 static struct clk_branch gcc_pdm2_clk = {
5024 .halt_reg = 0x3300c,
5025 .halt_check = BRANCH_HALT,
5026 .clkr = {
5027 .enable_reg = 0x3300c,
5028 .enable_mask = BIT(0),
5029 .hw.init = &(const struct clk_init_data) {
5030 .name = "gcc_pdm2_clk",
5031 .parent_hws = (const struct clk_hw*[]) {
5032 &gcc_pdm2_clk_src.clkr.hw,
5033 },
5034 .num_parents = 1,
5035 .flags = CLK_SET_RATE_PARENT,
5036 .ops = &clk_branch2_ops,
5037 },
5038 },
5039 };
5040
5041 static struct clk_branch gcc_pdm_ahb_clk = {
5042 .halt_reg = 0x33004,
5043 .halt_check = BRANCH_HALT_VOTED,
5044 .hwcg_reg = 0x33004,
5045 .hwcg_bit = 1,
5046 .clkr = {
5047 .enable_reg = 0x33004,
5048 .enable_mask = BIT(0),
5049 .hw.init = &(const struct clk_init_data) {
5050 .name = "gcc_pdm_ahb_clk",
5051 .ops = &clk_branch2_ops,
5052 },
5053 },
5054 };
5055
5056 static struct clk_branch gcc_pdm_xo4_clk = {
5057 .halt_reg = 0x33008,
5058 .halt_check = BRANCH_HALT,
5059 .clkr = {
5060 .enable_reg = 0x33008,
5061 .enable_mask = BIT(0),
5062 .hw.init = &(const struct clk_init_data) {
5063 .name = "gcc_pdm_xo4_clk",
5064 .ops = &clk_branch2_ops,
5065 },
5066 },
5067 };
5068
5069 static struct clk_branch gcc_qmip_av1e_ahb_clk = {
5070 .halt_reg = 0x9b048,
5071 .halt_check = BRANCH_HALT_VOTED,
5072 .hwcg_reg = 0x9b048,
5073 .hwcg_bit = 1,
5074 .clkr = {
5075 .enable_reg = 0x9b048,
5076 .enable_mask = BIT(0),
5077 .hw.init = &(const struct clk_init_data) {
5078 .name = "gcc_qmip_av1e_ahb_clk",
5079 .ops = &clk_branch2_ops,
5080 },
5081 },
5082 };
5083
5084 static struct clk_branch gcc_qmip_camera_cmd_ahb_clk = {
5085 .halt_reg = 0x26010,
5086 .halt_check = BRANCH_HALT_VOTED,
5087 .hwcg_reg = 0x26010,
5088 .hwcg_bit = 1,
5089 .clkr = {
5090 .enable_reg = 0x26010,
5091 .enable_mask = BIT(0),
5092 .hw.init = &(const struct clk_init_data) {
5093 .name = "gcc_qmip_camera_cmd_ahb_clk",
5094 .ops = &clk_branch2_ops,
5095 },
5096 },
5097 };
5098
5099 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
5100 .halt_reg = 0x26008,
5101 .halt_check = BRANCH_HALT_VOTED,
5102 .hwcg_reg = 0x26008,
5103 .hwcg_bit = 1,
5104 .clkr = {
5105 .enable_reg = 0x26008,
5106 .enable_mask = BIT(0),
5107 .hw.init = &(const struct clk_init_data) {
5108 .name = "gcc_qmip_camera_nrt_ahb_clk",
5109 .ops = &clk_branch2_ops,
5110 },
5111 },
5112 };
5113
5114 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
5115 .halt_reg = 0x2600c,
5116 .halt_check = BRANCH_HALT_VOTED,
5117 .hwcg_reg = 0x2600c,
5118 .hwcg_bit = 1,
5119 .clkr = {
5120 .enable_reg = 0x2600c,
5121 .enable_mask = BIT(0),
5122 .hw.init = &(const struct clk_init_data) {
5123 .name = "gcc_qmip_camera_rt_ahb_clk",
5124 .ops = &clk_branch2_ops,
5125 },
5126 },
5127 };
5128
5129 static struct clk_branch gcc_qmip_gpu_ahb_clk = {
5130 .halt_reg = 0x71008,
5131 .halt_check = BRANCH_HALT_VOTED,
5132 .hwcg_reg = 0x71008,
5133 .hwcg_bit = 1,
5134 .clkr = {
5135 .enable_reg = 0x71008,
5136 .enable_mask = BIT(0),
5137 .hw.init = &(const struct clk_init_data) {
5138 .name = "gcc_qmip_gpu_ahb_clk",
5139 .ops = &clk_branch2_ops,
5140 },
5141 },
5142 };
5143
5144 static struct clk_branch gcc_qmip_pcie_3a_ahb_clk = {
5145 .halt_reg = 0xdc018,
5146 .halt_check = BRANCH_HALT_VOTED,
5147 .hwcg_reg = 0xdc018,
5148 .hwcg_bit = 1,
5149 .clkr = {
5150 .enable_reg = 0x62028,
5151 .enable_mask = BIT(11),
5152 .hw.init = &(const struct clk_init_data) {
5153 .name = "gcc_qmip_pcie_3a_ahb_clk",
5154 .ops = &clk_branch2_ops,
5155 },
5156 },
5157 };
5158
5159 static struct clk_branch gcc_qmip_pcie_3b_ahb_clk = {
5160 .halt_reg = 0x94018,
5161 .halt_check = BRANCH_HALT_VOTED,
5162 .hwcg_reg = 0x94018,
5163 .hwcg_bit = 1,
5164 .clkr = {
5165 .enable_reg = 0x62028,
5166 .enable_mask = BIT(20),
5167 .hw.init = &(const struct clk_init_data) {
5168 .name = "gcc_qmip_pcie_3b_ahb_clk",
5169 .ops = &clk_branch2_ops,
5170 },
5171 },
5172 };
5173
5174 static struct clk_branch gcc_qmip_pcie_4_ahb_clk = {
5175 .halt_reg = 0x88018,
5176 .halt_check = BRANCH_HALT_VOTED,
5177 .hwcg_reg = 0x88018,
5178 .hwcg_bit = 1,
5179 .clkr = {
5180 .enable_reg = 0x62030,
5181 .enable_mask = BIT(12),
5182 .hw.init = &(const struct clk_init_data) {
5183 .name = "gcc_qmip_pcie_4_ahb_clk",
5184 .ops = &clk_branch2_ops,
5185 },
5186 },
5187 };
5188
5189 static struct clk_branch gcc_qmip_pcie_5_ahb_clk = {
5190 .halt_reg = 0xc3018,
5191 .halt_check = BRANCH_HALT_VOTED,
5192 .hwcg_reg = 0xc3018,
5193 .hwcg_bit = 1,
5194 .clkr = {
5195 .enable_reg = 0x62030,
5196 .enable_mask = BIT(0),
5197 .hw.init = &(const struct clk_init_data) {
5198 .name = "gcc_qmip_pcie_5_ahb_clk",
5199 .ops = &clk_branch2_ops,
5200 },
5201 },
5202 };
5203
5204 static struct clk_branch gcc_qmip_pcie_6_ahb_clk = {
5205 .halt_reg = 0x8a018,
5206 .halt_check = BRANCH_HALT_VOTED,
5207 .hwcg_reg = 0x8a018,
5208 .hwcg_bit = 1,
5209 .clkr = {
5210 .enable_reg = 0x62030,
5211 .enable_mask = BIT(22),
5212 .hw.init = &(const struct clk_init_data) {
5213 .name = "gcc_qmip_pcie_6_ahb_clk",
5214 .ops = &clk_branch2_ops,
5215 },
5216 },
5217 };
5218
5219 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
5220 .halt_reg = 0x32018,
5221 .halt_check = BRANCH_HALT_VOTED,
5222 .hwcg_reg = 0x32018,
5223 .hwcg_bit = 1,
5224 .clkr = {
5225 .enable_reg = 0x32018,
5226 .enable_mask = BIT(0),
5227 .hw.init = &(const struct clk_init_data) {
5228 .name = "gcc_qmip_video_cv_cpu_ahb_clk",
5229 .ops = &clk_branch2_ops,
5230 },
5231 },
5232 };
5233
5234 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
5235 .halt_reg = 0x32008,
5236 .halt_check = BRANCH_HALT_VOTED,
5237 .hwcg_reg = 0x32008,
5238 .hwcg_bit = 1,
5239 .clkr = {
5240 .enable_reg = 0x32008,
5241 .enable_mask = BIT(0),
5242 .hw.init = &(const struct clk_init_data) {
5243 .name = "gcc_qmip_video_cvp_ahb_clk",
5244 .ops = &clk_branch2_ops,
5245 },
5246 },
5247 };
5248
5249 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
5250 .halt_reg = 0x32014,
5251 .halt_check = BRANCH_HALT_VOTED,
5252 .hwcg_reg = 0x32014,
5253 .hwcg_bit = 1,
5254 .clkr = {
5255 .enable_reg = 0x32014,
5256 .enable_mask = BIT(0),
5257 .hw.init = &(const struct clk_init_data) {
5258 .name = "gcc_qmip_video_v_cpu_ahb_clk",
5259 .ops = &clk_branch2_ops,
5260 },
5261 },
5262 };
5263
5264 static struct clk_branch gcc_qmip_video_vcodec1_ahb_clk = {
5265 .halt_reg = 0x32010,
5266 .halt_check = BRANCH_HALT_VOTED,
5267 .hwcg_reg = 0x32010,
5268 .hwcg_bit = 1,
5269 .clkr = {
5270 .enable_reg = 0x32010,
5271 .enable_mask = BIT(0),
5272 .hw.init = &(const struct clk_init_data) {
5273 .name = "gcc_qmip_video_vcodec1_ahb_clk",
5274 .ops = &clk_branch2_ops,
5275 },
5276 },
5277 };
5278
5279 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
5280 .halt_reg = 0x3200c,
5281 .halt_check = BRANCH_HALT_VOTED,
5282 .hwcg_reg = 0x3200c,
5283 .hwcg_bit = 1,
5284 .clkr = {
5285 .enable_reg = 0x3200c,
5286 .enable_mask = BIT(0),
5287 .hw.init = &(const struct clk_init_data) {
5288 .name = "gcc_qmip_video_vcodec_ahb_clk",
5289 .ops = &clk_branch2_ops,
5290 },
5291 },
5292 };
5293
5294 static struct clk_branch gcc_qupv3_oob_core_2x_clk = {
5295 .halt_reg = 0xc5040,
5296 .halt_check = BRANCH_HALT_VOTED,
5297 .clkr = {
5298 .enable_reg = 0x62018,
5299 .enable_mask = BIT(5),
5300 .hw.init = &(const struct clk_init_data) {
5301 .name = "gcc_qupv3_oob_core_2x_clk",
5302 .ops = &clk_branch2_ops,
5303 },
5304 },
5305 };
5306
5307 static struct clk_branch gcc_qupv3_oob_core_clk = {
5308 .halt_reg = 0xc502c,
5309 .halt_check = BRANCH_HALT_VOTED,
5310 .clkr = {
5311 .enable_reg = 0x62018,
5312 .enable_mask = BIT(4),
5313 .hw.init = &(const struct clk_init_data) {
5314 .name = "gcc_qupv3_oob_core_clk",
5315 .ops = &clk_branch2_ops,
5316 },
5317 },
5318 };
5319
5320 static struct clk_branch gcc_qupv3_oob_m_ahb_clk = {
5321 .halt_reg = 0xe7004,
5322 .halt_check = BRANCH_HALT_VOTED,
5323 .hwcg_reg = 0xe7004,
5324 .hwcg_bit = 1,
5325 .clkr = {
5326 .enable_reg = 0xe7004,
5327 .enable_mask = BIT(0),
5328 .hw.init = &(const struct clk_init_data) {
5329 .name = "gcc_qupv3_oob_m_ahb_clk",
5330 .ops = &clk_branch2_ops,
5331 },
5332 },
5333 };
5334
5335 static struct clk_branch gcc_qupv3_oob_qspi_s0_clk = {
5336 .halt_reg = 0xe7040,
5337 .halt_check = BRANCH_HALT_VOTED,
5338 .clkr = {
5339 .enable_reg = 0x62018,
5340 .enable_mask = BIT(9),
5341 .hw.init = &(const struct clk_init_data) {
5342 .name = "gcc_qupv3_oob_qspi_s0_clk",
5343 .parent_hws = (const struct clk_hw*[]) {
5344 &gcc_qupv3_oob_qspi_s0_clk_src.clkr.hw,
5345 },
5346 .num_parents = 1,
5347 .flags = CLK_SET_RATE_PARENT,
5348 .ops = &clk_branch2_ops,
5349 },
5350 },
5351 };
5352
5353 static struct clk_branch gcc_qupv3_oob_qspi_s1_clk = {
5354 .halt_reg = 0xe729c,
5355 .halt_check = BRANCH_HALT_VOTED,
5356 .clkr = {
5357 .enable_reg = 0x62018,
5358 .enable_mask = BIT(10),
5359 .hw.init = &(const struct clk_init_data) {
5360 .name = "gcc_qupv3_oob_qspi_s1_clk",
5361 .parent_hws = (const struct clk_hw*[]) {
5362 &gcc_qupv3_oob_qspi_s1_clk_src.clkr.hw,
5363 },
5364 .num_parents = 1,
5365 .flags = CLK_SET_RATE_PARENT,
5366 .ops = &clk_branch2_ops,
5367 },
5368 },
5369 };
5370
5371 static struct clk_branch gcc_qupv3_oob_s0_clk = {
5372 .halt_reg = 0xe7014,
5373 .halt_check = BRANCH_HALT_VOTED,
5374 .clkr = {
5375 .enable_reg = 0x62018,
5376 .enable_mask = BIT(6),
5377 .hw.init = &(const struct clk_init_data) {
5378 .name = "gcc_qupv3_oob_s0_clk",
5379 .parent_hws = (const struct clk_hw*[]) {
5380 &gcc_qupv3_oob_s0_clk_src.clkr.hw,
5381 },
5382 .num_parents = 1,
5383 .flags = CLK_SET_RATE_PARENT,
5384 .ops = &clk_branch2_ops,
5385 },
5386 },
5387 };
5388
5389 static struct clk_branch gcc_qupv3_oob_s1_clk = {
5390 .halt_reg = 0xe7028,
5391 .halt_check = BRANCH_HALT_VOTED,
5392 .clkr = {
5393 .enable_reg = 0x62018,
5394 .enable_mask = BIT(7),
5395 .hw.init = &(const struct clk_init_data) {
5396 .name = "gcc_qupv3_oob_s1_clk",
5397 .parent_hws = (const struct clk_hw*[]) {
5398 &gcc_qupv3_oob_s1_clk_src.clkr.hw,
5399 },
5400 .num_parents = 1,
5401 .flags = CLK_SET_RATE_PARENT,
5402 .ops = &clk_branch2_ops,
5403 },
5404 },
5405 };
5406
5407 static struct clk_branch gcc_qupv3_oob_s_ahb_clk = {
5408 .halt_reg = 0xc5028,
5409 .halt_check = BRANCH_HALT_VOTED,
5410 .hwcg_reg = 0xc5028,
5411 .hwcg_bit = 1,
5412 .clkr = {
5413 .enable_reg = 0x62018,
5414 .enable_mask = BIT(3),
5415 .hw.init = &(const struct clk_init_data) {
5416 .name = "gcc_qupv3_oob_s_ahb_clk",
5417 .ops = &clk_branch2_ops,
5418 },
5419 },
5420 };
5421
5422 static struct clk_branch gcc_qupv3_oob_tcxo_clk = {
5423 .halt_reg = 0xe703c,
5424 .halt_check = BRANCH_HALT_VOTED,
5425 .clkr = {
5426 .enable_reg = 0x62018,
5427 .enable_mask = BIT(8),
5428 .hw.init = &(const struct clk_init_data) {
5429 .name = "gcc_qupv3_oob_tcxo_clk",
5430 .ops = &clk_branch2_ops,
5431 },
5432 },
5433 };
5434
5435 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
5436 .halt_reg = 0xc5448,
5437 .halt_check = BRANCH_HALT_VOTED,
5438 .clkr = {
5439 .enable_reg = 0x62020,
5440 .enable_mask = BIT(12),
5441 .hw.init = &(const struct clk_init_data) {
5442 .name = "gcc_qupv3_wrap0_core_2x_clk",
5443 .ops = &clk_branch2_ops,
5444 },
5445 },
5446 };
5447
5448 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
5449 .halt_reg = 0xc5434,
5450 .halt_check = BRANCH_HALT_VOTED,
5451 .clkr = {
5452 .enable_reg = 0x62020,
5453 .enable_mask = BIT(11),
5454 .hw.init = &(const struct clk_init_data) {
5455 .name = "gcc_qupv3_wrap0_core_clk",
5456 .ops = &clk_branch2_ops,
5457 },
5458 },
5459 };
5460
5461 static struct clk_branch gcc_qupv3_wrap0_qspi_s2_clk = {
5462 .halt_reg = 0x2879c,
5463 .halt_check = BRANCH_HALT_VOTED,
5464 .clkr = {
5465 .enable_reg = 0x62020,
5466 .enable_mask = BIT(22),
5467 .hw.init = &(const struct clk_init_data) {
5468 .name = "gcc_qupv3_wrap0_qspi_s2_clk",
5469 .parent_hws = (const struct clk_hw*[]) {
5470 &gcc_qupv3_wrap0_qspi_s2_clk_src.clkr.hw,
5471 },
5472 .num_parents = 1,
5473 .flags = CLK_SET_RATE_PARENT,
5474 .ops = &clk_branch2_ops,
5475 },
5476 },
5477 };
5478
5479 static struct clk_branch gcc_qupv3_wrap0_qspi_s3_clk = {
5480 .halt_reg = 0x288cc,
5481 .halt_check = BRANCH_HALT_VOTED,
5482 .clkr = {
5483 .enable_reg = 0x62020,
5484 .enable_mask = BIT(23),
5485 .hw.init = &(const struct clk_init_data) {
5486 .name = "gcc_qupv3_wrap0_qspi_s3_clk",
5487 .parent_hws = (const struct clk_hw*[]) {
5488 &gcc_qupv3_wrap0_qspi_s3_clk_src.clkr.hw,
5489 },
5490 .num_parents = 1,
5491 .flags = CLK_SET_RATE_PARENT,
5492 .ops = &clk_branch2_ops,
5493 },
5494 },
5495 };
5496
5497 static struct clk_branch gcc_qupv3_wrap0_qspi_s6_clk = {
5498 .halt_reg = 0x28798,
5499 .halt_check = BRANCH_HALT_VOTED,
5500 .clkr = {
5501 .enable_reg = 0x62020,
5502 .enable_mask = BIT(21),
5503 .hw.init = &(const struct clk_init_data) {
5504 .name = "gcc_qupv3_wrap0_qspi_s6_clk",
5505 .parent_hws = (const struct clk_hw*[]) {
5506 &gcc_qupv3_wrap0_qspi_s6_clk_src.clkr.hw,
5507 },
5508 .num_parents = 1,
5509 .flags = CLK_SET_RATE_PARENT,
5510 .ops = &clk_branch2_ops,
5511 },
5512 },
5513 };
5514
5515 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
5516 .halt_reg = 0x28004,
5517 .halt_check = BRANCH_HALT_VOTED,
5518 .clkr = {
5519 .enable_reg = 0x62020,
5520 .enable_mask = BIT(13),
5521 .hw.init = &(const struct clk_init_data) {
5522 .name = "gcc_qupv3_wrap0_s0_clk",
5523 .parent_hws = (const struct clk_hw*[]) {
5524 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
5525 },
5526 .num_parents = 1,
5527 .flags = CLK_SET_RATE_PARENT,
5528 .ops = &clk_branch2_ops,
5529 },
5530 },
5531 };
5532
5533 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
5534 .halt_reg = 0x28140,
5535 .halt_check = BRANCH_HALT_VOTED,
5536 .clkr = {
5537 .enable_reg = 0x62020,
5538 .enable_mask = BIT(14),
5539 .hw.init = &(const struct clk_init_data) {
5540 .name = "gcc_qupv3_wrap0_s1_clk",
5541 .parent_hws = (const struct clk_hw*[]) {
5542 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
5543 },
5544 .num_parents = 1,
5545 .flags = CLK_SET_RATE_PARENT,
5546 .ops = &clk_branch2_ops,
5547 },
5548 },
5549 };
5550
5551 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
5552 .halt_reg = 0x2827c,
5553 .halt_check = BRANCH_HALT_VOTED,
5554 .clkr = {
5555 .enable_reg = 0x62020,
5556 .enable_mask = BIT(15),
5557 .hw.init = &(const struct clk_init_data) {
5558 .name = "gcc_qupv3_wrap0_s2_clk",
5559 .parent_hws = (const struct clk_hw*[]) {
5560 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
5561 },
5562 .num_parents = 1,
5563 .flags = CLK_SET_RATE_PARENT,
5564 .ops = &clk_branch2_ops,
5565 },
5566 },
5567 };
5568
5569 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
5570 .halt_reg = 0x28290,
5571 .halt_check = BRANCH_HALT_VOTED,
5572 .clkr = {
5573 .enable_reg = 0x62020,
5574 .enable_mask = BIT(16),
5575 .hw.init = &(const struct clk_init_data) {
5576 .name = "gcc_qupv3_wrap0_s3_clk",
5577 .parent_hws = (const struct clk_hw*[]) {
5578 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
5579 },
5580 .num_parents = 1,
5581 .flags = CLK_SET_RATE_PARENT,
5582 .ops = &clk_branch2_ops,
5583 },
5584 },
5585 };
5586
5587 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
5588 .halt_reg = 0x282a4,
5589 .halt_check = BRANCH_HALT_VOTED,
5590 .clkr = {
5591 .enable_reg = 0x62020,
5592 .enable_mask = BIT(17),
5593 .hw.init = &(const struct clk_init_data) {
5594 .name = "gcc_qupv3_wrap0_s4_clk",
5595 .parent_hws = (const struct clk_hw*[]) {
5596 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
5597 },
5598 .num_parents = 1,
5599 .flags = CLK_SET_RATE_PARENT,
5600 .ops = &clk_branch2_ops,
5601 },
5602 },
5603 };
5604
5605 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
5606 .halt_reg = 0x283e0,
5607 .halt_check = BRANCH_HALT_VOTED,
5608 .clkr = {
5609 .enable_reg = 0x62020,
5610 .enable_mask = BIT(18),
5611 .hw.init = &(const struct clk_init_data) {
5612 .name = "gcc_qupv3_wrap0_s5_clk",
5613 .parent_hws = (const struct clk_hw*[]) {
5614 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
5615 },
5616 .num_parents = 1,
5617 .flags = CLK_SET_RATE_PARENT,
5618 .ops = &clk_branch2_ops,
5619 },
5620 },
5621 };
5622
5623 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
5624 .halt_reg = 0x2851c,
5625 .halt_check = BRANCH_HALT_VOTED,
5626 .clkr = {
5627 .enable_reg = 0x62020,
5628 .enable_mask = BIT(19),
5629 .hw.init = &(const struct clk_init_data) {
5630 .name = "gcc_qupv3_wrap0_s6_clk",
5631 .parent_hws = (const struct clk_hw*[]) {
5632 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
5633 },
5634 .num_parents = 1,
5635 .flags = CLK_SET_RATE_PARENT,
5636 .ops = &clk_branch2_ops,
5637 },
5638 },
5639 };
5640
5641 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
5642 .halt_reg = 0x28530,
5643 .halt_check = BRANCH_HALT_VOTED,
5644 .clkr = {
5645 .enable_reg = 0x62020,
5646 .enable_mask = BIT(20),
5647 .hw.init = &(const struct clk_init_data) {
5648 .name = "gcc_qupv3_wrap0_s7_clk",
5649 .parent_hws = (const struct clk_hw*[]) {
5650 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
5651 },
5652 .num_parents = 1,
5653 .flags = CLK_SET_RATE_PARENT,
5654 .ops = &clk_branch2_ops,
5655 },
5656 },
5657 };
5658
5659 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
5660 .halt_reg = 0xc5198,
5661 .halt_check = BRANCH_HALT_VOTED,
5662 .clkr = {
5663 .enable_reg = 0x62018,
5664 .enable_mask = BIT(14),
5665 .hw.init = &(const struct clk_init_data) {
5666 .name = "gcc_qupv3_wrap1_core_2x_clk",
5667 .ops = &clk_branch2_ops,
5668 },
5669 },
5670 };
5671
5672 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
5673 .halt_reg = 0xc5184,
5674 .halt_check = BRANCH_HALT_VOTED,
5675 .clkr = {
5676 .enable_reg = 0x62018,
5677 .enable_mask = BIT(13),
5678 .hw.init = &(const struct clk_init_data) {
5679 .name = "gcc_qupv3_wrap1_core_clk",
5680 .ops = &clk_branch2_ops,
5681 },
5682 },
5683 };
5684
5685 static struct clk_branch gcc_qupv3_wrap1_qspi_s2_clk = {
5686 .halt_reg = 0xb379c,
5687 .halt_check = BRANCH_HALT_VOTED,
5688 .clkr = {
5689 .enable_reg = 0x62018,
5690 .enable_mask = BIT(24),
5691 .hw.init = &(const struct clk_init_data) {
5692 .name = "gcc_qupv3_wrap1_qspi_s2_clk",
5693 .parent_hws = (const struct clk_hw*[]) {
5694 &gcc_qupv3_wrap1_qspi_s2_clk_src.clkr.hw,
5695 },
5696 .num_parents = 1,
5697 .flags = CLK_SET_RATE_PARENT,
5698 .ops = &clk_branch2_ops,
5699 },
5700 },
5701 };
5702
5703 static struct clk_branch gcc_qupv3_wrap1_qspi_s3_clk = {
5704 .halt_reg = 0xb38cc,
5705 .halt_check = BRANCH_HALT_VOTED,
5706 .clkr = {
5707 .enable_reg = 0x62018,
5708 .enable_mask = BIT(25),
5709 .hw.init = &(const struct clk_init_data) {
5710 .name = "gcc_qupv3_wrap1_qspi_s3_clk",
5711 .parent_hws = (const struct clk_hw*[]) {
5712 &gcc_qupv3_wrap1_qspi_s3_clk_src.clkr.hw,
5713 },
5714 .num_parents = 1,
5715 .flags = CLK_SET_RATE_PARENT,
5716 .ops = &clk_branch2_ops,
5717 },
5718 },
5719 };
5720
5721 static struct clk_branch gcc_qupv3_wrap1_qspi_s6_clk = {
5722 .halt_reg = 0xb3798,
5723 .halt_check = BRANCH_HALT_VOTED,
5724 .clkr = {
5725 .enable_reg = 0x62018,
5726 .enable_mask = BIT(23),
5727 .hw.init = &(const struct clk_init_data) {
5728 .name = "gcc_qupv3_wrap1_qspi_s6_clk",
5729 .parent_hws = (const struct clk_hw*[]) {
5730 &gcc_qupv3_wrap1_qspi_s6_clk_src.clkr.hw,
5731 },
5732 .num_parents = 1,
5733 .flags = CLK_SET_RATE_PARENT,
5734 .ops = &clk_branch2_ops,
5735 },
5736 },
5737 };
5738
5739 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
5740 .halt_reg = 0xb3004,
5741 .halt_check = BRANCH_HALT_VOTED,
5742 .clkr = {
5743 .enable_reg = 0x62018,
5744 .enable_mask = BIT(15),
5745 .hw.init = &(const struct clk_init_data) {
5746 .name = "gcc_qupv3_wrap1_s0_clk",
5747 .parent_hws = (const struct clk_hw*[]) {
5748 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
5749 },
5750 .num_parents = 1,
5751 .flags = CLK_SET_RATE_PARENT,
5752 .ops = &clk_branch2_ops,
5753 },
5754 },
5755 };
5756
5757 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
5758 .halt_reg = 0xb3140,
5759 .halt_check = BRANCH_HALT_VOTED,
5760 .clkr = {
5761 .enable_reg = 0x62018,
5762 .enable_mask = BIT(16),
5763 .hw.init = &(const struct clk_init_data) {
5764 .name = "gcc_qupv3_wrap1_s1_clk",
5765 .parent_hws = (const struct clk_hw*[]) {
5766 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
5767 },
5768 .num_parents = 1,
5769 .flags = CLK_SET_RATE_PARENT,
5770 .ops = &clk_branch2_ops,
5771 },
5772 },
5773 };
5774
5775 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
5776 .halt_reg = 0xb327c,
5777 .halt_check = BRANCH_HALT_VOTED,
5778 .clkr = {
5779 .enable_reg = 0x62018,
5780 .enable_mask = BIT(17),
5781 .hw.init = &(const struct clk_init_data) {
5782 .name = "gcc_qupv3_wrap1_s2_clk",
5783 .parent_hws = (const struct clk_hw*[]) {
5784 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
5785 },
5786 .num_parents = 1,
5787 .flags = CLK_SET_RATE_PARENT,
5788 .ops = &clk_branch2_ops,
5789 },
5790 },
5791 };
5792
5793 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
5794 .halt_reg = 0xb3290,
5795 .halt_check = BRANCH_HALT_VOTED,
5796 .clkr = {
5797 .enable_reg = 0x62018,
5798 .enable_mask = BIT(18),
5799 .hw.init = &(const struct clk_init_data) {
5800 .name = "gcc_qupv3_wrap1_s3_clk",
5801 .parent_hws = (const struct clk_hw*[]) {
5802 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
5803 },
5804 .num_parents = 1,
5805 .flags = CLK_SET_RATE_PARENT,
5806 .ops = &clk_branch2_ops,
5807 },
5808 },
5809 };
5810
5811 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
5812 .halt_reg = 0xb32a4,
5813 .halt_check = BRANCH_HALT_VOTED,
5814 .clkr = {
5815 .enable_reg = 0x62018,
5816 .enable_mask = BIT(19),
5817 .hw.init = &(const struct clk_init_data) {
5818 .name = "gcc_qupv3_wrap1_s4_clk",
5819 .parent_hws = (const struct clk_hw*[]) {
5820 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
5821 },
5822 .num_parents = 1,
5823 .flags = CLK_SET_RATE_PARENT,
5824 .ops = &clk_branch2_ops,
5825 },
5826 },
5827 };
5828
5829 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
5830 .halt_reg = 0xb33e0,
5831 .halt_check = BRANCH_HALT_VOTED,
5832 .clkr = {
5833 .enable_reg = 0x62018,
5834 .enable_mask = BIT(20),
5835 .hw.init = &(const struct clk_init_data) {
5836 .name = "gcc_qupv3_wrap1_s5_clk",
5837 .parent_hws = (const struct clk_hw*[]) {
5838 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
5839 },
5840 .num_parents = 1,
5841 .flags = CLK_SET_RATE_PARENT,
5842 .ops = &clk_branch2_ops,
5843 },
5844 },
5845 };
5846
5847 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
5848 .halt_reg = 0xb351c,
5849 .halt_check = BRANCH_HALT_VOTED,
5850 .clkr = {
5851 .enable_reg = 0x62018,
5852 .enable_mask = BIT(21),
5853 .hw.init = &(const struct clk_init_data) {
5854 .name = "gcc_qupv3_wrap1_s6_clk",
5855 .parent_hws = (const struct clk_hw*[]) {
5856 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
5857 },
5858 .num_parents = 1,
5859 .flags = CLK_SET_RATE_PARENT,
5860 .ops = &clk_branch2_ops,
5861 },
5862 },
5863 };
5864
5865 static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
5866 .halt_reg = 0xb3530,
5867 .halt_check = BRANCH_HALT_VOTED,
5868 .clkr = {
5869 .enable_reg = 0x62018,
5870 .enable_mask = BIT(22),
5871 .hw.init = &(const struct clk_init_data) {
5872 .name = "gcc_qupv3_wrap1_s7_clk",
5873 .parent_hws = (const struct clk_hw*[]) {
5874 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
5875 },
5876 .num_parents = 1,
5877 .flags = CLK_SET_RATE_PARENT,
5878 .ops = &clk_branch2_ops,
5879 },
5880 },
5881 };
5882
5883 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
5884 .halt_reg = 0xc52f0,
5885 .halt_check = BRANCH_HALT_VOTED,
5886 .clkr = {
5887 .enable_reg = 0x62018,
5888 .enable_mask = BIT(29),
5889 .hw.init = &(const struct clk_init_data) {
5890 .name = "gcc_qupv3_wrap2_core_2x_clk",
5891 .ops = &clk_branch2_ops,
5892 },
5893 },
5894 };
5895
5896 static struct clk_branch gcc_qupv3_wrap2_core_clk = {
5897 .halt_reg = 0xc52dc,
5898 .halt_check = BRANCH_HALT_VOTED,
5899 .clkr = {
5900 .enable_reg = 0x62018,
5901 .enable_mask = BIT(28),
5902 .hw.init = &(const struct clk_init_data) {
5903 .name = "gcc_qupv3_wrap2_core_clk",
5904 .ops = &clk_branch2_ops,
5905 },
5906 },
5907 };
5908
5909 static struct clk_branch gcc_qupv3_wrap2_qspi_s2_clk = {
5910 .halt_reg = 0xb479c,
5911 .halt_check = BRANCH_HALT_VOTED,
5912 .clkr = {
5913 .enable_reg = 0x62020,
5914 .enable_mask = BIT(7),
5915 .hw.init = &(const struct clk_init_data) {
5916 .name = "gcc_qupv3_wrap2_qspi_s2_clk",
5917 .parent_hws = (const struct clk_hw*[]) {
5918 &gcc_qupv3_wrap2_qspi_s2_clk_src.clkr.hw,
5919 },
5920 .num_parents = 1,
5921 .flags = CLK_SET_RATE_PARENT,
5922 .ops = &clk_branch2_ops,
5923 },
5924 },
5925 };
5926
5927 static struct clk_branch gcc_qupv3_wrap2_qspi_s3_clk = {
5928 .halt_reg = 0xb48cc,
5929 .halt_check = BRANCH_HALT_VOTED,
5930 .clkr = {
5931 .enable_reg = 0x62020,
5932 .enable_mask = BIT(8),
5933 .hw.init = &(const struct clk_init_data) {
5934 .name = "gcc_qupv3_wrap2_qspi_s3_clk",
5935 .parent_hws = (const struct clk_hw*[]) {
5936 &gcc_qupv3_wrap2_qspi_s3_clk_src.clkr.hw,
5937 },
5938 .num_parents = 1,
5939 .flags = CLK_SET_RATE_PARENT,
5940 .ops = &clk_branch2_ops,
5941 },
5942 },
5943 };
5944
5945 static struct clk_branch gcc_qupv3_wrap2_qspi_s6_clk = {
5946 .halt_reg = 0xb4798,
5947 .halt_check = BRANCH_HALT_VOTED,
5948 .clkr = {
5949 .enable_reg = 0x62020,
5950 .enable_mask = BIT(6),
5951 .hw.init = &(const struct clk_init_data) {
5952 .name = "gcc_qupv3_wrap2_qspi_s6_clk",
5953 .parent_hws = (const struct clk_hw*[]) {
5954 &gcc_qupv3_wrap2_qspi_s6_clk_src.clkr.hw,
5955 },
5956 .num_parents = 1,
5957 .flags = CLK_SET_RATE_PARENT,
5958 .ops = &clk_branch2_ops,
5959 },
5960 },
5961 };
5962
5963 static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
5964 .halt_reg = 0xb4004,
5965 .halt_check = BRANCH_HALT_VOTED,
5966 .clkr = {
5967 .enable_reg = 0x62018,
5968 .enable_mask = BIT(30),
5969 .hw.init = &(const struct clk_init_data) {
5970 .name = "gcc_qupv3_wrap2_s0_clk",
5971 .parent_hws = (const struct clk_hw*[]) {
5972 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
5973 },
5974 .num_parents = 1,
5975 .flags = CLK_SET_RATE_PARENT,
5976 .ops = &clk_branch2_ops,
5977 },
5978 },
5979 };
5980
5981 static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
5982 .halt_reg = 0xb4140,
5983 .halt_check = BRANCH_HALT_VOTED,
5984 .clkr = {
5985 .enable_reg = 0x62018,
5986 .enable_mask = BIT(31),
5987 .hw.init = &(const struct clk_init_data) {
5988 .name = "gcc_qupv3_wrap2_s1_clk",
5989 .parent_hws = (const struct clk_hw*[]) {
5990 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
5991 },
5992 .num_parents = 1,
5993 .flags = CLK_SET_RATE_PARENT,
5994 .ops = &clk_branch2_ops,
5995 },
5996 },
5997 };
5998
5999 static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
6000 .halt_reg = 0xb427c,
6001 .halt_check = BRANCH_HALT_VOTED,
6002 .clkr = {
6003 .enable_reg = 0x62020,
6004 .enable_mask = BIT(0),
6005 .hw.init = &(const struct clk_init_data) {
6006 .name = "gcc_qupv3_wrap2_s2_clk",
6007 .parent_hws = (const struct clk_hw*[]) {
6008 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
6009 },
6010 .num_parents = 1,
6011 .flags = CLK_SET_RATE_PARENT,
6012 .ops = &clk_branch2_ops,
6013 },
6014 },
6015 };
6016
6017 static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
6018 .halt_reg = 0xb4290,
6019 .halt_check = BRANCH_HALT_VOTED,
6020 .clkr = {
6021 .enable_reg = 0x62020,
6022 .enable_mask = BIT(1),
6023 .hw.init = &(const struct clk_init_data) {
6024 .name = "gcc_qupv3_wrap2_s3_clk",
6025 .parent_hws = (const struct clk_hw*[]) {
6026 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
6027 },
6028 .num_parents = 1,
6029 .flags = CLK_SET_RATE_PARENT,
6030 .ops = &clk_branch2_ops,
6031 },
6032 },
6033 };
6034
6035 static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
6036 .halt_reg = 0xb42a4,
6037 .halt_check = BRANCH_HALT_VOTED,
6038 .clkr = {
6039 .enable_reg = 0x62020,
6040 .enable_mask = BIT(2),
6041 .hw.init = &(const struct clk_init_data) {
6042 .name = "gcc_qupv3_wrap2_s4_clk",
6043 .parent_hws = (const struct clk_hw*[]) {
6044 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
6045 },
6046 .num_parents = 1,
6047 .flags = CLK_SET_RATE_PARENT,
6048 .ops = &clk_branch2_ops,
6049 },
6050 },
6051 };
6052
6053 static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
6054 .halt_reg = 0xb43e0,
6055 .halt_check = BRANCH_HALT_VOTED,
6056 .clkr = {
6057 .enable_reg = 0x62020,
6058 .enable_mask = BIT(3),
6059 .hw.init = &(const struct clk_init_data) {
6060 .name = "gcc_qupv3_wrap2_s5_clk",
6061 .parent_hws = (const struct clk_hw*[]) {
6062 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
6063 },
6064 .num_parents = 1,
6065 .flags = CLK_SET_RATE_PARENT,
6066 .ops = &clk_branch2_ops,
6067 },
6068 },
6069 };
6070
6071 static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
6072 .halt_reg = 0xb451c,
6073 .halt_check = BRANCH_HALT_VOTED,
6074 .clkr = {
6075 .enable_reg = 0x62020,
6076 .enable_mask = BIT(4),
6077 .hw.init = &(const struct clk_init_data) {
6078 .name = "gcc_qupv3_wrap2_s6_clk",
6079 .parent_hws = (const struct clk_hw*[]) {
6080 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
6081 },
6082 .num_parents = 1,
6083 .flags = CLK_SET_RATE_PARENT,
6084 .ops = &clk_branch2_ops,
6085 },
6086 },
6087 };
6088
6089 static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
6090 .halt_reg = 0xb4530,
6091 .halt_check = BRANCH_HALT_VOTED,
6092 .clkr = {
6093 .enable_reg = 0x62020,
6094 .enable_mask = BIT(5),
6095 .hw.init = &(const struct clk_init_data) {
6096 .name = "gcc_qupv3_wrap2_s7_clk",
6097 .parent_hws = (const struct clk_hw*[]) {
6098 &gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
6099 },
6100 .num_parents = 1,
6101 .flags = CLK_SET_RATE_PARENT,
6102 .ops = &clk_branch2_ops,
6103 },
6104 },
6105 };
6106
6107 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
6108 .halt_reg = 0xc542c,
6109 .halt_check = BRANCH_HALT_VOTED,
6110 .hwcg_reg = 0xc542c,
6111 .hwcg_bit = 1,
6112 .clkr = {
6113 .enable_reg = 0x62020,
6114 .enable_mask = BIT(9),
6115 .hw.init = &(const struct clk_init_data) {
6116 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
6117 .ops = &clk_branch2_ops,
6118 },
6119 },
6120 };
6121
6122 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
6123 .halt_reg = 0xc5430,
6124 .halt_check = BRANCH_HALT_VOTED,
6125 .hwcg_reg = 0xc5430,
6126 .hwcg_bit = 1,
6127 .clkr = {
6128 .enable_reg = 0x62020,
6129 .enable_mask = BIT(10),
6130 .hw.init = &(const struct clk_init_data) {
6131 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
6132 .ops = &clk_branch2_ops,
6133 },
6134 },
6135 };
6136
6137 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
6138 .halt_reg = 0xc517c,
6139 .halt_check = BRANCH_HALT_VOTED,
6140 .hwcg_reg = 0xc517c,
6141 .hwcg_bit = 1,
6142 .clkr = {
6143 .enable_reg = 0x62018,
6144 .enable_mask = BIT(11),
6145 .hw.init = &(const struct clk_init_data) {
6146 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
6147 .ops = &clk_branch2_ops,
6148 },
6149 },
6150 };
6151
6152 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
6153 .halt_reg = 0xc5180,
6154 .halt_check = BRANCH_HALT_VOTED,
6155 .hwcg_reg = 0xc5180,
6156 .hwcg_bit = 1,
6157 .clkr = {
6158 .enable_reg = 0x62018,
6159 .enable_mask = BIT(12),
6160 .hw.init = &(const struct clk_init_data) {
6161 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
6162 .ops = &clk_branch2_ops,
6163 },
6164 },
6165 };
6166
6167 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
6168 .halt_reg = 0xc52d4,
6169 .halt_check = BRANCH_HALT_VOTED,
6170 .hwcg_reg = 0xc52d4,
6171 .hwcg_bit = 1,
6172 .clkr = {
6173 .enable_reg = 0x62018,
6174 .enable_mask = BIT(26),
6175 .hw.init = &(const struct clk_init_data) {
6176 .name = "gcc_qupv3_wrap_2_m_ahb_clk",
6177 .ops = &clk_branch2_ops,
6178 },
6179 },
6180 };
6181
6182 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
6183 .halt_reg = 0xc52d8,
6184 .halt_check = BRANCH_HALT_VOTED,
6185 .hwcg_reg = 0xc52d8,
6186 .hwcg_bit = 1,
6187 .clkr = {
6188 .enable_reg = 0x62018,
6189 .enable_mask = BIT(27),
6190 .hw.init = &(const struct clk_init_data) {
6191 .name = "gcc_qupv3_wrap_2_s_ahb_clk",
6192 .ops = &clk_branch2_ops,
6193 },
6194 },
6195 };
6196
6197 static struct clk_branch gcc_sdcc2_ahb_clk = {
6198 .halt_reg = 0xb0014,
6199 .halt_check = BRANCH_HALT,
6200 .clkr = {
6201 .enable_reg = 0xb0014,
6202 .enable_mask = BIT(0),
6203 .hw.init = &(const struct clk_init_data) {
6204 .name = "gcc_sdcc2_ahb_clk",
6205 .ops = &clk_branch2_ops,
6206 },
6207 },
6208 };
6209
6210 static struct clk_branch gcc_sdcc2_apps_clk = {
6211 .halt_reg = 0xb0004,
6212 .halt_check = BRANCH_HALT,
6213 .clkr = {
6214 .enable_reg = 0xb0004,
6215 .enable_mask = BIT(0),
6216 .hw.init = &(const struct clk_init_data) {
6217 .name = "gcc_sdcc2_apps_clk",
6218 .parent_hws = (const struct clk_hw*[]) {
6219 &gcc_sdcc2_apps_clk_src.clkr.hw,
6220 },
6221 .num_parents = 1,
6222 .flags = CLK_SET_RATE_PARENT,
6223 .ops = &clk_branch2_ops,
6224 },
6225 },
6226 };
6227
6228 static struct clk_branch gcc_sdcc4_ahb_clk = {
6229 .halt_reg = 0xdf014,
6230 .halt_check = BRANCH_HALT,
6231 .clkr = {
6232 .enable_reg = 0xdf014,
6233 .enable_mask = BIT(0),
6234 .hw.init = &(const struct clk_init_data) {
6235 .name = "gcc_sdcc4_ahb_clk",
6236 .ops = &clk_branch2_ops,
6237 },
6238 },
6239 };
6240
6241 static struct clk_branch gcc_sdcc4_apps_clk = {
6242 .halt_reg = 0xdf004,
6243 .halt_check = BRANCH_HALT,
6244 .clkr = {
6245 .enable_reg = 0xdf004,
6246 .enable_mask = BIT(0),
6247 .hw.init = &(const struct clk_init_data) {
6248 .name = "gcc_sdcc4_apps_clk",
6249 .parent_hws = (const struct clk_hw*[]) {
6250 &gcc_sdcc4_apps_clk_src.clkr.hw,
6251 },
6252 .num_parents = 1,
6253 .flags = CLK_SET_RATE_PARENT,
6254 .ops = &clk_branch2_ops,
6255 },
6256 },
6257 };
6258
6259 static struct clk_branch gcc_ufs_phy_ahb_clk = {
6260 .halt_reg = 0xba504,
6261 .halt_check = BRANCH_HALT_VOTED,
6262 .hwcg_reg = 0xba504,
6263 .hwcg_bit = 1,
6264 .clkr = {
6265 .enable_reg = 0xba504,
6266 .enable_mask = BIT(0),
6267 .hw.init = &(const struct clk_init_data) {
6268 .name = "gcc_ufs_phy_ahb_clk",
6269 .ops = &clk_branch2_ops,
6270 },
6271 },
6272 };
6273
6274 static struct clk_branch gcc_ufs_phy_axi_clk = {
6275 .halt_reg = 0x7701c,
6276 .halt_check = BRANCH_HALT_VOTED,
6277 .hwcg_reg = 0x7701c,
6278 .hwcg_bit = 1,
6279 .clkr = {
6280 .enable_reg = 0x7701c,
6281 .enable_mask = BIT(0),
6282 .hw.init = &(const struct clk_init_data) {
6283 .name = "gcc_ufs_phy_axi_clk",
6284 .parent_hws = (const struct clk_hw*[]) {
6285 &gcc_ufs_phy_axi_clk_src.clkr.hw,
6286 },
6287 .num_parents = 1,
6288 .flags = CLK_SET_RATE_PARENT,
6289 .ops = &clk_branch2_ops,
6290 },
6291 },
6292 };
6293
6294 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
6295 .halt_reg = 0x77080,
6296 .halt_check = BRANCH_HALT_VOTED,
6297 .hwcg_reg = 0x77080,
6298 .hwcg_bit = 1,
6299 .clkr = {
6300 .enable_reg = 0x77080,
6301 .enable_mask = BIT(0),
6302 .hw.init = &(const struct clk_init_data) {
6303 .name = "gcc_ufs_phy_ice_core_clk",
6304 .parent_hws = (const struct clk_hw*[]) {
6305 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
6306 },
6307 .num_parents = 1,
6308 .flags = CLK_SET_RATE_PARENT,
6309 .ops = &clk_branch2_ops,
6310 },
6311 },
6312 };
6313
6314 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
6315 .halt_reg = 0x770c0,
6316 .halt_check = BRANCH_HALT_VOTED,
6317 .hwcg_reg = 0x770c0,
6318 .hwcg_bit = 1,
6319 .clkr = {
6320 .enable_reg = 0x770c0,
6321 .enable_mask = BIT(0),
6322 .hw.init = &(const struct clk_init_data) {
6323 .name = "gcc_ufs_phy_phy_aux_clk",
6324 .parent_hws = (const struct clk_hw*[]) {
6325 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
6326 },
6327 .num_parents = 1,
6328 .flags = CLK_SET_RATE_PARENT,
6329 .ops = &clk_branch2_ops,
6330 },
6331 },
6332 };
6333
6334 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
6335 .halt_reg = 0x77034,
6336 .halt_check = BRANCH_HALT_DELAY,
6337 .clkr = {
6338 .enable_reg = 0x77034,
6339 .enable_mask = BIT(0),
6340 .hw.init = &(const struct clk_init_data) {
6341 .name = "gcc_ufs_phy_rx_symbol_0_clk",
6342 .parent_hws = (const struct clk_hw*[]) {
6343 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
6344 },
6345 .num_parents = 1,
6346 .flags = CLK_SET_RATE_PARENT,
6347 .ops = &clk_branch2_ops,
6348 },
6349 },
6350 };
6351
6352 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
6353 .halt_reg = 0x770dc,
6354 .halt_check = BRANCH_HALT_DELAY,
6355 .clkr = {
6356 .enable_reg = 0x770dc,
6357 .enable_mask = BIT(0),
6358 .hw.init = &(const struct clk_init_data) {
6359 .name = "gcc_ufs_phy_rx_symbol_1_clk",
6360 .parent_hws = (const struct clk_hw*[]) {
6361 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
6362 },
6363 .num_parents = 1,
6364 .flags = CLK_SET_RATE_PARENT,
6365 .ops = &clk_branch2_ops,
6366 },
6367 },
6368 };
6369
6370 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
6371 .halt_reg = 0x77030,
6372 .halt_check = BRANCH_HALT_DELAY,
6373 .clkr = {
6374 .enable_reg = 0x77030,
6375 .enable_mask = BIT(0),
6376 .hw.init = &(const struct clk_init_data) {
6377 .name = "gcc_ufs_phy_tx_symbol_0_clk",
6378 .parent_hws = (const struct clk_hw*[]) {
6379 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
6380 },
6381 .num_parents = 1,
6382 .flags = CLK_SET_RATE_PARENT,
6383 .ops = &clk_branch2_ops,
6384 },
6385 },
6386 };
6387
6388 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
6389 .halt_reg = 0x77070,
6390 .halt_check = BRANCH_HALT_VOTED,
6391 .hwcg_reg = 0x77070,
6392 .hwcg_bit = 1,
6393 .clkr = {
6394 .enable_reg = 0x77070,
6395 .enable_mask = BIT(0),
6396 .hw.init = &(const struct clk_init_data) {
6397 .name = "gcc_ufs_phy_unipro_core_clk",
6398 .parent_hws = (const struct clk_hw*[]) {
6399 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
6400 },
6401 .num_parents = 1,
6402 .flags = CLK_SET_RATE_PARENT,
6403 .ops = &clk_branch2_ops,
6404 },
6405 },
6406 };
6407
6408 static struct clk_branch gcc_usb20_master_clk = {
6409 .halt_reg = 0xbc018,
6410 .halt_check = BRANCH_HALT,
6411 .clkr = {
6412 .enable_reg = 0xbc018,
6413 .enable_mask = BIT(0),
6414 .hw.init = &(const struct clk_init_data) {
6415 .name = "gcc_usb20_master_clk",
6416 .parent_hws = (const struct clk_hw*[]) {
6417 &gcc_usb20_master_clk_src.clkr.hw,
6418 },
6419 .num_parents = 1,
6420 .flags = CLK_SET_RATE_PARENT,
6421 .ops = &clk_branch2_ops,
6422 },
6423 },
6424 };
6425
6426 static struct clk_branch gcc_usb20_mock_utmi_clk = {
6427 .halt_reg = 0xbc02c,
6428 .halt_check = BRANCH_HALT,
6429 .clkr = {
6430 .enable_reg = 0xbc02c,
6431 .enable_mask = BIT(0),
6432 .hw.init = &(const struct clk_init_data) {
6433 .name = "gcc_usb20_mock_utmi_clk",
6434 .parent_hws = (const struct clk_hw*[]) {
6435 &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw,
6436 },
6437 .num_parents = 1,
6438 .flags = CLK_SET_RATE_PARENT,
6439 .ops = &clk_branch2_ops,
6440 },
6441 },
6442 };
6443
6444 static struct clk_branch gcc_usb20_sleep_clk = {
6445 .halt_reg = 0xbc028,
6446 .halt_check = BRANCH_HALT,
6447 .clkr = {
6448 .enable_reg = 0xbc028,
6449 .enable_mask = BIT(0),
6450 .hw.init = &(const struct clk_init_data) {
6451 .name = "gcc_usb20_sleep_clk",
6452 .ops = &clk_branch2_ops,
6453 },
6454 },
6455 };
6456
6457 static struct clk_branch gcc_usb30_mp_master_clk = {
6458 .halt_reg = 0x9a024,
6459 .halt_check = BRANCH_HALT,
6460 .clkr = {
6461 .enable_reg = 0x9a024,
6462 .enable_mask = BIT(0),
6463 .hw.init = &(const struct clk_init_data) {
6464 .name = "gcc_usb30_mp_master_clk",
6465 .parent_hws = (const struct clk_hw*[]) {
6466 &gcc_usb30_mp_master_clk_src.clkr.hw,
6467 },
6468 .num_parents = 1,
6469 .flags = CLK_SET_RATE_PARENT,
6470 .ops = &clk_branch2_ops,
6471 },
6472 },
6473 };
6474
6475 static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {
6476 .halt_reg = 0x9a038,
6477 .halt_check = BRANCH_HALT,
6478 .clkr = {
6479 .enable_reg = 0x9a038,
6480 .enable_mask = BIT(0),
6481 .hw.init = &(const struct clk_init_data) {
6482 .name = "gcc_usb30_mp_mock_utmi_clk",
6483 .parent_hws = (const struct clk_hw*[]) {
6484 &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw,
6485 },
6486 .num_parents = 1,
6487 .flags = CLK_SET_RATE_PARENT,
6488 .ops = &clk_branch2_ops,
6489 },
6490 },
6491 };
6492
6493 static struct clk_branch gcc_usb30_mp_sleep_clk = {
6494 .halt_reg = 0x9a034,
6495 .halt_check = BRANCH_HALT,
6496 .clkr = {
6497 .enable_reg = 0x9a034,
6498 .enable_mask = BIT(0),
6499 .hw.init = &(const struct clk_init_data) {
6500 .name = "gcc_usb30_mp_sleep_clk",
6501 .ops = &clk_branch2_ops,
6502 },
6503 },
6504 };
6505
6506 static struct clk_branch gcc_usb30_prim_master_clk = {
6507 .halt_reg = 0x3f030,
6508 .halt_check = BRANCH_HALT,
6509 .clkr = {
6510 .enable_reg = 0x3f030,
6511 .enable_mask = BIT(0),
6512 .hw.init = &(const struct clk_init_data) {
6513 .name = "gcc_usb30_prim_master_clk",
6514 .parent_hws = (const struct clk_hw*[]) {
6515 &gcc_usb30_prim_master_clk_src.clkr.hw,
6516 },
6517 .num_parents = 1,
6518 .flags = CLK_SET_RATE_PARENT,
6519 .ops = &clk_branch2_ops,
6520 },
6521 },
6522 };
6523
6524 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
6525 .halt_reg = 0x3f048,
6526 .halt_check = BRANCH_HALT,
6527 .clkr = {
6528 .enable_reg = 0x3f048,
6529 .enable_mask = BIT(0),
6530 .hw.init = &(const struct clk_init_data) {
6531 .name = "gcc_usb30_prim_mock_utmi_clk",
6532 .parent_hws = (const struct clk_hw*[]) {
6533 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
6534 },
6535 .num_parents = 1,
6536 .flags = CLK_SET_RATE_PARENT,
6537 .ops = &clk_branch2_ops,
6538 },
6539 },
6540 };
6541
6542 static struct clk_branch gcc_usb30_prim_sleep_clk = {
6543 .halt_reg = 0x3f044,
6544 .halt_check = BRANCH_HALT,
6545 .clkr = {
6546 .enable_reg = 0x3f044,
6547 .enable_mask = BIT(0),
6548 .hw.init = &(const struct clk_init_data) {
6549 .name = "gcc_usb30_prim_sleep_clk",
6550 .ops = &clk_branch2_ops,
6551 },
6552 },
6553 };
6554
6555 static struct clk_branch gcc_usb30_sec_master_clk = {
6556 .halt_reg = 0xe2024,
6557 .halt_check = BRANCH_HALT,
6558 .clkr = {
6559 .enable_reg = 0xe2024,
6560 .enable_mask = BIT(0),
6561 .hw.init = &(const struct clk_init_data) {
6562 .name = "gcc_usb30_sec_master_clk",
6563 .parent_hws = (const struct clk_hw*[]) {
6564 &gcc_usb30_sec_master_clk_src.clkr.hw,
6565 },
6566 .num_parents = 1,
6567 .flags = CLK_SET_RATE_PARENT,
6568 .ops = &clk_branch2_ops,
6569 },
6570 },
6571 };
6572
6573 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
6574 .halt_reg = 0xe2038,
6575 .halt_check = BRANCH_HALT,
6576 .clkr = {
6577 .enable_reg = 0xe2038,
6578 .enable_mask = BIT(0),
6579 .hw.init = &(const struct clk_init_data) {
6580 .name = "gcc_usb30_sec_mock_utmi_clk",
6581 .parent_hws = (const struct clk_hw*[]) {
6582 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
6583 },
6584 .num_parents = 1,
6585 .flags = CLK_SET_RATE_PARENT,
6586 .ops = &clk_branch2_ops,
6587 },
6588 },
6589 };
6590
6591 static struct clk_branch gcc_usb30_sec_sleep_clk = {
6592 .halt_reg = 0xe2034,
6593 .halt_check = BRANCH_HALT,
6594 .clkr = {
6595 .enable_reg = 0xe2034,
6596 .enable_mask = BIT(0),
6597 .hw.init = &(const struct clk_init_data) {
6598 .name = "gcc_usb30_sec_sleep_clk",
6599 .ops = &clk_branch2_ops,
6600 },
6601 },
6602 };
6603
6604 static struct clk_branch gcc_usb30_tert_master_clk = {
6605 .halt_reg = 0xe1024,
6606 .halt_check = BRANCH_HALT,
6607 .clkr = {
6608 .enable_reg = 0xe1024,
6609 .enable_mask = BIT(0),
6610 .hw.init = &(const struct clk_init_data) {
6611 .name = "gcc_usb30_tert_master_clk",
6612 .parent_hws = (const struct clk_hw*[]) {
6613 &gcc_usb30_tert_master_clk_src.clkr.hw,
6614 },
6615 .num_parents = 1,
6616 .flags = CLK_SET_RATE_PARENT,
6617 .ops = &clk_branch2_ops,
6618 },
6619 },
6620 };
6621
6622 static struct clk_branch gcc_usb30_tert_mock_utmi_clk = {
6623 .halt_reg = 0xe1038,
6624 .halt_check = BRANCH_HALT,
6625 .clkr = {
6626 .enable_reg = 0xe1038,
6627 .enable_mask = BIT(0),
6628 .hw.init = &(const struct clk_init_data) {
6629 .name = "gcc_usb30_tert_mock_utmi_clk",
6630 .parent_hws = (const struct clk_hw*[]) {
6631 &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr.hw,
6632 },
6633 .num_parents = 1,
6634 .flags = CLK_SET_RATE_PARENT,
6635 .ops = &clk_branch2_ops,
6636 },
6637 },
6638 };
6639
6640 static struct clk_branch gcc_usb30_tert_sleep_clk = {
6641 .halt_reg = 0xe1034,
6642 .halt_check = BRANCH_HALT,
6643 .clkr = {
6644 .enable_reg = 0xe1034,
6645 .enable_mask = BIT(0),
6646 .hw.init = &(const struct clk_init_data) {
6647 .name = "gcc_usb30_tert_sleep_clk",
6648 .ops = &clk_branch2_ops,
6649 },
6650 },
6651 };
6652
6653 static struct clk_branch gcc_usb3_mp_phy_aux_clk = {
6654 .halt_reg = 0x9a070,
6655 .halt_check = BRANCH_HALT,
6656 .clkr = {
6657 .enable_reg = 0x9a070,
6658 .enable_mask = BIT(0),
6659 .hw.init = &(const struct clk_init_data) {
6660 .name = "gcc_usb3_mp_phy_aux_clk",
6661 .parent_hws = (const struct clk_hw*[]) {
6662 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
6663 },
6664 .num_parents = 1,
6665 .flags = CLK_SET_RATE_PARENT,
6666 .ops = &clk_branch2_ops,
6667 },
6668 },
6669 };
6670
6671 static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {
6672 .halt_reg = 0x9a074,
6673 .halt_check = BRANCH_HALT,
6674 .clkr = {
6675 .enable_reg = 0x9a074,
6676 .enable_mask = BIT(0),
6677 .hw.init = &(const struct clk_init_data) {
6678 .name = "gcc_usb3_mp_phy_com_aux_clk",
6679 .parent_hws = (const struct clk_hw*[]) {
6680 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
6681 },
6682 .num_parents = 1,
6683 .flags = CLK_SET_RATE_PARENT,
6684 .ops = &clk_branch2_ops,
6685 },
6686 },
6687 };
6688
6689 static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {
6690 .halt_reg = 0x9a078,
6691 .halt_check = BRANCH_HALT_SKIP,
6692 .clkr = {
6693 .enable_reg = 0x9a078,
6694 .enable_mask = BIT(0),
6695 .hw.init = &(const struct clk_init_data) {
6696 .name = "gcc_usb3_mp_phy_pipe_0_clk",
6697 .parent_hws = (const struct clk_hw*[]) {
6698 &gcc_usb3_mp_phy_pipe_0_clk_src.clkr.hw,
6699 },
6700 .num_parents = 1,
6701 .flags = CLK_SET_RATE_PARENT,
6702 .ops = &clk_branch2_ops,
6703 },
6704 },
6705 };
6706
6707 static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {
6708 .halt_reg = 0x9a080,
6709 .halt_check = BRANCH_HALT_SKIP,
6710 .clkr = {
6711 .enable_reg = 0x9a080,
6712 .enable_mask = BIT(0),
6713 .hw.init = &(const struct clk_init_data) {
6714 .name = "gcc_usb3_mp_phy_pipe_1_clk",
6715 .parent_hws = (const struct clk_hw*[]) {
6716 &gcc_usb3_mp_phy_pipe_1_clk_src.clkr.hw,
6717 },
6718 .num_parents = 1,
6719 .flags = CLK_SET_RATE_PARENT,
6720 .ops = &clk_branch2_ops,
6721 },
6722 },
6723 };
6724
6725 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
6726 .halt_reg = 0x3f080,
6727 .halt_check = BRANCH_HALT,
6728 .clkr = {
6729 .enable_reg = 0x3f080,
6730 .enable_mask = BIT(0),
6731 .hw.init = &(const struct clk_init_data) {
6732 .name = "gcc_usb3_prim_phy_aux_clk",
6733 .parent_hws = (const struct clk_hw*[]) {
6734 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
6735 },
6736 .num_parents = 1,
6737 .flags = CLK_SET_RATE_PARENT,
6738 .ops = &clk_branch2_ops,
6739 },
6740 },
6741 };
6742
6743 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
6744 .halt_reg = 0x3f084,
6745 .halt_check = BRANCH_HALT,
6746 .clkr = {
6747 .enable_reg = 0x3f084,
6748 .enable_mask = BIT(0),
6749 .hw.init = &(const struct clk_init_data) {
6750 .name = "gcc_usb3_prim_phy_com_aux_clk",
6751 .parent_hws = (const struct clk_hw*[]) {
6752 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
6753 },
6754 .num_parents = 1,
6755 .flags = CLK_SET_RATE_PARENT,
6756 .ops = &clk_branch2_ops,
6757 },
6758 },
6759 };
6760
6761 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
6762 .halt_reg = 0x3f088,
6763 .halt_check = BRANCH_HALT_DELAY,
6764 .hwcg_reg = 0x3f088,
6765 .hwcg_bit = 1,
6766 .clkr = {
6767 .enable_reg = 0x3f088,
6768 .enable_mask = BIT(0),
6769 .hw.init = &(const struct clk_init_data) {
6770 .name = "gcc_usb3_prim_phy_pipe_clk",
6771 .parent_hws = (const struct clk_hw*[]) {
6772 &gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
6773 },
6774 .num_parents = 1,
6775 .flags = CLK_SET_RATE_PARENT,
6776 .ops = &clk_branch2_ops,
6777 },
6778 },
6779 };
6780
6781 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
6782 .halt_reg = 0xe2070,
6783 .halt_check = BRANCH_HALT,
6784 .clkr = {
6785 .enable_reg = 0xe2070,
6786 .enable_mask = BIT(0),
6787 .hw.init = &(const struct clk_init_data) {
6788 .name = "gcc_usb3_sec_phy_aux_clk",
6789 .parent_hws = (const struct clk_hw*[]) {
6790 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
6791 },
6792 .num_parents = 1,
6793 .flags = CLK_SET_RATE_PARENT,
6794 .ops = &clk_branch2_ops,
6795 },
6796 },
6797 };
6798
6799 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
6800 .halt_reg = 0xe2074,
6801 .halt_check = BRANCH_HALT,
6802 .clkr = {
6803 .enable_reg = 0xe2074,
6804 .enable_mask = BIT(0),
6805 .hw.init = &(const struct clk_init_data) {
6806 .name = "gcc_usb3_sec_phy_com_aux_clk",
6807 .parent_hws = (const struct clk_hw*[]) {
6808 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
6809 },
6810 .num_parents = 1,
6811 .flags = CLK_SET_RATE_PARENT,
6812 .ops = &clk_branch2_ops,
6813 },
6814 },
6815 };
6816
6817 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
6818 .halt_reg = 0xe2078,
6819 .halt_check = BRANCH_HALT_VOTED,
6820 .hwcg_reg = 0xe2078,
6821 .hwcg_bit = 1,
6822 .clkr = {
6823 .enable_reg = 0xe2078,
6824 .enable_mask = BIT(0),
6825 .hw.init = &(const struct clk_init_data) {
6826 .name = "gcc_usb3_sec_phy_pipe_clk",
6827 .parent_hws = (const struct clk_hw*[]) {
6828 &gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
6829 },
6830 .num_parents = 1,
6831 .flags = CLK_SET_RATE_PARENT,
6832 .ops = &clk_branch2_ops,
6833 },
6834 },
6835 };
6836
6837 static struct clk_branch gcc_usb3_tert_phy_aux_clk = {
6838 .halt_reg = 0xe1070,
6839 .halt_check = BRANCH_HALT,
6840 .clkr = {
6841 .enable_reg = 0xe1070,
6842 .enable_mask = BIT(0),
6843 .hw.init = &(const struct clk_init_data) {
6844 .name = "gcc_usb3_tert_phy_aux_clk",
6845 .parent_hws = (const struct clk_hw*[]) {
6846 &gcc_usb3_tert_phy_aux_clk_src.clkr.hw,
6847 },
6848 .num_parents = 1,
6849 .flags = CLK_SET_RATE_PARENT,
6850 .ops = &clk_branch2_ops,
6851 },
6852 },
6853 };
6854
6855 static struct clk_branch gcc_usb3_tert_phy_com_aux_clk = {
6856 .halt_reg = 0xe1074,
6857 .halt_check = BRANCH_HALT,
6858 .clkr = {
6859 .enable_reg = 0xe1074,
6860 .enable_mask = BIT(0),
6861 .hw.init = &(const struct clk_init_data) {
6862 .name = "gcc_usb3_tert_phy_com_aux_clk",
6863 .parent_hws = (const struct clk_hw*[]) {
6864 &gcc_usb3_tert_phy_aux_clk_src.clkr.hw,
6865 },
6866 .num_parents = 1,
6867 .flags = CLK_SET_RATE_PARENT,
6868 .ops = &clk_branch2_ops,
6869 },
6870 },
6871 };
6872
6873 static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
6874 .halt_reg = 0xe1078,
6875 .halt_check = BRANCH_HALT_VOTED,
6876 .hwcg_reg = 0xe1078,
6877 .hwcg_bit = 1,
6878 .clkr = {
6879 .enable_reg = 0xe1078,
6880 .enable_mask = BIT(0),
6881 .hw.init = &(const struct clk_init_data) {
6882 .name = "gcc_usb3_tert_phy_pipe_clk",
6883 .parent_hws = (const struct clk_hw*[]) {
6884 &gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
6885 },
6886 .num_parents = 1,
6887 .flags = CLK_SET_RATE_PARENT,
6888 .ops = &clk_branch2_ops,
6889 },
6890 },
6891 };
6892
6893 static struct clk_branch gcc_usb4_0_cfg_ahb_clk = {
6894 .halt_reg = 0xba450,
6895 .halt_check = BRANCH_HALT_VOTED,
6896 .hwcg_reg = 0xba450,
6897 .hwcg_bit = 1,
6898 .clkr = {
6899 .enable_reg = 0xba450,
6900 .enable_mask = BIT(0),
6901 .hw.init = &(const struct clk_init_data) {
6902 .name = "gcc_usb4_0_cfg_ahb_clk",
6903 .ops = &clk_branch2_ops,
6904 },
6905 },
6906 };
6907
6908 static struct clk_branch gcc_usb4_0_dp0_clk = {
6909 .halt_reg = 0x2b070,
6910 .halt_check = BRANCH_HALT,
6911 .clkr = {
6912 .enable_reg = 0x2b070,
6913 .enable_mask = BIT(0),
6914 .hw.init = &(const struct clk_init_data) {
6915 .name = "gcc_usb4_0_dp0_clk",
6916 .parent_hws = (const struct clk_hw*[]) {
6917 &gcc_usb4_0_phy_dp0_clk_src.clkr.hw,
6918 },
6919 .num_parents = 1,
6920 .flags = CLK_SET_RATE_PARENT,
6921 .ops = &clk_branch2_ops,
6922 },
6923 },
6924 };
6925
6926 static struct clk_branch gcc_usb4_0_dp1_clk = {
6927 .halt_reg = 0x2b124,
6928 .halt_check = BRANCH_HALT,
6929 .clkr = {
6930 .enable_reg = 0x2b124,
6931 .enable_mask = BIT(0),
6932 .hw.init = &(const struct clk_init_data) {
6933 .name = "gcc_usb4_0_dp1_clk",
6934 .parent_hws = (const struct clk_hw*[]) {
6935 &gcc_usb4_0_phy_dp1_clk_src.clkr.hw,
6936 },
6937 .num_parents = 1,
6938 .flags = CLK_SET_RATE_PARENT,
6939 .ops = &clk_branch2_ops,
6940 },
6941 },
6942 };
6943
6944 static struct clk_branch gcc_usb4_0_master_clk = {
6945 .halt_reg = 0x2b01c,
6946 .halt_check = BRANCH_HALT,
6947 .clkr = {
6948 .enable_reg = 0x2b01c,
6949 .enable_mask = BIT(0),
6950 .hw.init = &(const struct clk_init_data) {
6951 .name = "gcc_usb4_0_master_clk",
6952 .parent_hws = (const struct clk_hw*[]) {
6953 &gcc_usb4_0_master_clk_src.clkr.hw,
6954 },
6955 .num_parents = 1,
6956 .flags = CLK_SET_RATE_PARENT,
6957 .ops = &clk_branch2_ops,
6958 },
6959 },
6960 };
6961
6962 static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = {
6963 .halt_reg = 0x2b0f4,
6964 .halt_check = BRANCH_HALT,
6965 .clkr = {
6966 .enable_reg = 0x2b0f4,
6967 .enable_mask = BIT(0),
6968 .hw.init = &(const struct clk_init_data) {
6969 .name = "gcc_usb4_0_phy_p2rr2p_pipe_clk",
6970 .parent_hws = (const struct clk_hw*[]) {
6971 &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr.hw,
6972 },
6973 .num_parents = 1,
6974 .flags = CLK_SET_RATE_PARENT,
6975 .ops = &clk_branch2_ops,
6976 },
6977 },
6978 };
6979
6980 static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = {
6981 .halt_reg = 0x2b04c,
6982 .halt_check = BRANCH_HALT_VOTED,
6983 .clkr = {
6984 .enable_reg = 0x62010,
6985 .enable_mask = BIT(11),
6986 .hw.init = &(const struct clk_init_data) {
6987 .name = "gcc_usb4_0_phy_pcie_pipe_clk",
6988 .parent_hws = (const struct clk_hw*[]) {
6989 &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
6990 },
6991 .num_parents = 1,
6992 .flags = CLK_SET_RATE_PARENT,
6993 .ops = &clk_branch2_ops,
6994 },
6995 },
6996 };
6997
6998 static struct clk_branch gcc_usb4_0_phy_rx0_clk = {
6999 .halt_reg = 0x2b0c4,
7000 .halt_check = BRANCH_HALT,
7001 .clkr = {
7002 .enable_reg = 0x2b0c4,
7003 .enable_mask = BIT(0),
7004 .hw.init = &(const struct clk_init_data) {
7005 .name = "gcc_usb4_0_phy_rx0_clk",
7006 .parent_hws = (const struct clk_hw*[]) {
7007 &gcc_usb4_0_phy_rx0_clk_src.clkr.hw,
7008 },
7009 .num_parents = 1,
7010 .flags = CLK_SET_RATE_PARENT,
7011 .ops = &clk_branch2_ops,
7012 },
7013 },
7014 };
7015
7016 static struct clk_branch gcc_usb4_0_phy_rx1_clk = {
7017 .halt_reg = 0x2b0d8,
7018 .halt_check = BRANCH_HALT,
7019 .clkr = {
7020 .enable_reg = 0x2b0d8,
7021 .enable_mask = BIT(0),
7022 .hw.init = &(const struct clk_init_data) {
7023 .name = "gcc_usb4_0_phy_rx1_clk",
7024 .parent_hws = (const struct clk_hw*[]) {
7025 &gcc_usb4_0_phy_rx1_clk_src.clkr.hw,
7026 },
7027 .num_parents = 1,
7028 .flags = CLK_SET_RATE_PARENT,
7029 .ops = &clk_branch2_ops,
7030 },
7031 },
7032 };
7033
7034 static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = {
7035 .halt_reg = 0x2b0bc,
7036 .halt_check = BRANCH_HALT_VOTED,
7037 .hwcg_reg = 0x2b0bc,
7038 .hwcg_bit = 1,
7039 .clkr = {
7040 .enable_reg = 0x2b0bc,
7041 .enable_mask = BIT(0),
7042 .hw.init = &(const struct clk_init_data) {
7043 .name = "gcc_usb4_0_phy_usb_pipe_clk",
7044 .parent_hws = (const struct clk_hw*[]) {
7045 &gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
7046 },
7047 .num_parents = 1,
7048 .flags = CLK_SET_RATE_PARENT,
7049 .ops = &clk_branch2_ops,
7050 },
7051 },
7052 };
7053
7054 static struct clk_branch gcc_usb4_0_sb_if_clk = {
7055 .halt_reg = 0x2b048,
7056 .halt_check = BRANCH_HALT,
7057 .clkr = {
7058 .enable_reg = 0x2b048,
7059 .enable_mask = BIT(0),
7060 .hw.init = &(const struct clk_init_data) {
7061 .name = "gcc_usb4_0_sb_if_clk",
7062 .parent_hws = (const struct clk_hw*[]) {
7063 &gcc_usb4_0_sb_if_clk_src.clkr.hw,
7064 },
7065 .num_parents = 1,
7066 .flags = CLK_SET_RATE_PARENT,
7067 .ops = &clk_branch2_ops,
7068 },
7069 },
7070 };
7071
7072 static struct clk_branch gcc_usb4_0_sys_clk = {
7073 .halt_reg = 0x2b05c,
7074 .halt_check = BRANCH_HALT,
7075 .clkr = {
7076 .enable_reg = 0x2b05c,
7077 .enable_mask = BIT(0),
7078 .hw.init = &(const struct clk_init_data) {
7079 .name = "gcc_usb4_0_sys_clk",
7080 .parent_hws = (const struct clk_hw*[]) {
7081 &gcc_usb4_0_phy_sys_clk_src.clkr.hw,
7082 },
7083 .num_parents = 1,
7084 .flags = CLK_SET_RATE_PARENT,
7085 .ops = &clk_branch2_ops,
7086 },
7087 },
7088 };
7089
7090 static struct clk_branch gcc_usb4_0_tmu_clk = {
7091 .halt_reg = 0x2b09c,
7092 .halt_check = BRANCH_HALT_VOTED,
7093 .hwcg_reg = 0x2b09c,
7094 .hwcg_bit = 1,
7095 .clkr = {
7096 .enable_reg = 0x2b09c,
7097 .enable_mask = BIT(0),
7098 .hw.init = &(const struct clk_init_data) {
7099 .name = "gcc_usb4_0_tmu_clk",
7100 .parent_hws = (const struct clk_hw*[]) {
7101 &gcc_usb4_0_tmu_clk_src.clkr.hw,
7102 },
7103 .num_parents = 1,
7104 .flags = CLK_SET_RATE_PARENT,
7105 .ops = &clk_branch2_ops,
7106 },
7107 },
7108 };
7109
7110 static struct clk_branch gcc_usb4_0_uc_hrr_clk = {
7111 .halt_reg = 0x2b06c,
7112 .halt_check = BRANCH_HALT,
7113 .clkr = {
7114 .enable_reg = 0x2b06c,
7115 .enable_mask = BIT(0),
7116 .hw.init = &(const struct clk_init_data) {
7117 .name = "gcc_usb4_0_uc_hrr_clk",
7118 .parent_hws = (const struct clk_hw*[]) {
7119 &gcc_usb4_0_phy_sys_clk_src.clkr.hw,
7120 },
7121 .num_parents = 1,
7122 .flags = CLK_SET_RATE_PARENT,
7123 .ops = &clk_branch2_ops,
7124 },
7125 },
7126 };
7127
7128 static struct clk_branch gcc_usb4_1_cfg_ahb_clk = {
7129 .halt_reg = 0xba454,
7130 .halt_check = BRANCH_HALT_VOTED,
7131 .hwcg_reg = 0xba454,
7132 .hwcg_bit = 1,
7133 .clkr = {
7134 .enable_reg = 0xba454,
7135 .enable_mask = BIT(0),
7136 .hw.init = &(const struct clk_init_data) {
7137 .name = "gcc_usb4_1_cfg_ahb_clk",
7138 .ops = &clk_branch2_ops,
7139 },
7140 },
7141 };
7142
7143 static struct clk_branch gcc_usb4_1_dp0_clk = {
7144 .halt_reg = 0x2d07c,
7145 .halt_check = BRANCH_HALT,
7146 .clkr = {
7147 .enable_reg = 0x2d07c,
7148 .enable_mask = BIT(0),
7149 .hw.init = &(const struct clk_init_data) {
7150 .name = "gcc_usb4_1_dp0_clk",
7151 .parent_hws = (const struct clk_hw*[]) {
7152 &gcc_usb4_1_phy_dp0_clk_src.clkr.hw,
7153 },
7154 .num_parents = 1,
7155 .flags = CLK_SET_RATE_PARENT,
7156 .ops = &clk_branch2_ops,
7157 },
7158 },
7159 };
7160
7161 static struct clk_branch gcc_usb4_1_dp1_clk = {
7162 .halt_reg = 0x2d144,
7163 .halt_check = BRANCH_HALT,
7164 .clkr = {
7165 .enable_reg = 0x2d144,
7166 .enable_mask = BIT(0),
7167 .hw.init = &(const struct clk_init_data) {
7168 .name = "gcc_usb4_1_dp1_clk",
7169 .parent_hws = (const struct clk_hw*[]) {
7170 &gcc_usb4_1_phy_dp1_clk_src.clkr.hw,
7171 },
7172 .num_parents = 1,
7173 .flags = CLK_SET_RATE_PARENT,
7174 .ops = &clk_branch2_ops,
7175 },
7176 },
7177 };
7178
7179 static struct clk_branch gcc_usb4_1_master_clk = {
7180 .halt_reg = 0x2d01c,
7181 .halt_check = BRANCH_HALT,
7182 .clkr = {
7183 .enable_reg = 0x2d01c,
7184 .enable_mask = BIT(0),
7185 .hw.init = &(const struct clk_init_data) {
7186 .name = "gcc_usb4_1_master_clk",
7187 .parent_hws = (const struct clk_hw*[]) {
7188 &gcc_usb4_1_master_clk_src.clkr.hw,
7189 },
7190 .num_parents = 1,
7191 .flags = CLK_SET_RATE_PARENT,
7192 .ops = &clk_branch2_ops,
7193 },
7194 },
7195 };
7196
7197 static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
7198 .halt_reg = 0x2d118,
7199 .halt_check = BRANCH_HALT,
7200 .clkr = {
7201 .enable_reg = 0x2d118,
7202 .enable_mask = BIT(0),
7203 .hw.init = &(const struct clk_init_data) {
7204 .name = "gcc_usb4_1_phy_p2rr2p_pipe_clk",
7205 .parent_hws = (const struct clk_hw*[]) {
7206 &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw,
7207 },
7208 .num_parents = 1,
7209 .flags = CLK_SET_RATE_PARENT,
7210 .ops = &clk_branch2_ops,
7211 },
7212 },
7213 };
7214
7215 static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
7216 .halt_reg = 0x2d04c,
7217 .halt_check = BRANCH_HALT_VOTED,
7218 .clkr = {
7219 .enable_reg = 0x62010,
7220 .enable_mask = BIT(12),
7221 .hw.init = &(const struct clk_init_data) {
7222 .name = "gcc_usb4_1_phy_pcie_pipe_clk",
7223 .parent_hws = (const struct clk_hw*[]) {
7224 &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
7225 },
7226 .num_parents = 1,
7227 .flags = CLK_SET_RATE_PARENT,
7228 .ops = &clk_branch2_ops,
7229 },
7230 },
7231 };
7232
7233 static struct clk_branch gcc_usb4_1_phy_rx0_clk = {
7234 .halt_reg = 0x2d0e8,
7235 .halt_check = BRANCH_HALT,
7236 .clkr = {
7237 .enable_reg = 0x2d0e8,
7238 .enable_mask = BIT(0),
7239 .hw.init = &(const struct clk_init_data) {
7240 .name = "gcc_usb4_1_phy_rx0_clk",
7241 .parent_hws = (const struct clk_hw*[]) {
7242 &gcc_usb4_1_phy_rx0_clk_src.clkr.hw,
7243 },
7244 .num_parents = 1,
7245 .flags = CLK_SET_RATE_PARENT,
7246 .ops = &clk_branch2_ops,
7247 },
7248 },
7249 };
7250
7251 static struct clk_branch gcc_usb4_1_phy_rx1_clk = {
7252 .halt_reg = 0x2d0fc,
7253 .halt_check = BRANCH_HALT,
7254 .clkr = {
7255 .enable_reg = 0x2d0fc,
7256 .enable_mask = BIT(0),
7257 .hw.init = &(const struct clk_init_data) {
7258 .name = "gcc_usb4_1_phy_rx1_clk",
7259 .parent_hws = (const struct clk_hw*[]) {
7260 &gcc_usb4_1_phy_rx1_clk_src.clkr.hw,
7261 },
7262 .num_parents = 1,
7263 .flags = CLK_SET_RATE_PARENT,
7264 .ops = &clk_branch2_ops,
7265 },
7266 },
7267 };
7268
7269 static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {
7270 .halt_reg = 0x2d0e0,
7271 .halt_check = BRANCH_HALT_VOTED,
7272 .hwcg_reg = 0x2d0e0,
7273 .hwcg_bit = 1,
7274 .clkr = {
7275 .enable_reg = 0x2d0e0,
7276 .enable_mask = BIT(0),
7277 .hw.init = &(const struct clk_init_data) {
7278 .name = "gcc_usb4_1_phy_usb_pipe_clk",
7279 .parent_hws = (const struct clk_hw*[]) {
7280 &gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
7281 },
7282 .num_parents = 1,
7283 .flags = CLK_SET_RATE_PARENT,
7284 .ops = &clk_branch2_ops,
7285 },
7286 },
7287 };
7288
7289 static struct clk_branch gcc_usb4_1_sb_if_clk = {
7290 .halt_reg = 0x2d048,
7291 .halt_check = BRANCH_HALT,
7292 .clkr = {
7293 .enable_reg = 0x2d048,
7294 .enable_mask = BIT(0),
7295 .hw.init = &(const struct clk_init_data) {
7296 .name = "gcc_usb4_1_sb_if_clk",
7297 .parent_hws = (const struct clk_hw*[]) {
7298 &gcc_usb4_1_sb_if_clk_src.clkr.hw,
7299 },
7300 .num_parents = 1,
7301 .flags = CLK_SET_RATE_PARENT,
7302 .ops = &clk_branch2_ops,
7303 },
7304 },
7305 };
7306
7307 static struct clk_branch gcc_usb4_1_sys_clk = {
7308 .halt_reg = 0x2d05c,
7309 .halt_check = BRANCH_HALT,
7310 .clkr = {
7311 .enable_reg = 0x2d05c,
7312 .enable_mask = BIT(0),
7313 .hw.init = &(const struct clk_init_data) {
7314 .name = "gcc_usb4_1_sys_clk",
7315 .parent_hws = (const struct clk_hw*[]) {
7316 &gcc_usb4_1_phy_sys_clk_src.clkr.hw,
7317 },
7318 .num_parents = 1,
7319 .flags = CLK_SET_RATE_PARENT,
7320 .ops = &clk_branch2_ops,
7321 },
7322 },
7323 };
7324
7325 static struct clk_branch gcc_usb4_1_tmu_clk = {
7326 .halt_reg = 0x2d0a8,
7327 .halt_check = BRANCH_HALT_VOTED,
7328 .hwcg_reg = 0x2d0a8,
7329 .hwcg_bit = 1,
7330 .clkr = {
7331 .enable_reg = 0x2d0a8,
7332 .enable_mask = BIT(0),
7333 .hw.init = &(const struct clk_init_data) {
7334 .name = "gcc_usb4_1_tmu_clk",
7335 .parent_hws = (const struct clk_hw*[]) {
7336 &gcc_usb4_1_tmu_clk_src.clkr.hw,
7337 },
7338 .num_parents = 1,
7339 .flags = CLK_SET_RATE_PARENT,
7340 .ops = &clk_branch2_ops,
7341 },
7342 },
7343 };
7344
7345 static struct clk_branch gcc_usb4_1_uc_hrr_clk = {
7346 .halt_reg = 0x2d06c,
7347 .halt_check = BRANCH_HALT,
7348 .clkr = {
7349 .enable_reg = 0x2d06c,
7350 .enable_mask = BIT(0),
7351 .hw.init = &(const struct clk_init_data) {
7352 .name = "gcc_usb4_1_uc_hrr_clk",
7353 .parent_hws = (const struct clk_hw*[]) {
7354 &gcc_usb4_1_phy_sys_clk_src.clkr.hw,
7355 },
7356 .num_parents = 1,
7357 .flags = CLK_SET_RATE_PARENT,
7358 .ops = &clk_branch2_ops,
7359 },
7360 },
7361 };
7362
7363 static struct clk_branch gcc_usb4_2_cfg_ahb_clk = {
7364 .halt_reg = 0xba458,
7365 .halt_check = BRANCH_HALT_VOTED,
7366 .hwcg_reg = 0xba458,
7367 .hwcg_bit = 1,
7368 .clkr = {
7369 .enable_reg = 0xba458,
7370 .enable_mask = BIT(0),
7371 .hw.init = &(const struct clk_init_data) {
7372 .name = "gcc_usb4_2_cfg_ahb_clk",
7373 .ops = &clk_branch2_ops,
7374 },
7375 },
7376 };
7377
7378 static struct clk_branch gcc_usb4_2_dp0_clk = {
7379 .halt_reg = 0xe0070,
7380 .halt_check = BRANCH_HALT,
7381 .clkr = {
7382 .enable_reg = 0xe0070,
7383 .enable_mask = BIT(0),
7384 .hw.init = &(const struct clk_init_data) {
7385 .name = "gcc_usb4_2_dp0_clk",
7386 .parent_hws = (const struct clk_hw*[]) {
7387 &gcc_usb4_2_phy_dp0_clk_src.clkr.hw,
7388 },
7389 .num_parents = 1,
7390 .flags = CLK_SET_RATE_PARENT,
7391 .ops = &clk_branch2_ops,
7392 },
7393 },
7394 };
7395
7396 static struct clk_branch gcc_usb4_2_dp1_clk = {
7397 .halt_reg = 0xe0128,
7398 .halt_check = BRANCH_HALT,
7399 .clkr = {
7400 .enable_reg = 0xe0128,
7401 .enable_mask = BIT(0),
7402 .hw.init = &(const struct clk_init_data) {
7403 .name = "gcc_usb4_2_dp1_clk",
7404 .parent_hws = (const struct clk_hw*[]) {
7405 &gcc_usb4_2_phy_dp1_clk_src.clkr.hw,
7406 },
7407 .num_parents = 1,
7408 .flags = CLK_SET_RATE_PARENT,
7409 .ops = &clk_branch2_ops,
7410 },
7411 },
7412 };
7413
7414 static struct clk_branch gcc_usb4_2_master_clk = {
7415 .halt_reg = 0xe001c,
7416 .halt_check = BRANCH_HALT,
7417 .clkr = {
7418 .enable_reg = 0xe001c,
7419 .enable_mask = BIT(0),
7420 .hw.init = &(const struct clk_init_data) {
7421 .name = "gcc_usb4_2_master_clk",
7422 .parent_hws = (const struct clk_hw*[]) {
7423 &gcc_usb4_2_master_clk_src.clkr.hw,
7424 },
7425 .num_parents = 1,
7426 .flags = CLK_SET_RATE_PARENT,
7427 .ops = &clk_branch2_ops,
7428 },
7429 },
7430 };
7431
7432 static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = {
7433 .halt_reg = 0xe00f8,
7434 .halt_check = BRANCH_HALT,
7435 .clkr = {
7436 .enable_reg = 0xe00f8,
7437 .enable_mask = BIT(0),
7438 .hw.init = &(const struct clk_init_data) {
7439 .name = "gcc_usb4_2_phy_p2rr2p_pipe_clk",
7440 .parent_hws = (const struct clk_hw*[]) {
7441 &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr.hw,
7442 },
7443 .num_parents = 1,
7444 .flags = CLK_SET_RATE_PARENT,
7445 .ops = &clk_branch2_ops,
7446 },
7447 },
7448 };
7449
7450 static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = {
7451 .halt_reg = 0xe004c,
7452 .halt_check = BRANCH_HALT_VOTED,
7453 .clkr = {
7454 .enable_reg = 0x62010,
7455 .enable_mask = BIT(13),
7456 .hw.init = &(const struct clk_init_data) {
7457 .name = "gcc_usb4_2_phy_pcie_pipe_clk",
7458 .parent_hws = (const struct clk_hw*[]) {
7459 &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
7460 },
7461 .num_parents = 1,
7462 .flags = CLK_SET_RATE_PARENT,
7463 .ops = &clk_branch2_ops,
7464 },
7465 },
7466 };
7467
7468 static struct clk_branch gcc_usb4_2_phy_rx0_clk = {
7469 .halt_reg = 0xe00c8,
7470 .halt_check = BRANCH_HALT,
7471 .clkr = {
7472 .enable_reg = 0xe00c8,
7473 .enable_mask = BIT(0),
7474 .hw.init = &(const struct clk_init_data) {
7475 .name = "gcc_usb4_2_phy_rx0_clk",
7476 .parent_hws = (const struct clk_hw*[]) {
7477 &gcc_usb4_2_phy_rx0_clk_src.clkr.hw,
7478 },
7479 .num_parents = 1,
7480 .flags = CLK_SET_RATE_PARENT,
7481 .ops = &clk_branch2_ops,
7482 },
7483 },
7484 };
7485
7486 static struct clk_branch gcc_usb4_2_phy_rx1_clk = {
7487 .halt_reg = 0xe00dc,
7488 .halt_check = BRANCH_HALT,
7489 .clkr = {
7490 .enable_reg = 0xe00dc,
7491 .enable_mask = BIT(0),
7492 .hw.init = &(const struct clk_init_data) {
7493 .name = "gcc_usb4_2_phy_rx1_clk",
7494 .parent_hws = (const struct clk_hw*[]) {
7495 &gcc_usb4_2_phy_rx1_clk_src.clkr.hw,
7496 },
7497 .num_parents = 1,
7498 .flags = CLK_SET_RATE_PARENT,
7499 .ops = &clk_branch2_ops,
7500 },
7501 },
7502 };
7503
7504 static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = {
7505 .halt_reg = 0xe00c0,
7506 .halt_check = BRANCH_HALT_VOTED,
7507 .hwcg_reg = 0xe00c0,
7508 .hwcg_bit = 1,
7509 .clkr = {
7510 .enable_reg = 0xe00c0,
7511 .enable_mask = BIT(0),
7512 .hw.init = &(const struct clk_init_data) {
7513 .name = "gcc_usb4_2_phy_usb_pipe_clk",
7514 .parent_hws = (const struct clk_hw*[]) {
7515 &gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
7516 },
7517 .num_parents = 1,
7518 .flags = CLK_SET_RATE_PARENT,
7519 .ops = &clk_branch2_ops,
7520 },
7521 },
7522 };
7523
7524 static struct clk_branch gcc_usb4_2_sb_if_clk = {
7525 .halt_reg = 0xe0048,
7526 .halt_check = BRANCH_HALT,
7527 .clkr = {
7528 .enable_reg = 0xe0048,
7529 .enable_mask = BIT(0),
7530 .hw.init = &(const struct clk_init_data) {
7531 .name = "gcc_usb4_2_sb_if_clk",
7532 .parent_hws = (const struct clk_hw*[]) {
7533 &gcc_usb4_2_sb_if_clk_src.clkr.hw,
7534 },
7535 .num_parents = 1,
7536 .flags = CLK_SET_RATE_PARENT,
7537 .ops = &clk_branch2_ops,
7538 },
7539 },
7540 };
7541
7542 static struct clk_branch gcc_usb4_2_sys_clk = {
7543 .halt_reg = 0xe005c,
7544 .halt_check = BRANCH_HALT,
7545 .clkr = {
7546 .enable_reg = 0xe005c,
7547 .enable_mask = BIT(0),
7548 .hw.init = &(const struct clk_init_data) {
7549 .name = "gcc_usb4_2_sys_clk",
7550 .parent_hws = (const struct clk_hw*[]) {
7551 &gcc_usb4_2_phy_sys_clk_src.clkr.hw,
7552 },
7553 .num_parents = 1,
7554 .flags = CLK_SET_RATE_PARENT,
7555 .ops = &clk_branch2_ops,
7556 },
7557 },
7558 };
7559
7560 static struct clk_branch gcc_usb4_2_tmu_clk = {
7561 .halt_reg = 0xe00a0,
7562 .halt_check = BRANCH_HALT_VOTED,
7563 .hwcg_reg = 0xe00a0,
7564 .hwcg_bit = 1,
7565 .clkr = {
7566 .enable_reg = 0xe00a0,
7567 .enable_mask = BIT(0),
7568 .hw.init = &(const struct clk_init_data) {
7569 .name = "gcc_usb4_2_tmu_clk",
7570 .parent_hws = (const struct clk_hw*[]) {
7571 &gcc_usb4_2_tmu_clk_src.clkr.hw,
7572 },
7573 .num_parents = 1,
7574 .flags = CLK_SET_RATE_PARENT,
7575 .ops = &clk_branch2_ops,
7576 },
7577 },
7578 };
7579
7580 static struct clk_branch gcc_usb4_2_uc_hrr_clk = {
7581 .halt_reg = 0xe006c,
7582 .halt_check = BRANCH_HALT,
7583 .clkr = {
7584 .enable_reg = 0xe006c,
7585 .enable_mask = BIT(0),
7586 .hw.init = &(const struct clk_init_data) {
7587 .name = "gcc_usb4_2_uc_hrr_clk",
7588 .parent_hws = (const struct clk_hw*[]) {
7589 &gcc_usb4_2_phy_sys_clk_src.clkr.hw,
7590 },
7591 .num_parents = 1,
7592 .flags = CLK_SET_RATE_PARENT,
7593 .ops = &clk_branch2_ops,
7594 },
7595 },
7596 };
7597
7598 static struct clk_branch gcc_video_axi0_clk = {
7599 .halt_reg = 0x3201c,
7600 .halt_check = BRANCH_HALT_SKIP,
7601 .hwcg_reg = 0x3201c,
7602 .hwcg_bit = 1,
7603 .clkr = {
7604 .enable_reg = 0x3201c,
7605 .enable_mask = BIT(0),
7606 .hw.init = &(const struct clk_init_data) {
7607 .name = "gcc_video_axi0_clk",
7608 .ops = &clk_branch2_ops,
7609 },
7610 },
7611 };
7612
7613 static struct clk_branch gcc_video_axi0c_clk = {
7614 .halt_reg = 0x32030,
7615 .halt_check = BRANCH_HALT_SKIP,
7616 .hwcg_reg = 0x32030,
7617 .hwcg_bit = 1,
7618 .clkr = {
7619 .enable_reg = 0x32030,
7620 .enable_mask = BIT(0),
7621 .hw.init = &(const struct clk_init_data) {
7622 .name = "gcc_video_axi0c_clk",
7623 .ops = &clk_branch2_ops,
7624 },
7625 },
7626 };
7627
7628 static struct clk_branch gcc_video_axi1_clk = {
7629 .halt_reg = 0x32044,
7630 .halt_check = BRANCH_HALT_SKIP,
7631 .hwcg_reg = 0x32044,
7632 .hwcg_bit = 1,
7633 .clkr = {
7634 .enable_reg = 0x32044,
7635 .enable_mask = BIT(0),
7636 .hw.init = &(const struct clk_init_data) {
7637 .name = "gcc_video_axi1_clk",
7638 .ops = &clk_branch2_ops,
7639 },
7640 },
7641 };
7642
7643 static struct gdsc gcc_pcie_0_tunnel_gdsc = {
7644 .gdscr = 0xc8004,
7645 .en_rest_wait_val = 0x2,
7646 .en_few_wait_val = 0x2,
7647 .clk_dis_wait_val = 0xf,
7648 .pd = {
7649 .name = "gcc_pcie_0_tunnel_gdsc",
7650 },
7651 .pwrsts = PWRSTS_OFF_ON,
7652 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7653 };
7654
7655 static struct gdsc gcc_pcie_1_tunnel_gdsc = {
7656 .gdscr = 0x2e004,
7657 .en_rest_wait_val = 0x2,
7658 .en_few_wait_val = 0x2,
7659 .clk_dis_wait_val = 0xf,
7660 .pd = {
7661 .name = "gcc_pcie_1_tunnel_gdsc",
7662 },
7663 .pwrsts = PWRSTS_OFF_ON,
7664 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7665 };
7666
7667 static struct gdsc gcc_pcie_2_tunnel_gdsc = {
7668 .gdscr = 0xc0004,
7669 .en_rest_wait_val = 0x2,
7670 .en_few_wait_val = 0x2,
7671 .clk_dis_wait_val = 0xf,
7672 .pd = {
7673 .name = "gcc_pcie_2_tunnel_gdsc",
7674 },
7675 .pwrsts = PWRSTS_OFF_ON,
7676 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7677 };
7678
7679 static struct gdsc gcc_pcie_3a_gdsc = {
7680 .gdscr = 0xdc004,
7681 .en_rest_wait_val = 0x2,
7682 .en_few_wait_val = 0x2,
7683 .clk_dis_wait_val = 0xf,
7684 .pd = {
7685 .name = "gcc_pcie_3a_gdsc",
7686 },
7687 .pwrsts = PWRSTS_OFF_ON,
7688 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7689 };
7690
7691 static struct gdsc gcc_pcie_3a_phy_gdsc = {
7692 .gdscr = 0x6c004,
7693 .en_rest_wait_val = 0x2,
7694 .en_few_wait_val = 0x2,
7695 .clk_dis_wait_val = 0x2,
7696 .pd = {
7697 .name = "gcc_pcie_3a_phy_gdsc",
7698 },
7699 .pwrsts = PWRSTS_OFF_ON,
7700 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7701 };
7702
7703 static struct gdsc gcc_pcie_3b_gdsc = {
7704 .gdscr = 0x94004,
7705 .en_rest_wait_val = 0x2,
7706 .en_few_wait_val = 0x2,
7707 .clk_dis_wait_val = 0xf,
7708 .pd = {
7709 .name = "gcc_pcie_3b_gdsc",
7710 },
7711 .pwrsts = PWRSTS_OFF_ON,
7712 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7713 };
7714
7715 static struct gdsc gcc_pcie_3b_phy_gdsc = {
7716 .gdscr = 0x75004,
7717 .en_rest_wait_val = 0x2,
7718 .en_few_wait_val = 0x2,
7719 .clk_dis_wait_val = 0x2,
7720 .pd = {
7721 .name = "gcc_pcie_3b_phy_gdsc",
7722 },
7723 .pwrsts = PWRSTS_OFF_ON,
7724 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7725 };
7726
7727 static struct gdsc gcc_pcie_4_gdsc = {
7728 .gdscr = 0x88004,
7729 .en_rest_wait_val = 0x2,
7730 .en_few_wait_val = 0x2,
7731 .clk_dis_wait_val = 0xf,
7732 .pd = {
7733 .name = "gcc_pcie_4_gdsc",
7734 },
7735 .pwrsts = PWRSTS_OFF_ON,
7736 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7737 };
7738
7739 static struct gdsc gcc_pcie_4_phy_gdsc = {
7740 .gdscr = 0xd3004,
7741 .en_rest_wait_val = 0x2,
7742 .en_few_wait_val = 0x2,
7743 .clk_dis_wait_val = 0x2,
7744 .pd = {
7745 .name = "gcc_pcie_4_phy_gdsc",
7746 },
7747 .pwrsts = PWRSTS_OFF_ON,
7748 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7749 };
7750
7751 static struct gdsc gcc_pcie_5_gdsc = {
7752 .gdscr = 0xc3004,
7753 .en_rest_wait_val = 0x2,
7754 .en_few_wait_val = 0x2,
7755 .clk_dis_wait_val = 0xf,
7756 .pd = {
7757 .name = "gcc_pcie_5_gdsc",
7758 },
7759 .pwrsts = PWRSTS_OFF_ON,
7760 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7761 };
7762
7763 static struct gdsc gcc_pcie_5_phy_gdsc = {
7764 .gdscr = 0xd2004,
7765 .en_rest_wait_val = 0x2,
7766 .en_few_wait_val = 0x2,
7767 .clk_dis_wait_val = 0x2,
7768 .pd = {
7769 .name = "gcc_pcie_5_phy_gdsc",
7770 },
7771 .pwrsts = PWRSTS_OFF_ON,
7772 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7773 };
7774
7775 static struct gdsc gcc_pcie_6_gdsc = {
7776 .gdscr = 0x8a004,
7777 .en_rest_wait_val = 0x2,
7778 .en_few_wait_val = 0x2,
7779 .clk_dis_wait_val = 0xf,
7780 .pd = {
7781 .name = "gcc_pcie_6_gdsc",
7782 },
7783 .pwrsts = PWRSTS_OFF_ON,
7784 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7785 };
7786
7787 static struct gdsc gcc_pcie_6_phy_gdsc = {
7788 .gdscr = 0xd4004,
7789 .en_rest_wait_val = 0x2,
7790 .en_few_wait_val = 0x2,
7791 .clk_dis_wait_val = 0x2,
7792 .pd = {
7793 .name = "gcc_pcie_6_phy_gdsc",
7794 },
7795 .pwrsts = PWRSTS_OFF_ON,
7796 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7797 };
7798
7799 static struct gdsc gcc_ufs_phy_gdsc = {
7800 .gdscr = 0x77008,
7801 .en_rest_wait_val = 0x2,
7802 .en_few_wait_val = 0x2,
7803 .clk_dis_wait_val = 0xf,
7804 .pd = {
7805 .name = "gcc_ufs_phy_gdsc",
7806 },
7807 .pwrsts = PWRSTS_OFF_ON,
7808 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7809 };
7810
7811 static struct gdsc gcc_usb20_prim_gdsc = {
7812 .gdscr = 0xbc004,
7813 .en_rest_wait_val = 0x2,
7814 .en_few_wait_val = 0x2,
7815 .clk_dis_wait_val = 0xf,
7816 .pd = {
7817 .name = "gcc_usb20_prim_gdsc",
7818 },
7819 .pwrsts = PWRSTS_OFF_ON,
7820 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7821 };
7822
7823 static struct gdsc gcc_usb30_mp_gdsc = {
7824 .gdscr = 0x9a010,
7825 .en_rest_wait_val = 0x2,
7826 .en_few_wait_val = 0x2,
7827 .clk_dis_wait_val = 0xf,
7828 .pd = {
7829 .name = "gcc_usb30_mp_gdsc",
7830 },
7831 .pwrsts = PWRSTS_OFF_ON,
7832 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7833 };
7834
7835 static struct gdsc gcc_usb30_prim_gdsc = {
7836 .gdscr = 0x3f01c,
7837 .en_rest_wait_val = 0x2,
7838 .en_few_wait_val = 0x2,
7839 .clk_dis_wait_val = 0xf,
7840 .pd = {
7841 .name = "gcc_usb30_prim_gdsc",
7842 },
7843 .pwrsts = PWRSTS_OFF_ON,
7844 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7845 };
7846
7847 static struct gdsc gcc_usb30_sec_gdsc = {
7848 .gdscr = 0xe2010,
7849 .en_rest_wait_val = 0x2,
7850 .en_few_wait_val = 0x2,
7851 .clk_dis_wait_val = 0xf,
7852 .pd = {
7853 .name = "gcc_usb30_sec_gdsc",
7854 },
7855 .pwrsts = PWRSTS_OFF_ON,
7856 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7857 };
7858
7859 static struct gdsc gcc_usb30_tert_gdsc = {
7860 .gdscr = 0xe1010,
7861 .en_rest_wait_val = 0x2,
7862 .en_few_wait_val = 0x2,
7863 .clk_dis_wait_val = 0xf,
7864 .pd = {
7865 .name = "gcc_usb30_tert_gdsc",
7866 },
7867 .pwrsts = PWRSTS_OFF_ON,
7868 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7869 };
7870
7871 static struct gdsc gcc_usb3_mp_ss0_phy_gdsc = {
7872 .gdscr = 0x5400c,
7873 .en_rest_wait_val = 0x2,
7874 .en_few_wait_val = 0x2,
7875 .clk_dis_wait_val = 0x2,
7876 .pd = {
7877 .name = "gcc_usb3_mp_ss0_phy_gdsc",
7878 },
7879 .pwrsts = PWRSTS_OFF_ON,
7880 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7881 };
7882
7883 static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = {
7884 .gdscr = 0x5402c,
7885 .en_rest_wait_val = 0x2,
7886 .en_few_wait_val = 0x2,
7887 .clk_dis_wait_val = 0x2,
7888 .pd = {
7889 .name = "gcc_usb3_mp_ss1_phy_gdsc",
7890 },
7891 .pwrsts = PWRSTS_OFF_ON,
7892 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7893 };
7894
7895 static struct gdsc gcc_usb4_0_gdsc = {
7896 .gdscr = 0x2b008,
7897 .en_rest_wait_val = 0x2,
7898 .en_few_wait_val = 0x2,
7899 .clk_dis_wait_val = 0xf,
7900 .pd = {
7901 .name = "gcc_usb4_0_gdsc",
7902 },
7903 .pwrsts = PWRSTS_OFF_ON,
7904 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7905 };
7906
7907 static struct gdsc gcc_usb4_1_gdsc = {
7908 .gdscr = 0x2d008,
7909 .en_rest_wait_val = 0x2,
7910 .en_few_wait_val = 0x2,
7911 .clk_dis_wait_val = 0xf,
7912 .pd = {
7913 .name = "gcc_usb4_1_gdsc",
7914 },
7915 .pwrsts = PWRSTS_OFF_ON,
7916 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7917 };
7918
7919 static struct gdsc gcc_usb4_2_gdsc = {
7920 .gdscr = 0xe0008,
7921 .en_rest_wait_val = 0x2,
7922 .en_few_wait_val = 0x2,
7923 .clk_dis_wait_val = 0xf,
7924 .pd = {
7925 .name = "gcc_usb4_2_gdsc",
7926 },
7927 .pwrsts = PWRSTS_OFF_ON,
7928 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7929 };
7930
7931 static struct gdsc gcc_usb_0_phy_gdsc = {
7932 .gdscr = 0xdb024,
7933 .en_rest_wait_val = 0x2,
7934 .en_few_wait_val = 0x2,
7935 .clk_dis_wait_val = 0x2,
7936 .pd = {
7937 .name = "gcc_usb_0_phy_gdsc",
7938 },
7939 .pwrsts = PWRSTS_OFF_ON,
7940 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7941 };
7942
7943 static struct gdsc gcc_usb_1_phy_gdsc = {
7944 .gdscr = 0x2c024,
7945 .en_rest_wait_val = 0x2,
7946 .en_few_wait_val = 0x2,
7947 .clk_dis_wait_val = 0x2,
7948 .pd = {
7949 .name = "gcc_usb_1_phy_gdsc",
7950 },
7951 .pwrsts = PWRSTS_OFF_ON,
7952 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7953 };
7954
7955 static struct gdsc gcc_usb_2_phy_gdsc = {
7956 .gdscr = 0xbe024,
7957 .en_rest_wait_val = 0x2,
7958 .en_few_wait_val = 0x2,
7959 .clk_dis_wait_val = 0x2,
7960 .pd = {
7961 .name = "gcc_usb_2_phy_gdsc",
7962 },
7963 .pwrsts = PWRSTS_OFF_ON,
7964 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7965 };
7966
7967 static struct clk_regmap *gcc_glymur_clocks[] = {
7968 [GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_3a_west_sf_axi_clk.clkr,
7969 [GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_3b_west_sf_axi_clk.clkr,
7970 [GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_4_west_sf_axi_clk.clkr,
7971 [GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_5_east_sf_axi_clk.clkr,
7972 [GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_6_west_sf_axi_clk.clkr,
7973 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
7974 [GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr,
7975 [GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr,
7976 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
7977 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
7978 [GCC_AGGRE_USB3_TERT_AXI_CLK] = &gcc_aggre_usb3_tert_axi_clk.clkr,
7979 [GCC_AGGRE_USB4_0_AXI_CLK] = &gcc_aggre_usb4_0_axi_clk.clkr,
7980 [GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr,
7981 [GCC_AGGRE_USB4_2_AXI_CLK] = &gcc_aggre_usb4_2_axi_clk.clkr,
7982 [GCC_AV1E_AHB_CLK] = &gcc_av1e_ahb_clk.clkr,
7983 [GCC_AV1E_AXI_CLK] = &gcc_av1e_axi_clk.clkr,
7984 [GCC_AV1E_XO_CLK] = &gcc_av1e_xo_clk.clkr,
7985 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
7986 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
7987 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
7988 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
7989 [GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_south_ahb_clk.clkr,
7990 [GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr,
7991 [GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
7992 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
7993 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
7994 [GCC_CFG_NOC_USB3_TERT_AXI_CLK] = &gcc_cfg_noc_usb3_tert_axi_clk.clkr,
7995 [GCC_CFG_NOC_USB_ANOC_AHB_CLK] = &gcc_cfg_noc_usb_anoc_ahb_clk.clkr,
7996 [GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_south_ahb_clk.clkr,
7997 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
7998 [GCC_EVA_AHB_CLK] = &gcc_eva_ahb_clk.clkr,
7999 [GCC_EVA_AXI0_CLK] = &gcc_eva_axi0_clk.clkr,
8000 [GCC_EVA_AXI0C_CLK] = &gcc_eva_axi0c_clk.clkr,
8001 [GCC_EVA_XO_CLK] = &gcc_eva_xo_clk.clkr,
8002 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
8003 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
8004 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
8005 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
8006 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
8007 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
8008 [GCC_GPLL0] = &gcc_gpll0.clkr,
8009 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
8010 [GCC_GPLL1] = &gcc_gpll1.clkr,
8011 [GCC_GPLL14] = &gcc_gpll14.clkr,
8012 [GCC_GPLL14_OUT_EVEN] = &gcc_gpll14_out_even.clkr,
8013 [GCC_GPLL4] = &gcc_gpll4.clkr,
8014 [GCC_GPLL5] = &gcc_gpll5.clkr,
8015 [GCC_GPLL7] = &gcc_gpll7.clkr,
8016 [GCC_GPLL8] = &gcc_gpll8.clkr,
8017 [GCC_GPLL9] = &gcc_gpll9.clkr,
8018 [GCC_GPU_GEMNOC_GFX_CLK] = &gcc_gpu_gemnoc_gfx_clk.clkr,
8019 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
8020 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
8021 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
8022 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
8023 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
8024 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
8025 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
8026 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
8027 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
8028 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
8029 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
8030 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
8031 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
8032 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
8033 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
8034 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
8035 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
8036 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
8037 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
8038 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
8039 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
8040 [GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,
8041 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
8042 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
8043 [GCC_PCIE_2_PHY_RCHNG_CLK] = &gcc_pcie_2_phy_rchng_clk.clkr,
8044 [GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr,
8045 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
8046 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
8047 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
8048 [GCC_PCIE_3A_AUX_CLK] = &gcc_pcie_3a_aux_clk.clkr,
8049 [GCC_PCIE_3A_AUX_CLK_SRC] = &gcc_pcie_3a_aux_clk_src.clkr,
8050 [GCC_PCIE_3A_CFG_AHB_CLK] = &gcc_pcie_3a_cfg_ahb_clk.clkr,
8051 [GCC_PCIE_3A_MSTR_AXI_CLK] = &gcc_pcie_3a_mstr_axi_clk.clkr,
8052 [GCC_PCIE_3A_PHY_RCHNG_CLK] = &gcc_pcie_3a_phy_rchng_clk.clkr,
8053 [GCC_PCIE_3A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3a_phy_rchng_clk_src.clkr,
8054 [GCC_PCIE_3A_PIPE_CLK] = &gcc_pcie_3a_pipe_clk.clkr,
8055 [GCC_PCIE_3A_PIPE_CLK_SRC] = &gcc_pcie_3a_pipe_clk_src.clkr,
8056 [GCC_PCIE_3A_SLV_AXI_CLK] = &gcc_pcie_3a_slv_axi_clk.clkr,
8057 [GCC_PCIE_3A_SLV_Q2A_AXI_CLK] = &gcc_pcie_3a_slv_q2a_axi_clk.clkr,
8058 [GCC_PCIE_3B_AUX_CLK] = &gcc_pcie_3b_aux_clk.clkr,
8059 [GCC_PCIE_3B_AUX_CLK_SRC] = &gcc_pcie_3b_aux_clk_src.clkr,
8060 [GCC_PCIE_3B_CFG_AHB_CLK] = &gcc_pcie_3b_cfg_ahb_clk.clkr,
8061 [GCC_PCIE_3B_MSTR_AXI_CLK] = &gcc_pcie_3b_mstr_axi_clk.clkr,
8062 [GCC_PCIE_3B_PHY_RCHNG_CLK] = &gcc_pcie_3b_phy_rchng_clk.clkr,
8063 [GCC_PCIE_3B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3b_phy_rchng_clk_src.clkr,
8064 [GCC_PCIE_3B_PIPE_CLK] = &gcc_pcie_3b_pipe_clk.clkr,
8065 [GCC_PCIE_3B_PIPE_CLK_SRC] = &gcc_pcie_3b_pipe_clk_src.clkr,
8066 [GCC_PCIE_3B_PIPE_DIV2_CLK] = &gcc_pcie_3b_pipe_div2_clk.clkr,
8067 [GCC_PCIE_3B_PIPE_DIV_CLK_SRC] = &gcc_pcie_3b_pipe_div_clk_src.clkr,
8068 [GCC_PCIE_3B_SLV_AXI_CLK] = &gcc_pcie_3b_slv_axi_clk.clkr,
8069 [GCC_PCIE_3B_SLV_Q2A_AXI_CLK] = &gcc_pcie_3b_slv_q2a_axi_clk.clkr,
8070 [GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr,
8071 [GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr,
8072 [GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr,
8073 [GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr,
8074 [GCC_PCIE_4_PHY_RCHNG_CLK] = &gcc_pcie_4_phy_rchng_clk.clkr,
8075 [GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr,
8076 [GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr,
8077 [GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr,
8078 [GCC_PCIE_4_PIPE_DIV2_CLK] = &gcc_pcie_4_pipe_div2_clk.clkr,
8079 [GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr,
8080 [GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr,
8081 [GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr,
8082 [GCC_PCIE_5_AUX_CLK] = &gcc_pcie_5_aux_clk.clkr,
8083 [GCC_PCIE_5_AUX_CLK_SRC] = &gcc_pcie_5_aux_clk_src.clkr,
8084 [GCC_PCIE_5_CFG_AHB_CLK] = &gcc_pcie_5_cfg_ahb_clk.clkr,
8085 [GCC_PCIE_5_MSTR_AXI_CLK] = &gcc_pcie_5_mstr_axi_clk.clkr,
8086 [GCC_PCIE_5_PHY_RCHNG_CLK] = &gcc_pcie_5_phy_rchng_clk.clkr,
8087 [GCC_PCIE_5_PHY_RCHNG_CLK_SRC] = &gcc_pcie_5_phy_rchng_clk_src.clkr,
8088 [GCC_PCIE_5_PIPE_CLK] = &gcc_pcie_5_pipe_clk.clkr,
8089 [GCC_PCIE_5_PIPE_CLK_SRC] = &gcc_pcie_5_pipe_clk_src.clkr,
8090 [GCC_PCIE_5_PIPE_DIV2_CLK] = &gcc_pcie_5_pipe_div2_clk.clkr,
8091 [GCC_PCIE_5_PIPE_DIV_CLK_SRC] = &gcc_pcie_5_pipe_div_clk_src.clkr,
8092 [GCC_PCIE_5_SLV_AXI_CLK] = &gcc_pcie_5_slv_axi_clk.clkr,
8093 [GCC_PCIE_5_SLV_Q2A_AXI_CLK] = &gcc_pcie_5_slv_q2a_axi_clk.clkr,
8094 [GCC_PCIE_6_AUX_CLK] = &gcc_pcie_6_aux_clk.clkr,
8095 [GCC_PCIE_6_AUX_CLK_SRC] = &gcc_pcie_6_aux_clk_src.clkr,
8096 [GCC_PCIE_6_CFG_AHB_CLK] = &gcc_pcie_6_cfg_ahb_clk.clkr,
8097 [GCC_PCIE_6_MSTR_AXI_CLK] = &gcc_pcie_6_mstr_axi_clk.clkr,
8098 [GCC_PCIE_6_PHY_RCHNG_CLK] = &gcc_pcie_6_phy_rchng_clk.clkr,
8099 [GCC_PCIE_6_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6_phy_rchng_clk_src.clkr,
8100 [GCC_PCIE_6_PIPE_CLK] = &gcc_pcie_6_pipe_clk.clkr,
8101 [GCC_PCIE_6_PIPE_CLK_SRC] = &gcc_pcie_6_pipe_clk_src.clkr,
8102 [GCC_PCIE_6_PIPE_DIV2_CLK] = &gcc_pcie_6_pipe_div2_clk.clkr,
8103 [GCC_PCIE_6_PIPE_DIV_CLK_SRC] = &gcc_pcie_6_pipe_div_clk_src.clkr,
8104 [GCC_PCIE_6_SLV_AXI_CLK] = &gcc_pcie_6_slv_axi_clk.clkr,
8105 [GCC_PCIE_6_SLV_Q2A_AXI_CLK] = &gcc_pcie_6_slv_q2a_axi_clk.clkr,
8106 [GCC_PCIE_NOC_PWRCTL_CLK] = &gcc_pcie_noc_pwrctl_clk.clkr,
8107 [GCC_PCIE_NOC_QOSGEN_EXTREF_CLK] = &gcc_pcie_noc_qosgen_extref_clk.clkr,
8108 [GCC_PCIE_NOC_SF_CENTER_CLK] = &gcc_pcie_noc_sf_center_clk.clkr,
8109 [GCC_PCIE_NOC_SLAVE_SF_EAST_CLK] = &gcc_pcie_noc_slave_sf_east_clk.clkr,
8110 [GCC_PCIE_NOC_SLAVE_SF_WEST_CLK] = &gcc_pcie_noc_slave_sf_west_clk.clkr,
8111 [GCC_PCIE_NOC_TSCTR_CLK] = &gcc_pcie_noc_tsctr_clk.clkr,
8112 [GCC_PCIE_PHY_3A_AUX_CLK] = &gcc_pcie_phy_3a_aux_clk.clkr,
8113 [GCC_PCIE_PHY_3A_AUX_CLK_SRC] = &gcc_pcie_phy_3a_aux_clk_src.clkr,
8114 [GCC_PCIE_PHY_3B_AUX_CLK] = &gcc_pcie_phy_3b_aux_clk.clkr,
8115 [GCC_PCIE_PHY_3B_AUX_CLK_SRC] = &gcc_pcie_phy_3b_aux_clk_src.clkr,
8116 [GCC_PCIE_PHY_4_AUX_CLK] = &gcc_pcie_phy_4_aux_clk.clkr,
8117 [GCC_PCIE_PHY_4_AUX_CLK_SRC] = &gcc_pcie_phy_4_aux_clk_src.clkr,
8118 [GCC_PCIE_PHY_5_AUX_CLK] = &gcc_pcie_phy_5_aux_clk.clkr,
8119 [GCC_PCIE_PHY_5_AUX_CLK_SRC] = &gcc_pcie_phy_5_aux_clk_src.clkr,
8120 [GCC_PCIE_PHY_6_AUX_CLK] = &gcc_pcie_phy_6_aux_clk.clkr,
8121 [GCC_PCIE_PHY_6_AUX_CLK_SRC] = &gcc_pcie_phy_6_aux_clk_src.clkr,
8122 [GCC_PCIE_RSCC_CFG_AHB_CLK] = &gcc_pcie_rscc_cfg_ahb_clk.clkr,
8123 [GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr,
8124 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
8125 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
8126 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
8127 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
8128 [GCC_QMIP_AV1E_AHB_CLK] = &gcc_qmip_av1e_ahb_clk.clkr,
8129 [GCC_QMIP_CAMERA_CMD_AHB_CLK] = &gcc_qmip_camera_cmd_ahb_clk.clkr,
8130 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
8131 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
8132 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
8133 [GCC_QMIP_PCIE_3A_AHB_CLK] = &gcc_qmip_pcie_3a_ahb_clk.clkr,
8134 [GCC_QMIP_PCIE_3B_AHB_CLK] = &gcc_qmip_pcie_3b_ahb_clk.clkr,
8135 [GCC_QMIP_PCIE_4_AHB_CLK] = &gcc_qmip_pcie_4_ahb_clk.clkr,
8136 [GCC_QMIP_PCIE_5_AHB_CLK] = &gcc_qmip_pcie_5_ahb_clk.clkr,
8137 [GCC_QMIP_PCIE_6_AHB_CLK] = &gcc_qmip_pcie_6_ahb_clk.clkr,
8138 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
8139 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
8140 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
8141 [GCC_QMIP_VIDEO_VCODEC1_AHB_CLK] = &gcc_qmip_video_vcodec1_ahb_clk.clkr,
8142 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
8143 [GCC_QUPV3_OOB_CORE_2X_CLK] = &gcc_qupv3_oob_core_2x_clk.clkr,
8144 [GCC_QUPV3_OOB_CORE_CLK] = &gcc_qupv3_oob_core_clk.clkr,
8145 [GCC_QUPV3_OOB_M_AHB_CLK] = &gcc_qupv3_oob_m_ahb_clk.clkr,
8146 [GCC_QUPV3_OOB_QSPI_S0_CLK] = &gcc_qupv3_oob_qspi_s0_clk.clkr,
8147 [GCC_QUPV3_OOB_QSPI_S0_CLK_SRC] = &gcc_qupv3_oob_qspi_s0_clk_src.clkr,
8148 [GCC_QUPV3_OOB_QSPI_S1_CLK] = &gcc_qupv3_oob_qspi_s1_clk.clkr,
8149 [GCC_QUPV3_OOB_QSPI_S1_CLK_SRC] = &gcc_qupv3_oob_qspi_s1_clk_src.clkr,
8150 [GCC_QUPV3_OOB_S0_CLK] = &gcc_qupv3_oob_s0_clk.clkr,
8151 [GCC_QUPV3_OOB_S0_CLK_SRC] = &gcc_qupv3_oob_s0_clk_src.clkr,
8152 [GCC_QUPV3_OOB_S1_CLK] = &gcc_qupv3_oob_s1_clk.clkr,
8153 [GCC_QUPV3_OOB_S1_CLK_SRC] = &gcc_qupv3_oob_s1_clk_src.clkr,
8154 [GCC_QUPV3_OOB_S_AHB_CLK] = &gcc_qupv3_oob_s_ahb_clk.clkr,
8155 [GCC_QUPV3_OOB_TCXO_CLK] = &gcc_qupv3_oob_tcxo_clk.clkr,
8156 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
8157 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
8158 [GCC_QUPV3_WRAP0_QSPI_S2_CLK] = &gcc_qupv3_wrap0_qspi_s2_clk.clkr,
8159 [GCC_QUPV3_WRAP0_QSPI_S2_CLK_SRC] = &gcc_qupv3_wrap0_qspi_s2_clk_src.clkr,
8160 [GCC_QUPV3_WRAP0_QSPI_S3_CLK] = &gcc_qupv3_wrap0_qspi_s3_clk.clkr,
8161 [GCC_QUPV3_WRAP0_QSPI_S3_CLK_SRC] = &gcc_qupv3_wrap0_qspi_s3_clk_src.clkr,
8162 [GCC_QUPV3_WRAP0_QSPI_S6_CLK] = &gcc_qupv3_wrap0_qspi_s6_clk.clkr,
8163 [GCC_QUPV3_WRAP0_QSPI_S6_CLK_SRC] = &gcc_qupv3_wrap0_qspi_s6_clk_src.clkr,
8164 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
8165 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
8166 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
8167 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
8168 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
8169 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
8170 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
8171 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
8172 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
8173 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
8174 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
8175 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
8176 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
8177 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
8178 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
8179 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
8180 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
8181 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
8182 [GCC_QUPV3_WRAP1_QSPI_S2_CLK] = &gcc_qupv3_wrap1_qspi_s2_clk.clkr,
8183 [GCC_QUPV3_WRAP1_QSPI_S2_CLK_SRC] = &gcc_qupv3_wrap1_qspi_s2_clk_src.clkr,
8184 [GCC_QUPV3_WRAP1_QSPI_S3_CLK] = &gcc_qupv3_wrap1_qspi_s3_clk.clkr,
8185 [GCC_QUPV3_WRAP1_QSPI_S3_CLK_SRC] = &gcc_qupv3_wrap1_qspi_s3_clk_src.clkr,
8186 [GCC_QUPV3_WRAP1_QSPI_S6_CLK] = &gcc_qupv3_wrap1_qspi_s6_clk.clkr,
8187 [GCC_QUPV3_WRAP1_QSPI_S6_CLK_SRC] = &gcc_qupv3_wrap1_qspi_s6_clk_src.clkr,
8188 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
8189 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
8190 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
8191 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
8192 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
8193 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
8194 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
8195 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
8196 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
8197 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
8198 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
8199 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
8200 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
8201 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
8202 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
8203 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
8204 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
8205 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
8206 [GCC_QUPV3_WRAP2_QSPI_S2_CLK] = &gcc_qupv3_wrap2_qspi_s2_clk.clkr,
8207 [GCC_QUPV3_WRAP2_QSPI_S2_CLK_SRC] = &gcc_qupv3_wrap2_qspi_s2_clk_src.clkr,
8208 [GCC_QUPV3_WRAP2_QSPI_S3_CLK] = &gcc_qupv3_wrap2_qspi_s3_clk.clkr,
8209 [GCC_QUPV3_WRAP2_QSPI_S3_CLK_SRC] = &gcc_qupv3_wrap2_qspi_s3_clk_src.clkr,
8210 [GCC_QUPV3_WRAP2_QSPI_S6_CLK] = &gcc_qupv3_wrap2_qspi_s6_clk.clkr,
8211 [GCC_QUPV3_WRAP2_QSPI_S6_CLK_SRC] = &gcc_qupv3_wrap2_qspi_s6_clk_src.clkr,
8212 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
8213 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
8214 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
8215 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
8216 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
8217 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
8218 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
8219 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
8220 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
8221 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
8222 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
8223 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
8224 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
8225 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
8226 [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
8227 [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
8228 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
8229 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
8230 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
8231 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
8232 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
8233 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
8234 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
8235 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
8236 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
8237 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
8238 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
8239 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
8240 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
8241 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
8242 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
8243 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
8244 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
8245 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
8246 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
8247 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
8248 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
8249 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
8250 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
8251 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
8252 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
8253 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
8254 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
8255 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
8256 [GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
8257 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
8258 [GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr,
8259 [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr,
8260 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
8261 [GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr,
8262 [GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr,
8263 [GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr,
8264 [GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr,
8265 [GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr,
8266 [GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr,
8267 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
8268 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
8269 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
8270 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
8271 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
8272 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
8273 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
8274 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
8275 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
8276 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
8277 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
8278 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
8279 [GCC_USB30_TERT_MASTER_CLK] = &gcc_usb30_tert_master_clk.clkr,
8280 [GCC_USB30_TERT_MASTER_CLK_SRC] = &gcc_usb30_tert_master_clk_src.clkr,
8281 [GCC_USB30_TERT_MOCK_UTMI_CLK] = &gcc_usb30_tert_mock_utmi_clk.clkr,
8282 [GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr,
8283 [GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr,
8284 [GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr,
8285 [GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr,
8286 [GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr,
8287 [GCC_USB34_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb34_tert_phy_pipe_clk_src.clkr,
8288 [GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
8289 [GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
8290 [GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
8291 [GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,
8292 [GCC_USB3_MP_PHY_PIPE_0_CLK_SRC] = &gcc_usb3_mp_phy_pipe_0_clk_src.clkr,
8293 [GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,
8294 [GCC_USB3_MP_PHY_PIPE_1_CLK_SRC] = &gcc_usb3_mp_phy_pipe_1_clk_src.clkr,
8295 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
8296 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
8297 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
8298 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
8299 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
8300 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
8301 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
8302 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
8303 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
8304 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
8305 [GCC_USB3_TERT_PHY_AUX_CLK] = &gcc_usb3_tert_phy_aux_clk.clkr,
8306 [GCC_USB3_TERT_PHY_AUX_CLK_SRC] = &gcc_usb3_tert_phy_aux_clk_src.clkr,
8307 [GCC_USB3_TERT_PHY_COM_AUX_CLK] = &gcc_usb3_tert_phy_com_aux_clk.clkr,
8308 [GCC_USB3_TERT_PHY_PIPE_CLK] = &gcc_usb3_tert_phy_pipe_clk.clkr,
8309 [GCC_USB3_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb3_tert_phy_pipe_clk_src.clkr,
8310 [GCC_USB4_0_CFG_AHB_CLK] = &gcc_usb4_0_cfg_ahb_clk.clkr,
8311 [GCC_USB4_0_DP0_CLK] = &gcc_usb4_0_dp0_clk.clkr,
8312 [GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr,
8313 [GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr,
8314 [GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr,
8315 [GCC_USB4_0_PHY_DP0_CLK_SRC] = &gcc_usb4_0_phy_dp0_clk_src.clkr,
8316 [GCC_USB4_0_PHY_DP1_CLK_SRC] = &gcc_usb4_0_phy_dp1_clk_src.clkr,
8317 [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr,
8318 [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr,
8319 [GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr,
8320 [GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr,
8321 [GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr,
8322 [GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr,
8323 [GCC_USB4_0_PHY_RX0_CLK_SRC] = &gcc_usb4_0_phy_rx0_clk_src.clkr,
8324 [GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr,
8325 [GCC_USB4_0_PHY_RX1_CLK_SRC] = &gcc_usb4_0_phy_rx1_clk_src.clkr,
8326 [GCC_USB4_0_PHY_SYS_CLK_SRC] = &gcc_usb4_0_phy_sys_clk_src.clkr,
8327 [GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr,
8328 [GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr,
8329 [GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr,
8330 [GCC_USB4_0_SYS_CLK] = &gcc_usb4_0_sys_clk.clkr,
8331 [GCC_USB4_0_TMU_CLK] = &gcc_usb4_0_tmu_clk.clkr,
8332 [GCC_USB4_0_TMU_CLK_SRC] = &gcc_usb4_0_tmu_clk_src.clkr,
8333 [GCC_USB4_0_UC_HRR_CLK] = &gcc_usb4_0_uc_hrr_clk.clkr,
8334 [GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr,
8335 [GCC_USB4_1_DP0_CLK] = &gcc_usb4_1_dp0_clk.clkr,
8336 [GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr,
8337 [GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr,
8338 [GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr,
8339 [GCC_USB4_1_PHY_DP0_CLK_SRC] = &gcc_usb4_1_phy_dp0_clk_src.clkr,
8340 [GCC_USB4_1_PHY_DP1_CLK_SRC] = &gcc_usb4_1_phy_dp1_clk_src.clkr,
8341 [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr,
8342 [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr,
8343 [GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr,
8344 [GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr,
8345 [GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr,
8346 [GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pll_pipe_clk_src.clkr,
8347 [GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr,
8348 [GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr,
8349 [GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr,
8350 [GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr,
8351 [GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr,
8352 [GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr,
8353 [GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr,
8354 [GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr,
8355 [GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr,
8356 [GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr,
8357 [GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr,
8358 [GCC_USB4_1_UC_HRR_CLK] = &gcc_usb4_1_uc_hrr_clk.clkr,
8359 [GCC_USB4_2_CFG_AHB_CLK] = &gcc_usb4_2_cfg_ahb_clk.clkr,
8360 [GCC_USB4_2_DP0_CLK] = &gcc_usb4_2_dp0_clk.clkr,
8361 [GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr,
8362 [GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr,
8363 [GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr,
8364 [GCC_USB4_2_PHY_DP0_CLK_SRC] = &gcc_usb4_2_phy_dp0_clk_src.clkr,
8365 [GCC_USB4_2_PHY_DP1_CLK_SRC] = &gcc_usb4_2_phy_dp1_clk_src.clkr,
8366 [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr,
8367 [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr,
8368 [GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr,
8369 [GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr,
8370 [GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr,
8371 [GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr,
8372 [GCC_USB4_2_PHY_RX0_CLK_SRC] = &gcc_usb4_2_phy_rx0_clk_src.clkr,
8373 [GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr,
8374 [GCC_USB4_2_PHY_RX1_CLK_SRC] = &gcc_usb4_2_phy_rx1_clk_src.clkr,
8375 [GCC_USB4_2_PHY_SYS_CLK_SRC] = &gcc_usb4_2_phy_sys_clk_src.clkr,
8376 [GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr,
8377 [GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr,
8378 [GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr,
8379 [GCC_USB4_2_SYS_CLK] = &gcc_usb4_2_sys_clk.clkr,
8380 [GCC_USB4_2_TMU_CLK] = &gcc_usb4_2_tmu_clk.clkr,
8381 [GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr,
8382 [GCC_USB4_2_UC_HRR_CLK] = &gcc_usb4_2_uc_hrr_clk.clkr,
8383 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
8384 [GCC_VIDEO_AXI0C_CLK] = &gcc_video_axi0c_clk.clkr,
8385 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
8386 };
8387
8388 static struct gdsc *gcc_glymur_gdscs[] = {
8389 [GCC_PCIE_0_TUNNEL_GDSC] = &gcc_pcie_0_tunnel_gdsc,
8390 [GCC_PCIE_1_TUNNEL_GDSC] = &gcc_pcie_1_tunnel_gdsc,
8391 [GCC_PCIE_2_TUNNEL_GDSC] = &gcc_pcie_2_tunnel_gdsc,
8392 [GCC_PCIE_3A_GDSC] = &gcc_pcie_3a_gdsc,
8393 [GCC_PCIE_3A_PHY_GDSC] = &gcc_pcie_3a_phy_gdsc,
8394 [GCC_PCIE_3B_GDSC] = &gcc_pcie_3b_gdsc,
8395 [GCC_PCIE_3B_PHY_GDSC] = &gcc_pcie_3b_phy_gdsc,
8396 [GCC_PCIE_4_GDSC] = &gcc_pcie_4_gdsc,
8397 [GCC_PCIE_4_PHY_GDSC] = &gcc_pcie_4_phy_gdsc,
8398 [GCC_PCIE_5_GDSC] = &gcc_pcie_5_gdsc,
8399 [GCC_PCIE_5_PHY_GDSC] = &gcc_pcie_5_phy_gdsc,
8400 [GCC_PCIE_6_GDSC] = &gcc_pcie_6_gdsc,
8401 [GCC_PCIE_6_PHY_GDSC] = &gcc_pcie_6_phy_gdsc,
8402 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
8403 [GCC_USB20_PRIM_GDSC] = &gcc_usb20_prim_gdsc,
8404 [GCC_USB30_MP_GDSC] = &gcc_usb30_mp_gdsc,
8405 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
8406 [GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc,
8407 [GCC_USB30_TERT_GDSC] = &gcc_usb30_tert_gdsc,
8408 [GCC_USB3_MP_SS0_PHY_GDSC] = &gcc_usb3_mp_ss0_phy_gdsc,
8409 [GCC_USB3_MP_SS1_PHY_GDSC] = &gcc_usb3_mp_ss1_phy_gdsc,
8410 [GCC_USB4_0_GDSC] = &gcc_usb4_0_gdsc,
8411 [GCC_USB4_1_GDSC] = &gcc_usb4_1_gdsc,
8412 [GCC_USB4_2_GDSC] = &gcc_usb4_2_gdsc,
8413 [GCC_USB_0_PHY_GDSC] = &gcc_usb_0_phy_gdsc,
8414 [GCC_USB_1_PHY_GDSC] = &gcc_usb_1_phy_gdsc,
8415 [GCC_USB_2_PHY_GDSC] = &gcc_usb_2_phy_gdsc,
8416 };
8417
8418 static const struct qcom_reset_map gcc_glymur_resets[] = {
8419 [GCC_AV1E_BCR] = { 0x9b028 },
8420 [GCC_CAMERA_BCR] = { 0x26000 },
8421 [GCC_DISPLAY_BCR] = { 0x27000 },
8422 [GCC_EVA_BCR] = { 0x9b000 },
8423 [GCC_GPU_BCR] = { 0x71000 },
8424 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbc2d0 },
8425 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbc2dc },
8426 [GCC_PCIE_0_PHY_BCR] = { 0xbc2d8 },
8427 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbc2e0 },
8428 [GCC_PCIE_0_TUNNEL_BCR] = { 0xc8000 },
8429 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x7f018 },
8430 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x7f024 },
8431 [GCC_PCIE_1_PHY_BCR] = { 0x7f020 },
8432 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x7f028 },
8433 [GCC_PCIE_1_TUNNEL_BCR] = { 0x2e000 },
8434 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x281d0 },
8435 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x281dc },
8436 [GCC_PCIE_2_PHY_BCR] = { 0x281d8 },
8437 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x281e0 },
8438 [GCC_PCIE_2_TUNNEL_BCR] = { 0xc0000 },
8439 [GCC_PCIE_3A_BCR] = { 0xdc000 },
8440 [GCC_PCIE_3A_LINK_DOWN_BCR] = { 0x7b0a0 },
8441 [GCC_PCIE_3A_NOCSR_COM_PHY_BCR] = { 0x7b0ac },
8442 [GCC_PCIE_3A_PHY_BCR] = { 0x6c000 },
8443 [GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR] = { 0x7b0b0 },
8444 [GCC_PCIE_3B_BCR] = { 0x94000 },
8445 [GCC_PCIE_3B_LINK_DOWN_BCR] = { 0x7a0c0 },
8446 [GCC_PCIE_3B_NOCSR_COM_PHY_BCR] = { 0x7a0cc },
8447 [GCC_PCIE_3B_PHY_BCR] = { 0x75000 },
8448 [GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR] = { 0x7a0c8 },
8449 [GCC_PCIE_4_BCR] = { 0x88000 },
8450 [GCC_PCIE_4_LINK_DOWN_BCR] = { 0x980c0 },
8451 [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0x980cc },
8452 [GCC_PCIE_4_PHY_BCR] = { 0xd3000 },
8453 [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0x980d0 },
8454 [GCC_PCIE_5_BCR] = { 0xc3000 },
8455 [GCC_PCIE_5_LINK_DOWN_BCR] = { 0x850c0 },
8456 [GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0x850cc },
8457 [GCC_PCIE_5_PHY_BCR] = { 0xd2000 },
8458 [GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0x850d0 },
8459 [GCC_PCIE_6_BCR] = { 0x8a000 },
8460 [GCC_PCIE_6_LINK_DOWN_BCR] = { 0x3a0b0 },
8461 [GCC_PCIE_6_NOCSR_COM_PHY_BCR] = { 0x3a0bc },
8462 [GCC_PCIE_6_PHY_BCR] = { 0xd4000 },
8463 [GCC_PCIE_6_PHY_NOCSR_COM_PHY_BCR] = { 0x3a0c0 },
8464 [GCC_PCIE_NOC_BCR] = { 0xba294 },
8465 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
8466 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
8467 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
8468 [GCC_PCIE_RSCC_BCR] = { 0xb8000 },
8469 [GCC_PDM_BCR] = { 0x33000 },
8470 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x28000 },
8471 [GCC_QUPV3_WRAPPER_1_BCR] = { 0xb3000 },
8472 [GCC_QUPV3_WRAPPER_2_BCR] = { 0xb4000 },
8473 [GCC_QUPV3_WRAPPER_OOB_BCR] = { 0xe7000 },
8474 [GCC_QUSB2PHY_HS0_MP_BCR] = { 0xca000 },
8475 [GCC_QUSB2PHY_HS1_MP_BCR] = { 0xe6000 },
8476 [GCC_QUSB2PHY_PRIM_BCR] = { 0xad024 },
8477 [GCC_QUSB2PHY_SEC_BCR] = { 0xae000 },
8478 [GCC_QUSB2PHY_TERT_BCR] = { 0xc9000 },
8479 [GCC_QUSB2PHY_USB20_HS_BCR] = { 0xe9000 },
8480 [GCC_SDCC2_BCR] = { 0xb0000 },
8481 [GCC_SDCC4_BCR] = { 0xdf000 },
8482 [GCC_TCSR_PCIE_BCR] = { 0x281e4 },
8483 [GCC_UFS_PHY_BCR] = { 0x77004 },
8484 [GCC_USB20_PRIM_BCR] = { 0xbc000 },
8485 [GCC_USB30_MP_BCR] = { 0x9a00c },
8486 [GCC_USB30_PRIM_BCR] = { 0x3f018 },
8487 [GCC_USB30_SEC_BCR] = { 0xe200c },
8488 [GCC_USB30_TERT_BCR] = { 0xe100c },
8489 [GCC_USB3_MP_SS0_PHY_BCR] = { 0x54008 },
8490 [GCC_USB3_MP_SS1_PHY_BCR] = { 0x54028 },
8491 [GCC_USB3_PHY_PRIM_BCR] = { 0xdb000 },
8492 [GCC_USB3_PHY_SEC_BCR] = { 0x2c000 },
8493 [GCC_USB3_PHY_TERT_BCR] = { 0xbe000 },
8494 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x54000 },
8495 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x54020 },
8496 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0xdb004 },
8497 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x2c004 },
8498 [GCC_USB3PHY_PHY_TERT_BCR] = { 0xbe004 },
8499 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x54004 },
8500 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54024 },
8501 [GCC_USB4_0_BCR] = { 0x2b004 },
8502 [GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0xdb010 },
8503 [GCC_USB4_1_BCR] = { 0x2d004 },
8504 [GCC_USB4_2_BCR] = { 0xe0004 },
8505 [GCC_USB_0_PHY_BCR] = { 0xdb020 },
8506 [GCC_USB_1_PHY_BCR] = { 0x2c020 },
8507 [GCC_USB_2_PHY_BCR] = { 0xbe020 },
8508 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x3201c, 2 },
8509 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32044, 2 },
8510 [GCC_VIDEO_BCR] = { 0x32000 },
8511 };
8512
8513 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
8514 DEFINE_RCG_DFS(gcc_qupv3_oob_qspi_s0_clk_src),
8515 DEFINE_RCG_DFS(gcc_qupv3_oob_qspi_s1_clk_src),
8516 DEFINE_RCG_DFS(gcc_qupv3_wrap0_qspi_s2_clk_src),
8517 DEFINE_RCG_DFS(gcc_qupv3_wrap0_qspi_s3_clk_src),
8518 DEFINE_RCG_DFS(gcc_qupv3_wrap0_qspi_s6_clk_src),
8519 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
8520 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
8521 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
8522 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
8523 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
8524 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_s2_clk_src),
8525 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_s3_clk_src),
8526 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_s6_clk_src),
8527 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
8528 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
8529 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
8530 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
8531 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
8532 DEFINE_RCG_DFS(gcc_qupv3_wrap2_qspi_s2_clk_src),
8533 DEFINE_RCG_DFS(gcc_qupv3_wrap2_qspi_s3_clk_src),
8534 DEFINE_RCG_DFS(gcc_qupv3_wrap2_qspi_s6_clk_src),
8535 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
8536 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
8537 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
8538 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
8539 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
8540 };
8541
8542 static u32 gcc_glymur_critical_cbcrs[] = {
8543 0x26004, /* GCC_CAMERA_AHB_CLK */
8544 0x26040, /* GCC_CAMERA_XO_CLK */
8545 0x27004, /* GCC_DISP_AHB_CLK */
8546 0x71004, /* GCC_GPU_CFG_AHB_CLK */
8547 0x32004, /* GCC_VIDEO_AHB_CLK */
8548 0x32058, /* GCC_VIDEO_XO_CLK */
8549 };
8550
8551 static const struct regmap_config gcc_glymur_regmap_config = {
8552 .reg_bits = 32,
8553 .reg_stride = 4,
8554 .val_bits = 32,
8555 .max_register = 0x1f8ff0,
8556 .fast_io = true,
8557 };
8558
clk_glymur_regs_configure(struct device * dev,struct regmap * regmap)8559 static void clk_glymur_regs_configure(struct device *dev, struct regmap *regmap)
8560 {
8561 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
8562 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
8563 }
8564
8565 static struct qcom_cc_driver_data gcc_glymur_driver_data = {
8566 .clk_cbcrs = gcc_glymur_critical_cbcrs,
8567 .num_clk_cbcrs = ARRAY_SIZE(gcc_glymur_critical_cbcrs),
8568 .dfs_rcgs = gcc_dfs_clocks,
8569 .num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
8570 .clk_regs_configure = clk_glymur_regs_configure,
8571 };
8572
8573 static const struct qcom_cc_desc gcc_glymur_desc = {
8574 .config = &gcc_glymur_regmap_config,
8575 .clks = gcc_glymur_clocks,
8576 .num_clks = ARRAY_SIZE(gcc_glymur_clocks),
8577 .resets = gcc_glymur_resets,
8578 .num_resets = ARRAY_SIZE(gcc_glymur_resets),
8579 .gdscs = gcc_glymur_gdscs,
8580 .num_gdscs = ARRAY_SIZE(gcc_glymur_gdscs),
8581 .driver_data = &gcc_glymur_driver_data,
8582 };
8583
8584 static const struct of_device_id gcc_glymur_match_table[] = {
8585 { .compatible = "qcom,glymur-gcc" },
8586 { }
8587 };
8588 MODULE_DEVICE_TABLE(of, gcc_glymur_match_table);
8589
gcc_glymur_probe(struct platform_device * pdev)8590 static int gcc_glymur_probe(struct platform_device *pdev)
8591 {
8592 return qcom_cc_probe(pdev, &gcc_glymur_desc);
8593 }
8594
8595 static struct platform_driver gcc_glymur_driver = {
8596 .probe = gcc_glymur_probe,
8597 .driver = {
8598 .name = "gcc-glymur",
8599 .of_match_table = gcc_glymur_match_table,
8600 },
8601 };
8602
gcc_glymur_init(void)8603 static int __init gcc_glymur_init(void)
8604 {
8605 return platform_driver_register(&gcc_glymur_driver);
8606 }
8607 subsys_initcall(gcc_glymur_init);
8608
gcc_glymur_exit(void)8609 static void __exit gcc_glymur_exit(void)
8610 {
8611 platform_driver_unregister(&gcc_glymur_driver);
8612 }
8613 module_exit(gcc_glymur_exit);
8614
8615 MODULE_DESCRIPTION("QTI GCC GLYMUR Driver");
8616 MODULE_LICENSE("GPL");
8617