1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2004-2005 HighPoint Technologies, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <sys/bus.h>
33 #include <sys/malloc.h>
34 #include <sys/resource.h>
35 #include <sys/time.h>
36 #include <sys/callout.h>
37 #include <sys/signalvar.h>
38 #include <sys/eventhandler.h>
39 #include <sys/proc.h>
40 #include <sys/kthread.h>
41
42 #include <sys/mutex.h>
43 #include <sys/module.h>
44 #include <sys/sx.h>
45
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcivar.h>
48
49 #ifndef __KERNEL__
50 #define __KERNEL__
51 #endif
52
53 #include <dev/hptmv/global.h>
54 #include <dev/hptmv/hptintf.h>
55 #include <dev/hptmv/osbsd.h>
56 #include <dev/hptmv/access601.h>
57
58
59 #ifdef DEBUG
60 #ifdef DEBUG_LEVEL
61 int hpt_dbg_level = DEBUG_LEVEL;
62 #else
63 int hpt_dbg_level = 0;
64 #endif
65 #endif
66
67 #define MV_ERROR printf
68
69 /*
70 * CAM SIM entry points
71 */
72 static int hpt_probe (device_t dev);
73 static void launch_worker_thread(void);
74 static int hpt_attach(device_t dev);
75 static int hpt_detach(device_t dev);
76 static int hpt_shutdown(device_t dev);
77 static void hpt_poll(struct cam_sim *sim);
78 static void hpt_intr(void *arg);
79 static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg);
80 static void hpt_action(struct cam_sim *sim, union ccb *ccb);
81
82 static device_method_t driver_methods[] = {
83 /* Device interface */
84 DEVMETHOD(device_probe, hpt_probe),
85 DEVMETHOD(device_attach, hpt_attach),
86 DEVMETHOD(device_detach, hpt_detach),
87
88 DEVMETHOD(device_shutdown, hpt_shutdown),
89 DEVMETHOD_END
90 };
91
92 static driver_t hpt_pci_driver = {
93 __str(PROC_DIR_NAME),
94 driver_methods,
95 sizeof(IAL_ADAPTER_T)
96 };
97
98 #define __DRIVER_MODULE(p1, p2, p3, p4, p5) DRIVER_MODULE(p1, p2, p3, p4, p5)
99 __DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, 0, 0);
100 MODULE_DEPEND(PROC_DIR_NAME, cam, 1, 1, 1);
101
102 #define ccb_ccb_ptr spriv_ptr0
103 #define ccb_adapter ccb_h.spriv_ptr1
104
105 static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev);
106 static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb);
107 static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd);
108 static void ccb_done(union ccb *ccb);
109 static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb);
110 static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb);
111 static void hpt_intr_locked(IAL_ADAPTER_T *pAdapter);
112 static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter);
113 static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
114 static void handleEdmaError(_VBUS_ARG PCommand pCmd);
115 static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
116 static int fResetActiveCommands(PVBus _vbus_p);
117 static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter);
118 static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter);
119 static void hptmv_handle_event_disconnect(void *data);
120 static void hptmv_handle_event_connect(void *data);
121 static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum);
122 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel);
123 static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel);
124 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg,
125 int logical);
126 static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
127 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId,
128 MV_U16 responseFlags, MV_U32 timeStamp,
129 MV_STORAGE_DEVICE_REGISTERS *registerStruct);
130 static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter,
131 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2);
132
133 #define ccb_ccb_ptr spriv_ptr0
134 #define ccb_adapter ccb_h.spriv_ptr1
135
136 static struct sx hptmv_list_lock;
137 SX_SYSINIT(hptmv_list_lock, &hptmv_list_lock, "hptmv list");
138 IAL_ADAPTER_T *gIal_Adapter = NULL;
139 IAL_ADAPTER_T *pCurAdapter = NULL;
140 static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM];
141
142 typedef struct st_HPT_DPC {
143 IAL_ADAPTER_T *pAdapter;
144 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR);
145 void *arg;
146 UCHAR flags;
147 } ST_HPT_DPC;
148
149 #define MAX_DPC 16
150 UCHAR DPC_Request_Nums = 0;
151 static ST_HPT_DPC DpcQueue[MAX_DPC];
152 static int DpcQueue_First=0;
153 static int DpcQueue_Last = 0;
154 static struct mtx DpcQueue_Lock;
155 MTX_SYSINIT(hpmtv_dpc_lock, &DpcQueue_Lock, "hptmv dpc", MTX_DEF);
156
157 char DRIVER_VERSION[] = "v1.16";
158
159 /*******************************************************************************
160 * Name: hptmv_free_channel
161 *
162 * Description: free allocated queues for the given channel
163 *
164 * Parameters: pMvSataAdapter - pointer to the RR18xx controller this
165 * channel connected to.
166 * channelNum - channel number.
167 *
168 ******************************************************************************/
169 static void
hptmv_free_channel(IAL_ADAPTER_T * pAdapter,MV_U8 channelNum)170 hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
171 {
172 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM);
173 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL;
174 }
175
failDevice(PVDevice pVDev)176 static void failDevice(PVDevice pVDev)
177 {
178 PVBus _vbus_p = pVDev->pVBus;
179 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt;
180
181 pVDev->u.disk.df_on_line = 0;
182 pVDev->vf_online = 0;
183 if (pVDev->pfnDeviceFailed)
184 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev);
185
186 fNotifyGUI(ET_DEVICE_REMOVED, pVDev);
187
188 #ifndef FOR_DEMO
189 if (pAdapter->ver_601==2 && !pAdapter->beeping) {
190 pAdapter->beeping = 1;
191 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress);
192 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1);
193 }
194 #endif
195 }
196
197 int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel);
198
199 static void
handleEdmaError(_VBUS_ARG PCommand pCmd)200 handleEdmaError(_VBUS_ARG PCommand pCmd)
201 {
202 PDevice pDevice = &pCmd->pVDevice->u.disk;
203 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter;
204
205 if (!pDevice->df_on_line) {
206 KdPrint(("Device is offline"));
207 pCmd->Result = RETURN_BAD_DEVICE;
208 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
209 return;
210 }
211
212 if (pCmd->RetryCount++>5) {
213 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber));
214 failed:
215 failDevice(pCmd->pVDevice);
216 pCmd->Result = RETURN_IDE_ERROR;
217 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
218 return;
219 }
220
221 /* reset the channel and retry the command */
222 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber))
223 goto failed;
224
225 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice));
226
227 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber));
228 fDeviceSendCommand(_VBUS_P pCmd);
229 }
230
231 /****************************************************************
232 * Name: hptmv_init_channel
233 *
234 * Description: allocate request and response queues for the EDMA of the
235 * given channel and sets other fields.
236 *
237 * Parameters:
238 * pAdapter - pointer to the emulated adapter data structure
239 * channelNum - channel number.
240 * Return: 0 on success, otherwise on failure
241 ****************************************************************/
242 static int
hptmv_init_channel(IAL_ADAPTER_T * pAdapter,MV_U8 channelNum)243 hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
244 {
245 MV_SATA_CHANNEL *pMvSataChannel;
246 dma_addr_t req_dma_addr;
247 dma_addr_t rsp_dma_addr;
248
249 if (channelNum >= MV_SATA_CHANNELS_NUM)
250 {
251 MV_ERROR("RR18xx[%d]: Bad channelNum=%d",
252 pAdapter->mvSataAdapter.adapterId, channelNum);
253 return -1;
254 }
255
256 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum];
257 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel;
258 pMvSataChannel->channelNumber = channelNum;
259 pMvSataChannel->lba48Address = MV_FALSE;
260 pMvSataChannel->maxReadTransfer = MV_FALSE;
261
262 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *)
263 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE));
264 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE);
265
266
267 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr));
268
269 /* check the 1K alignment of the request queue*/
270 if (req_dma_addr & 0x3ff)
271 {
272 MV_ERROR("RR18xx[%d]: request queue allocated isn't 1 K aligned,"
273 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId,
274 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum);
275 return -1;
276 }
277 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr;
278 pMvSataChannel->requestQueuePciHiAddress = 0;
279 KdPrint(("RR18xx[%d,%d]: request queue allocated: 0x%p",
280 pAdapter->mvSataAdapter.adapterId, channelNum,
281 pMvSataChannel->requestQueue));
282 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *)
283 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE));
284 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE);
285
286 /* check the 256 alignment of the response queue*/
287 if (rsp_dma_addr & 0xff)
288 {
289 MV_ERROR("RR18xx[%d,%d]: response queue allocated isn't 256 byte "
290 "aligned, dma_addr=%llx\n",
291 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr);
292 return -1;
293 }
294 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr;
295 pMvSataChannel->responseQueuePciHiAddress = 0;
296 KdPrint(("RR18xx[%d,%d]: response queue allocated: 0x%p",
297 pAdapter->mvSataAdapter.adapterId, channelNum,
298 pMvSataChannel->responseQueue));
299
300 pAdapter->mvChannel[channelNum].online = MV_TRUE;
301 return 0;
302 }
303
304 /******************************************************************************
305 * Name: hptmv_parse_identify_results
306 *
307 * Description: this functions parses the identify command results, checks
308 * that the connected deives can be accesed by RR18xx EDMA,
309 * and updates the channel structure accordingly.
310 *
311 * Parameters: pMvSataChannel, pointer to the channel data structure.
312 *
313 * Returns: =0 ->success, < 0 ->failure.
314 *
315 ******************************************************************************/
316 static int
hptmv_parse_identify_results(MV_SATA_CHANNEL * pMvSataChannel)317 hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel)
318 {
319 MV_U16 *iden = pMvSataChannel->identifyDevice;
320
321 /*LBA addressing*/
322 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200))
323 {
324 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n"));
325 return -1;
326 }
327 else
328 {
329 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported"));
330 }
331 /*DMA support*/
332 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100))
333 {
334 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n"));
335 return -1;
336 }
337 else
338 {
339 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported"));
340 }
341 /* PIO */
342 if ((iden[IDEN_VALID] & 2) == 0)
343 {
344 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n"));
345 return -1;
346 }
347 KdPrint(("%25s - 0x%02x\n", "PIO modes supported",
348 iden[IDEN_PIO_MODE_SPPORTED] & 0xff));
349
350 /*UDMA*/
351 if ((iden[IDEN_VALID] & 4) == 0)
352 {
353 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n"));
354 return -1;
355 }
356
357 /* 48 bit address */
358 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400))
359 {
360 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported"));
361 pMvSataChannel->lba48Address = MV_TRUE;
362 }
363 else
364 {
365 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported"));
366 pMvSataChannel->lba48Address = MV_FALSE;
367 }
368 return 0;
369 }
370
371 static void
init_vdev_params(IAL_ADAPTER_T * pAdapter,MV_U8 channel)372 init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel)
373 {
374 PVDevice pVDev = &pAdapter->VDevices[channel];
375 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel];
376 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice;
377
378 pMvSataChannel->outstandingCommands = 0;
379
380 pVDev->u.disk.mv = pMvSataChannel;
381 pVDev->u.disk.df_on_line = 1;
382 pVDev->u.disk.pVBus = &pAdapter->VBus;
383 pVDev->pVBus = &pAdapter->VBus;
384
385 #ifdef SUPPORT_48BIT_LBA
386 if (pMvSataChannel->lba48Address == MV_TRUE)
387 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1;
388 else
389 #endif
390 if(IdentifyData[53] & 1) {
391 pVDev->u.disk.dDeRealCapacity =
392 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ?
393 (IdentifyData[61]<<16 | IdentifyData[60]) :
394 (IdentifyData[58]<<16 | IdentifyData[57])) - 1;
395 } else
396 pVDev->u.disk.dDeRealCapacity =
397 (IdentifyData[61]<<16 | IdentifyData[60]) - 1;
398
399 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
400 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0;
401
402 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) {
403 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting =
404 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8;
405 }
406 }
407
device_change(IAL_ADAPTER_T * pAdapter,MV_U8 channelIndex,int plugged)408 static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged)
409 {
410 PVDevice pVDev;
411 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
412 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex];
413
414 if (!pMvSataChannel) return;
415
416 if (plugged)
417 {
418 pVDev = &(pAdapter->VDevices[channelIndex]);
419 init_vdev_params(pAdapter, channelIndex);
420
421 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI :
422 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK;
423
424 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO;
425 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
426 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
427 pVDev->vf_online = 1;
428
429 #ifdef SUPPORT_ARRAY
430 if(pVDev->pParent)
431 {
432 int iMember;
433 for (iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++)
434 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev)
435 pVDev->pParent->u.array.pMember[iMember] = NULL;
436 pVDev->pParent = NULL;
437 }
438 #endif
439 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev);
440 fCheckBootable(pVDev);
441 RegisterVDevice(pVDev);
442
443 #ifndef FOR_DEMO
444 if (pAdapter->beeping) {
445 pAdapter->beeping = 0;
446 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress);
447 }
448 #endif
449
450 }
451 else
452 {
453 pVDev = &(pAdapter->VDevices[channelIndex]);
454 failDevice(pVDev);
455 }
456 }
457
458 static int
start_channel(IAL_ADAPTER_T * pAdapter,MV_U8 channelNum)459 start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum)
460 {
461 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
462 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum];
463 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]);
464 MV_U32 udmaMode,pioMode;
465
466 KdPrint(("RR18xx [%d]: start channel (%d)", pMvSataAdapter->adapterId,
467 channelNum));
468
469
470 /* Software reset channel */
471 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
472 {
473 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n",
474 pMvSataAdapter->adapterId, channelNum);
475 return -1;
476 }
477
478 /* Hardware reset channel */
479 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
480 {
481 /* If failed, try again - this is when trying to hardreset a channel */
482 /* when drive is just spinning up */
483 StallExec(5000000); /* wait 5 sec before trying again */
484 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
485 {
486 MV_ERROR("RR18xx [%d,%d]: failed to perform Hard reset\n",
487 pMvSataAdapter->adapterId, channelNum);
488 return -1;
489 }
490 }
491
492 /* identify device*/
493 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE)
494 {
495 MV_ERROR("RR18xx [%d,%d]: failed to perform ATA Identify command\n"
496 , pMvSataAdapter->adapterId, channelNum);
497 return -1;
498 }
499 if (hptmv_parse_identify_results(pMvSataChannel))
500 {
501 MV_ERROR("RR18xx [%d,%d]: Error in parsing ATA Identify message\n"
502 , pMvSataAdapter->adapterId, channelNum);
503 return -1;
504 }
505
506 /* mvStorageDevATASetFeatures */
507 /* Disable 8 bit PIO in case CFA enabled */
508 if (pMvSataChannel->identifyDevice[86] & 4)
509 {
510 KdPrint(("RR18xx [%d]: Disable 8 bit PIO (CFA enabled) \n",
511 pMvSataAdapter->adapterId));
512 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
513 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0,
514 0, 0, 0) == MV_FALSE)
515 {
516 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures"
517 " failed\n", pMvSataAdapter->adapterId, channelNum);
518 return -1;
519 }
520 }
521 /* Write cache */
522 #ifdef ENABLE_WRITE_CACHE
523 if (pMvSataChannel->identifyDevice[82] & 0x20)
524 {
525 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */
526 {
527 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
528 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0,
529 0, 0, 0) == MV_FALSE)
530 {
531 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n",
532 pMvSataAdapter->adapterId, channelNum);
533 return -1;
534 }
535 }
536 KdPrint(("RR18xx [%d]: channel %d, write cache enabled\n",
537 pMvSataAdapter->adapterId, channelNum));
538 }
539 else
540 {
541 KdPrint(("RR18xx [%d]: channel %d, write cache not supported\n",
542 pMvSataAdapter->adapterId, channelNum));
543 }
544 #else /* disable write cache */
545 {
546 if (pMvSataChannel->identifyDevice[85] & 0x20)
547 {
548 KdPrint(("RR18xx [%d]: channel =%d, disable write cache\n",
549 pMvSataAdapter->adapterId, channelNum));
550 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
551 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0,
552 0, 0, 0) == MV_FALSE)
553 {
554 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n",
555 pMvSataAdapter->adapterId, channelNum);
556 return -1;
557 }
558 }
559 KdPrint(("RR18xx [%d]: channel=%d, write cache disabled\n",
560 pMvSataAdapter->adapterId, channelNum));
561 }
562 #endif
563
564 /* Set transfer mode */
565 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_SLOW\n",
566 pMvSataAdapter->adapterId));
567 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
568 MV_ATA_SET_FEATURES_TRANSFER,
569 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) ==
570 MV_FALSE)
571 {
572 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
573 pMvSataAdapter->adapterId, channelNum);
574 return -1;
575 }
576
577 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1)
578 {
579 pioMode = MV_ATA_TRANSFER_PIO_4;
580 }
581 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2)
582 {
583 pioMode = MV_ATA_TRANSFER_PIO_3;
584 }
585 else
586 {
587 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n");
588 pioMode = MV_ATA_TRANSFER_PIO_SLOW;
589 }
590
591 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_4\n",
592 pMvSataAdapter->adapterId));
593 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode;
594 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
595 MV_ATA_SET_FEATURES_TRANSFER,
596 pioMode, 0, 0, 0) == MV_FALSE)
597 {
598 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
599 pMvSataAdapter->adapterId, channelNum);
600 return -1;
601 }
602
603 udmaMode = MV_ATA_TRANSFER_UDMA_0;
604 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40)
605 {
606 udmaMode = MV_ATA_TRANSFER_UDMA_6;
607 }
608 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20)
609 {
610 udmaMode = MV_ATA_TRANSFER_UDMA_5;
611 }
612 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10)
613 {
614 udmaMode = MV_ATA_TRANSFER_UDMA_4;
615 }
616 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8)
617 {
618 udmaMode = MV_ATA_TRANSFER_UDMA_3;
619 }
620 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4)
621 {
622 udmaMode = MV_ATA_TRANSFER_UDMA_2;
623 }
624
625 KdPrint(("RR18xx [%d] Set transfer mode XFER_UDMA_%d\n",
626 pMvSataAdapter->adapterId, udmaMode & 0xf));
627 pChannelInfo->maxUltraDmaModeSupported = udmaMode;
628
629 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
630 MV_ATA_SET_FEATURES_TRANSFER, udmaMode,
631 0, 0, 0) == MV_FALSE)
632 {
633 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
634 pMvSataAdapter->adapterId, channelNum);
635 return -1;
636 }*/
637 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF)
638 return TRUE;
639 else
640 do
641 {
642 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
643 MV_ATA_SET_FEATURES_TRANSFER,
644 pChannelInfo->maxUltraDmaModeSupported,
645 0, 0, 0) == MV_FALSE)
646 {
647 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0)
648 {
649 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
650 {
651 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress,
652 pMvSataChannel->eDmaRegsOffset +
653 0x11c, /* command reg */
654 MV_ATA_COMMAND_IDLE_IMMEDIATE);
655 mvMicroSecondsDelay(10000);
656 mvSataChannelHardReset(pMvSataAdapter, channelNum);
657 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE)
658 return FALSE;
659 }
660 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE)
661 return FALSE;
662 pChannelInfo->maxUltraDmaModeSupported--;
663 continue;
664 }
665 else return FALSE;
666 }
667 break;
668 }while (1);
669
670 /* Read look ahead */
671 #ifdef ENABLE_READ_AHEAD
672 if (pMvSataChannel->identifyDevice[82] & 0x40)
673 {
674 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */
675 {
676 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
677 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0,
678 0, 0) == MV_FALSE)
679 {
680 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n",
681 pMvSataAdapter->adapterId, channelNum);
682 return -1;
683 }
684 }
685 KdPrint(("RR18xx [%d]: channel=%d, read look ahead enabled\n",
686 pMvSataAdapter->adapterId, channelNum));
687 }
688 else
689 {
690 KdPrint(("RR18xx [%d]: channel %d, Read Look Ahead not supported\n",
691 pMvSataAdapter->adapterId, channelNum));
692 }
693 #else
694 {
695 if (pMvSataChannel->identifyDevice[86] & 0x20)
696 {
697 KdPrint(("RR18xx [%d]:channel %d, disable read look ahead\n",
698 pMvSataAdapter->adapterId, channelNum));
699 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum,
700 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0,
701 0, 0) == MV_FALSE)
702 {
703 MV_ERROR("RR18xx [%d]:channel %d: ATA Set Features failed\n",
704 pMvSataAdapter->adapterId, channelNum);
705 return -1;
706 }
707 }
708 KdPrint(("RR18xx [%d]:channel %d, read look ahead disabled\n",
709 pMvSataAdapter->adapterId, channelNum));
710 }
711 #endif
712
713
714 {
715 KdPrint(("RR18xx [%d]: channel %d config EDMA, Non Queued Mode\n",
716 pMvSataAdapter->adapterId,
717 channelNum));
718 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum,
719 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE)
720 {
721 MV_ERROR("RR18xx [%d] channel %d Error: mvSataConfigEdmaMode failed\n",
722 pMvSataAdapter->adapterId, channelNum);
723 return -1;
724 }
725 }
726 /* Enable EDMA */
727 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE)
728 {
729 MV_ERROR("RR18xx [%d] Failed to enable DMA, channel=%d\n",
730 pMvSataAdapter->adapterId, channelNum);
731 return -1;
732 }
733 MV_ERROR("RR18xx [%d,%d]: channel started successfully\n",
734 pMvSataAdapter->adapterId, channelNum);
735
736 #ifndef FOR_DEMO
737 set_fail_led(pMvSataAdapter, channelNum, 0);
738 #endif
739 return 0;
740 }
741
742 static void
hptmv_handle_event(void * data,int flag)743 hptmv_handle_event(void * data, int flag)
744 {
745 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data;
746 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter;
747 MV_U8 channelIndex;
748
749 mtx_assert(&pAdapter->lock, MA_OWNED);
750 /* mvOsSemTake(&pMvSataAdapter->semaphore); */
751 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++)
752 {
753 switch(pAdapter->sataEvents[channelIndex])
754 {
755 case SATA_EVENT_CHANNEL_CONNECTED:
756 /* Handle only connects */
757 if (flag == 1)
758 break;
759 KdPrint(("RR18xx [%d,%d]: new device connected\n",
760 pMvSataAdapter->adapterId, channelIndex));
761 hptmv_init_channel(pAdapter, channelIndex);
762 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE)
763 {
764 MV_ERROR("RR18xx [%d,%d] Failed to configure\n",
765 pMvSataAdapter->adapterId, channelIndex);
766 hptmv_free_channel(pAdapter, channelIndex);
767 }
768 else
769 {
770 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/
771 if (start_channel( pAdapter, channelIndex))
772 {
773 MV_ERROR("RR18xx [%d,%d]Failed to start channel\n",
774 pMvSataAdapter->adapterId, channelIndex);
775 hptmv_free_channel(pAdapter, channelIndex);
776 }
777 else
778 {
779 device_change(pAdapter, channelIndex, TRUE);
780 }
781 }
782 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE;
783 break;
784
785 case SATA_EVENT_CHANNEL_DISCONNECTED:
786 /* Handle only disconnects */
787 if (flag == 0)
788 break;
789 KdPrint(("RR18xx [%d,%d]: device disconnected\n",
790 pMvSataAdapter->adapterId, channelIndex));
791 /* Flush pending commands */
792 if(pMvSataAdapter->sataChannel[channelIndex])
793 {
794 _VBUS_INST(&pAdapter->VBus)
795 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex,
796 MV_FLUSH_TYPE_CALLBACK);
797 CheckPendingCall(_VBUS_P0);
798 mvSataRemoveChannel(pMvSataAdapter,channelIndex);
799 hptmv_free_channel(pAdapter, channelIndex);
800 pMvSataAdapter->sataChannel[channelIndex] = NULL;
801 KdPrint(("RR18xx [%d,%d]: channel removed\n",
802 pMvSataAdapter->adapterId, channelIndex));
803 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
804 Check_Idle_Call(pAdapter);
805 }
806 else
807 {
808 KdPrint(("RR18xx [%d,%d]: channel already removed!!\n",
809 pMvSataAdapter->adapterId, channelIndex));
810 }
811 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE;
812 break;
813
814 case SATA_EVENT_NO_CHANGE:
815 break;
816
817 default:
818 break;
819 }
820 }
821 /* mvOsSemRelease(&pMvSataAdapter->semaphore); */
822 }
823
824 #define EVENT_CONNECT 1
825 #define EVENT_DISCONNECT 0
826
827 static void
hptmv_handle_event_connect(void * data)828 hptmv_handle_event_connect(void *data)
829 {
830 hptmv_handle_event (data, 0);
831 }
832
833 static void
hptmv_handle_event_disconnect(void * data)834 hptmv_handle_event_disconnect(void *data)
835 {
836 hptmv_handle_event (data, 1);
837 }
838
839 static MV_BOOLEAN
hptmv_event_notify(MV_SATA_ADAPTER * pMvSataAdapter,MV_EVENT_TYPE eventType,MV_U32 param1,MV_U32 param2)840 hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType,
841 MV_U32 param1, MV_U32 param2)
842 {
843 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData;
844
845 switch (eventType)
846 {
847 case MV_EVENT_TYPE_SATA_CABLE:
848 {
849 MV_U8 channel = param2;
850
851 if (param1 == EVENT_CONNECT)
852 {
853 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED;
854 KdPrint(("RR18xx [%d,%d]: device connected event received\n",
855 pMvSataAdapter->adapterId, channel));
856 /* Delete previous timers (if multiple drives connected in the same time */
857 callout_reset(&pAdapter->event_timer_connect, 10 * hz, hptmv_handle_event_connect, pAdapter);
858 }
859 else if (param1 == EVENT_DISCONNECT)
860 {
861 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED;
862 KdPrint(("RR18xx [%d,%d]: device disconnected event received \n",
863 pMvSataAdapter->adapterId, channel));
864 device_change(pAdapter, channel, FALSE);
865 /* Delete previous timers (if multiple drives disconnected in the same time */
866 /*callout_reset(&pAdapter->event_timer_disconnect, 10 * hz, hptmv_handle_event_disconnect, pAdapter); */
867 /*It is not necessary to wait, handle it directly*/
868 hptmv_handle_event_disconnect(pAdapter);
869 }
870 else
871 {
872
873 MV_ERROR("RR18xx: illegal value for param1(%d) at "
874 "connect/disconnect event, host=%d\n", param1,
875 pMvSataAdapter->adapterId );
876
877 }
878 }
879 break;
880 case MV_EVENT_TYPE_ADAPTER_ERROR:
881 KdPrint(("RR18xx: DEVICE error event received, pci cause "
882 "reg=%x, don't how to handle this\n", param1));
883 return MV_TRUE;
884 default:
885 MV_ERROR("RR18xx[%d]: unknown event type (%d)\n",
886 pMvSataAdapter->adapterId, eventType);
887 return MV_FALSE;
888 }
889 return MV_TRUE;
890 }
891
892 static int
hptmv_allocate_edma_queues(IAL_ADAPTER_T * pAdapter)893 hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter)
894 {
895 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE,
896 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
897 if (pAdapter->requestsArrayBaseAddr == NULL)
898 {
899 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA request"
900 " queues\n", pAdapter->mvSataAdapter.adapterId);
901 return -1;
902 }
903 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr);
904 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr;
905 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
906 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *)
907 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1));
908 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr;
909 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE;
910 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1);
911
912 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) !=
913 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr))
914 {
915 MV_ERROR("RR18xx[%d]: Error in Request Quueues Alignment\n",
916 pAdapter->mvSataAdapter.adapterId);
917 free(pAdapter->requestsArrayBaseAddr, M_DEVBUF);
918 return -1;
919 }
920 /* response queues */
921 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE,
922 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
923 if (pAdapter->responsesArrayBaseAddr == NULL)
924 {
925 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA response"
926 " queues\n", pAdapter->mvSataAdapter.adapterId);
927 free(pAdapter->requestsArrayBaseAddr, M_DEVBUF);
928 return -1;
929 }
930 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr);
931 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr;
932 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
933 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *)
934 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1));
935 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr;
936 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE;
937 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1);
938
939 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) !=
940 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr))
941 {
942 MV_ERROR("RR18xx[%d]: Error in Response Queues Alignment\n",
943 pAdapter->mvSataAdapter.adapterId);
944 free(pAdapter->requestsArrayBaseAddr, M_DEVBUF);
945 free(pAdapter->responsesArrayBaseAddr, M_DEVBUF);
946 return -1;
947 }
948 return 0;
949 }
950
951 static void
hptmv_free_edma_queues(IAL_ADAPTER_T * pAdapter)952 hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter)
953 {
954 free(pAdapter->requestsArrayBaseAddr, M_DEVBUF);
955 free(pAdapter->responsesArrayBaseAddr, M_DEVBUF);
956 }
957
958 static PVOID
AllocatePRDTable(IAL_ADAPTER_T * pAdapter)959 AllocatePRDTable(IAL_ADAPTER_T *pAdapter)
960 {
961 PVOID ret;
962 if (pAdapter->pFreePRDLink) {
963 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink));
964 ret = pAdapter->pFreePRDLink;
965 pAdapter->pFreePRDLink = *(void**)ret;
966 return ret;
967 }
968 return NULL;
969 }
970
971 static void
FreePRDTable(IAL_ADAPTER_T * pAdapter,PVOID PRDTable)972 FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable)
973 {
974 *(void**)PRDTable = pAdapter->pFreePRDLink;
975 pAdapter->pFreePRDLink = PRDTable;
976 }
977
978 extern PVDevice fGetFirstChild(PVDevice pLogical);
979 extern void fResetBootMark(PVDevice pLogical);
980 static void
fRegisterVdevice(IAL_ADAPTER_T * pAdapter)981 fRegisterVdevice(IAL_ADAPTER_T *pAdapter)
982 {
983 PVDevice pPhysical, pLogical;
984 PVBus pVBus;
985 int i,j;
986
987 for (i = 0; i < MV_SATA_CHANNELS_NUM; i++) {
988 pPhysical = &(pAdapter->VDevices[i]);
989 pLogical = pPhysical;
990 while (pLogical->pParent) pLogical = pLogical->pParent;
991 if (pLogical->vf_online==0) {
992 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0;
993 continue;
994 }
995 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical))
996 continue;
997
998 pVBus = &pAdapter->VBus;
999 if(pVBus)
1000 {
1001 j=0;
1002 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++;
1003 if(j<MAX_VDEVICE_PER_VBUS){
1004 pVBus->pVDevice[j] = pLogical;
1005 pLogical->pVBus = pVBus;
1006
1007 if (j>0 && pLogical->vf_bootmark) {
1008 if (pVBus->pVDevice[0]->vf_bootmark) {
1009 fResetBootMark(pLogical);
1010 }
1011 else {
1012 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j);
1013 pVBus->pVDevice[0] = pLogical;
1014 }
1015 }
1016 }
1017 }
1018 }
1019 }
1020
1021 PVDevice
GetSpareDisk(_VBUS_ARG PVDevice pArray)1022 GetSpareDisk(_VBUS_ARG PVDevice pArray)
1023 {
1024 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt;
1025 LBA_T capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1);
1026 LBA_T thiscap, maxcap = MAX_LBA_T;
1027 PVDevice pVDevice, pFind = NULL;
1028 int i;
1029
1030 for (i=0; i < MV_SATA_CHANNELS_NUM; i++) {
1031 pVDevice = &pAdapter->VDevices[i];
1032 if(!pVDevice)
1033 continue;
1034 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity;
1035 /* find the smallest usable spare disk */
1036 if (pVDevice->VDeviceType==VD_SPARE &&
1037 pVDevice->u.disk.df_on_line &&
1038 thiscap < maxcap &&
1039 thiscap >= capacity)
1040 {
1041 maxcap = pVDevice->VDeviceCapacity;
1042 pFind = pVDevice;
1043 }
1044 }
1045 return pFind;
1046 }
1047
1048 /******************************************************************
1049 * IO ATA Command
1050 *******************************************************************/
1051 int HPTLIBAPI
fDeReadWrite(PDevice pDev,ULONG Lba,UCHAR Cmd,void * tmpBuffer)1052 fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer)
1053 {
1054 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer);
1055 }
1056
fDeSelectMode(PDevice pDev,UCHAR NewMode)1057 void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode)
1058 {
1059 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1060 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1061 MV_U8 channelIndex = pSataChannel->channelNumber;
1062 UCHAR mvMode;
1063 /* 508x don't use MW-DMA? */
1064 if (NewMode>4 && NewMode<8) NewMode = 4;
1065 pDev->bDeModeSetting = NewMode;
1066 if (NewMode<=4)
1067 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode;
1068 else
1069 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8);
1070
1071 /*To fix 88i8030 bug*/
1072 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4)
1073 mvMode = MV_ATA_TRANSFER_UDMA_0;
1074
1075 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1076 /* Flush pending commands */
1077 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE);
1078
1079 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1080 MV_ATA_SET_FEATURES_TRANSFER,
1081 mvMode, 0, 0, 0) == MV_FALSE)
1082 {
1083 KdPrint(("channel %d: Set Features failed\n", channelIndex));
1084 }
1085 /* Enable EDMA */
1086 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE)
1087 KdPrint(("Failed to enable DMA, channel=%d", channelIndex));
1088 }
1089
fDeSetTCQ(PDevice pDev,int enable,int depth)1090 int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth)
1091 {
1092 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1093 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1094 MV_U8 channelIndex = pSataChannel->channelNumber;
1095 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1096 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1097 int dmaActive = pSataChannel->queueCommandsEnabled;
1098 int ret = 0;
1099
1100 if (dmaActive) {
1101 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1102 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1103 }
1104
1105 if (enable) {
1106 if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED &&
1107 (pSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & (0x2))) {
1108 UCHAR depth = ((pSataChannel->identifyDevice[IDEN_QUEUE_DEPTH]) & 0x1f) + 1;
1109 channelInfo->queueDepth = (depth==32)? 31 : depth;
1110 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_QUEUED, depth);
1111 ret = 1;
1112 }
1113 }
1114 else
1115 {
1116 if (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED) {
1117 channelInfo->queueDepth = 2;
1118 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_NOT_QUEUED, 0);
1119 ret = 1;
1120 }
1121 }
1122
1123 if (dmaActive)
1124 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1125 return ret;
1126 }
1127
fDeSetNCQ(PDevice pDev,int enable,int depth)1128 int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth)
1129 {
1130 return 0;
1131 }
1132
fDeSetWriteCache(PDevice pDev,int enable)1133 int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable)
1134 {
1135 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1136 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1137 MV_U8 channelIndex = pSataChannel->channelNumber;
1138 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1139 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1140 int dmaActive = pSataChannel->queueCommandsEnabled;
1141 int ret = 0;
1142
1143 if (dmaActive) {
1144 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1145 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1146 }
1147
1148 if ((pSataChannel->identifyDevice[82] & (0x20))) {
1149 if (enable) {
1150 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1151 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 0, 0, 0))
1152 {
1153 channelInfo->writeCacheEnabled = MV_TRUE;
1154 ret = 1;
1155 }
1156 }
1157 else {
1158 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1159 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0))
1160 {
1161 channelInfo->writeCacheEnabled = MV_FALSE;
1162 ret = 1;
1163 }
1164 }
1165 }
1166
1167 if (dmaActive)
1168 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1169 return ret;
1170 }
1171
fDeSetReadAhead(PDevice pDev,int enable)1172 int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable)
1173 {
1174 MV_SATA_CHANNEL *pSataChannel = pDev->mv;
1175 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter;
1176 MV_U8 channelIndex = pSataChannel->channelNumber;
1177 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData;
1178 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]);
1179 int dmaActive = pSataChannel->queueCommandsEnabled;
1180 int ret = 0;
1181
1182 if (dmaActive) {
1183 mvSataDisableChannelDma(pSataAdapter, channelIndex);
1184 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK);
1185 }
1186
1187 if ((pSataChannel->identifyDevice[82] & (0x40))) {
1188 if (enable) {
1189 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1190 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 0, 0))
1191 {
1192 channelInfo->readAheadEnabled = MV_TRUE;
1193 ret = 1;
1194 }
1195 }
1196 else {
1197 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex,
1198 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0))
1199 {
1200 channelInfo->readAheadEnabled = MV_FALSE;
1201 ret = 1;
1202 }
1203 }
1204 }
1205
1206 if (dmaActive)
1207 mvSataEnableChannelDma(pSataAdapter,channelIndex);
1208 return ret;
1209 }
1210
1211 #ifdef SUPPORT_ARRAY
1212 #define IdeRegisterVDevice fCheckArray
1213 #else
1214 void
IdeRegisterVDevice(PDevice pDev)1215 IdeRegisterVDevice(PDevice pDev)
1216 {
1217 PVDevice pVDev = Map2pVDevice(pDev);
1218
1219 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI :
1220 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK;
1221 pVDev->vf_online = 1;
1222 pVDev->VDeviceCapacity = pDev->dDeRealCapacity;
1223 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType];
1224 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType];
1225 }
1226 #endif
1227
1228 static __inline PBUS_DMAMAP
dmamap_get(struct IALAdapter * pAdapter)1229 dmamap_get(struct IALAdapter * pAdapter)
1230 {
1231 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list;
1232 if (p)
1233 pAdapter->pbus_dmamap_list = p-> next;
1234 return p;
1235 }
1236
1237 static __inline void
dmamap_put(PBUS_DMAMAP p)1238 dmamap_put(PBUS_DMAMAP p)
1239 {
1240 p->next = p->pAdapter->pbus_dmamap_list;
1241 p->pAdapter->pbus_dmamap_list = p;
1242 }
1243
1244 static int num_adapters = 0;
1245 static int
init_adapter(IAL_ADAPTER_T * pAdapter)1246 init_adapter(IAL_ADAPTER_T *pAdapter)
1247 {
1248 PVBus _vbus_p = &pAdapter->VBus;
1249 MV_SATA_ADAPTER *pMvSataAdapter;
1250 int i, channel, rid;
1251
1252 PVDevice pVDev;
1253
1254 mtx_init(&pAdapter->lock, "hptsleeplock", NULL, MTX_DEF);
1255 callout_init_mtx(&pAdapter->event_timer_connect, &pAdapter->lock, 0);
1256 callout_init_mtx(&pAdapter->event_timer_disconnect, &pAdapter->lock, 0);
1257
1258 sx_xlock(&hptmv_list_lock);
1259 pAdapter->next = 0;
1260
1261 if(gIal_Adapter == NULL){
1262 gIal_Adapter = pAdapter;
1263 pCurAdapter = gIal_Adapter;
1264 }
1265 else {
1266 pCurAdapter->next = pAdapter;
1267 pCurAdapter = pAdapter;
1268 }
1269 sx_xunlock(&hptmv_list_lock);
1270
1271 pAdapter->outstandingCommands = 0;
1272
1273 pMvSataAdapter = &(pAdapter->mvSataAdapter);
1274 _vbus_p->OsExt = (void *)pAdapter;
1275 pMvSataAdapter->IALData = pAdapter;
1276
1277 if (bus_dma_tag_create(bus_get_dma_tag(pAdapter->hpt_dev),/* parent */
1278 4, /* alignment */
1279 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */
1280 BUS_SPACE_MAXADDR, /* lowaddr */
1281 BUS_SPACE_MAXADDR, /* highaddr */
1282 NULL, NULL, /* filter, filterarg */
1283 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */
1284 MAX_SG_DESCRIPTORS, /* nsegments */
1285 0x10000, /* maxsegsize */
1286 BUS_DMA_WAITOK, /* flags */
1287 busdma_lock_mutex, /* lockfunc */
1288 &pAdapter->lock, /* lockfuncarg */
1289 &pAdapter->io_dma_parent /* tag */))
1290 {
1291 return ENXIO;
1292 }
1293
1294
1295 if (hptmv_allocate_edma_queues(pAdapter))
1296 {
1297 MV_ERROR("RR18xx: Failed to allocate memory for EDMA queues\n");
1298 return ENOMEM;
1299 }
1300
1301 /* also map EPROM address */
1302 rid = 0x10;
1303 if (!(pAdapter->mem_res = bus_alloc_resource_any(pAdapter->hpt_dev,
1304 SYS_RES_MEMORY, &rid, RF_ACTIVE))
1305 ||
1306 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res)))
1307 {
1308 MV_ERROR("RR18xx: Failed to remap memory space\n");
1309 hptmv_free_edma_queues(pAdapter);
1310 return ENXIO;
1311 }
1312 else
1313 {
1314 KdPrint(("RR18xx: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress));
1315 }
1316
1317 pMvSataAdapter->adapterId = num_adapters++;
1318 /* get the revision ID */
1319 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1);
1320 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev);
1321
1322 /* init RR18xx */
1323 pMvSataAdapter->intCoalThre[0]= 1;
1324 pMvSataAdapter->intCoalThre[1]= 1;
1325 pMvSataAdapter->intTimeThre[0] = 1;
1326 pMvSataAdapter->intTimeThre[1] = 1;
1327 pMvSataAdapter->pciCommand = 0x0107E371;
1328 pMvSataAdapter->pciSerrMask = 0xd77fe6ul;
1329 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul;
1330 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify;
1331
1332 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE)
1333 {
1334 MV_ERROR("RR18xx[%d]: core failed to initialize the adapter\n",
1335 pMvSataAdapter->adapterId);
1336 unregister:
1337 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res);
1338 hptmv_free_edma_queues(pAdapter);
1339 return ENXIO;
1340 }
1341 pAdapter->ver_601 = pMvSataAdapter->pcbVersion;
1342
1343 #ifndef FOR_DEMO
1344 set_fail_leds(pMvSataAdapter, 0);
1345 #endif
1346
1347 /* setup command blocks */
1348 KdPrint(("Allocate command blocks\n"));
1349 _vbus_(pFreeCommands) = 0;
1350 pAdapter->pCommandBlocks =
1351 malloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT);
1352 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks));
1353 if (!pAdapter->pCommandBlocks) {
1354 MV_ERROR("insufficient memory\n");
1355 goto unregister;
1356 }
1357
1358 for (i = 0; i < MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) {
1359 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i]));
1360 }
1361
1362 /*Set up the bus_dmamap*/
1363 pAdapter->pbus_dmamap = (PBUS_DMAMAP)malloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT);
1364 if(!pAdapter->pbus_dmamap) {
1365 MV_ERROR("insufficient memory\n");
1366 free(pAdapter->pCommandBlocks, M_DEVBUF);
1367 goto unregister;
1368 }
1369
1370 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM);
1371 pAdapter->pbus_dmamap_list = 0;
1372 for (i = 0; i < MAX_QUEUE_COMM; i++) {
1373 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]);
1374 pmap->pAdapter = pAdapter;
1375 dmamap_put(pmap);
1376
1377 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) {
1378 MV_ERROR("Can not allocate dma map\n");
1379 free(pAdapter->pCommandBlocks, M_DEVBUF);
1380 free(pAdapter->pbus_dmamap, M_DEVBUF);
1381 goto unregister;
1382 }
1383 callout_init_mtx(&pmap->timeout, &pAdapter->lock, 0);
1384 }
1385 /* setup PRD Tables */
1386 KdPrint(("Allocate PRD Tables\n"));
1387 pAdapter->pFreePRDLink = 0;
1388
1389 pAdapter->prdTableAddr = (PUCHAR)contigmalloc(
1390 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul);
1391
1392 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr));
1393 if (!pAdapter->prdTableAddr) {
1394 MV_ERROR("insufficient PRD Tables\n");
1395 goto unregister;
1396 }
1397 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL);
1398 {
1399 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr;
1400 for (i = 0; i < PRD_TABLES_FOR_VBUS; i++)
1401 {
1402 /* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */
1403 FreePRDTable(pAdapter, PRDTable);
1404 PRDTable += PRD_ENTRIES_SIZE;
1405 }
1406 }
1407
1408 /* enable the adapter interrupts */
1409
1410 /* configure and start the connected channels*/
1411 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++)
1412 {
1413 pAdapter->mvChannel[channel].online = MV_FALSE;
1414 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel)
1415 == MV_TRUE)
1416 {
1417 KdPrint(("RR18xx[%d]: channel %d is connected\n",
1418 pMvSataAdapter->adapterId, channel));
1419
1420 if (hptmv_init_channel(pAdapter, channel) == 0)
1421 {
1422 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE)
1423 {
1424 MV_ERROR("RR18xx[%d]: Failed to configure channel"
1425 " %d\n",pMvSataAdapter->adapterId, channel);
1426 hptmv_free_channel(pAdapter, channel);
1427 }
1428 else
1429 {
1430 if (start_channel(pAdapter, channel))
1431 {
1432 MV_ERROR("RR18xx[%d]: Failed to start channel,"
1433 " channel=%d\n",pMvSataAdapter->adapterId,
1434 channel);
1435 hptmv_free_channel(pAdapter, channel);
1436 }
1437 pAdapter->mvChannel[channel].online = MV_TRUE;
1438 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter,
1439 channel,
1440 MV_TRUE);*/
1441 }
1442 }
1443 }
1444 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n",
1445 pAdapter->mvChannel[channel].online, channel));
1446 }
1447
1448 #ifdef SUPPORT_ARRAY
1449 for (i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) {
1450 pVDev = ArrayTables(i);
1451 mArFreeArrayTable(pVDev);
1452 }
1453 #endif
1454
1455 KdPrint(("Initialize Devices\n"));
1456 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1457 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1458 if (pMvSataChannel) {
1459 init_vdev_params(pAdapter, channel);
1460 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk);
1461 }
1462 }
1463 #ifdef SUPPORT_ARRAY
1464 CheckArrayCritical(_VBUS_P0);
1465 #endif
1466 _vbus_p->nInstances = 1;
1467 fRegisterVdevice(pAdapter);
1468
1469 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1470 pVDev = _vbus_p->pVDevice[channel];
1471 if (pVDev && pVDev->vf_online)
1472 fCheckBootable(pVDev);
1473 }
1474
1475 #if defined(SUPPORT_ARRAY) && defined(_RAID5N_)
1476 init_raid5_memory(_VBUS_P0);
1477 _vbus_(r5).enable_write_back = 1;
1478 printf("RR18xx: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled");
1479 #endif
1480
1481 mvSataUnmaskAdapterInterrupt(pMvSataAdapter);
1482 return 0;
1483 }
1484
1485 int
MvSataResetChannel(MV_SATA_ADAPTER * pMvSataAdapter,MV_U8 channel)1486 MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel)
1487 {
1488 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData;
1489
1490 mvSataDisableChannelDma(pMvSataAdapter, channel);
1491 /* Flush pending commands */
1492 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1493
1494 /* Software reset channel */
1495 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE)
1496 {
1497 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n",
1498 pMvSataAdapter->adapterId, channel);
1499 hptmv_free_channel(pAdapter, channel);
1500 return -1;
1501 }
1502
1503 /* Hardware reset channel */
1504 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE)
1505 {
1506 MV_ERROR("RR18xx [%d,%d] Failed to Hard reser the SATA channel\n",
1507 pMvSataAdapter->adapterId, channel);
1508 hptmv_free_channel(pAdapter, channel);
1509 return -1;
1510 }
1511
1512 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE)
1513 {
1514 MV_ERROR("RR18xx [%d,%d] Failed to Connect Device\n",
1515 pMvSataAdapter->adapterId, channel);
1516 hptmv_free_channel(pAdapter, channel);
1517 return -1;
1518 }else
1519 {
1520 MV_ERROR("channel %d: perform recalibrate command", channel);
1521 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel,
1522 MV_NON_UDMA_PROTOCOL_NON_DATA,
1523 MV_FALSE,
1524 NULL, /* pBuffer*/
1525 0, /* count */
1526 0, /*features*/
1527 /* sectorCount */
1528 0,
1529 0, /* lbaLow */
1530 0, /* lbaMid */
1531 /* lbaHigh */
1532 0,
1533 0, /* device */
1534 /* command */
1535 0x10))
1536 MV_ERROR("channel %d: recalibrate failed", channel);
1537
1538 /* Set transfer mode */
1539 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1540 MV_ATA_SET_FEATURES_TRANSFER,
1541 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) ||
1542 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1543 MV_ATA_SET_FEATURES_TRANSFER,
1544 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) ||
1545 (mvStorageDevATASetFeatures(pMvSataAdapter, channel,
1546 MV_ATA_SET_FEATURES_TRANSFER,
1547 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) )
1548 {
1549 MV_ERROR("channel %d: Set Features failed", channel);
1550 hptmv_free_channel(pAdapter, channel);
1551 return -1;
1552 }
1553 /* Enable EDMA */
1554 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE)
1555 {
1556 MV_ERROR("Failed to enable DMA, channel=%d", channel);
1557 hptmv_free_channel(pAdapter, channel);
1558 return -1;
1559 }
1560 }
1561 return 0;
1562 }
1563
1564 static int
fResetActiveCommands(PVBus _vbus_p)1565 fResetActiveCommands(PVBus _vbus_p)
1566 {
1567 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1568 MV_U8 channel;
1569 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1570 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands)
1571 MvSataResetChannel(pMvSataAdapter,channel);
1572 }
1573 return 0;
1574 }
1575
fCompleteAllCommandsSynchronously(PVBus _vbus_p)1576 void fCompleteAllCommandsSynchronously(PVBus _vbus_p)
1577 {
1578 UINT cont;
1579 ULONG ticks = 0;
1580 MV_U8 channel;
1581 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter;
1582 MV_SATA_CHANNEL *pMvSataChannel;
1583
1584 do {
1585 check_cmds:
1586 cont = 0;
1587 CheckPendingCall(_VBUS_P0);
1588 #ifdef _RAID5N_
1589 dataxfer_poll();
1590 xor_poll();
1591 #endif
1592 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) {
1593 pMvSataChannel = pMvSataAdapter->sataChannel[channel];
1594 if (pMvSataChannel && pMvSataChannel->outstandingCommands)
1595 {
1596 while (pMvSataChannel->outstandingCommands) {
1597 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) {
1598 StallExec(1000);
1599 if (ticks++ > 3000) {
1600 MvSataResetChannel(pMvSataAdapter,channel);
1601 goto check_cmds;
1602 }
1603 }
1604 else
1605 ticks = 0;
1606 }
1607 cont = 1;
1608 }
1609 }
1610 } while (cont);
1611 }
1612
1613 void
fResetVBus(_VBUS_ARG0)1614 fResetVBus(_VBUS_ARG0)
1615 {
1616 KdPrint(("fMvResetBus(%p)", _vbus_p));
1617
1618 /* some commands may already finished. */
1619 CheckPendingCall(_VBUS_P0);
1620
1621 fResetActiveCommands(_vbus_p);
1622 /*
1623 * the other pending commands may still be finished successfully.
1624 */
1625 fCompleteAllCommandsSynchronously(_vbus_p);
1626
1627 /* Now there should be no pending commands. No more action needed. */
1628 CheckIdleCall(_VBUS_P0);
1629
1630 KdPrint(("fMvResetBus() done"));
1631 }
1632
1633 /*No rescan function*/
1634 void
fRescanAllDevice(_VBUS_ARG0)1635 fRescanAllDevice(_VBUS_ARG0)
1636 {
1637 }
1638
1639 static MV_BOOLEAN
CommandCompletionCB(MV_SATA_ADAPTER * pMvSataAdapter,MV_U8 channelNum,MV_COMPLETION_TYPE comp_type,MV_VOID_PTR commandId,MV_U16 responseFlags,MV_U32 timeStamp,MV_STORAGE_DEVICE_REGISTERS * registerStruct)1640 CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter,
1641 MV_U8 channelNum,
1642 MV_COMPLETION_TYPE comp_type,
1643 MV_VOID_PTR commandId,
1644 MV_U16 responseFlags,
1645 MV_U32 timeStamp,
1646 MV_STORAGE_DEVICE_REGISTERS *registerStruct)
1647 {
1648 PCommand pCmd = (PCommand) commandId;
1649 _VBUS_INST(pCmd->pVDevice->pVBus)
1650
1651 if (pCmd->uScratch.sata_param.prdAddr)
1652 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr);
1653
1654 switch (comp_type)
1655 {
1656 case MV_COMPLETION_TYPE_NORMAL:
1657 pCmd->Result = RETURN_SUCCESS;
1658 break;
1659 case MV_COMPLETION_TYPE_ABORT:
1660 pCmd->Result = RETURN_BUS_RESET;
1661 break;
1662 case MV_COMPLETION_TYPE_ERROR:
1663 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n",
1664 pMvSataAdapter->adapterId, channelNum, responseFlags);
1665
1666 if (responseFlags & 4) {
1667 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x,"
1668 " LBA high %x, device %x, status %x\n",
1669 registerStruct->errorRegister,
1670 registerStruct->sectorCountRegister,
1671 registerStruct->lbaLowRegister,
1672 registerStruct->lbaMidRegister,
1673 registerStruct->lbaHighRegister,
1674 registerStruct->deviceRegister,
1675 registerStruct->statusRegister);
1676 }
1677 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by
1678 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/
1679 pCmd->uScratch.sata_param.responseFlags = responseFlags;
1680 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister;
1681 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister;
1682 pCmd->pVDevice->u.disk.QueueLength--;
1683 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd);
1684 return TRUE;
1685
1686 default:
1687 MV_ERROR(" Unknown completion type (%d)\n", comp_type);
1688 return MV_FALSE;
1689 }
1690
1691 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) {
1692 pCmd->uScratch.sata_param.cmd_priv --;
1693 return TRUE;
1694 }
1695 pCmd->pVDevice->u.disk.QueueLength--;
1696 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1697 return TRUE;
1698 }
1699
1700 void
fDeviceSendCommand(_VBUS_ARG PCommand pCmd)1701 fDeviceSendCommand(_VBUS_ARG PCommand pCmd)
1702 {
1703 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0;
1704 MV_SATA_ADAPTER *pMvSataAdapter;
1705 MV_SATA_CHANNEL *pMvSataChannel;
1706 PVDevice pVDevice = pCmd->pVDevice;
1707 PDevice pDevice = &pVDevice->u.disk;
1708 LBA_T Lba = pCmd->uCmd.Ide.Lba;
1709 USHORT nSector = pCmd->uCmd.Ide.nSectors;
1710
1711 MV_QUEUE_COMMAND_RESULT result;
1712 MV_QUEUE_COMMAND_INFO commandInfo;
1713 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand;
1714 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand;
1715
1716 MV_BOOLEAN is48bit;
1717 MV_U8 channel;
1718 int i = 0;
1719
1720 DECLARE_BUFFER(FPSCAT_GATH, tmpSg);
1721
1722 if (!pDevice->df_on_line) {
1723 MV_ERROR("Device is offline");
1724 pCmd->Result = RETURN_BAD_DEVICE;
1725 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1726 return;
1727 }
1728
1729 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors;
1730 pMvSataChannel = pDevice->mv;
1731 pMvSataAdapter = pMvSataChannel->mvSataAdapter;
1732 channel = pMvSataChannel->channelNumber;
1733
1734 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */
1735 Lba += pDevice->dDeHiddenLba;
1736 /* check LBA */
1737 if (Lba+nSector-1 > pDevice->dDeRealCapacity) {
1738 pCmd->Result = RETURN_INVALID_REQUEST;
1739 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1740 return;
1741 }
1742
1743 /*
1744 * always use 48bit LBA if drive supports it.
1745 * Some Seagate drives report error if you use a 28-bit command
1746 * to access sector 0xfffffff.
1747 */
1748 is48bit = pMvSataChannel->lba48Address;
1749
1750 switch (pCmd->uCmd.Ide.Command)
1751 {
1752 case IDE_COMMAND_READ:
1753 case IDE_COMMAND_WRITE:
1754 if (pDevice->bDeModeSetting<8) goto pio;
1755
1756 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA;
1757 pUdmaParams->isEXT = is48bit;
1758 pUdmaParams->numOfSectors = nSector;
1759 pUdmaParams->lowLBAAddress = Lba;
1760 pUdmaParams->highLBAAddress = 0;
1761 pUdmaParams->prdHighAddr = 0;
1762 pUdmaParams->callBack = CommandCompletionCB;
1763 pUdmaParams->commandId = (MV_VOID_PTR )pCmd;
1764 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ)
1765 pUdmaParams->readWrite = MV_UDMA_TYPE_READ;
1766 else
1767 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE;
1768
1769 if (pCmd->pSgTable && pCmd->cf_physical_sg) {
1770 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1771 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1772 }
1773 else {
1774 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) {
1775 pio:
1776 mvSataDisableChannelDma(pMvSataAdapter, channel);
1777 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK);
1778
1779 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) {
1780 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable;
1781 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0);
1782 }
1783 else {
1784 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) {
1785 pCmd->Result = RETURN_NEED_LOGICAL_SG;
1786 goto finish_cmd;
1787 }
1788 }
1789
1790 do {
1791 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000;
1792 ULONG_PTR addr = tmpSg->dSgAddress;
1793 if (size & 0x1ff) {
1794 pCmd->Result = RETURN_INVALID_REQUEST;
1795 goto finish_cmd;
1796 }
1797 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel,
1798 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN,
1799 is48bit,
1800 (MV_U16_PTR)addr,
1801 size >> 1, /* count */
1802 0, /* features N/A */
1803 (MV_U16)(size>>9), /*sector count*/
1804 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/
1805 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */
1806 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */
1807 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */
1808 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command)
1809 )==MV_FALSE)
1810 {
1811 pCmd->Result = RETURN_IDE_ERROR;
1812 goto finish_cmd;
1813 }
1814 Lba += size>>9;
1815 if(Lba & 0xF0000000) is48bit = MV_TRUE;
1816 }
1817 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1818 pCmd->Result = RETURN_SUCCESS;
1819 finish_cmd:
1820 mvSataEnableChannelDma(pMvSataAdapter,channel);
1821 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1822 return;
1823 }
1824 }
1825
1826 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData);
1827 KdPrint(("pPRDTable:%p\n",pPRDTable));
1828 if (!pPRDTable) {
1829 pCmd->Result = RETURN_DEVICE_BUSY;
1830 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1831 HPT_ASSERT(0);
1832 return;
1833 }
1834
1835 do{
1836 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0);
1837 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag;
1838 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize;
1839 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress;
1840 pPRDTable[i].reserved = 0;
1841 i++;
1842 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0);
1843
1844 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable);
1845 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) {
1846 pUdmaParams->numOfSectors = 0;
1847 }
1848
1849 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable;
1850
1851 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1852
1853 if (result != MV_QUEUE_COMMAND_RESULT_OK)
1854 {
1855 queue_failed:
1856 switch (result)
1857 {
1858 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS:
1859 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA "
1860 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress);
1861 pCmd->Result = RETURN_IDE_ERROR;
1862 break;
1863 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED:
1864 MV_ERROR("IAL Error: Edma Queue command failed. EDMA"
1865 " disabled adapter %d channel %d\n",
1866 pMvSataAdapter->adapterId, channel);
1867 mvSataEnableChannelDma(pMvSataAdapter,channel);
1868 pCmd->Result = RETURN_IDE_ERROR;
1869 break;
1870 case MV_QUEUE_COMMAND_RESULT_FULL:
1871 MV_ERROR("IAL Error: Edma Queue command failed. Queue is"
1872 " Full adapter %d channel %d\n",
1873 pMvSataAdapter->adapterId, channel);
1874 pCmd->Result = RETURN_DEVICE_BUSY;
1875 break;
1876 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS:
1877 MV_ERROR("IAL Error: Edma Queue command failed. (Bad "
1878 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n",
1879 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]);
1880 pCmd->Result = RETURN_IDE_ERROR;
1881 break;
1882 default:
1883 MV_ERROR("IAL Error: Bad result value (%d) from queue"
1884 " command\n", result);
1885 pCmd->Result = RETURN_IDE_ERROR;
1886 }
1887 if(pPRDTable)
1888 FreePRDTable(pMvSataAdapter->IALData,pPRDTable);
1889 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1890 }
1891 pDevice->QueueLength++;
1892 return;
1893
1894 case IDE_COMMAND_VERIFY:
1895 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA;
1896 pNoUdmaParams->bufPtr = NULL;
1897 pNoUdmaParams->callBack = CommandCompletionCB;
1898 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd;
1899 pNoUdmaParams->count = 0;
1900 pNoUdmaParams->features = 0;
1901 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA;
1902
1903 pCmd->uScratch.sata_param.cmd_priv = 1;
1904 if (pMvSataChannel->lba48Address == MV_TRUE){
1905 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT;
1906 pNoUdmaParams->isEXT = MV_TRUE;
1907 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1908 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1909 pNoUdmaParams->lbaLow =
1910 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff));
1911 pNoUdmaParams->sectorCount = nSector;
1912 pNoUdmaParams->device = 0x40;
1913 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1914 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1915 goto queue_failed;
1916 }
1917 return;
1918 }
1919 else{
1920 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS;
1921 pNoUdmaParams->isEXT = MV_FALSE;
1922 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16);
1923 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8);
1924 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff);
1925 pNoUdmaParams->sectorCount = 0xff & nSector;
1926 pNoUdmaParams->device = (MV_U8)(0x40 |
1927 ((Lba & 0xf000000) >> 24));
1928 pNoUdmaParams->callBack = CommandCompletionCB;
1929 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo);
1930 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/
1931 if (result != MV_QUEUE_COMMAND_RESULT_OK){
1932 goto queue_failed;
1933 }
1934 }
1935 break;
1936 default:
1937 pCmd->Result = RETURN_INVALID_REQUEST;
1938 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd);
1939 break;
1940 }
1941 }
1942
1943 /**********************************************************
1944 *
1945 * Probe the hostadapter.
1946 *
1947 **********************************************************/
1948 static int
hpt_probe(device_t dev)1949 hpt_probe(device_t dev)
1950 {
1951 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) &&
1952 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081
1953 #ifdef FOR_DEMO
1954 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080
1955 #endif
1956 ))
1957 {
1958 KdPrintI((CONTROLLER_NAME " found\n"));
1959 device_set_desc(dev, CONTROLLER_NAME);
1960 return (BUS_PROBE_DEFAULT);
1961 }
1962 else
1963 return(ENXIO);
1964 }
1965
1966 /***********************************************************
1967 *
1968 * Auto configuration: attach and init a host adapter.
1969 *
1970 ***********************************************************/
1971 static int
hpt_attach(device_t dev)1972 hpt_attach(device_t dev)
1973 {
1974 IAL_ADAPTER_T * pAdapter = device_get_softc(dev);
1975 int rid;
1976 union ccb *ccb;
1977 struct cam_devq *devq;
1978 struct cam_sim *hpt_vsim;
1979
1980 device_printf(dev, "%s Version %s \n", DRIVER_NAME, DRIVER_VERSION);
1981
1982 pAdapter->hpt_dev = dev;
1983
1984 rid = init_adapter(pAdapter);
1985 if (rid)
1986 return rid;
1987
1988 rid = 0;
1989 if ((pAdapter->hpt_irq = bus_alloc_resource_any(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE)) == NULL)
1990 {
1991 hpt_printk(("can't allocate interrupt\n"));
1992 return(ENXIO);
1993 }
1994
1995 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq,
1996 INTR_TYPE_CAM | INTR_MPSAFE,
1997 NULL, hpt_intr, pAdapter, &pAdapter->hpt_intr))
1998 {
1999 hpt_printk(("can't set up interrupt\n"));
2000 free(pAdapter, M_DEVBUF);
2001 return(ENXIO);
2002 }
2003
2004
2005 ccb = xpt_alloc_ccb();
2006 ccb->ccb_h.pinfo.priority = 1;
2007 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX;
2008
2009 /*
2010 * Create the device queue for our SIM(s).
2011 */
2012 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL)
2013 {
2014 KdPrint(("ENXIO\n"));
2015 return ENOMEM;
2016 }
2017
2018 /*
2019 * Construct our SIM entry
2020 */
2021 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME),
2022 pAdapter, device_get_unit(pAdapter->hpt_dev),
2023 &pAdapter->lock, 1, 8, devq);
2024 if (hpt_vsim == NULL) {
2025 cam_simq_free(devq);
2026 return ENOMEM;
2027 }
2028
2029 mtx_lock(&pAdapter->lock);
2030 if (xpt_bus_register(hpt_vsim, dev, 0) != CAM_SUCCESS)
2031 {
2032 cam_sim_free(hpt_vsim, /*free devq*/ TRUE);
2033 mtx_unlock(&pAdapter->lock);
2034 hpt_vsim = NULL;
2035 return ENXIO;
2036 }
2037
2038 if(xpt_create_path(&pAdapter->path, /*periph */ NULL,
2039 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD,
2040 CAM_LUN_WILDCARD) != CAM_REQ_CMP)
2041 {
2042 xpt_bus_deregister(cam_sim_path(hpt_vsim));
2043 cam_sim_free(hpt_vsim, /*free_devq*/TRUE);
2044 mtx_unlock(&pAdapter->lock);
2045 hpt_vsim = NULL;
2046 return ENXIO;
2047 }
2048 mtx_unlock(&pAdapter->lock);
2049
2050 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5);
2051 ccb->ccb_h.func_code = XPT_SASYNC_CB;
2052 ccb->csa.event_enable = AC_LOST_DEVICE;
2053 ccb->csa.callback = hpt_async;
2054 ccb->csa.callback_arg = hpt_vsim;
2055 xpt_action((union ccb *)ccb);
2056 xpt_free_ccb(ccb);
2057
2058 if (device_get_unit(dev) == 0) {
2059 /* Start the work thread. XXX */
2060 launch_worker_thread();
2061 }
2062
2063 return 0;
2064 }
2065
2066 static int
hpt_detach(device_t dev)2067 hpt_detach(device_t dev)
2068 {
2069 return (EBUSY);
2070 }
2071
2072
2073 /***************************************************************
2074 * The poll function is used to simulate the interrupt when
2075 * the interrupt subsystem is not functioning.
2076 *
2077 ***************************************************************/
2078 static void
hpt_poll(struct cam_sim * sim)2079 hpt_poll(struct cam_sim *sim)
2080 {
2081
2082 hpt_intr_locked((void *)cam_sim_softc(sim));
2083 }
2084
2085 /****************************************************************
2086 * Name: hpt_intr
2087 * Description: Interrupt handler.
2088 ****************************************************************/
2089 static void
hpt_intr(void * arg)2090 hpt_intr(void *arg)
2091 {
2092 IAL_ADAPTER_T *pAdapter;
2093
2094 pAdapter = arg;
2095 mtx_lock(&pAdapter->lock);
2096 hpt_intr_locked(pAdapter);
2097 mtx_unlock(&pAdapter->lock);
2098 }
2099
2100 static void
hpt_intr_locked(IAL_ADAPTER_T * pAdapter)2101 hpt_intr_locked(IAL_ADAPTER_T *pAdapter)
2102 {
2103
2104 mtx_assert(&pAdapter->lock, MA_OWNED);
2105 /* KdPrintI(("----- Entering Isr() -----\n")); */
2106 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE)
2107 {
2108 _VBUS_INST(&pAdapter->VBus)
2109 CheckPendingCall(_VBUS_P0);
2110 }
2111
2112 /* KdPrintI(("----- Leaving Isr() -----\n")); */
2113 }
2114
2115 /**********************************************************
2116 * Asynchronous Events
2117 *********************************************************/
2118 #if (!defined(UNREFERENCED_PARAMETER))
2119 #define UNREFERENCED_PARAMETER(x) (void)(x)
2120 #endif
2121
2122 static void
hpt_async(void * callback_arg,u_int32_t code,struct cam_path * path,void * arg)2123 hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path,
2124 void * arg)
2125 {
2126 /* debug XXXX */
2127 panic("Here");
2128 UNREFERENCED_PARAMETER(callback_arg);
2129 UNREFERENCED_PARAMETER(code);
2130 UNREFERENCED_PARAMETER(path);
2131 UNREFERENCED_PARAMETER(arg);
2132
2133 }
2134
2135 static void
FlushAdapter(IAL_ADAPTER_T * pAdapter)2136 FlushAdapter(IAL_ADAPTER_T *pAdapter)
2137 {
2138 int i;
2139
2140 hpt_printk(("flush all devices\n"));
2141
2142 /* flush all devices */
2143 for (i = 0; i < MAX_VDEVICE_PER_VBUS; i++) {
2144 PVDevice pVDev = pAdapter->VBus.pVDevice[i];
2145 if(pVDev) fFlushVDev(pVDev);
2146 }
2147 }
2148
2149 static int
hpt_shutdown(device_t dev)2150 hpt_shutdown(device_t dev)
2151 {
2152 IAL_ADAPTER_T *pAdapter;
2153
2154 pAdapter = device_get_softc(dev);
2155
2156 mtx_lock(&pAdapter->lock);
2157 FlushAdapter(pAdapter);
2158 mtx_unlock(&pAdapter->lock);
2159 /* give the flush some time to happen,
2160 *otherwise "shutdown -p now" will make file system corrupted */
2161 DELAY(1000 * 1000 * 5);
2162 return 0;
2163 }
2164
2165 void
Check_Idle_Call(IAL_ADAPTER_T * pAdapter)2166 Check_Idle_Call(IAL_ADAPTER_T *pAdapter)
2167 {
2168 _VBUS_INST(&pAdapter->VBus)
2169
2170 if (mWaitingForIdle(_VBUS_P0)) {
2171 CheckIdleCall(_VBUS_P0);
2172 #ifdef SUPPORT_ARRAY
2173 {
2174 int i;
2175 PVDevice pArray;
2176 for (i = 0; i < MAX_ARRAY_PER_VBUS; i++) {
2177 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2178 continue;
2179 else if (pArray->u.array.rf_auto_rebuild) {
2180 KdPrint(("auto rebuild.\n"));
2181 pArray->u.array.rf_auto_rebuild = 0;
2182 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE);
2183 }
2184 }
2185 }
2186 #endif
2187 }
2188 /* launch the awaiting commands blocked by mWaitingForIdle */
2189 while(pAdapter->pending_Q!= NULL)
2190 {
2191 _VBUS_INST(&pAdapter->VBus)
2192 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr;
2193 hpt_free_ccb(&pAdapter->pending_Q, ccb);
2194 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb);
2195 }
2196 }
2197
2198 static void
ccb_done(union ccb * ccb)2199 ccb_done(union ccb *ccb)
2200 {
2201 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2202 IAL_ADAPTER_T * pAdapter = pmap->pAdapter;
2203 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status));
2204
2205 dmamap_put(pmap);
2206 xpt_done(ccb);
2207
2208 pAdapter->outstandingCommands--;
2209
2210 if (pAdapter->outstandingCommands == 0)
2211 {
2212 if(DPC_Request_Nums == 0)
2213 Check_Idle_Call(pAdapter);
2214 wakeup(pAdapter);
2215 }
2216 }
2217
2218 /****************************************************************
2219 * Name: hpt_action
2220 * Description: Process a queued command from the CAM layer.
2221 * Parameters: sim - Pointer to SIM object
2222 * ccb - Pointer to SCSI command structure.
2223 ****************************************************************/
2224
2225 void
hpt_action(struct cam_sim * sim,union ccb * ccb)2226 hpt_action(struct cam_sim *sim, union ccb *ccb)
2227 {
2228 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim);
2229 PBUS_DMAMAP pmap;
2230 _VBUS_INST(&pAdapter->VBus)
2231
2232 mtx_assert(&pAdapter->lock, MA_OWNED);
2233 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n"));
2234 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code));
2235
2236 switch (ccb->ccb_h.func_code)
2237 {
2238 case XPT_SCSI_IO: /* Execute the requested I/O operation */
2239 {
2240 /* ccb->ccb_h.path_id is not our bus id - don't check it */
2241
2242 if (ccb->ccb_h.target_lun) {
2243 ccb->ccb_h.status = CAM_LUN_INVALID;
2244 xpt_done(ccb);
2245 return;
2246 }
2247 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS ||
2248 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) {
2249 ccb->ccb_h.status = CAM_TID_INVALID;
2250 xpt_done(ccb);
2251 return;
2252 }
2253
2254 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0)
2255 Check_Idle_Call(pAdapter);
2256
2257 pmap = dmamap_get(pAdapter);
2258 HPT_ASSERT(pmap);
2259 ccb->ccb_adapter = pmap;
2260 memset((void *)pmap->psg, 0, sizeof(pmap->psg));
2261
2262 if (mWaitingForIdle(_VBUS_P0))
2263 hpt_queue_ccb(&pAdapter->pending_Q, ccb);
2264 else
2265 OsSendCommand(_VBUS_P ccb);
2266
2267 /* KdPrint(("leave scsiio\n")); */
2268 break;
2269 }
2270
2271 case XPT_RESET_BUS:
2272 KdPrint(("reset bus\n"));
2273 fResetVBus(_VBUS_P0);
2274 xpt_done(ccb);
2275 break;
2276
2277 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2278 case XPT_ABORT: /* Abort the specified CCB */
2279 case XPT_TERM_IO: /* Terminate the I/O process */
2280 /* XXX Implement */
2281 ccb->ccb_h.status = CAM_REQ_INVALID;
2282 xpt_done(ccb);
2283 break;
2284
2285 case XPT_GET_TRAN_SETTINGS:
2286 case XPT_SET_TRAN_SETTINGS:
2287 /* XXX Implement */
2288 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
2289 xpt_done(ccb);
2290 break;
2291
2292 case XPT_CALC_GEOMETRY:
2293 cam_calc_geometry(&ccb->ccg, 1);
2294 xpt_done(ccb);
2295 break;
2296
2297 case XPT_PATH_INQ: /* Path routing inquiry */
2298 {
2299 struct ccb_pathinq *cpi = &ccb->cpi;
2300
2301 cpi->version_num = 1; /* XXX??? */
2302 cpi->hba_inquiry = PI_SDTR_ABLE;
2303 cpi->target_sprt = 0;
2304 /* Not necessary to reset bus */
2305 cpi->hba_misc = PIM_NOBUSRESET;
2306 cpi->hba_eng_cnt = 0;
2307
2308 cpi->max_target = MAX_VDEVICE_PER_VBUS;
2309 cpi->max_lun = 0;
2310 cpi->initiator_id = MAX_VDEVICE_PER_VBUS;
2311
2312 cpi->bus_id = cam_sim_bus(sim);
2313 cpi->base_transfer_speed = 3300;
2314 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2315 strlcpy(cpi->hba_vid, "HPT ", HBA_IDLEN);
2316 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2317 cpi->unit_number = cam_sim_unit(sim);
2318 cpi->transport = XPORT_SPI;
2319 cpi->transport_version = 2;
2320 cpi->protocol = PROTO_SCSI;
2321 cpi->protocol_version = SCSI_REV_2;
2322 cpi->ccb_h.status = CAM_REQ_CMP;
2323 xpt_done(ccb);
2324 break;
2325 }
2326
2327 default:
2328 KdPrint(("invalid cmd\n"));
2329 ccb->ccb_h.status = CAM_REQ_INVALID;
2330 xpt_done(ccb);
2331 break;
2332 }
2333 /* KdPrint(("leave hpt_action..............\n")); */
2334 }
2335
2336 /* shall be called at lock_driver() */
2337 static void
hpt_queue_ccb(union ccb ** ccb_Q,union ccb * ccb)2338 hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb)
2339 {
2340 if(*ccb_Q == NULL)
2341 ccb->ccb_h.ccb_ccb_ptr = ccb;
2342 else {
2343 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr;
2344 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb;
2345 }
2346
2347 *ccb_Q = ccb;
2348 }
2349
2350 /* shall be called at lock_driver() */
2351 static void
hpt_free_ccb(union ccb ** ccb_Q,union ccb * ccb)2352 hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb)
2353 {
2354 union ccb *TempCCB;
2355
2356 TempCCB = *ccb_Q;
2357
2358 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/
2359 *ccb_Q = NULL;
2360 else {
2361 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb)
2362 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr;
2363
2364 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr;
2365
2366 if(*ccb_Q == ccb)
2367 *ccb_Q = TempCCB;
2368 }
2369 }
2370
2371 #ifdef SUPPORT_ARRAY
2372 /***************************************************************************
2373 * Function: hpt_worker_thread
2374 * Description: Do background rebuilding. Execute in kernel thread context.
2375 * Returns: None
2376 ***************************************************************************/
hpt_worker_thread(void)2377 static void hpt_worker_thread(void)
2378 {
2379
2380 for (;;) {
2381 mtx_lock(&DpcQueue_Lock);
2382 while (DpcQueue_First!=DpcQueue_Last) {
2383 ST_HPT_DPC p;
2384 p = DpcQueue[DpcQueue_First];
2385 DpcQueue_First++;
2386 DpcQueue_First %= MAX_DPC;
2387 DPC_Request_Nums++;
2388 mtx_unlock(&DpcQueue_Lock);
2389 p.dpc(p.pAdapter, p.arg, p.flags);
2390
2391 mtx_lock(&p.pAdapter->lock);
2392 mtx_lock(&DpcQueue_Lock);
2393 DPC_Request_Nums--;
2394 /* since we may have prevented Check_Idle_Call, do it here */
2395 if (DPC_Request_Nums==0) {
2396 if (p.pAdapter->outstandingCommands == 0) {
2397 _VBUS_INST(&p.pAdapter->VBus);
2398 Check_Idle_Call(p.pAdapter);
2399 CheckPendingCall(_VBUS_P0);
2400 }
2401 }
2402 mtx_unlock(&p.pAdapter->lock);
2403 mtx_unlock(&DpcQueue_Lock);
2404
2405 /*Schedule out*/
2406 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) {
2407 /* abort rebuilding process. */
2408 IAL_ADAPTER_T *pAdapter;
2409 PVDevice pArray;
2410 PVBus _vbus_p;
2411 int i;
2412
2413 sx_slock(&hptmv_list_lock);
2414 pAdapter = gIal_Adapter;
2415
2416 while(pAdapter != NULL){
2417 mtx_lock(&pAdapter->lock);
2418 _vbus_p = &pAdapter->VBus;
2419
2420 for (i = 0; i < MAX_ARRAY_PER_VBUS; i++)
2421 {
2422 if ((pArray=ArrayTables(i))->u.array.dArStamp==0)
2423 continue;
2424 else if (pArray->u.array.rf_rebuilding ||
2425 pArray->u.array.rf_verifying ||
2426 pArray->u.array.rf_initializing)
2427 {
2428 pArray->u.array.rf_abort_rebuild = 1;
2429 }
2430 }
2431 mtx_unlock(&pAdapter->lock);
2432 pAdapter = pAdapter->next;
2433 }
2434 sx_sunlock(&hptmv_list_lock);
2435 }
2436 mtx_lock(&DpcQueue_Lock);
2437 }
2438 mtx_unlock(&DpcQueue_Lock);
2439
2440 /*Remove this debug option*/
2441 /*
2442 #ifdef DEBUG
2443 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP))
2444 pause("hptrdy", 2*hz);
2445 #endif
2446 */
2447 kproc_suspend_check(curproc);
2448 pause("-", 2*hz); /* wait for something to do */
2449 }
2450 }
2451
2452 static struct proc *hptdaemonproc;
2453 static struct kproc_desc hpt_kp = {
2454 "hpt_wt",
2455 hpt_worker_thread,
2456 &hptdaemonproc
2457 };
2458
2459 /*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/
2460 static void
launch_worker_thread(void)2461 launch_worker_thread(void)
2462 {
2463 IAL_ADAPTER_T *pAdapTemp;
2464
2465 kproc_start(&hpt_kp);
2466
2467 sx_slock(&hptmv_list_lock);
2468 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) {
2469
2470 _VBUS_INST(&pAdapTemp->VBus)
2471 int i;
2472 PVDevice pVDev;
2473
2474 for (i = 0; i < MAX_ARRAY_PER_VBUS; i++)
2475 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0)
2476 continue;
2477 else{
2478 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding)
2479 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev,
2480 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY));
2481 }
2482 }
2483 sx_sunlock(&hptmv_list_lock);
2484
2485 /*
2486 * hpt_worker_thread needs to be suspended after shutdown sync, when fs sync finished.
2487 */
2488 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown, hptdaemonproc,
2489 SHUTDOWN_PRI_LAST);
2490 }
2491 /*
2492 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL);
2493 */
2494
2495 #endif
2496
2497 /********************************************************************************/
2498
fOsBuildSgl(_VBUS_ARG PCommand pCmd,FPSCAT_GATH pSg,int logical)2499 int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical)
2500 {
2501 union ccb *ccb = (union ccb *)pCmd->pOrgCommand;
2502
2503 if (logical) {
2504 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr;
2505 pSg->wSgSize = ccb->csio.dxfer_len;
2506 pSg->wSgFlag = SG_FLAG_EOT;
2507 return TRUE;
2508 }
2509 /* since we have provided physical sg, nobody will ask us to build physical sg */
2510 HPT_ASSERT(0);
2511 return FALSE;
2512 }
2513
2514 /*******************************************************************************/
2515 ULONG HPTLIBAPI
GetStamp(void)2516 GetStamp(void)
2517 {
2518 /*
2519 * the system variable, ticks, can't be used since it hasn't yet been active
2520 * when our driver starts (ticks==0, it's a invalid stamp value)
2521 */
2522 ULONG stamp;
2523 do { stamp = random(); } while (stamp==0);
2524 return stamp;
2525 }
2526
2527
2528 static void
SetInquiryData(PINQUIRYDATA inquiryData,PVDevice pVDev)2529 SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev)
2530 {
2531 int i;
2532 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice;
2533
2534 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/
2535 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5);
2536 #ifndef SERIAL_CMDS
2537 inquiryData->CommandQueue = 1;
2538 #endif
2539
2540 switch(pVDev->VDeviceType) {
2541 case VD_SINGLE_DISK:
2542 case VD_ATAPI:
2543 case VD_REMOVABLE:
2544 /* Set the removable bit, if applicable. */
2545 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80))
2546 inquiryData->RemovableMedia = 1;
2547
2548 /* Fill in vendor identification fields. */
2549 for (i = 0; i < 20; i += 2) {
2550 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1];
2551 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i];
2552
2553 }
2554
2555 /* Initialize unused portion of product id. */
2556 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' ';
2557
2558 /* firmware revision */
2559 for (i = 0; i < 4; i += 2)
2560 {
2561 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1];
2562 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i];
2563 }
2564 break;
2565 default:
2566 memcpy(&inquiryData->VendorId, "RR18xx ", 8);
2567 #ifdef SUPPORT_ARRAY
2568 switch(pVDev->VDeviceType){
2569 case VD_RAID_0:
2570 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) ||
2571 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1])))
2572 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16);
2573 else
2574 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16);
2575 break;
2576 case VD_RAID_1:
2577 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) ||
2578 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1])))
2579 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16);
2580 else
2581 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16);
2582 break;
2583 case VD_RAID_5:
2584 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16);
2585 break;
2586 case VD_JBOD:
2587 memcpy(&inquiryData->ProductId, "JBOD Array ", 16);
2588 break;
2589 }
2590 #endif
2591 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4);
2592 break;
2593 }
2594 }
2595
2596 static void
hpt_timeout(void * arg)2597 hpt_timeout(void *arg)
2598 {
2599 PBUS_DMAMAP pmap = (PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter;
2600 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2601 _VBUS_INST(&pAdapter->VBus)
2602
2603 mtx_assert(&pAdapter->lock, MA_OWNED);
2604 fResetVBus(_VBUS_P0);
2605 }
2606
2607 static void
hpt_io_dmamap_callback(void * arg,bus_dma_segment_t * segs,int nsegs,int error)2608 hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2609 {
2610 PCommand pCmd = (PCommand)arg;
2611 union ccb *ccb = pCmd->pOrgCommand;
2612 struct ccb_hdr *ccb_h = &ccb->ccb_h;
2613 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter;
2614 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2615 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2616 FPSCAT_GATH psg = pCmd->pSgTable;
2617 int idx;
2618 _VBUS_INST(pVDev->pVBus)
2619
2620 HPT_ASSERT(pCmd->cf_physical_sg);
2621
2622 if (error)
2623 panic("busdma error");
2624
2625 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS);
2626
2627 if (nsegs != 0) {
2628 for (idx = 0; idx < nsegs; idx++, psg++) {
2629 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr;
2630 psg->wSgSize = segs[idx].ds_len;
2631 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0;
2632 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */
2633 }
2634 /* psg[-1].wSgFlag = SG_FLAG_EOT; */
2635
2636 if (pCmd->cf_data_in) {
2637 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map,
2638 BUS_DMASYNC_PREREAD);
2639 }
2640 else if (pCmd->cf_data_out) {
2641 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map,
2642 BUS_DMASYNC_PREWRITE);
2643 }
2644 }
2645
2646 callout_reset(&pmap->timeout, 20 * hz, hpt_timeout, ccb);
2647 pVDev->pfnSendCommand(_VBUS_P pCmd);
2648 CheckPendingCall(_VBUS_P0);
2649 }
2650
2651
2652
2653 static void HPTLIBAPI
OsSendCommand(_VBUS_ARG union ccb * ccb)2654 OsSendCommand(_VBUS_ARG union ccb *ccb)
2655 {
2656 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2657 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2658 struct ccb_hdr *ccb_h = &ccb->ccb_h;
2659 struct ccb_scsiio *csio = &ccb->csio;
2660 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id];
2661
2662 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n",
2663 ccb,
2664 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0],
2665 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4],
2666 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8]
2667 ));
2668
2669 pAdapter->outstandingCommands++;
2670
2671 if (pVDev == NULL || pVDev->vf_online == 0) {
2672 ccb->ccb_h.status = CAM_REQ_INVALID;
2673 ccb_done(ccb);
2674 goto Command_Complished;
2675 }
2676
2677 switch(ccb->csio.cdb_io.cdb_bytes[0])
2678 {
2679 case TEST_UNIT_READY:
2680 case START_STOP_UNIT:
2681 case SYNCHRONIZE_CACHE:
2682 /* FALLTHROUGH */
2683 ccb->ccb_h.status = CAM_REQ_CMP;
2684 break;
2685
2686 case INQUIRY:
2687 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len);
2688 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev);
2689 ccb_h->status = CAM_REQ_CMP;
2690 break;
2691
2692 case READ_CAPACITY:
2693 {
2694 UCHAR *rbuf=csio->data_ptr;
2695 unsigned int cap;
2696
2697 if (pVDev->VDeviceCapacity > 0xfffffffful) {
2698 cap = 0xfffffffful;
2699 } else {
2700 cap = pVDev->VDeviceCapacity - 1;
2701 }
2702
2703 rbuf[0] = (UCHAR)(cap>>24);
2704 rbuf[1] = (UCHAR)(cap>>16);
2705 rbuf[2] = (UCHAR)(cap>>8);
2706 rbuf[3] = (UCHAR)cap;
2707 /* Claim 512 byte blocks (big-endian). */
2708 rbuf[4] = 0;
2709 rbuf[5] = 0;
2710 rbuf[6] = 2;
2711 rbuf[7] = 0;
2712
2713 ccb_h->status = CAM_REQ_CMP;
2714 break;
2715 }
2716
2717 case 0x9e: /*SERVICE_ACTION_IN*/
2718 {
2719 UCHAR *rbuf = csio->data_ptr;
2720 LBA_T cap = pVDev->VDeviceCapacity - 1;
2721
2722 rbuf[0] = (UCHAR)(cap>>56);
2723 rbuf[1] = (UCHAR)(cap>>48);
2724 rbuf[2] = (UCHAR)(cap>>40);
2725 rbuf[3] = (UCHAR)(cap>>32);
2726 rbuf[4] = (UCHAR)(cap>>24);
2727 rbuf[5] = (UCHAR)(cap>>16);
2728 rbuf[6] = (UCHAR)(cap>>8);
2729 rbuf[7] = (UCHAR)cap;
2730 rbuf[8] = 0;
2731 rbuf[9] = 0;
2732 rbuf[10] = 2;
2733 rbuf[11] = 0;
2734
2735 ccb_h->status = CAM_REQ_CMP;
2736 break;
2737 }
2738
2739 case READ_6:
2740 case WRITE_6:
2741 case READ_10:
2742 case WRITE_10:
2743 case 0x88: /* READ_16 */
2744 case 0x8a: /* WRITE_16 */
2745 case 0x13:
2746 case 0x2f:
2747 {
2748 UCHAR Cdb[16];
2749 UCHAR CdbLength;
2750 _VBUS_INST(pVDev->pVBus)
2751 PCommand pCmd = AllocateCommand(_VBUS_P0);
2752 int error;
2753 HPT_ASSERT(pCmd);
2754
2755 CdbLength = csio->cdb_len;
2756 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0)
2757 {
2758 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0)
2759 {
2760 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength);
2761 }
2762 else
2763 {
2764 KdPrintE(("ERROR!!!\n"));
2765 ccb->ccb_h.status = CAM_REQ_INVALID;
2766 break;
2767 }
2768 }
2769 else
2770 {
2771 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength);
2772 }
2773
2774 pCmd->pOrgCommand = ccb;
2775 pCmd->pVDevice = pVDev;
2776 pCmd->pfnCompletion = fOsCommandDone;
2777 pCmd->pfnBuildSgl = fOsBuildSgl;
2778 pCmd->pSgTable = pmap->psg;
2779
2780 switch (Cdb[0])
2781 {
2782 case READ_6:
2783 case WRITE_6:
2784 case 0x13:
2785 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3];
2786 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4];
2787 break;
2788
2789 case 0x88: /* READ_16 */
2790 case 0x8a: /* WRITE_16 */
2791 pCmd->uCmd.Ide.Lba =
2792 (HPT_U64)Cdb[2] << 56 |
2793 (HPT_U64)Cdb[3] << 48 |
2794 (HPT_U64)Cdb[4] << 40 |
2795 (HPT_U64)Cdb[5] << 32 |
2796 (HPT_U64)Cdb[6] << 24 |
2797 (HPT_U64)Cdb[7] << 16 |
2798 (HPT_U64)Cdb[8] << 8 |
2799 (HPT_U64)Cdb[9];
2800 pCmd->uCmd.Ide.nSectors = (USHORT)Cdb[12] << 8 | (USHORT)Cdb[13];
2801 break;
2802
2803 default:
2804 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24);
2805 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8);
2806 break;
2807 }
2808
2809 switch (Cdb[0])
2810 {
2811 case READ_6:
2812 case READ_10:
2813 case 0x88: /* READ_16 */
2814 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ;
2815 pCmd->cf_data_in = 1;
2816 break;
2817
2818 case WRITE_6:
2819 case WRITE_10:
2820 case 0x8a: /* WRITE_16 */
2821 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE;
2822 pCmd->cf_data_out = 1;
2823 break;
2824 case 0x13:
2825 case 0x2f:
2826 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY;
2827 break;
2828 }
2829 /*///////////////////////// */
2830 pCmd->cf_physical_sg = 1;
2831 error = bus_dmamap_load_ccb(pAdapter->io_dma_parent,
2832 pmap->dma_map,
2833 ccb,
2834 hpt_io_dmamap_callback,
2835 pCmd, BUS_DMA_WAITOK
2836 );
2837 KdPrint(("bus_dmamap_load return %d\n", error));
2838 if (error && error!=EINPROGRESS) {
2839 hpt_printk(("bus_dmamap_load error %d\n", error));
2840 FreeCommand(_VBUS_P pCmd);
2841 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
2842 dmamap_put(pmap);
2843 pAdapter->outstandingCommands--;
2844 if (pAdapter->outstandingCommands == 0)
2845 wakeup(pAdapter);
2846 xpt_done(ccb);
2847 }
2848 goto Command_Complished;
2849 }
2850
2851 default:
2852 ccb->ccb_h.status = CAM_REQ_INVALID;
2853 break;
2854 }
2855 ccb_done(ccb);
2856 Command_Complished:
2857 CheckPendingCall(_VBUS_P0);
2858 return;
2859 }
2860
2861 static void HPTLIBAPI
fOsCommandDone(_VBUS_ARG PCommand pCmd)2862 fOsCommandDone(_VBUS_ARG PCommand pCmd)
2863 {
2864 union ccb *ccb = pCmd->pOrgCommand;
2865 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter;
2866 IAL_ADAPTER_T *pAdapter = pmap->pAdapter;
2867
2868 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result));
2869
2870 callout_stop(&pmap->timeout);
2871
2872 switch(pCmd->Result) {
2873 case RETURN_SUCCESS:
2874 ccb->ccb_h.status = CAM_REQ_CMP;
2875 break;
2876 case RETURN_BAD_DEVICE:
2877 ccb->ccb_h.status = CAM_DEV_NOT_THERE;
2878 break;
2879 case RETURN_DEVICE_BUSY:
2880 ccb->ccb_h.status = CAM_BUSY;
2881 break;
2882 case RETURN_INVALID_REQUEST:
2883 ccb->ccb_h.status = CAM_REQ_INVALID;
2884 break;
2885 case RETURN_SELECTION_TIMEOUT:
2886 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2887 break;
2888 case RETURN_RETRY:
2889 ccb->ccb_h.status = CAM_BUSY;
2890 break;
2891 default:
2892 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
2893 break;
2894 }
2895
2896 if (pCmd->cf_data_in) {
2897 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD);
2898 }
2899 else if (pCmd->cf_data_out) {
2900 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE);
2901 }
2902
2903 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map);
2904
2905 FreeCommand(_VBUS_P pCmd);
2906 ccb_done(ccb);
2907 }
2908
2909 int
hpt_queue_dpc(HPT_DPC dpc,IAL_ADAPTER_T * pAdapter,void * arg,UCHAR flags)2910 hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags)
2911 {
2912 int p;
2913
2914 mtx_lock(&DpcQueue_Lock);
2915 p = (DpcQueue_Last + 1) % MAX_DPC;
2916 if (p==DpcQueue_First) {
2917 KdPrint(("DPC Queue full!\n"));
2918 mtx_unlock(&DpcQueue_Lock);
2919 return -1;
2920 }
2921
2922 DpcQueue[DpcQueue_Last].dpc = dpc;
2923 DpcQueue[DpcQueue_Last].pAdapter = pAdapter;
2924 DpcQueue[DpcQueue_Last].arg = arg;
2925 DpcQueue[DpcQueue_Last].flags = flags;
2926 DpcQueue_Last = p;
2927 mtx_unlock(&DpcQueue_Lock);
2928
2929 return 0;
2930 }
2931
2932 #ifdef _RAID5N_
2933 /*
2934 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices.
2935 * How about the memory for 5081 request/response array and PRD table?
2936 */
2937 void
os_alloc_page(_VBUS_ARG0)2938 *os_alloc_page(_VBUS_ARG0)
2939 {
2940 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul);
2941 }
2942
2943 void
os_alloc_dma_page(_VBUS_ARG0)2944 *os_alloc_dma_page(_VBUS_ARG0)
2945 {
2946 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul);
2947 }
2948
2949 void
os_free_page(_VBUS_ARG void * p)2950 os_free_page(_VBUS_ARG void *p)
2951 {
2952 free(p, M_DEVBUF);
2953 }
2954
2955 void
os_free_dma_page(_VBUS_ARG void * p)2956 os_free_dma_page(_VBUS_ARG void *p)
2957 {
2958 free(p, M_DEVBUF);
2959 }
2960
2961 void
DoXor1(ULONG * p0,ULONG * p1,ULONG * p2,UINT nBytes)2962 DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes)
2963 {
2964 UINT i;
2965 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++;
2966 }
2967
2968 void
DoXor2(ULONG * p0,ULONG * p2,UINT nBytes)2969 DoXor2(ULONG *p0, ULONG *p2, UINT nBytes)
2970 {
2971 UINT i;
2972 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++;
2973 }
2974 #endif
2975