1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 1995, David Greenman
5 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 */
31
32 #include <sys/cdefs.h>
33 /*
34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
35 */
36
37 #ifdef HAVE_KERNEL_OPTION_HEADERS
38 #include "opt_device_polling.h"
39 #endif
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/bus.h>
44 #include <sys/endian.h>
45 #include <sys/kernel.h>
46 #include <sys/mbuf.h>
47 #include <sys/lock.h>
48 #include <sys/malloc.h>
49 #include <sys/module.h>
50 #include <sys/mutex.h>
51 #include <sys/rman.h>
52 #include <sys/socket.h>
53 #include <sys/sockio.h>
54 #include <sys/sysctl.h>
55
56 #include <net/bpf.h>
57 #include <net/ethernet.h>
58 #include <net/if.h>
59 #include <net/if_var.h>
60 #include <net/if_arp.h>
61 #include <net/if_dl.h>
62 #include <net/if_media.h>
63 #include <net/if_types.h>
64 #include <net/if_vlan_var.h>
65
66 #include <netinet/in.h>
67 #include <netinet/in_systm.h>
68 #include <netinet/ip.h>
69 #include <netinet/tcp.h>
70 #include <netinet/udp.h>
71
72 #include <machine/bus.h>
73 #include <machine/in_cksum.h>
74 #include <machine/resource.h>
75
76 #include <dev/pci/pcivar.h>
77 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */
78
79 #include <dev/mii/mii.h>
80 #include <dev/mii/miivar.h>
81
82 #include <dev/fxp/if_fxpreg.h>
83 #include <dev/fxp/if_fxpvar.h>
84 #include <dev/fxp/rcvbundl.h>
85
86 MODULE_DEPEND(fxp, pci, 1, 1, 1);
87 MODULE_DEPEND(fxp, ether, 1, 1, 1);
88 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
89 #include "miibus_if.h"
90
91 /*
92 * NOTE! On !x86 we typically have an alignment constraint. The
93 * card DMAs the packet immediately following the RFA. However,
94 * the first thing in the packet is a 14-byte Ethernet header.
95 * This means that the packet is misaligned. To compensate,
96 * we actually offset the RFA 2 bytes into the cluster. This
97 * alignes the packet after the Ethernet header at a 32-bit
98 * boundary. HOWEVER! This means that the RFA is misaligned!
99 */
100 #define RFA_ALIGNMENT_FUDGE 2
101
102 /*
103 * Set initial transmit threshold at 64 (512 bytes). This is
104 * increased by 64 (512 bytes) at a time, to maximum of 192
105 * (1536 bytes), if an underrun occurs.
106 */
107 static int tx_threshold = 64;
108
109 /*
110 * The configuration byte map has several undefined fields which
111 * must be one or must be zero. Set up a template for these bits.
112 * The actual configuration is performed in fxp_init_body.
113 *
114 * See struct fxp_cb_config for the bit definitions.
115 */
116 static const u_char fxp_cb_config_template[] = {
117 0x0, 0x0, /* cb_status */
118 0x0, 0x0, /* cb_command */
119 0x0, 0x0, 0x0, 0x0, /* link_addr */
120 0x0, /* 0 */
121 0x0, /* 1 */
122 0x0, /* 2 */
123 0x0, /* 3 */
124 0x0, /* 4 */
125 0x0, /* 5 */
126 0x32, /* 6 */
127 0x0, /* 7 */
128 0x0, /* 8 */
129 0x0, /* 9 */
130 0x6, /* 10 */
131 0x0, /* 11 */
132 0x0, /* 12 */
133 0x0, /* 13 */
134 0xf2, /* 14 */
135 0x48, /* 15 */
136 0x0, /* 16 */
137 0x40, /* 17 */
138 0xf0, /* 18 */
139 0x0, /* 19 */
140 0x3f, /* 20 */
141 0x5, /* 21 */
142 0x0, /* 22 */
143 0x0, /* 23 */
144 0x0, /* 24 */
145 0x0, /* 25 */
146 0x0, /* 26 */
147 0x0, /* 27 */
148 0x0, /* 28 */
149 0x0, /* 29 */
150 0x0, /* 30 */
151 0x0 /* 31 */
152 };
153
154 /*
155 * Claim various Intel PCI device identifiers for this driver. The
156 * sub-vendor and sub-device field are extensively used to identify
157 * particular variants, but we don't currently differentiate between
158 * them.
159 */
160 static const struct fxp_ident fxp_ident_table[] = {
161 { 0x8086, 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" },
162 { 0x8086, 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" },
163 { 0x8086, 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
164 { 0x8086, 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
165 { 0x8086, 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
166 { 0x8086, 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
167 { 0x8086, 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
168 { 0x8086, 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
169 { 0x8086, 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
170 { 0x8086, 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
171 { 0x8086, 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
172 { 0x8086, 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
173 { 0x8086, 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
174 { 0x8086, 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
175 { 0x8086, 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
176 { 0x8086, 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
177 { 0x8086, 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
178 { 0x8086, 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
179 { 0x8086, 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" },
180 { 0x8086, 0x1064, -1, 6, "Intel 82562EZ (ICH6)" },
181 { 0x8086, 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
182 { 0x8086, 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
183 { 0x8086, 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
184 { 0x8086, 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" },
185 { 0x8086, 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" },
186 { 0x8086, 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" },
187 { 0x8086, 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" },
188 { 0x8086, 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" },
189 { 0x8086, 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" },
190 { 0x8086, 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" },
191 { 0x8086, 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" },
192 { 0x8086, 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" },
193 { 0x8086, 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" },
194 { 0x8086, 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" },
195 { 0x8086, 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" },
196 { 0x8086, 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" },
197 { 0x8086, 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" },
198 { 0x8086, 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" },
199 { 0x8086, 0x1229, 0x0d, 0, "Intel 82550C Pro/100 Ethernet" },
200 { 0x8086, 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" },
201 { 0x8086, 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" },
202 { 0x8086, 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" },
203 { 0x8086, 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" },
204 { 0x8086, 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
205 { 0x8086, 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" },
206 { 0, 0, -1, 0, NULL },
207 };
208
209 #ifdef FXP_IP_CSUM_WAR
210 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
211 #else
212 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
213 #endif
214
215 static int fxp_probe(device_t dev);
216 static int fxp_attach(device_t dev);
217 static int fxp_detach(device_t dev);
218 static int fxp_shutdown(device_t dev);
219 static int fxp_suspend(device_t dev);
220 static int fxp_resume(device_t dev);
221
222 static const struct fxp_ident *fxp_find_ident(device_t dev);
223 static void fxp_intr(void *xsc);
224 static void fxp_rxcsum(struct fxp_softc *sc, if_t ifp,
225 struct mbuf *m, uint16_t status, int pos);
226 static int fxp_intr_body(struct fxp_softc *sc, if_t ifp,
227 uint8_t statack, int count);
228 static void fxp_init(void *xsc);
229 static void fxp_init_body(struct fxp_softc *sc, int);
230 static void fxp_tick(void *xsc);
231 static void fxp_start(if_t ifp);
232 static void fxp_start_body(if_t ifp);
233 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head);
234 static void fxp_txeof(struct fxp_softc *sc);
235 static void fxp_stop(struct fxp_softc *sc);
236 static void fxp_release(struct fxp_softc *sc);
237 static int fxp_ioctl(if_t ifp, u_long command,
238 caddr_t data);
239 static void fxp_watchdog(struct fxp_softc *sc);
240 static void fxp_add_rfabuf(struct fxp_softc *sc,
241 struct fxp_rx *rxp);
242 static void fxp_discard_rfabuf(struct fxp_softc *sc,
243 struct fxp_rx *rxp);
244 static int fxp_new_rfabuf(struct fxp_softc *sc,
245 struct fxp_rx *rxp);
246 static void fxp_mc_addrs(struct fxp_softc *sc);
247 static void fxp_mc_setup(struct fxp_softc *sc);
248 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
249 int autosize);
250 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
251 uint16_t data);
252 static void fxp_autosize_eeprom(struct fxp_softc *sc);
253 static void fxp_load_eeprom(struct fxp_softc *sc);
254 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
255 int offset, int words);
256 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
257 int offset, int words);
258 static int fxp_ifmedia_upd(if_t ifp);
259 static void fxp_ifmedia_sts(if_t ifp,
260 struct ifmediareq *ifmr);
261 static int fxp_serial_ifmedia_upd(if_t ifp);
262 static void fxp_serial_ifmedia_sts(if_t ifp,
263 struct ifmediareq *ifmr);
264 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
265 static int fxp_miibus_writereg(device_t dev, int phy, int reg,
266 int value);
267 static void fxp_miibus_statchg(device_t dev);
268 static void fxp_load_ucode(struct fxp_softc *sc);
269 static void fxp_update_stats(struct fxp_softc *sc);
270 static void fxp_sysctl_node(struct fxp_softc *sc);
271 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
272 int low, int high);
273 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
274 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
275 static void fxp_scb_wait(struct fxp_softc *sc);
276 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
277 static void fxp_dma_wait(struct fxp_softc *sc,
278 volatile uint16_t *status, bus_dma_tag_t dmat,
279 bus_dmamap_t map);
280
281 static device_method_t fxp_methods[] = {
282 /* Device interface */
283 DEVMETHOD(device_probe, fxp_probe),
284 DEVMETHOD(device_attach, fxp_attach),
285 DEVMETHOD(device_detach, fxp_detach),
286 DEVMETHOD(device_shutdown, fxp_shutdown),
287 DEVMETHOD(device_suspend, fxp_suspend),
288 DEVMETHOD(device_resume, fxp_resume),
289
290 /* MII interface */
291 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
292 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
293 DEVMETHOD(miibus_statchg, fxp_miibus_statchg),
294
295 DEVMETHOD_END
296 };
297
298 static driver_t fxp_driver = {
299 "fxp",
300 fxp_methods,
301 sizeof(struct fxp_softc),
302 };
303
304 DRIVER_MODULE_ORDERED(fxp, pci, fxp_driver, NULL, NULL, SI_ORDER_ANY);
305 MODULE_PNP_INFO("U16:vendor;U16:device", pci, fxp, fxp_ident_table,
306 nitems(fxp_ident_table) - 1);
307 DRIVER_MODULE(miibus, fxp, miibus_driver, NULL, NULL);
308
309 static struct resource_spec fxp_res_spec_mem[] = {
310 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE },
311 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
312 { -1, 0 }
313 };
314
315 static struct resource_spec fxp_res_spec_io[] = {
316 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE },
317 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
318 { -1, 0 }
319 };
320
321 /*
322 * Wait for the previous command to be accepted (but not necessarily
323 * completed).
324 */
325 static void
fxp_scb_wait(struct fxp_softc * sc)326 fxp_scb_wait(struct fxp_softc *sc)
327 {
328 union {
329 uint16_t w;
330 uint8_t b[2];
331 } flowctl;
332 int i = 10000;
333
334 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
335 DELAY(2);
336 if (i == 0) {
337 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
338 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);
339 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
340 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
341 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
342 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
343 }
344 }
345
346 static void
fxp_scb_cmd(struct fxp_softc * sc,int cmd)347 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
348 {
349
350 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
351 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
352 fxp_scb_wait(sc);
353 }
354 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
355 }
356
357 static void
fxp_dma_wait(struct fxp_softc * sc,volatile uint16_t * status,bus_dma_tag_t dmat,bus_dmamap_t map)358 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status,
359 bus_dma_tag_t dmat, bus_dmamap_t map)
360 {
361 int i;
362
363 for (i = 10000; i > 0; i--) {
364 DELAY(2);
365 bus_dmamap_sync(dmat, map,
366 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
367 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0)
368 break;
369 }
370 if (i == 0)
371 device_printf(sc->dev, "DMA timeout\n");
372 }
373
374 static const struct fxp_ident *
fxp_find_ident(device_t dev)375 fxp_find_ident(device_t dev)
376 {
377 uint16_t vendor;
378 uint16_t device;
379 uint8_t revid;
380 const struct fxp_ident *ident;
381
382 vendor = pci_get_vendor(dev);
383 device = pci_get_device(dev);
384 revid = pci_get_revid(dev);
385 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
386 if (ident->vendor == vendor && ident->device == device &&
387 (ident->revid == revid || ident->revid == -1)) {
388 return (ident);
389 }
390 }
391 return (NULL);
392 }
393
394 /*
395 * Return identification string if this device is ours.
396 */
397 static int
fxp_probe(device_t dev)398 fxp_probe(device_t dev)
399 {
400 const struct fxp_ident *ident;
401
402 ident = fxp_find_ident(dev);
403 if (ident != NULL) {
404 device_set_desc(dev, ident->name);
405 return (BUS_PROBE_DEFAULT);
406 }
407 return (ENXIO);
408 }
409
410 static void
fxp_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)411 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
412 {
413 uint32_t *addr;
414
415 if (error)
416 return;
417
418 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
419 addr = arg;
420 *addr = segs->ds_addr;
421 }
422
423 static int
fxp_attach(device_t dev)424 fxp_attach(device_t dev)
425 {
426 struct fxp_softc *sc;
427 struct fxp_cb_tx *tcbp;
428 struct fxp_tx *txp;
429 struct fxp_rx *rxp;
430 if_t ifp;
431 uint32_t val;
432 uint16_t data;
433 u_char eaddr[ETHER_ADDR_LEN];
434 int error, flags, i, prefer_iomap;
435
436 error = 0;
437 sc = device_get_softc(dev);
438 sc->dev = dev;
439 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
440 MTX_DEF);
441 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
442 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
443 fxp_serial_ifmedia_sts);
444
445 ifp = sc->ifp = if_gethandle(IFT_ETHER);
446
447 /*
448 * Enable bus mastering.
449 */
450 pci_enable_busmaster(dev);
451
452 /*
453 * Figure out which we should try first - memory mapping or i/o mapping?
454 * We default to memory mapping. Then we accept an override from the
455 * command line. Then we check to see which one is enabled.
456 */
457 prefer_iomap = 0;
458 resource_int_value(device_get_name(dev), device_get_unit(dev),
459 "prefer_iomap", &prefer_iomap);
460 if (prefer_iomap)
461 sc->fxp_spec = fxp_res_spec_io;
462 else
463 sc->fxp_spec = fxp_res_spec_mem;
464
465 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
466 if (error) {
467 if (sc->fxp_spec == fxp_res_spec_mem)
468 sc->fxp_spec = fxp_res_spec_io;
469 else
470 sc->fxp_spec = fxp_res_spec_mem;
471 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
472 }
473 if (error) {
474 device_printf(dev, "could not allocate resources\n");
475 error = ENXIO;
476 goto fail;
477 }
478
479 if (bootverbose) {
480 device_printf(dev, "using %s space register mapping\n",
481 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
482 }
483
484 /*
485 * Put CU/RU idle state and prepare full reset.
486 */
487 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
488 DELAY(10);
489 /* Full reset and disable interrupts. */
490 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
491 DELAY(10);
492 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
493
494 /*
495 * Find out how large of an SEEPROM we have.
496 */
497 fxp_autosize_eeprom(sc);
498 fxp_load_eeprom(sc);
499
500 /*
501 * Find out the chip revision; lump all 82557 revs together.
502 */
503 sc->ident = fxp_find_ident(dev);
504 if (sc->ident->ich > 0) {
505 /* Assume ICH controllers are 82559. */
506 sc->revision = FXP_REV_82559_A0;
507 } else {
508 data = sc->eeprom[FXP_EEPROM_MAP_CNTR];
509 if ((data >> 8) == 1)
510 sc->revision = FXP_REV_82557;
511 else
512 sc->revision = pci_get_revid(dev);
513 }
514
515 /*
516 * Check availability of WOL. 82559ER does not support WOL.
517 */
518 if (sc->revision >= FXP_REV_82558_A4 &&
519 sc->revision != FXP_REV_82559S_A) {
520 data = sc->eeprom[FXP_EEPROM_MAP_ID];
521 if ((data & 0x20) != 0 && pci_has_pm(sc->dev))
522 sc->flags |= FXP_FLAG_WOLCAP;
523 }
524
525 if (sc->revision == FXP_REV_82550_C) {
526 /*
527 * 82550C with server extension requires microcode to
528 * receive fragmented UDP datagrams. However if the
529 * microcode is used for client-only featured 82550C
530 * it locks up controller.
531 */
532 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
533 if ((data & 0x0400) == 0)
534 sc->flags |= FXP_FLAG_NO_UCODE;
535 }
536
537 /* Receiver lock-up workaround detection. */
538 if (sc->revision < FXP_REV_82558_A4) {
539 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
540 if ((data & 0x03) != 0x03) {
541 sc->flags |= FXP_FLAG_RXBUG;
542 device_printf(dev, "Enabling Rx lock-up workaround\n");
543 }
544 }
545
546 /*
547 * Determine whether we must use the 503 serial interface.
548 */
549 data = sc->eeprom[FXP_EEPROM_MAP_PRI_PHY];
550 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
551 && (data & FXP_PHY_SERIAL_ONLY))
552 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
553
554 fxp_sysctl_node(sc);
555 /*
556 * Enable workarounds for certain chip revision deficiencies.
557 *
558 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
559 * some systems based a normal 82559 design, have a defect where
560 * the chip can cause a PCI protocol violation if it receives
561 * a CU_RESUME command when it is entering the IDLE state. The
562 * workaround is to disable Dynamic Standby Mode, so the chip never
563 * deasserts CLKRUN#, and always remains in an active state.
564 *
565 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
566 */
567 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) ||
568 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) {
569 data = sc->eeprom[FXP_EEPROM_MAP_ID];
570 if (data & 0x02) { /* STB enable */
571 uint16_t cksum;
572 int i;
573
574 device_printf(dev,
575 "Disabling dynamic standby mode in EEPROM\n");
576 data &= ~0x02;
577 sc->eeprom[FXP_EEPROM_MAP_ID] = data;
578 fxp_write_eeprom(sc, &data, FXP_EEPROM_MAP_ID, 1);
579 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
580 cksum = 0;
581 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
582 cksum += sc->eeprom[i];
583 i = (1 << sc->eeprom_size) - 1;
584 cksum = 0xBABA - cksum;
585 fxp_write_eeprom(sc, &cksum, i, 1);
586 device_printf(dev,
587 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
588 i, sc->eeprom[i], cksum);
589 sc->eeprom[i] = cksum;
590 /*
591 * If the user elects to continue, try the software
592 * workaround, as it is better than nothing.
593 */
594 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
595 }
596 }
597
598 /*
599 * If we are not a 82557 chip, we can enable extended features.
600 */
601 if (sc->revision != FXP_REV_82557) {
602 /*
603 * If MWI is enabled in the PCI configuration, and there
604 * is a valid cacheline size (8 or 16 dwords), then tell
605 * the board to turn on MWI.
606 */
607 val = pci_read_config(dev, PCIR_COMMAND, 2);
608 if (val & PCIM_CMD_MWRICEN &&
609 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
610 sc->flags |= FXP_FLAG_MWI_ENABLE;
611
612 /* turn on the extended TxCB feature */
613 sc->flags |= FXP_FLAG_EXT_TXCB;
614
615 /* enable reception of long frames for VLAN */
616 sc->flags |= FXP_FLAG_LONG_PKT_EN;
617 } else {
618 /* a hack to get long VLAN frames on a 82557 */
619 sc->flags |= FXP_FLAG_SAVE_BAD;
620 }
621
622 /* For 82559 or later chips, Rx checksum offload is supported. */
623 if (sc->revision >= FXP_REV_82559_A0) {
624 /* 82559ER does not support Rx checksum offloading. */
625 if (sc->ident->device != 0x1209)
626 sc->flags |= FXP_FLAG_82559_RXCSUM;
627 }
628 /*
629 * Enable use of extended RFDs and TCBs for 82550
630 * and later chips. Note: we need extended TXCB support
631 * too, but that's already enabled by the code above.
632 * Be careful to do this only on the right devices.
633 */
634 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C ||
635 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F
636 || sc->revision == FXP_REV_82551_10) {
637 sc->rfa_size = sizeof (struct fxp_rfa);
638 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
639 sc->flags |= FXP_FLAG_EXT_RFA;
640 /* Use extended RFA instead of 82559 checksum mode. */
641 sc->flags &= ~FXP_FLAG_82559_RXCSUM;
642 } else {
643 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
644 sc->tx_cmd = FXP_CB_COMMAND_XMIT;
645 }
646
647 /*
648 * Allocate DMA tags and DMA safe memory.
649 */
650 sc->maxtxseg = FXP_NTXSEG;
651 sc->maxsegsize = MCLBYTES;
652 if (sc->flags & FXP_FLAG_EXT_RFA) {
653 sc->maxtxseg--;
654 sc->maxsegsize = FXP_TSO_SEGSIZE;
655 }
656 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
657 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
658 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header),
659 sc->maxtxseg, sc->maxsegsize, 0, NULL, NULL, &sc->fxp_txmtag);
660 if (error) {
661 device_printf(dev, "could not create TX DMA tag\n");
662 goto fail;
663 }
664
665 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
666 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
667 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->fxp_rxmtag);
668 if (error) {
669 device_printf(dev, "could not create RX DMA tag\n");
670 goto fail;
671 }
672
673 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
674 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
675 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
676 NULL, NULL, &sc->fxp_stag);
677 if (error) {
678 device_printf(dev, "could not create stats DMA tag\n");
679 goto fail;
680 }
681
682 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
683 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap);
684 if (error) {
685 device_printf(dev, "could not allocate stats DMA memory\n");
686 goto fail;
687 }
688 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
689 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr,
690 BUS_DMA_NOWAIT);
691 if (error) {
692 device_printf(dev, "could not load the stats DMA buffer\n");
693 goto fail;
694 }
695
696 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
697 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
698 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, NULL, NULL, &sc->cbl_tag);
699 if (error) {
700 device_printf(dev, "could not create TxCB DMA tag\n");
701 goto fail;
702 }
703
704 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
705 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map);
706 if (error) {
707 device_printf(dev, "could not allocate TxCB DMA memory\n");
708 goto fail;
709 }
710
711 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
712 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
713 &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT);
714 if (error) {
715 device_printf(dev, "could not load TxCB DMA buffer\n");
716 goto fail;
717 }
718
719 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
720 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
721 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
722 NULL, NULL, &sc->mcs_tag);
723 if (error) {
724 device_printf(dev,
725 "could not create multicast setup DMA tag\n");
726 goto fail;
727 }
728
729 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
730 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map);
731 if (error) {
732 device_printf(dev,
733 "could not allocate multicast setup DMA memory\n");
734 goto fail;
735 }
736 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
737 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr,
738 BUS_DMA_NOWAIT);
739 if (error) {
740 device_printf(dev,
741 "can't load the multicast setup DMA buffer\n");
742 goto fail;
743 }
744
745 /*
746 * Pre-allocate the TX DMA maps and setup the pointers to
747 * the TX command blocks.
748 */
749 txp = sc->fxp_desc.tx_list;
750 tcbp = sc->fxp_desc.cbl_list;
751 for (i = 0; i < FXP_NTXCB; i++) {
752 txp[i].tx_cb = tcbp + i;
753 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map);
754 if (error) {
755 device_printf(dev, "can't create DMA map for TX\n");
756 goto fail;
757 }
758 }
759 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map);
760 if (error) {
761 device_printf(dev, "can't create spare DMA map\n");
762 goto fail;
763 }
764
765 /*
766 * Pre-allocate our receive buffers.
767 */
768 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
769 for (i = 0; i < FXP_NRFABUFS; i++) {
770 rxp = &sc->fxp_desc.rx_list[i];
771 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map);
772 if (error) {
773 device_printf(dev, "can't create DMA map for RX\n");
774 goto fail;
775 }
776 if (fxp_new_rfabuf(sc, rxp) != 0) {
777 error = ENOMEM;
778 goto fail;
779 }
780 fxp_add_rfabuf(sc, rxp);
781 }
782
783 /*
784 * Read MAC address.
785 */
786 eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff;
787 eaddr[1] = sc->eeprom[FXP_EEPROM_MAP_IA0] >> 8;
788 eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff;
789 eaddr[3] = sc->eeprom[FXP_EEPROM_MAP_IA1] >> 8;
790 eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff;
791 eaddr[5] = sc->eeprom[FXP_EEPROM_MAP_IA2] >> 8;
792 if (bootverbose) {
793 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
794 pci_get_vendor(dev), pci_get_device(dev),
795 pci_get_subvendor(dev), pci_get_subdevice(dev),
796 pci_get_revid(dev));
797 device_printf(dev, "Dynamic Standby mode is %s\n",
798 sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" :
799 "disabled");
800 }
801
802 /*
803 * If this is only a 10Mbps device, then there is no MII, and
804 * the PHY will use a serial interface instead.
805 *
806 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
807 * doesn't have a programming interface of any sort. The
808 * media is sensed automatically based on how the link partner
809 * is configured. This is, in essence, manual configuration.
810 */
811 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
812 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
813 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
814 } else {
815 /*
816 * i82557 wedge when isolating all of their PHYs.
817 */
818 flags = MIIF_NOISOLATE;
819 if (sc->revision >= FXP_REV_82558_A4)
820 flags |= MIIF_DOPAUSE;
821 error = mii_attach(dev, &sc->miibus, ifp,
822 (ifm_change_cb_t)fxp_ifmedia_upd,
823 (ifm_stat_cb_t)fxp_ifmedia_sts, BMSR_DEFCAPMASK,
824 MII_PHY_ANY, MII_OFFSET_ANY, flags);
825 if (error != 0) {
826 device_printf(dev, "attaching PHYs failed\n");
827 goto fail;
828 }
829 }
830
831 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
832 if_setdev(ifp, dev);
833 if_setinitfn(ifp, fxp_init);
834 if_setsoftc(ifp, sc);
835 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
836 if_setioctlfn(ifp, fxp_ioctl);
837 if_setstartfn(ifp, fxp_start);
838
839 if_setcapabilities(ifp, 0);
840 if_setcapenable(ifp, 0);
841
842 /* Enable checksum offload/TSO for 82550 or better chips */
843 if (sc->flags & FXP_FLAG_EXT_RFA) {
844 if_sethwassist(ifp, FXP_CSUM_FEATURES | CSUM_TSO);
845 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
846 if_setcapenablebit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
847 }
848
849 if (sc->flags & FXP_FLAG_82559_RXCSUM) {
850 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0);
851 if_setcapenablebit(ifp, IFCAP_RXCSUM, 0);
852 }
853
854 if (sc->flags & FXP_FLAG_WOLCAP) {
855 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0);
856 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 0);
857 }
858
859 #ifdef DEVICE_POLLING
860 /* Inform the world we support polling. */
861 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
862 #endif
863
864 /*
865 * Attach the interface.
866 */
867 ether_ifattach(ifp, eaddr);
868
869 /*
870 * Tell the upper layer(s) we support long frames.
871 * Must appear after the call to ether_ifattach() because
872 * ether_ifattach() sets ifi_hdrlen to the default value.
873 */
874 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
875 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
876 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0);
877 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
878 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING |
879 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
880 if_setcapenablebit(ifp, IFCAP_VLAN_HWTAGGING |
881 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
882 }
883
884 /*
885 * Let the system queue as many packets as we have available
886 * TX descriptors.
887 */
888 if_setsendqlen(ifp, FXP_NTXCB - 1);
889 if_setsendqready(ifp);
890
891 /*
892 * Hook our interrupt after all initialization is complete.
893 */
894 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
895 NULL, fxp_intr, sc, &sc->ih);
896 if (error) {
897 device_printf(dev, "could not setup irq\n");
898 ether_ifdetach(sc->ifp);
899 goto fail;
900 }
901
902 /*
903 * Configure hardware to reject magic frames otherwise
904 * system will hang on recipt of magic frames.
905 */
906 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
907 FXP_LOCK(sc);
908 /* Clear wakeup events. */
909 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
910 fxp_init_body(sc, 0);
911 fxp_stop(sc);
912 FXP_UNLOCK(sc);
913 }
914
915 fail:
916 if (error)
917 fxp_release(sc);
918 return (error);
919 }
920
921 /*
922 * Release all resources. The softc lock should not be held and the
923 * interrupt should already be torn down.
924 */
925 static void
fxp_release(struct fxp_softc * sc)926 fxp_release(struct fxp_softc *sc)
927 {
928 struct fxp_rx *rxp;
929 struct fxp_tx *txp;
930 int i;
931
932 FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
933 KASSERT(sc->ih == NULL,
934 ("fxp_release() called with intr handle still active"));
935 bus_generic_detach(sc->dev);
936 ifmedia_removeall(&sc->sc_media);
937 if (sc->fxp_desc.cbl_list) {
938 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
939 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
940 sc->cbl_map);
941 }
942 if (sc->fxp_stats) {
943 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
944 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
945 }
946 if (sc->mcsp) {
947 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
948 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
949 }
950 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
951 if (sc->fxp_rxmtag) {
952 for (i = 0; i < FXP_NRFABUFS; i++) {
953 rxp = &sc->fxp_desc.rx_list[i];
954 if (rxp->rx_mbuf != NULL) {
955 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
956 BUS_DMASYNC_POSTREAD);
957 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
958 m_freem(rxp->rx_mbuf);
959 }
960 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map);
961 }
962 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map);
963 bus_dma_tag_destroy(sc->fxp_rxmtag);
964 }
965 if (sc->fxp_txmtag) {
966 for (i = 0; i < FXP_NTXCB; i++) {
967 txp = &sc->fxp_desc.tx_list[i];
968 if (txp->tx_mbuf != NULL) {
969 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
970 BUS_DMASYNC_POSTWRITE);
971 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
972 m_freem(txp->tx_mbuf);
973 }
974 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map);
975 }
976 bus_dma_tag_destroy(sc->fxp_txmtag);
977 }
978 if (sc->fxp_stag)
979 bus_dma_tag_destroy(sc->fxp_stag);
980 if (sc->cbl_tag)
981 bus_dma_tag_destroy(sc->cbl_tag);
982 if (sc->mcs_tag)
983 bus_dma_tag_destroy(sc->mcs_tag);
984 if (sc->ifp)
985 if_free(sc->ifp);
986
987 mtx_destroy(&sc->sc_mtx);
988 }
989
990 /*
991 * Detach interface.
992 */
993 static int
fxp_detach(device_t dev)994 fxp_detach(device_t dev)
995 {
996 struct fxp_softc *sc = device_get_softc(dev);
997
998 #ifdef DEVICE_POLLING
999 if (if_getcapenable(sc->ifp) & IFCAP_POLLING)
1000 ether_poll_deregister(sc->ifp);
1001 #endif
1002
1003 FXP_LOCK(sc);
1004 /*
1005 * Stop DMA and drop transmit queue, but disable interrupts first.
1006 */
1007 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1008 fxp_stop(sc);
1009 FXP_UNLOCK(sc);
1010 callout_drain(&sc->stat_ch);
1011
1012 /*
1013 * Close down routes etc.
1014 */
1015 ether_ifdetach(sc->ifp);
1016
1017 /*
1018 * Unhook interrupt before dropping lock. This is to prevent
1019 * races with fxp_intr().
1020 */
1021 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
1022 sc->ih = NULL;
1023
1024 /* Release our allocated resources. */
1025 fxp_release(sc);
1026 return (0);
1027 }
1028
1029 /*
1030 * Device shutdown routine. Called at system shutdown after sync. The
1031 * main purpose of this routine is to shut off receiver DMA so that
1032 * kernel memory doesn't get clobbered during warmboot.
1033 */
1034 static int
fxp_shutdown(device_t dev)1035 fxp_shutdown(device_t dev)
1036 {
1037
1038 /*
1039 * Make sure that DMA is disabled prior to reboot. Not doing
1040 * do could allow DMA to corrupt kernel memory during the
1041 * reboot before the driver initializes.
1042 */
1043 return (fxp_suspend(dev));
1044 }
1045
1046 /*
1047 * Device suspend routine. Stop the interface and save some PCI
1048 * settings in case the BIOS doesn't restore them properly on
1049 * resume.
1050 */
1051 static int
fxp_suspend(device_t dev)1052 fxp_suspend(device_t dev)
1053 {
1054 struct fxp_softc *sc = device_get_softc(dev);
1055 if_t ifp;
1056
1057 FXP_LOCK(sc);
1058
1059 ifp = sc->ifp;
1060 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) {
1061 /* Request PME. */
1062 pci_enable_pme(sc->dev);
1063 sc->flags |= FXP_FLAG_WOL;
1064 /* Reconfigure hardware to accept magic frames. */
1065 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1066 fxp_init_body(sc, 0);
1067 }
1068 fxp_stop(sc);
1069
1070 sc->suspended = 1;
1071
1072 FXP_UNLOCK(sc);
1073 return (0);
1074 }
1075
1076 /*
1077 * Device resume routine. re-enable busmastering, and restart the interface if
1078 * appropriate.
1079 */
1080 static int
fxp_resume(device_t dev)1081 fxp_resume(device_t dev)
1082 {
1083 struct fxp_softc *sc = device_get_softc(dev);
1084 if_t ifp = sc->ifp;
1085
1086 FXP_LOCK(sc);
1087
1088 if (pci_has_pm(sc->dev)) {
1089 sc->flags &= ~FXP_FLAG_WOL;
1090 if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1091 CSR_WRITE_1(sc, FXP_CSR_PMDR,
1092 CSR_READ_1(sc, FXP_CSR_PMDR));
1093 }
1094
1095 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1096 DELAY(10);
1097
1098 /* reinitialize interface if necessary */
1099 if (if_getflags(ifp) & IFF_UP)
1100 fxp_init_body(sc, 1);
1101
1102 sc->suspended = 0;
1103
1104 FXP_UNLOCK(sc);
1105 return (0);
1106 }
1107
1108 static void
fxp_eeprom_shiftin(struct fxp_softc * sc,int data,int length)1109 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1110 {
1111 uint16_t reg;
1112 int x;
1113
1114 /*
1115 * Shift in data.
1116 */
1117 for (x = 1 << (length - 1); x; x >>= 1) {
1118 if (data & x)
1119 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1120 else
1121 reg = FXP_EEPROM_EECS;
1122 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1123 DELAY(1);
1124 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1125 DELAY(1);
1126 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1127 DELAY(1);
1128 }
1129 }
1130
1131 /*
1132 * Read from the serial EEPROM. Basically, you manually shift in
1133 * the read opcode (one bit at a time) and then shift in the address,
1134 * and then you shift out the data (all of this one bit at a time).
1135 * The word size is 16 bits, so you have to provide the address for
1136 * every 16 bits of data.
1137 */
1138 static uint16_t
fxp_eeprom_getword(struct fxp_softc * sc,int offset,int autosize)1139 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1140 {
1141 uint16_t reg, data;
1142 int x;
1143
1144 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1145 /*
1146 * Shift in read opcode.
1147 */
1148 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1149 /*
1150 * Shift in address.
1151 */
1152 data = 0;
1153 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1154 if (offset & x)
1155 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1156 else
1157 reg = FXP_EEPROM_EECS;
1158 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1159 DELAY(1);
1160 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1161 DELAY(1);
1162 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1163 DELAY(1);
1164 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1165 data++;
1166 if (autosize && reg == 0) {
1167 sc->eeprom_size = data;
1168 break;
1169 }
1170 }
1171 /*
1172 * Shift out data.
1173 */
1174 data = 0;
1175 reg = FXP_EEPROM_EECS;
1176 for (x = 1 << 15; x; x >>= 1) {
1177 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1178 DELAY(1);
1179 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1180 data |= x;
1181 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1182 DELAY(1);
1183 }
1184 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1185 DELAY(1);
1186
1187 return (data);
1188 }
1189
1190 static void
fxp_eeprom_putword(struct fxp_softc * sc,int offset,uint16_t data)1191 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1192 {
1193 int i;
1194
1195 /*
1196 * Erase/write enable.
1197 */
1198 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1199 fxp_eeprom_shiftin(sc, 0x4, 3);
1200 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1201 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1202 DELAY(1);
1203 /*
1204 * Shift in write opcode, address, data.
1205 */
1206 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1207 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1208 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1209 fxp_eeprom_shiftin(sc, data, 16);
1210 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1211 DELAY(1);
1212 /*
1213 * Wait for EEPROM to finish up.
1214 */
1215 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1216 DELAY(1);
1217 for (i = 0; i < 1000; i++) {
1218 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1219 break;
1220 DELAY(50);
1221 }
1222 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1223 DELAY(1);
1224 /*
1225 * Erase/write disable.
1226 */
1227 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1228 fxp_eeprom_shiftin(sc, 0x4, 3);
1229 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1230 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1231 DELAY(1);
1232 }
1233
1234 /*
1235 * From NetBSD:
1236 *
1237 * Figure out EEPROM size.
1238 *
1239 * 559's can have either 64-word or 256-word EEPROMs, the 558
1240 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1241 * talks about the existence of 16 to 256 word EEPROMs.
1242 *
1243 * The only known sizes are 64 and 256, where the 256 version is used
1244 * by CardBus cards to store CIS information.
1245 *
1246 * The address is shifted in msb-to-lsb, and after the last
1247 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1248 * after which follows the actual data. We try to detect this zero, by
1249 * probing the data-out bit in the EEPROM control register just after
1250 * having shifted in a bit. If the bit is zero, we assume we've
1251 * shifted enough address bits. The data-out should be tri-state,
1252 * before this, which should translate to a logical one.
1253 */
1254 static void
fxp_autosize_eeprom(struct fxp_softc * sc)1255 fxp_autosize_eeprom(struct fxp_softc *sc)
1256 {
1257
1258 /* guess maximum size of 256 words */
1259 sc->eeprom_size = 8;
1260
1261 /* autosize */
1262 (void) fxp_eeprom_getword(sc, 0, 1);
1263 }
1264
1265 static void
fxp_read_eeprom(struct fxp_softc * sc,u_short * data,int offset,int words)1266 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1267 {
1268 int i;
1269
1270 for (i = 0; i < words; i++)
1271 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1272 }
1273
1274 static void
fxp_write_eeprom(struct fxp_softc * sc,u_short * data,int offset,int words)1275 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1276 {
1277 int i;
1278
1279 for (i = 0; i < words; i++)
1280 fxp_eeprom_putword(sc, offset + i, data[i]);
1281 }
1282
1283 static void
fxp_load_eeprom(struct fxp_softc * sc)1284 fxp_load_eeprom(struct fxp_softc *sc)
1285 {
1286 int i;
1287 uint16_t cksum;
1288
1289 fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size);
1290 cksum = 0;
1291 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
1292 cksum += sc->eeprom[i];
1293 cksum = 0xBABA - cksum;
1294 if (cksum != sc->eeprom[(1 << sc->eeprom_size) - 1])
1295 device_printf(sc->dev,
1296 "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n",
1297 cksum, sc->eeprom[(1 << sc->eeprom_size) - 1]);
1298 }
1299
1300 /*
1301 * Grab the softc lock and call the real fxp_start_body() routine
1302 */
1303 static void
fxp_start(if_t ifp)1304 fxp_start(if_t ifp)
1305 {
1306 struct fxp_softc *sc = if_getsoftc(ifp);
1307
1308 FXP_LOCK(sc);
1309 fxp_start_body(ifp);
1310 FXP_UNLOCK(sc);
1311 }
1312
1313 /*
1314 * Start packet transmission on the interface.
1315 * This routine must be called with the softc lock held, and is an
1316 * internal entry point only.
1317 */
1318 static void
fxp_start_body(if_t ifp)1319 fxp_start_body(if_t ifp)
1320 {
1321 struct fxp_softc *sc = if_getsoftc(ifp);
1322 struct mbuf *mb_head;
1323 int txqueued;
1324
1325 FXP_LOCK_ASSERT(sc, MA_OWNED);
1326
1327 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1328 IFF_DRV_RUNNING)
1329 return;
1330
1331 if (sc->tx_queued > FXP_NTXCB_HIWAT)
1332 fxp_txeof(sc);
1333 /*
1334 * We're finished if there is nothing more to add to the list or if
1335 * we're all filled up with buffers to transmit.
1336 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1337 * a NOP command when needed.
1338 */
1339 txqueued = 0;
1340 while (!if_sendq_empty(ifp) && sc->tx_queued < FXP_NTXCB - 1) {
1341
1342 /*
1343 * Grab a packet to transmit.
1344 */
1345 mb_head = if_dequeue(ifp);
1346 if (mb_head == NULL)
1347 break;
1348
1349 if (fxp_encap(sc, &mb_head)) {
1350 if (mb_head == NULL)
1351 break;
1352 if_sendq_prepend(ifp, mb_head);
1353 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1354 }
1355 txqueued++;
1356 /*
1357 * Pass packet to bpf if there is a listener.
1358 */
1359 bpf_mtap_if(ifp, mb_head);
1360 }
1361
1362 /*
1363 * We're finished. If we added to the list, issue a RESUME to get DMA
1364 * going again if suspended.
1365 */
1366 if (txqueued > 0) {
1367 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1368 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1369 fxp_scb_wait(sc);
1370 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1371 /*
1372 * Set a 5 second timer just in case we don't hear
1373 * from the card again.
1374 */
1375 sc->watchdog_timer = 5;
1376 }
1377 }
1378
1379 static int
fxp_encap(struct fxp_softc * sc,struct mbuf ** m_head)1380 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head)
1381 {
1382 struct mbuf *m;
1383 struct fxp_tx *txp;
1384 struct fxp_cb_tx *cbp;
1385 struct tcphdr *tcp;
1386 bus_dma_segment_t segs[FXP_NTXSEG];
1387 int error, i, nseg, tcp_payload;
1388
1389 FXP_LOCK_ASSERT(sc, MA_OWNED);
1390
1391 tcp_payload = 0;
1392 tcp = NULL;
1393 /*
1394 * Get pointer to next available tx desc.
1395 */
1396 txp = sc->fxp_desc.tx_last->tx_next;
1397
1398 /*
1399 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1400 * Ethernet Controller Family Open Source Software
1401 * Developer Manual says:
1402 * Using software parsing is only allowed with legal
1403 * TCP/IP or UDP/IP packets.
1404 * ...
1405 * For all other datagrams, hardware parsing must
1406 * be used.
1407 * Software parsing appears to truncate ICMP and
1408 * fragmented UDP packets that contain one to three
1409 * bytes in the second (and final) mbuf of the packet.
1410 */
1411 if (sc->flags & FXP_FLAG_EXT_RFA)
1412 txp->tx_cb->ipcb_ip_activation_high =
1413 FXP_IPCB_HARDWAREPARSING_ENABLE;
1414
1415 m = *m_head;
1416 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1417 /*
1418 * 82550/82551 requires ethernet/IP/TCP headers must be
1419 * contained in the first active transmit buffer.
1420 */
1421 struct ether_header *eh;
1422 struct ip *ip;
1423 uint32_t ip_off, poff;
1424
1425 if (M_WRITABLE(*m_head) == 0) {
1426 /* Get a writable copy. */
1427 m = m_dup(*m_head, M_NOWAIT);
1428 m_freem(*m_head);
1429 if (m == NULL) {
1430 *m_head = NULL;
1431 return (ENOBUFS);
1432 }
1433 *m_head = m;
1434 }
1435 ip_off = sizeof(struct ether_header);
1436 m = m_pullup(*m_head, ip_off);
1437 if (m == NULL) {
1438 *m_head = NULL;
1439 return (ENOBUFS);
1440 }
1441 eh = mtod(m, struct ether_header *);
1442 /* Check the existence of VLAN tag. */
1443 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1444 ip_off = sizeof(struct ether_vlan_header);
1445 m = m_pullup(m, ip_off);
1446 if (m == NULL) {
1447 *m_head = NULL;
1448 return (ENOBUFS);
1449 }
1450 }
1451 m = m_pullup(m, ip_off + sizeof(struct ip));
1452 if (m == NULL) {
1453 *m_head = NULL;
1454 return (ENOBUFS);
1455 }
1456 ip = (struct ip *)(mtod(m, char *) + ip_off);
1457 poff = ip_off + (ip->ip_hl << 2);
1458 m = m_pullup(m, poff + sizeof(struct tcphdr));
1459 if (m == NULL) {
1460 *m_head = NULL;
1461 return (ENOBUFS);
1462 }
1463 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1464 m = m_pullup(m, poff + (tcp->th_off << 2));
1465 if (m == NULL) {
1466 *m_head = NULL;
1467 return (ENOBUFS);
1468 }
1469
1470 /*
1471 * Since 82550/82551 doesn't modify IP length and pseudo
1472 * checksum in the first frame driver should compute it.
1473 */
1474 ip = (struct ip *)(mtod(m, char *) + ip_off);
1475 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1476 ip->ip_sum = 0;
1477 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) +
1478 (tcp->th_off << 2));
1479 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1480 htons(IPPROTO_TCP + (tcp->th_off << 2) +
1481 m->m_pkthdr.tso_segsz));
1482 /* Compute total TCP payload. */
1483 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2);
1484 tcp_payload -= tcp->th_off << 2;
1485 *m_head = m;
1486 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) {
1487 /*
1488 * Deal with TCP/IP checksum offload. Note that
1489 * in order for TCP checksum offload to work,
1490 * the pseudo header checksum must have already
1491 * been computed and stored in the checksum field
1492 * in the TCP header. The stack should have
1493 * already done this for us.
1494 */
1495 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1496 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1497 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET;
1498
1499 #ifdef FXP_IP_CSUM_WAR
1500 /*
1501 * XXX The 82550 chip appears to have trouble
1502 * dealing with IP header checksums in very small
1503 * datagrams, namely fragments from 1 to 3 bytes
1504 * in size. For example, say you want to transmit
1505 * a UDP packet of 1473 bytes. The packet will be
1506 * fragmented over two IP datagrams, the latter
1507 * containing only one byte of data. The 82550 will
1508 * botch the header checksum on the 1-byte fragment.
1509 * As long as the datagram contains 4 or more bytes
1510 * of data, you're ok.
1511 *
1512 * The following code attempts to work around this
1513 * problem: if the datagram is less than 38 bytes
1514 * in size (14 bytes ether header, 20 bytes IP header,
1515 * plus 4 bytes of data), we punt and compute the IP
1516 * header checksum by hand. This workaround doesn't
1517 * work very well, however, since it can be fooled
1518 * by things like VLAN tags and IP options that make
1519 * the header sizes/offsets vary.
1520 */
1521
1522 if (m->m_pkthdr.csum_flags & CSUM_IP) {
1523 if (m->m_pkthdr.len < 38) {
1524 struct ip *ip;
1525 m->m_data += ETHER_HDR_LEN;
1526 ip = mtod(m, struct ip *);
1527 ip->ip_sum = in_cksum(m, ip->ip_hl << 2);
1528 m->m_data -= ETHER_HDR_LEN;
1529 m->m_pkthdr.csum_flags &= ~CSUM_IP;
1530 } else {
1531 txp->tx_cb->ipcb_ip_activation_high =
1532 FXP_IPCB_HARDWAREPARSING_ENABLE;
1533 txp->tx_cb->ipcb_ip_schedule |=
1534 FXP_IPCB_IP_CHECKSUM_ENABLE;
1535 }
1536 }
1537 #endif
1538 }
1539
1540 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head,
1541 segs, &nseg, 0);
1542 if (error == EFBIG) {
1543 m = m_collapse(*m_head, M_NOWAIT, sc->maxtxseg);
1544 if (m == NULL) {
1545 m_freem(*m_head);
1546 *m_head = NULL;
1547 return (ENOMEM);
1548 }
1549 *m_head = m;
1550 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map,
1551 *m_head, segs, &nseg, 0);
1552 if (error != 0) {
1553 m_freem(*m_head);
1554 *m_head = NULL;
1555 return (ENOMEM);
1556 }
1557 } else if (error != 0)
1558 return (error);
1559 if (nseg == 0) {
1560 m_freem(*m_head);
1561 *m_head = NULL;
1562 return (EIO);
1563 }
1564
1565 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1566 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1567
1568 cbp = txp->tx_cb;
1569 for (i = 0; i < nseg; i++) {
1570 /*
1571 * If this is an 82550/82551, then we're using extended
1572 * TxCBs _and_ we're using checksum offload. This means
1573 * that the TxCB is really an IPCB. One major difference
1574 * between the two is that with plain extended TxCBs,
1575 * the bottom half of the TxCB contains two entries from
1576 * the TBD array, whereas IPCBs contain just one entry:
1577 * one entry (8 bytes) has been sacrificed for the TCP/IP
1578 * checksum offload control bits. So to make things work
1579 * right, we have to start filling in the TBD array
1580 * starting from a different place depending on whether
1581 * the chip is an 82550/82551 or not.
1582 */
1583 if (sc->flags & FXP_FLAG_EXT_RFA) {
1584 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1585 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1586 } else {
1587 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1588 cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1589 }
1590 }
1591 if (sc->flags & FXP_FLAG_EXT_RFA) {
1592 /* Configure dynamic TBD for 82550/82551. */
1593 cbp->tbd_number = 0xFF;
1594 cbp->tbd[nseg].tb_size |= htole32(0x8000);
1595 } else
1596 cbp->tbd_number = nseg;
1597 /* Configure TSO. */
1598 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1599 cbp->tbdtso.tb_size = htole32(m->m_pkthdr.tso_segsz << 16);
1600 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16);
1601 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE |
1602 FXP_IPCB_IP_CHECKSUM_ENABLE |
1603 FXP_IPCB_TCP_PACKET |
1604 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1605 }
1606 /* Configure VLAN hardware tag insertion. */
1607 if ((m->m_flags & M_VLANTAG) != 0) {
1608 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag);
1609 txp->tx_cb->ipcb_ip_activation_high |=
1610 FXP_IPCB_INSERTVLAN_ENABLE;
1611 }
1612
1613 txp->tx_mbuf = m;
1614 txp->tx_cb->cb_status = 0;
1615 txp->tx_cb->byte_count = 0;
1616 if (sc->tx_queued != FXP_CXINT_THRESH - 1)
1617 txp->tx_cb->cb_command =
1618 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1619 FXP_CB_COMMAND_S);
1620 else
1621 txp->tx_cb->cb_command =
1622 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1623 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1624 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1625 txp->tx_cb->tx_threshold = tx_threshold;
1626
1627 /*
1628 * Advance the end of list forward.
1629 */
1630 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1631 sc->fxp_desc.tx_last = txp;
1632
1633 /*
1634 * Advance the beginning of the list forward if there are
1635 * no other packets queued (when nothing is queued, tx_first
1636 * sits on the last TxCB that was sent out).
1637 */
1638 if (sc->tx_queued == 0)
1639 sc->fxp_desc.tx_first = txp;
1640
1641 sc->tx_queued++;
1642
1643 return (0);
1644 }
1645
1646 #ifdef DEVICE_POLLING
1647 static poll_handler_t fxp_poll;
1648
1649 static int
fxp_poll(if_t ifp,enum poll_cmd cmd,int count)1650 fxp_poll(if_t ifp, enum poll_cmd cmd, int count)
1651 {
1652 struct fxp_softc *sc = if_getsoftc(ifp);
1653 uint8_t statack;
1654 int rx_npkts = 0;
1655
1656 FXP_LOCK(sc);
1657 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
1658 FXP_UNLOCK(sc);
1659 return (rx_npkts);
1660 }
1661
1662 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1663 FXP_SCB_STATACK_FR;
1664 if (cmd == POLL_AND_CHECK_STATUS) {
1665 uint8_t tmp;
1666
1667 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1668 if (tmp == 0xff || tmp == 0) {
1669 FXP_UNLOCK(sc);
1670 return (rx_npkts); /* nothing to do */
1671 }
1672 tmp &= ~statack;
1673 /* ack what we can */
1674 if (tmp != 0)
1675 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1676 statack |= tmp;
1677 }
1678 rx_npkts = fxp_intr_body(sc, ifp, statack, count);
1679 FXP_UNLOCK(sc);
1680 return (rx_npkts);
1681 }
1682 #endif /* DEVICE_POLLING */
1683
1684 /*
1685 * Process interface interrupts.
1686 */
1687 static void
fxp_intr(void * xsc)1688 fxp_intr(void *xsc)
1689 {
1690 struct fxp_softc *sc = xsc;
1691 if_t ifp = sc->ifp;
1692 uint8_t statack;
1693
1694 FXP_LOCK(sc);
1695 if (sc->suspended) {
1696 FXP_UNLOCK(sc);
1697 return;
1698 }
1699
1700 #ifdef DEVICE_POLLING
1701 if (if_getcapenable(ifp) & IFCAP_POLLING) {
1702 FXP_UNLOCK(sc);
1703 return;
1704 }
1705 #endif
1706 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1707 /*
1708 * It should not be possible to have all bits set; the
1709 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1710 * all bits are set, this may indicate that the card has
1711 * been physically ejected, so ignore it.
1712 */
1713 if (statack == 0xff) {
1714 FXP_UNLOCK(sc);
1715 return;
1716 }
1717
1718 /*
1719 * First ACK all the interrupts in this pass.
1720 */
1721 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1722 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1723 fxp_intr_body(sc, ifp, statack, -1);
1724 }
1725 FXP_UNLOCK(sc);
1726 }
1727
1728 static void
fxp_txeof(struct fxp_softc * sc)1729 fxp_txeof(struct fxp_softc *sc)
1730 {
1731 if_t ifp;
1732 struct fxp_tx *txp;
1733
1734 ifp = sc->ifp;
1735 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1736 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1737 for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1738 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1739 txp = txp->tx_next) {
1740 if (txp->tx_mbuf != NULL) {
1741 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
1742 BUS_DMASYNC_POSTWRITE);
1743 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
1744 m_freem(txp->tx_mbuf);
1745 txp->tx_mbuf = NULL;
1746 /* clear this to reset csum offload bits */
1747 txp->tx_cb->tbd[0].tb_addr = 0;
1748 }
1749 sc->tx_queued--;
1750 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1751 }
1752 sc->fxp_desc.tx_first = txp;
1753 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1754 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1755 if (sc->tx_queued == 0)
1756 sc->watchdog_timer = 0;
1757 }
1758
1759 static void
fxp_rxcsum(struct fxp_softc * sc,if_t ifp,struct mbuf * m,uint16_t status,int pos)1760 fxp_rxcsum(struct fxp_softc *sc, if_t ifp, struct mbuf *m,
1761 uint16_t status, int pos)
1762 {
1763 struct ether_header *eh;
1764 struct ip *ip;
1765 struct udphdr *uh;
1766 int32_t hlen, len, pktlen, temp32;
1767 uint16_t csum, *opts;
1768
1769 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1770 if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1771 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1772 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1773 if (status & FXP_RFDX_CS_IP_CSUM_VALID)
1774 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1775 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1776 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1777 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1778 CSUM_PSEUDO_HDR;
1779 m->m_pkthdr.csum_data = 0xffff;
1780 }
1781 }
1782 return;
1783 }
1784
1785 pktlen = m->m_pkthdr.len;
1786 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
1787 return;
1788 eh = mtod(m, struct ether_header *);
1789 if (eh->ether_type != htons(ETHERTYPE_IP))
1790 return;
1791 ip = (struct ip *)(eh + 1);
1792 if (ip->ip_v != IPVERSION)
1793 return;
1794
1795 hlen = ip->ip_hl << 2;
1796 pktlen -= sizeof(struct ether_header);
1797 if (hlen < sizeof(struct ip))
1798 return;
1799 if (ntohs(ip->ip_len) < hlen)
1800 return;
1801 if (ntohs(ip->ip_len) != pktlen)
1802 return;
1803 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1804 return; /* can't handle fragmented packet */
1805
1806 switch (ip->ip_p) {
1807 case IPPROTO_TCP:
1808 if (pktlen < (hlen + sizeof(struct tcphdr)))
1809 return;
1810 break;
1811 case IPPROTO_UDP:
1812 if (pktlen < (hlen + sizeof(struct udphdr)))
1813 return;
1814 uh = (struct udphdr *)((caddr_t)ip + hlen);
1815 if (uh->uh_sum == 0)
1816 return; /* no checksum */
1817 break;
1818 default:
1819 return;
1820 }
1821 /* Extract computed checksum. */
1822 csum = be16dec(mtod(m, char *) + pos);
1823 /* checksum fixup for IP options */
1824 len = hlen - sizeof(struct ip);
1825 if (len > 0) {
1826 opts = (uint16_t *)(ip + 1);
1827 for (; len > 0; len -= sizeof(uint16_t), opts++) {
1828 temp32 = csum - *opts;
1829 temp32 = (temp32 >> 16) + (temp32 & 65535);
1830 csum = temp32 & 65535;
1831 }
1832 }
1833 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1834 m->m_pkthdr.csum_data = csum;
1835 }
1836
1837 static int
fxp_intr_body(struct fxp_softc * sc,if_t ifp,uint8_t statack,int count)1838 fxp_intr_body(struct fxp_softc *sc, if_t ifp, uint8_t statack,
1839 int count)
1840 {
1841 struct mbuf *m;
1842 struct fxp_rx *rxp;
1843 struct fxp_rfa *rfa;
1844 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1845 int rx_npkts;
1846 uint16_t status;
1847
1848 rx_npkts = 0;
1849 FXP_LOCK_ASSERT(sc, MA_OWNED);
1850
1851 if (rnr)
1852 sc->rnr++;
1853 #ifdef DEVICE_POLLING
1854 /* Pick up a deferred RNR condition if `count' ran out last time. */
1855 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1856 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1857 rnr = 1;
1858 }
1859 #endif
1860
1861 /*
1862 * Free any finished transmit mbuf chains.
1863 *
1864 * Handle the CNA event likt a CXTNO event. It used to
1865 * be that this event (control unit not ready) was not
1866 * encountered, but it is now with the SMPng modifications.
1867 * The exact sequence of events that occur when the interface
1868 * is brought up are different now, and if this event
1869 * goes unhandled, the configuration/rxfilter setup sequence
1870 * can stall for several seconds. The result is that no
1871 * packets go out onto the wire for about 5 to 10 seconds
1872 * after the interface is ifconfig'ed for the first time.
1873 */
1874 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA))
1875 fxp_txeof(sc);
1876
1877 /*
1878 * Try to start more packets transmitting.
1879 */
1880 if (!if_sendq_empty(ifp))
1881 fxp_start_body(ifp);
1882
1883 /*
1884 * Just return if nothing happened on the receive side.
1885 */
1886 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1887 return (rx_npkts);
1888
1889 /*
1890 * Process receiver interrupts. If a no-resource (RNR)
1891 * condition exists, get whatever packets we can and
1892 * re-start the receiver.
1893 *
1894 * When using polling, we do not process the list to completion,
1895 * so when we get an RNR interrupt we must defer the restart
1896 * until we hit the last buffer with the C bit set.
1897 * If we run out of cycles and rfa_headm has the C bit set,
1898 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1899 * that the info will be used in the subsequent polling cycle.
1900 */
1901 for (;;) {
1902 rxp = sc->fxp_desc.rx_head;
1903 m = rxp->rx_mbuf;
1904 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1905 RFA_ALIGNMENT_FUDGE);
1906 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
1907 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1908
1909 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1910 if (count >= 0 && count-- == 0) {
1911 if (rnr) {
1912 /* Defer RNR processing until the next time. */
1913 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1914 rnr = 0;
1915 }
1916 break;
1917 }
1918 #endif /* DEVICE_POLLING */
1919
1920 status = le16toh(rfa->rfa_status);
1921 if ((status & FXP_RFA_STATUS_C) == 0)
1922 break;
1923
1924 if ((status & FXP_RFA_STATUS_RNR) != 0)
1925 rnr++;
1926 /*
1927 * Advance head forward.
1928 */
1929 sc->fxp_desc.rx_head = rxp->rx_next;
1930
1931 /*
1932 * Add a new buffer to the receive chain.
1933 * If this fails, the old buffer is recycled
1934 * instead.
1935 */
1936 if (fxp_new_rfabuf(sc, rxp) == 0) {
1937 int total_len;
1938
1939 /*
1940 * Fetch packet length (the top 2 bits of
1941 * actual_size are flags set by the controller
1942 * upon completion), and drop the packet in case
1943 * of bogus length or CRC errors.
1944 */
1945 total_len = le16toh(rfa->actual_size) & 0x3fff;
1946 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1947 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
1948 /* Adjust for appended checksum bytes. */
1949 total_len -= 2;
1950 }
1951 if (total_len < (int)sizeof(struct ether_header) ||
1952 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE -
1953 sc->rfa_size) ||
1954 status & (FXP_RFA_STATUS_CRC |
1955 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) {
1956 m_freem(m);
1957 fxp_add_rfabuf(sc, rxp);
1958 continue;
1959 }
1960
1961 m->m_pkthdr.len = m->m_len = total_len;
1962 if_setrcvif(m, ifp);
1963
1964 /* Do IP checksum checking. */
1965 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
1966 fxp_rxcsum(sc, ifp, m, status, total_len);
1967 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
1968 (status & FXP_RFA_STATUS_VLAN) != 0) {
1969 m->m_pkthdr.ether_vtag =
1970 ntohs(rfa->rfax_vlan_id);
1971 m->m_flags |= M_VLANTAG;
1972 }
1973 /*
1974 * Drop locks before calling if_input() since it
1975 * may re-enter fxp_start() in the netisr case.
1976 * This would result in a lock reversal. Better
1977 * performance might be obtained by chaining all
1978 * packets received, dropping the lock, and then
1979 * calling if_input() on each one.
1980 */
1981 FXP_UNLOCK(sc);
1982 if_input(ifp, m);
1983 FXP_LOCK(sc);
1984 rx_npkts++;
1985 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1986 return (rx_npkts);
1987 } else {
1988 /* Reuse RFA and loaded DMA map. */
1989 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1990 fxp_discard_rfabuf(sc, rxp);
1991 }
1992 fxp_add_rfabuf(sc, rxp);
1993 }
1994 if (rnr) {
1995 fxp_scb_wait(sc);
1996 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1997 sc->fxp_desc.rx_head->rx_addr);
1998 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1999 }
2000 return (rx_npkts);
2001 }
2002
2003 static void
fxp_update_stats(struct fxp_softc * sc)2004 fxp_update_stats(struct fxp_softc *sc)
2005 {
2006 if_t ifp = sc->ifp;
2007 struct fxp_stats *sp = sc->fxp_stats;
2008 struct fxp_hwstats *hsp;
2009 uint32_t *status;
2010
2011 FXP_LOCK_ASSERT(sc, MA_OWNED);
2012
2013 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2014 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2015 /* Update statistical counters. */
2016 if (sc->revision >= FXP_REV_82559_A0)
2017 status = &sp->completion_status;
2018 else if (sc->revision >= FXP_REV_82558_A4)
2019 status = (uint32_t *)&sp->tx_tco;
2020 else
2021 status = &sp->tx_pause;
2022 if (*status == htole32(FXP_STATS_DR_COMPLETE)) {
2023 hsp = &sc->fxp_hwstats;
2024 hsp->tx_good += le32toh(sp->tx_good);
2025 hsp->tx_maxcols += le32toh(sp->tx_maxcols);
2026 hsp->tx_latecols += le32toh(sp->tx_latecols);
2027 hsp->tx_underruns += le32toh(sp->tx_underruns);
2028 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs);
2029 hsp->tx_deffered += le32toh(sp->tx_deffered);
2030 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions);
2031 hsp->tx_multiple_collisions +=
2032 le32toh(sp->tx_multiple_collisions);
2033 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions);
2034 hsp->rx_good += le32toh(sp->rx_good);
2035 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors);
2036 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors);
2037 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors);
2038 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors);
2039 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors);
2040 hsp->rx_shortframes += le32toh(sp->rx_shortframes);
2041 hsp->tx_pause += le32toh(sp->tx_pause);
2042 hsp->rx_pause += le32toh(sp->rx_pause);
2043 hsp->rx_controls += le32toh(sp->rx_controls);
2044 hsp->tx_tco += le16toh(sp->tx_tco);
2045 hsp->rx_tco += le16toh(sp->rx_tco);
2046
2047 if_inc_counter(ifp, IFCOUNTER_OPACKETS, le32toh(sp->tx_good));
2048 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2049 le32toh(sp->tx_total_collisions));
2050 if (sp->rx_good) {
2051 if_inc_counter(ifp, IFCOUNTER_IPACKETS,
2052 le32toh(sp->rx_good));
2053 sc->rx_idle_secs = 0;
2054 } else if (sc->flags & FXP_FLAG_RXBUG) {
2055 /*
2056 * Receiver's been idle for another second.
2057 */
2058 sc->rx_idle_secs++;
2059 }
2060 if_inc_counter(ifp, IFCOUNTER_IERRORS,
2061 le32toh(sp->rx_crc_errors) +
2062 le32toh(sp->rx_alignment_errors) +
2063 le32toh(sp->rx_rnr_errors) +
2064 le32toh(sp->rx_overrun_errors));
2065 /*
2066 * If any transmit underruns occurred, bump up the transmit
2067 * threshold by another 512 bytes (64 * 8).
2068 */
2069 if (sp->tx_underruns) {
2070 if_inc_counter(ifp, IFCOUNTER_OERRORS,
2071 le32toh(sp->tx_underruns));
2072 if (tx_threshold < 192)
2073 tx_threshold += 64;
2074 }
2075 *status = 0;
2076 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2077 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2078 }
2079 }
2080
2081 /*
2082 * Update packet in/out/collision statistics. The i82557 doesn't
2083 * allow you to access these counters without doing a fairly
2084 * expensive DMA to get _all_ of the statistics it maintains, so
2085 * we do this operation here only once per second. The statistics
2086 * counters in the kernel are updated from the previous dump-stats
2087 * DMA and then a new dump-stats DMA is started. The on-chip
2088 * counters are zeroed when the DMA completes. If we can't start
2089 * the DMA immediately, we don't wait - we just prepare to read
2090 * them again next time.
2091 */
2092 static void
fxp_tick(void * xsc)2093 fxp_tick(void *xsc)
2094 {
2095 struct fxp_softc *sc = xsc;
2096 if_t ifp = sc->ifp;
2097
2098 FXP_LOCK_ASSERT(sc, MA_OWNED);
2099
2100 /* Update statistical counters. */
2101 fxp_update_stats(sc);
2102
2103 /*
2104 * Release any xmit buffers that have completed DMA. This isn't
2105 * strictly necessary to do here, but it's advantagous for mbufs
2106 * with external storage to be released in a timely manner rather
2107 * than being defered for a potentially long time. This limits
2108 * the delay to a maximum of one second.
2109 */
2110 fxp_txeof(sc);
2111
2112 /*
2113 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
2114 * then assume the receiver has locked up and attempt to clear
2115 * the condition by reprogramming the multicast filter. This is
2116 * a work-around for a bug in the 82557 where the receiver locks
2117 * up if it gets certain types of garbage in the synchronization
2118 * bits prior to the packet header. This bug is supposed to only
2119 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
2120 * mode as well (perhaps due to a 10/100 speed transition).
2121 */
2122 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
2123 sc->rx_idle_secs = 0;
2124 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2125 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2126 fxp_init_body(sc, 1);
2127 }
2128 return;
2129 }
2130 /*
2131 * If there is no pending command, start another stats
2132 * dump. Otherwise punt for now.
2133 */
2134 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2135 /*
2136 * Start another stats dump.
2137 */
2138 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
2139 }
2140 if (sc->miibus != NULL)
2141 mii_tick(device_get_softc(sc->miibus));
2142
2143 /*
2144 * Check that chip hasn't hung.
2145 */
2146 fxp_watchdog(sc);
2147
2148 /*
2149 * Schedule another timeout one second from now.
2150 */
2151 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2152 }
2153
2154 /*
2155 * Stop the interface. Cancels the statistics updater and resets
2156 * the interface.
2157 */
2158 static void
fxp_stop(struct fxp_softc * sc)2159 fxp_stop(struct fxp_softc *sc)
2160 {
2161 if_t ifp = sc->ifp;
2162 struct fxp_tx *txp;
2163 int i;
2164
2165 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2166 sc->watchdog_timer = 0;
2167
2168 /*
2169 * Cancel stats updater.
2170 */
2171 callout_stop(&sc->stat_ch);
2172
2173 /*
2174 * Preserve PCI configuration, configure, IA/multicast
2175 * setup and put RU and CU into idle state.
2176 */
2177 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
2178 DELAY(50);
2179 /* Disable interrupts. */
2180 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2181
2182 fxp_update_stats(sc);
2183
2184 /*
2185 * Release any xmit buffers.
2186 */
2187 txp = sc->fxp_desc.tx_list;
2188 for (i = 0; i < FXP_NTXCB; i++) {
2189 if (txp[i].tx_mbuf != NULL) {
2190 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map,
2191 BUS_DMASYNC_POSTWRITE);
2192 bus_dmamap_unload(sc->fxp_txmtag, txp[i].tx_map);
2193 m_freem(txp[i].tx_mbuf);
2194 txp[i].tx_mbuf = NULL;
2195 /* clear this to reset csum offload bits */
2196 txp[i].tx_cb->tbd[0].tb_addr = 0;
2197 }
2198 }
2199 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2200 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2201 sc->tx_queued = 0;
2202 }
2203
2204 /*
2205 * Watchdog/transmission transmit timeout handler. Called when a
2206 * transmission is started on the interface, but no interrupt is
2207 * received before the timeout. This usually indicates that the
2208 * card has wedged for some reason.
2209 */
2210 static void
fxp_watchdog(struct fxp_softc * sc)2211 fxp_watchdog(struct fxp_softc *sc)
2212 {
2213 if_t ifp = sc->ifp;
2214
2215 FXP_LOCK_ASSERT(sc, MA_OWNED);
2216
2217 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
2218 return;
2219
2220 device_printf(sc->dev, "device timeout\n");
2221 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2222
2223 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2224 fxp_init_body(sc, 1);
2225 }
2226
2227 /*
2228 * Acquire locks and then call the real initialization function. This
2229 * is necessary because ether_ioctl() calls if_init() and this would
2230 * result in mutex recursion if the mutex was held.
2231 */
2232 static void
fxp_init(void * xsc)2233 fxp_init(void *xsc)
2234 {
2235 struct fxp_softc *sc = xsc;
2236
2237 FXP_LOCK(sc);
2238 fxp_init_body(sc, 1);
2239 FXP_UNLOCK(sc);
2240 }
2241
2242 /*
2243 * Perform device initialization. This routine must be called with the
2244 * softc lock held.
2245 */
2246 static void
fxp_init_body(struct fxp_softc * sc,int setmedia)2247 fxp_init_body(struct fxp_softc *sc, int setmedia)
2248 {
2249 if_t ifp = sc->ifp;
2250 struct mii_data *mii;
2251 struct fxp_cb_config *cbp;
2252 struct fxp_cb_ias *cb_ias;
2253 struct fxp_cb_tx *tcbp;
2254 struct fxp_tx *txp;
2255 int i, prm;
2256
2257 FXP_LOCK_ASSERT(sc, MA_OWNED);
2258
2259 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2260 return;
2261
2262 /*
2263 * Cancel any pending I/O
2264 */
2265 fxp_stop(sc);
2266
2267 /*
2268 * Issue software reset, which also unloads the microcode.
2269 */
2270 sc->flags &= ~FXP_FLAG_UCODE;
2271 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
2272 DELAY(50);
2273
2274 prm = (if_getflags(ifp) & IFF_PROMISC) ? 1 : 0;
2275
2276 /*
2277 * Initialize base of CBL and RFA memory. Loading with zero
2278 * sets it up for regular linear addressing.
2279 */
2280 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2281 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2282
2283 fxp_scb_wait(sc);
2284 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2285
2286 /*
2287 * Initialize base of dump-stats buffer.
2288 */
2289 fxp_scb_wait(sc);
2290 bzero(sc->fxp_stats, sizeof(struct fxp_stats));
2291 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2292 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2293 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2294 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2295
2296 /*
2297 * Attempt to load microcode if requested.
2298 * For ICH based controllers do not load microcode.
2299 */
2300 if (sc->ident->ich == 0) {
2301 if (if_getflags(ifp) & IFF_LINK0 &&
2302 (sc->flags & FXP_FLAG_UCODE) == 0)
2303 fxp_load_ucode(sc);
2304 }
2305
2306 /*
2307 * Set IFF_ALLMULTI status. It's needed in configure action
2308 * command.
2309 */
2310 fxp_mc_addrs(sc);
2311
2312 /*
2313 * We temporarily use memory that contains the TxCB list to
2314 * construct the config CB. The TxCB list memory is rebuilt
2315 * later.
2316 */
2317 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2318
2319 /*
2320 * This bcopy is kind of disgusting, but there are a bunch of must be
2321 * zero and must be one bits in this structure and this is the easiest
2322 * way to initialize them all to proper values.
2323 */
2324 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2325
2326 cbp->cb_status = 0;
2327 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
2328 FXP_CB_COMMAND_EL);
2329 cbp->link_addr = 0xffffffff; /* (no) next command */
2330 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2331 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
2332 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2333 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2334 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2335 cbp->type_enable = 0; /* actually reserved */
2336 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2337 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2338 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2339 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2340 cbp->dma_mbce = 0; /* (disable) dma max counters */
2341 cbp->late_scb = 0; /* (don't) defer SCB update */
2342 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2343 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2344 cbp->ci_int = 1; /* interrupt on CU idle */
2345 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2346 cbp->ext_stats_dis = 1; /* disable extended counters */
2347 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2348 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2349 cbp->disc_short_rx = !prm; /* discard short packets */
2350 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2351 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2352 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2353 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2354 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2355 cbp->csma_dis = 0; /* (don't) disable link */
2356 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2357 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) ? 1 : 0;
2358 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2359 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2360 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2361 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2362 cbp->nsai = 1; /* (don't) disable source addr insert */
2363 cbp->preamble_length = 2; /* (7 byte) preamble */
2364 cbp->loopback = 0; /* (don't) loopback */
2365 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2366 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2367 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2368 cbp->promiscuous = prm; /* promiscuous mode */
2369 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2370 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2371 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2372 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2373 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2374
2375 cbp->stripping = !prm; /* truncate rx packet to byte count */
2376 cbp->padding = 1; /* (do) pad short tx packets */
2377 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2378 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2379 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2380 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1;
2381 cbp->force_fdx = 0; /* (don't) force full duplex */
2382 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2383 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2384 cbp->mc_all = if_getflags(ifp) & IFF_ALLMULTI ? 1 : prm;
2385 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2386 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2387 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2388
2389 if (sc->revision == FXP_REV_82557) {
2390 /*
2391 * The 82557 has no hardware flow control, the values
2392 * below are the defaults for the chip.
2393 */
2394 cbp->fc_delay_lsb = 0;
2395 cbp->fc_delay_msb = 0x40;
2396 cbp->pri_fc_thresh = 3;
2397 cbp->tx_fc_dis = 0;
2398 cbp->rx_fc_restop = 0;
2399 cbp->rx_fc_restart = 0;
2400 cbp->fc_filter = 0;
2401 cbp->pri_fc_loc = 1;
2402 } else {
2403 /* Set pause RX FIFO threshold to 1KB. */
2404 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1);
2405 /* Set pause time. */
2406 cbp->fc_delay_lsb = 0xff;
2407 cbp->fc_delay_msb = 0xff;
2408 cbp->pri_fc_thresh = 3;
2409 mii = device_get_softc(sc->miibus);
2410 if ((IFM_OPTIONS(mii->mii_media_active) &
2411 IFM_ETH_TXPAUSE) != 0)
2412 /* enable transmit FC */
2413 cbp->tx_fc_dis = 0;
2414 else
2415 /* disable transmit FC */
2416 cbp->tx_fc_dis = 1;
2417 if ((IFM_OPTIONS(mii->mii_media_active) &
2418 IFM_ETH_RXPAUSE) != 0) {
2419 /* enable FC restart/restop frames */
2420 cbp->rx_fc_restart = 1;
2421 cbp->rx_fc_restop = 1;
2422 } else {
2423 /* disable FC restart/restop frames */
2424 cbp->rx_fc_restart = 0;
2425 cbp->rx_fc_restop = 0;
2426 }
2427 cbp->fc_filter = !prm; /* drop FC frames to host */
2428 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2429 }
2430
2431 /* Enable 82558 and 82559 extended statistics functionality. */
2432 if (sc->revision >= FXP_REV_82558_A4) {
2433 if (sc->revision >= FXP_REV_82559_A0) {
2434 /*
2435 * Extend configuration table size to 32
2436 * to include TCO configuration.
2437 */
2438 cbp->byte_count = 32;
2439 cbp->ext_stats_dis = 1;
2440 /* Enable TCO stats. */
2441 cbp->tno_int_or_tco_en = 1;
2442 cbp->gamla_rx = 1;
2443 } else
2444 cbp->ext_stats_dis = 0;
2445 }
2446
2447 /*
2448 * Start the config command/DMA.
2449 */
2450 fxp_scb_wait(sc);
2451 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2452 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2453 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2454 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2455 /* ...and wait for it to complete. */
2456 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2457
2458 /*
2459 * Now initialize the station address. Temporarily use the TxCB
2460 * memory area like we did above for the config CB.
2461 */
2462 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2463 cb_ias->cb_status = 0;
2464 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2465 cb_ias->link_addr = 0xffffffff;
2466 bcopy(if_getlladdr(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2467
2468 /*
2469 * Start the IAS (Individual Address Setup) command/DMA.
2470 */
2471 fxp_scb_wait(sc);
2472 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2473 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2474 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2475 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2476 /* ...and wait for it to complete. */
2477 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2478
2479 /*
2480 * Initialize the multicast address list.
2481 */
2482 fxp_mc_setup(sc);
2483
2484 /*
2485 * Initialize transmit control block (TxCB) list.
2486 */
2487 txp = sc->fxp_desc.tx_list;
2488 tcbp = sc->fxp_desc.cbl_list;
2489 bzero(tcbp, FXP_TXCB_SZ);
2490 for (i = 0; i < FXP_NTXCB; i++) {
2491 txp[i].tx_mbuf = NULL;
2492 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2493 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2494 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2495 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2496 if (sc->flags & FXP_FLAG_EXT_TXCB)
2497 tcbp[i].tbd_array_addr =
2498 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2499 else
2500 tcbp[i].tbd_array_addr =
2501 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2502 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2503 }
2504 /*
2505 * Set the suspend flag on the first TxCB and start the control
2506 * unit. It will execute the NOP and then suspend.
2507 */
2508 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2509 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2510 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2511 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2512 sc->tx_queued = 1;
2513
2514 fxp_scb_wait(sc);
2515 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2516 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2517
2518 /*
2519 * Initialize receiver buffer area - RFA.
2520 */
2521 fxp_scb_wait(sc);
2522 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2523 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2524
2525 if (sc->miibus != NULL && setmedia != 0)
2526 mii_mediachg(device_get_softc(sc->miibus));
2527
2528 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2529
2530 /*
2531 * Enable interrupts.
2532 */
2533 #ifdef DEVICE_POLLING
2534 /*
2535 * ... but only do that if we are not polling. And because (presumably)
2536 * the default is interrupts on, we need to disable them explicitly!
2537 */
2538 if (if_getcapenable(ifp) & IFCAP_POLLING )
2539 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2540 else
2541 #endif /* DEVICE_POLLING */
2542 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2543
2544 /*
2545 * Start stats updater.
2546 */
2547 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2548 }
2549
2550 static int
fxp_serial_ifmedia_upd(if_t ifp)2551 fxp_serial_ifmedia_upd(if_t ifp)
2552 {
2553
2554 return (0);
2555 }
2556
2557 static void
fxp_serial_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)2558 fxp_serial_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2559 {
2560
2561 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2562 }
2563
2564 /*
2565 * Change media according to request.
2566 */
2567 static int
fxp_ifmedia_upd(if_t ifp)2568 fxp_ifmedia_upd(if_t ifp)
2569 {
2570 struct fxp_softc *sc = if_getsoftc(ifp);
2571 struct mii_data *mii;
2572 struct mii_softc *miisc;
2573
2574 mii = device_get_softc(sc->miibus);
2575 FXP_LOCK(sc);
2576 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2577 PHY_RESET(miisc);
2578 mii_mediachg(mii);
2579 FXP_UNLOCK(sc);
2580 return (0);
2581 }
2582
2583 /*
2584 * Notify the world which media we're using.
2585 */
2586 static void
fxp_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)2587 fxp_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2588 {
2589 struct fxp_softc *sc = if_getsoftc(ifp);
2590 struct mii_data *mii;
2591
2592 mii = device_get_softc(sc->miibus);
2593 FXP_LOCK(sc);
2594 mii_pollstat(mii);
2595 ifmr->ifm_active = mii->mii_media_active;
2596 ifmr->ifm_status = mii->mii_media_status;
2597 FXP_UNLOCK(sc);
2598 }
2599
2600 /*
2601 * Add a buffer to the end of the RFA buffer list.
2602 * Return 0 if successful, 1 for failure. A failure results in
2603 * reusing the RFA buffer.
2604 * The RFA struct is stuck at the beginning of mbuf cluster and the
2605 * data pointer is fixed up to point just past it.
2606 */
2607 static int
fxp_new_rfabuf(struct fxp_softc * sc,struct fxp_rx * rxp)2608 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2609 {
2610 struct mbuf *m;
2611 struct fxp_rfa *rfa;
2612 bus_dmamap_t tmp_map;
2613 int error;
2614
2615 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2616 if (m == NULL)
2617 return (ENOBUFS);
2618
2619 /*
2620 * Move the data pointer up so that the incoming data packet
2621 * will be 32-bit aligned.
2622 */
2623 m->m_data += RFA_ALIGNMENT_FUDGE;
2624
2625 /*
2626 * Get a pointer to the base of the mbuf cluster and move
2627 * data start past it.
2628 */
2629 rfa = mtod(m, struct fxp_rfa *);
2630 m->m_data += sc->rfa_size;
2631 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2632
2633 rfa->rfa_status = 0;
2634 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2635 rfa->actual_size = 0;
2636 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE -
2637 sc->rfa_size;
2638
2639 /*
2640 * Initialize the rest of the RFA. Note that since the RFA
2641 * is misaligned, we cannot store values directly. We're thus
2642 * using the le32enc() function which handles endianness and
2643 * is also alignment-safe.
2644 */
2645 le32enc(&rfa->link_addr, 0xffffffff);
2646 le32enc(&rfa->rbd_addr, 0xffffffff);
2647
2648 /* Map the RFA into DMA memory. */
2649 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa,
2650 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2651 &rxp->rx_addr, BUS_DMA_NOWAIT);
2652 if (error) {
2653 m_freem(m);
2654 return (error);
2655 }
2656
2657 if (rxp->rx_mbuf != NULL)
2658 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
2659 tmp_map = sc->spare_map;
2660 sc->spare_map = rxp->rx_map;
2661 rxp->rx_map = tmp_map;
2662 rxp->rx_mbuf = m;
2663
2664 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2665 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2666 return (0);
2667 }
2668
2669 static void
fxp_add_rfabuf(struct fxp_softc * sc,struct fxp_rx * rxp)2670 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2671 {
2672 struct fxp_rfa *p_rfa;
2673 struct fxp_rx *p_rx;
2674
2675 /*
2676 * If there are other buffers already on the list, attach this
2677 * one to the end by fixing up the tail to point to this one.
2678 */
2679 if (sc->fxp_desc.rx_head != NULL) {
2680 p_rx = sc->fxp_desc.rx_tail;
2681 p_rfa = (struct fxp_rfa *)
2682 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2683 p_rx->rx_next = rxp;
2684 le32enc(&p_rfa->link_addr, rxp->rx_addr);
2685 p_rfa->rfa_control = 0;
2686 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map,
2687 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2688 } else {
2689 rxp->rx_next = NULL;
2690 sc->fxp_desc.rx_head = rxp;
2691 }
2692 sc->fxp_desc.rx_tail = rxp;
2693 }
2694
2695 static void
fxp_discard_rfabuf(struct fxp_softc * sc,struct fxp_rx * rxp)2696 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2697 {
2698 struct mbuf *m;
2699 struct fxp_rfa *rfa;
2700
2701 m = rxp->rx_mbuf;
2702 m->m_data = m->m_ext.ext_buf;
2703 /*
2704 * Move the data pointer up so that the incoming data packet
2705 * will be 32-bit aligned.
2706 */
2707 m->m_data += RFA_ALIGNMENT_FUDGE;
2708
2709 /*
2710 * Get a pointer to the base of the mbuf cluster and move
2711 * data start past it.
2712 */
2713 rfa = mtod(m, struct fxp_rfa *);
2714 m->m_data += sc->rfa_size;
2715 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2716
2717 rfa->rfa_status = 0;
2718 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2719 rfa->actual_size = 0;
2720
2721 /*
2722 * Initialize the rest of the RFA. Note that since the RFA
2723 * is misaligned, we cannot store values directly. We're thus
2724 * using the le32enc() function which handles endianness and
2725 * is also alignment-safe.
2726 */
2727 le32enc(&rfa->link_addr, 0xffffffff);
2728 le32enc(&rfa->rbd_addr, 0xffffffff);
2729
2730 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2731 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2732 }
2733
2734 static int
fxp_miibus_readreg(device_t dev,int phy,int reg)2735 fxp_miibus_readreg(device_t dev, int phy, int reg)
2736 {
2737 struct fxp_softc *sc = device_get_softc(dev);
2738 int count = 10000;
2739 int value;
2740
2741 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2742 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2743
2744 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2745 && count--)
2746 DELAY(10);
2747
2748 if (count <= 0)
2749 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2750
2751 return (value & 0xffff);
2752 }
2753
2754 static int
fxp_miibus_writereg(device_t dev,int phy,int reg,int value)2755 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2756 {
2757 struct fxp_softc *sc = device_get_softc(dev);
2758 int count = 10000;
2759
2760 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2761 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2762 (value & 0xffff));
2763
2764 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2765 count--)
2766 DELAY(10);
2767
2768 if (count <= 0)
2769 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2770 return (0);
2771 }
2772
2773 static void
fxp_miibus_statchg(device_t dev)2774 fxp_miibus_statchg(device_t dev)
2775 {
2776 struct fxp_softc *sc;
2777 struct mii_data *mii;
2778 if_t ifp;
2779
2780 sc = device_get_softc(dev);
2781 mii = device_get_softc(sc->miibus);
2782 ifp = sc->ifp;
2783 if (mii == NULL || ifp == (void *)NULL ||
2784 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 ||
2785 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) !=
2786 (IFM_AVALID | IFM_ACTIVE))
2787 return;
2788
2789 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T &&
2790 sc->flags & FXP_FLAG_CU_RESUME_BUG)
2791 sc->cu_resume_bug = 1;
2792 else
2793 sc->cu_resume_bug = 0;
2794 /*
2795 * Call fxp_init_body in order to adjust the flow control settings.
2796 * Note that the 82557 doesn't support hardware flow control.
2797 */
2798 if (sc->revision == FXP_REV_82557)
2799 return;
2800 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2801 fxp_init_body(sc, 0);
2802 }
2803
2804 static int
fxp_ioctl(if_t ifp,u_long command,caddr_t data)2805 fxp_ioctl(if_t ifp, u_long command, caddr_t data)
2806 {
2807 struct fxp_softc *sc = if_getsoftc(ifp);
2808 struct ifreq *ifr = (struct ifreq *)data;
2809 struct mii_data *mii;
2810 int flag, mask, error = 0, reinit;
2811
2812 switch (command) {
2813 case SIOCSIFFLAGS:
2814 FXP_LOCK(sc);
2815 /*
2816 * If interface is marked up and not running, then start it.
2817 * If it is marked down and running, stop it.
2818 * XXX If it's up then re-initialize it. This is so flags
2819 * such as IFF_PROMISC are handled.
2820 */
2821 if (if_getflags(ifp) & IFF_UP) {
2822 if (((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) &&
2823 ((if_getflags(ifp) ^ sc->if_flags) &
2824 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) {
2825 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2826 fxp_init_body(sc, 0);
2827 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2828 fxp_init_body(sc, 1);
2829 } else {
2830 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2831 fxp_stop(sc);
2832 }
2833 sc->if_flags = if_getflags(ifp);
2834 FXP_UNLOCK(sc);
2835 break;
2836
2837 case SIOCADDMULTI:
2838 case SIOCDELMULTI:
2839 FXP_LOCK(sc);
2840 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2841 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2842 fxp_init_body(sc, 0);
2843 }
2844 FXP_UNLOCK(sc);
2845 break;
2846
2847 case SIOCSIFMEDIA:
2848 case SIOCGIFMEDIA:
2849 if (sc->miibus != NULL) {
2850 mii = device_get_softc(sc->miibus);
2851 error = ifmedia_ioctl(ifp, ifr,
2852 &mii->mii_media, command);
2853 } else {
2854 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2855 }
2856 break;
2857
2858 case SIOCSIFCAP:
2859 reinit = 0;
2860 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap;
2861 #ifdef DEVICE_POLLING
2862 if (mask & IFCAP_POLLING) {
2863 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2864 error = ether_poll_register(fxp_poll, ifp);
2865 if (error)
2866 return(error);
2867 FXP_LOCK(sc);
2868 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2869 FXP_SCB_INTR_DISABLE);
2870 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
2871 FXP_UNLOCK(sc);
2872 } else {
2873 error = ether_poll_deregister(ifp);
2874 /* Enable interrupts in any case */
2875 FXP_LOCK(sc);
2876 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2877 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
2878 FXP_UNLOCK(sc);
2879 }
2880 }
2881 #endif
2882 FXP_LOCK(sc);
2883 if ((mask & IFCAP_TXCSUM) != 0 &&
2884 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
2885 if_togglecapenable(ifp, IFCAP_TXCSUM);
2886 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
2887 if_sethwassistbits(ifp, FXP_CSUM_FEATURES, 0);
2888 else
2889 if_sethwassistbits(ifp, 0, FXP_CSUM_FEATURES);
2890 }
2891 if ((mask & IFCAP_RXCSUM) != 0 &&
2892 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
2893 if_togglecapenable(ifp, IFCAP_RXCSUM);
2894 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2895 reinit++;
2896 }
2897 if ((mask & IFCAP_TSO4) != 0 &&
2898 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
2899 if_togglecapenable(ifp, IFCAP_TSO4);
2900 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
2901 if_sethwassistbits(ifp, CSUM_TSO, 0);
2902 else
2903 if_sethwassistbits(ifp, 0, CSUM_TSO);
2904 }
2905 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2906 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
2907 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
2908 if ((mask & IFCAP_VLAN_MTU) != 0 &&
2909 (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) != 0) {
2910 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
2911 if (sc->revision != FXP_REV_82557)
2912 flag = FXP_FLAG_LONG_PKT_EN;
2913 else /* a hack to get long frames on the old chip */
2914 flag = FXP_FLAG_SAVE_BAD;
2915 sc->flags ^= flag;
2916 if (if_getflags(ifp) & IFF_UP)
2917 reinit++;
2918 }
2919 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2920 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
2921 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
2922 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2923 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
2924 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
2925 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2926 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
2927 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
2928 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
2929 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO |
2930 IFCAP_VLAN_HWCSUM);
2931 reinit++;
2932 }
2933 if (reinit > 0 &&
2934 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2935 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2936 fxp_init_body(sc, 0);
2937 }
2938 FXP_UNLOCK(sc);
2939 if_vlancap(ifp);
2940 break;
2941
2942 default:
2943 error = ether_ioctl(ifp, command, data);
2944 }
2945 return (error);
2946 }
2947
2948 static u_int
fxp_setup_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)2949 fxp_setup_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
2950 {
2951 struct fxp_softc *sc = arg;
2952 struct fxp_cb_mcs *mcsp = sc->mcsp;
2953
2954 if (mcsp->mc_cnt < MAXMCADDR)
2955 bcopy(LLADDR(sdl), mcsp->mc_addr[mcsp->mc_cnt * ETHER_ADDR_LEN],
2956 ETHER_ADDR_LEN);
2957 mcsp->mc_cnt++;
2958 return (1);
2959 }
2960
2961 /*
2962 * Fill in the multicast address list and return number of entries.
2963 */
2964 static void
fxp_mc_addrs(struct fxp_softc * sc)2965 fxp_mc_addrs(struct fxp_softc *sc)
2966 {
2967 struct fxp_cb_mcs *mcsp = sc->mcsp;
2968 if_t ifp = sc->ifp;
2969
2970 if ((if_getflags(ifp) & IFF_ALLMULTI) == 0) {
2971 mcsp->mc_cnt = 0;
2972 if_foreach_llmaddr(sc->ifp, fxp_setup_maddr, sc);
2973 if (mcsp->mc_cnt >= MAXMCADDR) {
2974 if_setflagbits(ifp, IFF_ALLMULTI, 0);
2975 mcsp->mc_cnt = 0;
2976 }
2977 }
2978 mcsp->mc_cnt = htole16(mcsp->mc_cnt * ETHER_ADDR_LEN);
2979 }
2980
2981 /*
2982 * Program the multicast filter.
2983 *
2984 * We have an artificial restriction that the multicast setup command
2985 * must be the first command in the chain, so we take steps to ensure
2986 * this. By requiring this, it allows us to keep up the performance of
2987 * the pre-initialized command ring (esp. link pointers) by not actually
2988 * inserting the mcsetup command in the ring - i.e. its link pointer
2989 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2990 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2991 * lead into the regular TxCB ring when it completes.
2992 */
2993 static void
fxp_mc_setup(struct fxp_softc * sc)2994 fxp_mc_setup(struct fxp_softc *sc)
2995 {
2996 struct fxp_cb_mcs *mcsp;
2997 int count;
2998
2999 FXP_LOCK_ASSERT(sc, MA_OWNED);
3000
3001 mcsp = sc->mcsp;
3002 mcsp->cb_status = 0;
3003 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
3004 mcsp->link_addr = 0xffffffff;
3005 fxp_mc_addrs(sc);
3006
3007 /*
3008 * Wait until command unit is idle. This should never be the
3009 * case when nothing is queued, but make sure anyway.
3010 */
3011 count = 100;
3012 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=
3013 FXP_SCB_CUS_IDLE && --count)
3014 DELAY(10);
3015 if (count == 0) {
3016 device_printf(sc->dev, "command queue timeout\n");
3017 return;
3018 }
3019
3020 /*
3021 * Start the multicast setup command.
3022 */
3023 fxp_scb_wait(sc);
3024 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
3025 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3026 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
3027 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3028 /* ...and wait for it to complete. */
3029 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
3030 }
3031
3032 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
3033 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
3034 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
3035 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
3036 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
3037 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
3038 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
3039
3040 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t)
3041
3042 static const struct ucode {
3043 uint32_t revision;
3044 uint32_t *ucode;
3045 int length;
3046 u_short int_delay_offset;
3047 u_short bundle_max_offset;
3048 } ucode_table[] = {
3049 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
3050 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
3051 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
3052 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
3053 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
3054 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
3055 { FXP_REV_82550, UCODE(fxp_ucode_d102),
3056 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
3057 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
3058 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
3059 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
3060 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3061 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e),
3062 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3063 { 0, NULL, 0, 0, 0 }
3064 };
3065
3066 static void
fxp_load_ucode(struct fxp_softc * sc)3067 fxp_load_ucode(struct fxp_softc *sc)
3068 {
3069 const struct ucode *uc;
3070 struct fxp_cb_ucode *cbp;
3071 int i;
3072
3073 if (sc->flags & FXP_FLAG_NO_UCODE)
3074 return;
3075
3076 for (uc = ucode_table; uc->ucode != NULL; uc++)
3077 if (sc->revision == uc->revision)
3078 break;
3079 if (uc->ucode == NULL)
3080 return;
3081 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
3082 cbp->cb_status = 0;
3083 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
3084 cbp->link_addr = 0xffffffff; /* (no) next command */
3085 for (i = 0; i < uc->length; i++)
3086 cbp->ucode[i] = htole32(uc->ucode[i]);
3087 if (uc->int_delay_offset)
3088 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] =
3089 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
3090 if (uc->bundle_max_offset)
3091 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] =
3092 htole16(sc->tunable_bundle_max);
3093 /*
3094 * Download the ucode to the chip.
3095 */
3096 fxp_scb_wait(sc);
3097 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
3098 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3099 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
3100 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3101 /* ...and wait for it to complete. */
3102 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
3103 device_printf(sc->dev,
3104 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
3105 sc->tunable_int_delay,
3106 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
3107 sc->flags |= FXP_FLAG_UCODE;
3108 bzero(cbp, FXP_TXCB_SZ);
3109 }
3110
3111 #define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \
3112 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3113
3114 static void
fxp_sysctl_node(struct fxp_softc * sc)3115 fxp_sysctl_node(struct fxp_softc *sc)
3116 {
3117 struct sysctl_ctx_list *ctx;
3118 struct sysctl_oid_list *child, *parent;
3119 struct sysctl_oid *tree;
3120 struct fxp_hwstats *hsp;
3121
3122 ctx = device_get_sysctl_ctx(sc->dev);
3123 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
3124
3125 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_delay",
3126 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
3127 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
3128 "FXP driver receive interrupt microcode bundling delay");
3129 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "bundle_max",
3130 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
3131 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
3132 "FXP driver receive interrupt microcode bundle size limit");
3133 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
3134 "FXP RNR events");
3135
3136 /*
3137 * Pull in device tunables.
3138 */
3139 sc->tunable_int_delay = TUNABLE_INT_DELAY;
3140 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
3141 (void) resource_int_value(device_get_name(sc->dev),
3142 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay);
3143 (void) resource_int_value(device_get_name(sc->dev),
3144 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max);
3145 sc->rnr = 0;
3146
3147 hsp = &sc->fxp_hwstats;
3148 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
3149 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "FXP statistics");
3150 parent = SYSCTL_CHILDREN(tree);
3151
3152 /* Rx MAC statistics. */
3153 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
3154 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics");
3155 child = SYSCTL_CHILDREN(tree);
3156 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3157 &hsp->rx_good, "Good frames");
3158 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors",
3159 &hsp->rx_crc_errors, "CRC errors");
3160 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors",
3161 &hsp->rx_alignment_errors, "Alignment errors");
3162 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors",
3163 &hsp->rx_rnr_errors, "RNR errors");
3164 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors",
3165 &hsp->rx_overrun_errors, "Overrun errors");
3166 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors",
3167 &hsp->rx_cdt_errors, "Collision detect errors");
3168 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes",
3169 &hsp->rx_shortframes, "Short frame errors");
3170 if (sc->revision >= FXP_REV_82558_A4) {
3171 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3172 &hsp->rx_pause, "Pause frames");
3173 FXP_SYSCTL_STAT_ADD(ctx, child, "controls",
3174 &hsp->rx_controls, "Unsupported control frames");
3175 }
3176 if (sc->revision >= FXP_REV_82559_A0)
3177 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3178 &hsp->rx_tco, "TCO frames");
3179
3180 /* Tx MAC statistics. */
3181 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
3182 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
3183 child = SYSCTL_CHILDREN(tree);
3184 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3185 &hsp->tx_good, "Good frames");
3186 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols",
3187 &hsp->tx_maxcols, "Maximum collisions errors");
3188 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols",
3189 &hsp->tx_latecols, "Late collisions errors");
3190 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns",
3191 &hsp->tx_underruns, "Underrun errors");
3192 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs",
3193 &hsp->tx_lostcrs, "Lost carrier sense");
3194 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered",
3195 &hsp->tx_deffered, "Deferred");
3196 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions",
3197 &hsp->tx_single_collisions, "Single collisions");
3198 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions",
3199 &hsp->tx_multiple_collisions, "Multiple collisions");
3200 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions",
3201 &hsp->tx_total_collisions, "Total collisions");
3202 if (sc->revision >= FXP_REV_82558_A4)
3203 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3204 &hsp->tx_pause, "Pause frames");
3205 if (sc->revision >= FXP_REV_82559_A0)
3206 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3207 &hsp->tx_tco, "TCO frames");
3208 }
3209
3210 #undef FXP_SYSCTL_STAT_ADD
3211
3212 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3213 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3214 {
3215 int error, value;
3216
3217 value = *(int *)arg1;
3218 error = sysctl_handle_int(oidp, &value, 0, req);
3219 if (error || !req->newptr)
3220 return (error);
3221 if (value < low || value > high)
3222 return (EINVAL);
3223 *(int *)arg1 = value;
3224 return (0);
3225 }
3226
3227 /*
3228 * Interrupt delay is expressed in microseconds, a multiplier is used
3229 * to convert this to the appropriate clock ticks before using.
3230 */
3231 static int
sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)3232 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
3233 {
3234
3235 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
3236 }
3237
3238 static int
sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)3239 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
3240 {
3241
3242 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
3243 }
3244