1 /* 2 * Copyright 2016-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_VCN_H__ 25 #define __AMDGPU_VCN_H__ 26 27 #include "amdgpu_ras.h" 28 29 #define AMDGPU_VCN_STACK_SIZE (128*1024) 30 #define AMDGPU_VCN_CONTEXT_SIZE (512*1024) 31 32 #define AMDGPU_VCN_FIRMWARE_OFFSET 256 33 #define AMDGPU_VCN_MAX_ENC_RINGS 3 34 35 #define AMDGPU_MAX_VCN_INSTANCES 4 36 #define AMDGPU_MAX_VCN_ENC_RINGS (AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES) 37 38 #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0) 39 #define AMDGPU_VCN_HARVEST_VCN1 (1 << 1) 40 41 #define VCN_DEC_KMD_CMD 0x80000000 42 #define VCN_DEC_CMD_FENCE 0x00000000 43 #define VCN_DEC_CMD_TRAP 0x00000001 44 #define VCN_DEC_CMD_WRITE_REG 0x00000004 45 #define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006 46 #define VCN_DEC_CMD_PACKET_START 0x0000000a 47 #define VCN_DEC_CMD_PACKET_END 0x0000000b 48 49 #define VCN_DEC_SW_CMD_NO_OP 0x00000000 50 #define VCN_DEC_SW_CMD_END 0x00000001 51 #define VCN_DEC_SW_CMD_IB 0x00000002 52 #define VCN_DEC_SW_CMD_FENCE 0x00000003 53 #define VCN_DEC_SW_CMD_TRAP 0x00000004 54 #define VCN_DEC_SW_CMD_IB_AUTO 0x00000005 55 #define VCN_DEC_SW_CMD_SEMAPHORE 0x00000006 56 #define VCN_DEC_SW_CMD_PREEMPT_FENCE 0x00000009 57 #define VCN_DEC_SW_CMD_REG_WRITE 0x0000000b 58 #define VCN_DEC_SW_CMD_REG_WAIT 0x0000000c 59 60 #define VCN_ENC_CMD_NO_OP 0x00000000 61 #define VCN_ENC_CMD_END 0x00000001 62 #define VCN_ENC_CMD_IB 0x00000002 63 #define VCN_ENC_CMD_FENCE 0x00000003 64 #define VCN_ENC_CMD_TRAP 0x00000004 65 #define VCN_ENC_CMD_REG_WRITE 0x0000000b 66 #define VCN_ENC_CMD_REG_WAIT 0x0000000c 67 68 #define VCN_AON_SOC_ADDRESS_2_0 0x1f800 69 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 70 #define VCN_VID_IP_ADDRESS_2_0 0x0 71 #define VCN_AON_IP_ADDRESS_2_0 0x30000 72 73 #define mmUVD_RBC_XX_IB_REG_CHECK 0x026b 74 #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1 75 #define mmUVD_REG_XX_MASK 0x026c 76 #define mmUVD_REG_XX_MASK_BASE_IDX 1 77 78 /* 1 second timeout */ 79 #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000) 80 81 #define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \ 82 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \ 83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \ 84 UVD_DPG_LMA_CTL__MASK_EN_MASK | \ 85 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \ 86 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ 87 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ 88 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \ 89 }) 90 91 #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \ 92 do { \ 93 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \ 94 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \ 95 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \ 96 UVD_DPG_LMA_CTL__READ_WRITE_MASK | \ 97 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \ 98 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ 99 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ 100 } while (0) 101 102 #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \ 103 ({ \ 104 uint32_t internal_reg_offset, addr; \ 105 bool video_range, video1_range, aon_range, aon1_range; \ 106 \ 107 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \ 108 addr <<= 2; \ 109 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \ 110 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \ 111 video1_range = ((((0xFFFFF & addr) >= (VCN1_VID_SOC_ADDRESS_3_0)) && \ 112 ((0xFFFFF & addr) < ((VCN1_VID_SOC_ADDRESS_3_0 + 0x2600))))); \ 113 aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && \ 114 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600))))); \ 115 aon1_range = ((((0xFFFFF & addr) >= (VCN1_AON_SOC_ADDRESS_3_0)) && \ 116 ((0xFFFFF & addr) < ((VCN1_AON_SOC_ADDRESS_3_0 + 0x600))))); \ 117 if (video_range) \ 118 internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + \ 119 (VCN_VID_IP_ADDRESS_2_0)); \ 120 else if (aon_range) \ 121 internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + \ 122 (VCN_AON_IP_ADDRESS_2_0)); \ 123 else if (video1_range) \ 124 internal_reg_offset = ((0xFFFFF & addr) - (VCN1_VID_SOC_ADDRESS_3_0) + \ 125 (VCN_VID_IP_ADDRESS_2_0)); \ 126 else if (aon1_range) \ 127 internal_reg_offset = ((0xFFFFF & addr) - (VCN1_AON_SOC_ADDRESS_3_0) + \ 128 (VCN_AON_IP_ADDRESS_2_0)); \ 129 else \ 130 internal_reg_offset = (0xFFFFF & addr); \ 131 \ 132 internal_reg_offset >>= 2; \ 133 }) 134 135 #define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en) \ 136 ({ \ 137 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \ 138 (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \ 139 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \ 140 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \ 141 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \ 142 }) 143 144 #define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \ 145 do { \ 146 if (!indirect) { \ 147 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \ 148 mmUVD_DPG_LMA_DATA, value); \ 149 WREG32_SOC15( \ 150 VCN, GET_INST(VCN, inst_idx), \ 151 mmUVD_DPG_LMA_CTL, \ 152 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \ 153 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \ 154 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \ 155 } else { \ 156 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \ 157 offset; \ 158 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \ 159 value; \ 160 } \ 161 } while (0) 162 163 #define SOC24_DPG_MODE_OFFSET(ip, inst_idx, reg) \ 164 ({ \ 165 uint32_t internal_reg_offset, addr; \ 166 bool video_range, video1_range, aon_range, aon1_range; \ 167 \ 168 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \ 169 addr <<= 2; \ 170 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS)) && \ 171 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS + 0x2600))))); \ 172 video1_range = ((((0xFFFFF & addr) >= (VCN1_VID_SOC_ADDRESS)) && \ 173 ((0xFFFFF & addr) < ((VCN1_VID_SOC_ADDRESS + 0x2600))))); \ 174 aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS)) && \ 175 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS + 0x600))))); \ 176 aon1_range = ((((0xFFFFF & addr) >= (VCN1_AON_SOC_ADDRESS)) && \ 177 ((0xFFFFF & addr) < ((VCN1_AON_SOC_ADDRESS + 0x600))))); \ 178 if (video_range) \ 179 internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS) + \ 180 (VCN_VID_IP_ADDRESS)); \ 181 else if (aon_range) \ 182 internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS) + \ 183 (VCN_AON_IP_ADDRESS)); \ 184 else if (video1_range) \ 185 internal_reg_offset = ((0xFFFFF & addr) - (VCN1_VID_SOC_ADDRESS) + \ 186 (VCN_VID_IP_ADDRESS)); \ 187 else if (aon1_range) \ 188 internal_reg_offset = ((0xFFFFF & addr) - (VCN1_AON_SOC_ADDRESS) + \ 189 (VCN_AON_IP_ADDRESS)); \ 190 else \ 191 internal_reg_offset = (0xFFFFF & addr); \ 192 \ 193 internal_reg_offset >>= 2; \ 194 }) 195 196 #define WREG32_SOC24_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \ 197 do { \ 198 if (!indirect) { \ 199 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \ 200 regUVD_DPG_LMA_DATA, value); \ 201 WREG32_SOC15( \ 202 VCN, GET_INST(VCN, inst_idx), \ 203 regUVD_DPG_LMA_CTL, \ 204 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \ 205 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \ 206 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \ 207 } else { \ 208 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \ 209 offset; \ 210 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \ 211 value; \ 212 } \ 213 } while (0) 214 215 #define AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE (1 << 2) 216 #define AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT (1 << 4) 217 #define AMDGPU_VCN_FW_SHARED_FLAG_0_RB (1 << 6) 218 #define AMDGPU_VCN_MULTI_QUEUE_FLAG (1 << 8) 219 #define AMDGPU_VCN_SW_RING_FLAG (1 << 9) 220 #define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10) 221 #define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11) 222 #define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11) 223 #define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14) 224 #define AMDGPU_VCN_VF_RB_DECOUPLE_FLAG (1 << 15) 225 226 #define MAX_NUM_VCN_RB_SETUP 4 227 228 #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001 229 #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001 230 231 #define VCN_CODEC_DISABLE_MASK_AV1 (1 << 0) 232 #define VCN_CODEC_DISABLE_MASK_VP9 (1 << 1) 233 #define VCN_CODEC_DISABLE_MASK_HEVC (1 << 2) 234 #define VCN_CODEC_DISABLE_MASK_H264 (1 << 3) 235 236 #define AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU (0) 237 #define AMDGPU_VCN_SMU_DPM_INTERFACE_APU (1) 238 239 #define AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING 2 240 241 enum amdgpu_vcn_caps { 242 AMDGPU_VCN_RRMT_ENABLED, 243 }; 244 245 #define AMDGPU_VCN_CAPS(caps) BIT(AMDGPU_VCN_##caps) 246 247 enum fw_queue_mode { 248 FW_QUEUE_RING_RESET = 1, 249 FW_QUEUE_DPG_HOLD_OFF = 2, 250 }; 251 252 enum engine_status_constants { 253 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0, 254 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0, 255 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 = 0x2A2A8AA0, 256 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002, 257 UVD_STATUS__UVD_BUSY = 0x00000004, 258 GB_ADDR_CONFIG_DEFAULT = 0x26010011, 259 UVD_STATUS__IDLE = 0x2, 260 UVD_STATUS__BUSY = 0x5, 261 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1, 262 UVD_STATUS__RBC_BUSY = 0x1, 263 UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0, 264 }; 265 266 enum internal_dpg_state { 267 VCN_DPG_STATE__UNPAUSE = 0, 268 VCN_DPG_STATE__PAUSE, 269 }; 270 271 struct dpg_pause_state { 272 enum internal_dpg_state fw_based; 273 enum internal_dpg_state jpeg; 274 }; 275 276 struct amdgpu_vcn_reg{ 277 unsigned data0; 278 unsigned data1; 279 unsigned cmd; 280 unsigned nop; 281 unsigned context_id; 282 unsigned ib_vmid; 283 unsigned ib_bar_low; 284 unsigned ib_bar_high; 285 unsigned ib_size; 286 unsigned gp_scratch8; 287 unsigned scratch9; 288 }; 289 290 struct amdgpu_vcn_fw_shared { 291 void *cpu_addr; 292 uint64_t gpu_addr; 293 uint32_t mem_size; 294 uint32_t log_offset; 295 }; 296 297 struct amdgpu_vcn_inst { 298 struct amdgpu_device *adev; 299 int inst; 300 struct amdgpu_bo *vcpu_bo; 301 void *cpu_addr; 302 uint64_t gpu_addr; 303 void *saved_bo; 304 struct amdgpu_ring ring_dec; 305 struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS]; 306 atomic_t sched_score; 307 struct amdgpu_irq_src irq; 308 struct amdgpu_irq_src ras_poison_irq; 309 struct amdgpu_vcn_reg external; 310 struct amdgpu_bo *dpg_sram_bo; 311 struct dpg_pause_state pause_state; 312 void *dpg_sram_cpu_addr; 313 uint64_t dpg_sram_gpu_addr; 314 uint32_t *dpg_sram_curr_addr; 315 atomic_t dpg_enc_submission_cnt; 316 struct amdgpu_vcn_fw_shared fw_shared; 317 uint8_t aid_id; 318 const struct firmware *fw; /* VCN firmware */ 319 uint8_t vcn_config; 320 uint32_t vcn_codec_disable_mask; 321 atomic_t total_submission_cnt; 322 struct mutex vcn_pg_lock; 323 enum amd_powergating_state cur_state; 324 struct delayed_work idle_work; 325 unsigned fw_version; 326 unsigned num_enc_rings; 327 bool indirect_sram; 328 struct amdgpu_vcn_reg internal; 329 struct mutex vcn1_jpeg1_workaround; 330 int (*pause_dpg_mode)(struct amdgpu_vcn_inst *vinst, 331 struct dpg_pause_state *new_state); 332 int (*set_pg_state)(struct amdgpu_vcn_inst *vinst, 333 enum amd_powergating_state state); 334 bool using_unified_queue; 335 }; 336 337 struct amdgpu_vcn_ras { 338 struct amdgpu_ras_block_object ras_block; 339 }; 340 341 struct amdgpu_vcn { 342 uint8_t num_vcn_inst; 343 struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES]; 344 345 unsigned harvest_config; 346 347 struct ras_common_if *ras_if; 348 struct amdgpu_vcn_ras *ras; 349 350 uint16_t inst_mask; 351 uint8_t num_inst_per_aid; 352 353 /* IP reg dump */ 354 uint32_t *ip_dump; 355 356 uint32_t supported_reset; 357 uint32_t caps; 358 359 bool per_inst_fw; 360 unsigned fw_version; 361 362 bool workload_profile_active; 363 struct mutex workload_profile_mutex; 364 }; 365 366 struct amdgpu_fw_shared_rb_ptrs_struct { 367 /* to WA DPG R/W ptr issues.*/ 368 uint32_t rptr; 369 uint32_t wptr; 370 }; 371 372 struct amdgpu_fw_shared_multi_queue { 373 uint8_t decode_queue_mode; 374 uint8_t encode_generalpurpose_queue_mode; 375 uint8_t encode_lowlatency_queue_mode; 376 uint8_t encode_realtime_queue_mode; 377 uint8_t padding[4]; 378 }; 379 380 struct amdgpu_fw_shared_sw_ring { 381 uint8_t is_enabled; 382 uint8_t padding[3]; 383 }; 384 385 struct amdgpu_fw_shared_unified_queue_struct { 386 uint8_t is_enabled; 387 uint8_t queue_mode; 388 uint8_t queue_status; 389 uint8_t padding[5]; 390 }; 391 392 struct amdgpu_fw_shared_fw_logging { 393 uint8_t is_enabled; 394 uint32_t addr_lo; 395 uint32_t addr_hi; 396 uint32_t size; 397 }; 398 399 struct amdgpu_fw_shared_smu_interface_info { 400 uint8_t smu_interface_type; 401 uint8_t padding[3]; 402 }; 403 404 struct amdgpu_fw_shared { 405 uint32_t present_flag_0; 406 uint8_t pad[44]; 407 struct amdgpu_fw_shared_rb_ptrs_struct rb; 408 uint8_t pad1[1]; 409 struct amdgpu_fw_shared_multi_queue multi_queue; 410 struct amdgpu_fw_shared_sw_ring sw_ring; 411 struct amdgpu_fw_shared_fw_logging fw_log; 412 struct amdgpu_fw_shared_smu_interface_info smu_interface_info; 413 }; 414 415 struct amdgpu_vcn_rb_setup_info { 416 uint32_t rb_addr_lo; 417 uint32_t rb_addr_hi; 418 uint32_t rb_size; 419 }; 420 421 struct amdgpu_fw_shared_rb_setup { 422 uint32_t is_rb_enabled_flags; 423 424 union { 425 struct { 426 uint32_t rb_addr_lo; 427 uint32_t rb_addr_hi; 428 uint32_t rb_size; 429 uint32_t rb4_addr_lo; 430 uint32_t rb4_addr_hi; 431 uint32_t rb4_size; 432 uint32_t reserved[6]; 433 }; 434 435 struct { 436 struct amdgpu_vcn_rb_setup_info rb_info[MAX_NUM_VCN_RB_SETUP]; 437 }; 438 }; 439 }; 440 441 struct amdgpu_fw_shared_drm_key_wa { 442 uint8_t method; 443 uint8_t reserved[3]; 444 }; 445 446 struct amdgpu_fw_shared_queue_decouple { 447 uint8_t is_enabled; 448 uint8_t reserved[7]; 449 }; 450 451 struct amdgpu_vcn4_fw_shared { 452 uint32_t present_flag_0; 453 uint8_t pad[12]; 454 struct amdgpu_fw_shared_unified_queue_struct sq; 455 uint8_t pad1[8]; 456 struct amdgpu_fw_shared_fw_logging fw_log; 457 uint8_t pad2[20]; 458 struct amdgpu_fw_shared_rb_setup rb_setup; 459 struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface; 460 struct amdgpu_fw_shared_drm_key_wa drm_key_wa; 461 uint8_t pad3[9]; 462 struct amdgpu_fw_shared_queue_decouple decouple; 463 }; 464 465 struct amdgpu_vcn_fwlog { 466 uint32_t rptr; 467 uint32_t wptr; 468 uint32_t buffer_size; 469 uint32_t header_size; 470 uint8_t wrapped; 471 }; 472 473 struct amdgpu_vcn_decode_buffer { 474 uint32_t valid_buf_flag; 475 uint32_t msg_buffer_address_hi; 476 uint32_t msg_buffer_address_lo; 477 uint32_t pad[30]; 478 }; 479 480 struct amdgpu_vcn_rb_metadata { 481 uint32_t size; 482 uint32_t present_flag_0; 483 484 uint8_t version; 485 uint8_t ring_id; 486 uint8_t pad[26]; 487 }; 488 489 struct amdgpu_vcn5_fw_shared { 490 uint32_t present_flag_0; 491 uint8_t pad[12]; 492 struct amdgpu_fw_shared_unified_queue_struct sq; 493 uint8_t pad1[8]; 494 struct amdgpu_fw_shared_fw_logging fw_log; 495 uint8_t pad2[20]; 496 struct amdgpu_fw_shared_rb_setup rb_setup; 497 struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface; 498 struct amdgpu_fw_shared_drm_key_wa drm_key_wa; 499 uint8_t pad3[9]; 500 }; 501 502 #define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80 503 #define VCN_BLOCK_DECODE_DISABLE_MASK 0x40 504 #define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0 505 506 enum vcn_ring_type { 507 VCN_ENCODE_RING, 508 VCN_DECODE_RING, 509 VCN_UNIFIED_RING, 510 }; 511 512 int amdgpu_vcn_early_init(struct amdgpu_device *adev, int i); 513 int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int i); 514 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int i); 515 int amdgpu_vcn_suspend(struct amdgpu_device *adev, int i); 516 int amdgpu_vcn_resume(struct amdgpu_device *adev, int i); 517 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring); 518 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring); 519 520 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, 521 enum vcn_ring_type type, uint32_t vcn_instance); 522 523 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring); 524 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout); 525 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring); 526 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout); 527 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout); 528 529 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring); 530 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout); 531 532 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring); 533 534 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev, int i); 535 536 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn); 537 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, 538 uint8_t i, struct amdgpu_vcn_inst *vcn); 539 540 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev, 541 struct amdgpu_irq_src *source, 542 struct amdgpu_iv_entry *entry); 543 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, 544 struct ras_common_if *ras_block); 545 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev); 546 547 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, 548 enum AMDGPU_UCODE_ID ucode_id); 549 int amdgpu_vcn_save_vcpu_bo(struct amdgpu_device *adev); 550 int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev); 551 void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev); 552 void amdgpu_debugfs_vcn_sched_mask_init(struct amdgpu_device *adev); 553 554 int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block, 555 enum amd_powergating_state state); 556 557 #endif 558