1 /* SPDX-License-Identifier: ISC */
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #ifndef __MT7996_H
7 #define __MT7996_H
8
9 #include <linux/interrupt.h>
10 #include <linux/ktime.h>
11 #include "../mt76_connac.h"
12 #include "regs.h"
13
14 #define MT7996_MAX_RADIOS 3
15 #define MT7996_MAX_INTERFACES 19 /* per-band */
16 #define MT7996_MAX_WMM_SETS 4
17 #define MT7996_WTBL_BMC_SIZE (is_mt7996(&dev->mt76) ? 64 : 32)
18 #define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1)
19 #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \
20 mt7996_max_interface_num(dev))
21
22 #define MT7996_WATCHDOG_TIME (HZ / 10)
23 #define MT7996_RESET_TIMEOUT (30 * HZ)
24
25 #define MT7996_TX_RING_SIZE 2048
26 #define MT7996_TX_MCU_RING_SIZE 256
27 #define MT7996_TX_FWDL_RING_SIZE 128
28
29 #define MT7996_RX_RING_SIZE 1536
30 #define MT7996_RX_MCU_RING_SIZE 512
31 #define MT7996_RX_MCU_RING_SIZE_WA 1024
32 /* scatter-gather of mcu event is not supported in connac3 */
33 #define MT7996_RX_MCU_BUF_SIZE (2048 + \
34 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
35
36 #define MT7996_DEVICE_ID 0x7990
37 #define MT7996_DEVICE_ID_2 0x7991
38 #define MT7992_DEVICE_ID 0x7992
39 #define MT7992_DEVICE_ID_2 0x799a
40 #define MT7990_DEVICE_ID 0x7993
41 #define MT7990_DEVICE_ID_2 0x799b
42
43 #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin"
44 #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin"
45 #define MT7996_FIRMWARE_DSP "mediatek/mt7996/mt7996_dsp.bin"
46 #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin"
47
48 #define MT7996_FIRMWARE_WA_233 "mediatek/mt7996/mt7996_wa_233.bin"
49 #define MT7996_FIRMWARE_WM_233 "mediatek/mt7996/mt7996_wm_233.bin"
50 #define MT7996_FIRMWARE_DSP_233 MT7996_FIRMWARE_DSP
51 #define MT7996_ROM_PATCH_233 "mediatek/mt7996/mt7996_rom_patch_233.bin"
52
53 #define MT7992_FIRMWARE_WA "mediatek/mt7996/mt7992_wa.bin"
54 #define MT7992_FIRMWARE_WM "mediatek/mt7996/mt7992_wm.bin"
55 #define MT7992_FIRMWARE_DSP "mediatek/mt7996/mt7992_dsp.bin"
56 #define MT7992_ROM_PATCH "mediatek/mt7996/mt7992_rom_patch.bin"
57
58 #define MT7992_FIRMWARE_WA_23 "mediatek/mt7996/mt7992_wa_23.bin"
59 #define MT7992_FIRMWARE_WM_23 "mediatek/mt7996/mt7992_wm_23.bin"
60 #define MT7992_FIRMWARE_DSP_23 "mediatek/mt7996/mt7992_dsp_23.bin"
61 #define MT7992_ROM_PATCH_23 "mediatek/mt7996/mt7992_rom_patch_23.bin"
62
63 #define MT7990_FIRMWARE_WA ""
64 #define MT7990_FIRMWARE_WM "mediatek/mt7996/mt7990_wm.bin"
65 #define MT7990_FIRMWARE_DSP ""
66 #define MT7990_ROM_PATCH "mediatek/mt7996/mt7990_rom_patch.bin"
67
68 #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin"
69 #define MT7996_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7996_eeprom_2i5i6i.bin"
70 #define MT7996_EEPROM_DEFAULT_233 "mediatek/mt7996/mt7996_eeprom_233.bin"
71 #define MT7996_EEPROM_DEFAULT_233_INT "mediatek/mt7996/mt7996_eeprom_233_2i5i6i.bin"
72
73 #define MT7992_EEPROM_DEFAULT "mediatek/mt7996/mt7992_eeprom.bin"
74 #define MT7992_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7992_eeprom_2i5i.bin"
75 #define MT7992_EEPROM_DEFAULT_MIX "mediatek/mt7996/mt7992_eeprom_2i5e.bin"
76 #define MT7992_EEPROM_DEFAULT_23 "mediatek/mt7996/mt7992_eeprom_23.bin"
77 #define MT7992_EEPROM_DEFAULT_23_INT "mediatek/mt7996/mt7992_eeprom_23_2i5i.bin"
78
79 #define MT7990_EEPROM_DEFAULT "mediatek/mt7996/mt7990_eeprom.bin"
80 #define MT7990_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7990_eeprom_2i5i.bin"
81
82 #define MT7996_EEPROM_SIZE 7680
83 #define MT7996_EEPROM_BLOCK_SIZE 16
84 #define MT7996_TOKEN_SIZE 16384
85 #define MT7996_HW_TOKEN_SIZE 8192
86
87 #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */
88 #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */
89 #define MT7996_IBF_MAX_NC 2
90 #define MT7996_IBF_TIMEOUT 0x18
91 #define MT7996_IBF_TIMEOUT_LEGACY 0x48
92
93 #define MT7992_CFEND_RATE_DEFAULT 0x4b /* OFDM 6M */
94 #define MT7992_IBF_TIMEOUT 0xff
95
96 #define MT7996_SKU_RATE_NUM 417
97 #define MT7996_SKU_PATH_NUM 494
98
99 #define MT7996_MAX_TWT_AGRT 16
100 #define MT7996_MAX_STA_TWT_AGRT 8
101 #define MT7996_MIN_TWT_DUR 64
102 #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3)
103
104 /* NOTE: used to map mt76_rates. idx may change if firmware expands table */
105 #define MT7996_BASIC_RATES_TBL 31
106 #define MT7996_BEACON_RATES_TBL 25
107
108 #define MT7996_THERMAL_THROTTLE_MAX 100
109 #define MT7996_CDEV_THROTTLE_MAX 99
110 #define MT7996_CRIT_TEMP_IDX 0
111 #define MT7996_MAX_TEMP_IDX 1
112 #define MT7996_CRIT_TEMP 110
113 #define MT7996_MAX_TEMP 120
114
115 #define MT7996_MAX_HIF_RXD_IN_PG 5
116 #define MT7996_RRO_MSDU_PG_HASH_SIZE 127
117 #define MT7996_RRO_MAX_SESSION 1024
118 #define MT7996_RRO_WINDOW_MAX_LEN 1024
119 #define MT7996_RRO_ADDR_ELEM_LEN 128
120 #define MT7996_RRO_BA_BITMAP_LEN 2
121 #define MT7996_RRO_BA_BITMAP_CR_SIZE ((MT7996_RRO_MAX_SESSION * 128) / \
122 MT7996_RRO_BA_BITMAP_LEN)
123 #define MT7996_RRO_BA_BITMAP_SESSION_SIZE (MT7996_RRO_MAX_SESSION / \
124 MT7996_RRO_ADDR_ELEM_LEN)
125 #define MT7996_RRO_WINDOW_MAX_SIZE (MT7996_RRO_WINDOW_MAX_LEN * \
126 MT7996_RRO_BA_BITMAP_SESSION_SIZE)
127
128 #define MT7996_RX_BUF_SIZE (1800 + \
129 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
130 #define MT7996_RX_MSDU_PAGE_SIZE (128 + \
131 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
132
133 /* RRO 3.1 */
134 #define MT7996_RRO_MSDU_PG_CR_CNT 8
135 #define MT7996_RRO_MSDU_PG_SIZE_PER_CR 0x10000
136
137 struct mt7996_vif;
138 struct mt7996_sta;
139 struct mt7996_dfs_pulse;
140 struct mt7996_dfs_pattern;
141
142 enum mt7996_ram_type {
143 MT7996_RAM_TYPE_WM,
144 MT7996_RAM_TYPE_WA,
145 MT7996_RAM_TYPE_DSP,
146 };
147
148 enum mt7996_var_type {
149 MT7996_VAR_TYPE_444,
150 MT7996_VAR_TYPE_233,
151 };
152
153 enum mt7992_var_type {
154 MT7992_VAR_TYPE_44,
155 MT7992_VAR_TYPE_23,
156 };
157
158 enum mt7990_var_type {
159 MT7990_VAR_TYPE_23,
160 };
161
162 enum mt7996_fem_type {
163 MT7996_FEM_EXT,
164 MT7996_FEM_INT,
165 MT7996_FEM_MIX,
166 };
167
168 enum mt7996_txq_id {
169 MT7996_TXQ_FWDL = 16,
170 MT7996_TXQ_MCU_WM,
171 MT7996_TXQ_BAND0,
172 MT7996_TXQ_BAND1,
173 MT7996_TXQ_MCU_WA,
174 MT7996_TXQ_BAND2,
175 };
176
177 enum mt7996_rxq_id {
178 MT7996_RXQ_MCU_WM = 0,
179 MT7996_RXQ_MCU_WA,
180 MT7996_RXQ_MCU_WA_MAIN = 2,
181 MT7996_RXQ_MCU_WA_EXT = 3, /* for mt7992 */
182 MT7996_RXQ_MCU_WA_TRI = 3,
183 MT7996_RXQ_BAND0 = 4,
184 MT7996_RXQ_BAND1 = 5, /* for mt7992 */
185 MT7996_RXQ_BAND2 = 5,
186 MT7996_RXQ_RRO_BAND0 = 8,
187 MT7996_RXQ_RRO_BAND1 = 9,
188 MT7996_RXQ_RRO_BAND2 = 6,
189 MT7996_RXQ_MSDU_PG_BAND0 = 10,
190 MT7996_RXQ_MSDU_PG_BAND1 = 11,
191 MT7996_RXQ_MSDU_PG_BAND2 = 12,
192 MT7996_RXQ_TXFREE0 = 9,
193 MT7996_RXQ_TXFREE1 = 9,
194 MT7996_RXQ_TXFREE2 = 7,
195 MT7996_RXQ_RRO_IND = 0,
196 MT7996_RXQ_RRO_RXDMAD_C = 0,
197 MT7990_RXQ_TXFREE0 = 6,
198 MT7990_RXQ_TXFREE1 = 7,
199 };
200
201 struct mt7996_twt_flow {
202 struct list_head list;
203 u64 start_tsf;
204 u64 tsf;
205 u32 duration;
206 u16 wcid;
207 __le16 mantissa;
208 u8 exp;
209 u8 table_id;
210 u8 id;
211 u8 protection:1;
212 u8 flowtype:1;
213 u8 trigger:1;
214 u8 sched:1;
215 };
216
217 DECLARE_EWMA(avg_signal, 10, 8)
218
219 struct mt7996_sta_link {
220 struct mt76_wcid wcid; /* must be first */
221
222 struct mt7996_sta *sta;
223
224 struct list_head rc_list;
225 u32 airtime_ac[8];
226
227 int ack_signal;
228 struct ewma_avg_signal avg_ack_signal;
229
230 unsigned long changed;
231
232 struct mt76_connac_sta_key_conf bip;
233
234 struct {
235 u8 flowid_mask;
236 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT];
237 } twt;
238
239 struct rcu_head rcu_head;
240 };
241
242 struct mt7996_sta {
243 struct mt7996_sta_link deflink; /* must be first */
244 struct mt7996_sta_link __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS];
245 u8 deflink_id;
246
247 struct mt7996_vif *vif;
248 };
249
250 struct mt7996_vif_link {
251 struct mt76_vif_link mt76; /* must be first */
252
253 struct mt7996_sta_link msta_link;
254 struct mt7996_phy *phy;
255
256 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];
257 struct cfg80211_bitrate_mask bitrate_mask;
258
259 u8 mld_idx;
260 };
261
262 struct mt7996_vif {
263 struct mt7996_vif_link deflink; /* must be first */
264 struct mt76_vif_data mt76;
265
266 u8 mld_group_idx;
267 u8 mld_remap_idx;
268 };
269
270 /* crash-dump */
271 struct mt7996_crash_data {
272 guid_t guid;
273 struct timespec64 timestamp;
274
275 u8 *memdump_buf;
276 size_t memdump_buf_len;
277 };
278
279 struct mt7996_hif {
280 struct list_head list;
281
282 struct device *dev;
283 void __iomem *regs;
284 int irq;
285
286 enum pci_bus_speed speed;
287 enum pcie_link_width width;
288 };
289
290 #define WED_RRO_ADDR_SIGNATURE_MASK GENMASK(31, 24)
291 #define WED_RRO_ADDR_COUNT_MASK GENMASK(14, 4)
292 #define WED_RRO_ADDR_HEAD_HIGH_MASK GENMASK(3, 0)
293 struct mt7996_wed_rro_addr {
294 __le32 head_low;
295 __le32 data;
296 };
297
298 struct mt7996_wed_rro_session_id {
299 struct list_head list;
300 u16 id;
301 };
302
303 struct mt7996_msdu_page {
304 struct list_head list;
305
306 struct mt76_queue *q;
307 dma_addr_t dma_addr;
308 void *buf;
309 };
310
311 /* data1 */
312 #define RRO_HIF_DATA1_LS_MASK BIT(30)
313 #define RRO_HIF_DATA1_SDL_MASK GENMASK(29, 16)
314 /* data4 */
315 #define RRO_HIF_DATA4_RX_TOKEN_ID_MASK GENMASK(15, 0)
316 struct mt7996_rro_hif {
317 __le32 data0;
318 __le32 data1;
319 __le32 data2;
320 __le32 data3;
321 __le32 data4;
322 __le32 data5;
323 };
324
325 #define MSDU_PAGE_INFO_OWNER_MASK BIT(31)
326 #define MSDU_PAGE_INFO_PG_HIGH_MASK GENMASK(3, 0)
327 struct mt7996_msdu_page_info {
328 struct mt7996_rro_hif rxd[MT7996_MAX_HIF_RXD_IN_PG];
329 __le32 pg_low;
330 __le32 data;
331 };
332
333 #define MT7996_MAX_RRO_RRS_RING 4
334 struct mt7996_rro_queue_regs_emi {
335 struct {
336 __le16 idx;
337 __le16 rsv;
338 } ring[MT7996_MAX_RRO_RRS_RING];
339 };
340
341 struct mt7996_phy {
342 struct mt76_phy *mt76;
343 struct mt7996_dev *dev;
344
345 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
346
347 struct thermal_cooling_device *cdev;
348 u8 cdev_state;
349 u8 throttle_state;
350 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */
351
352 u32 rxfilter;
353 u64 omac_mask;
354
355 u16 noise;
356
357 s16 coverage_class;
358 u8 slottime;
359
360 u16 beacon_rate;
361
362 u32 rx_ampdu_ts;
363 u32 ampdu_ref;
364 int txpower;
365
366 struct mt76_mib_stats mib;
367 struct mt76_channel_state state_ts;
368
369 u16 orig_chainmask;
370 u16 orig_antenna_mask;
371
372 bool has_aux_rx;
373 bool counter_reset;
374 };
375
376 struct mt7996_dev {
377 union { /* must be first */
378 struct mt76_dev mt76;
379 struct mt76_phy mphy;
380 };
381
382 struct mt7996_phy *radio_phy[MT7996_MAX_RADIOS];
383 struct wiphy_radio radios[MT7996_MAX_RADIOS];
384 struct wiphy_radio_freq_range radio_freqs[MT7996_MAX_RADIOS];
385
386 struct mt7996_hif *hif2;
387 struct mt7996_reg_desc reg;
388 u8 q_id[MT7996_MAX_QUEUE];
389 u32 q_int_mask[MT7996_MAX_QUEUE];
390 u32 q_wfdma_mask;
391
392 u64 mld_idx_mask;
393 u64 mld_remap_idx_mask;
394
395 const struct mt76_bus_ops *bus_ops;
396 struct mt7996_phy phy;
397
398 /* monitor rx chain configured channel */
399 struct cfg80211_chan_def rdd2_chandef;
400 struct mt7996_phy *rdd2_phy;
401
402 u16 chainmask;
403 u8 chainshift[__MT_MAX_BAND];
404 u32 hif_idx;
405
406 struct work_struct init_work;
407 struct work_struct rc_work;
408 struct work_struct dump_work;
409 struct work_struct reset_work;
410 wait_queue_head_t reset_wait;
411 struct {
412 u32 state;
413 u32 wa_reset_count;
414 u32 wm_reset_count;
415 bool hw_full_reset:1;
416 bool hw_init_done:1;
417 bool restart:1;
418 } recovery;
419
420 /* protects coredump data */
421 struct mutex dump_mutex;
422 #ifdef CONFIG_DEV_COREDUMP
423 struct {
424 struct mt7996_crash_data *crash_data;
425 } coredump;
426 #endif
427
428 struct list_head sta_rc_list;
429 struct list_head twt_list;
430
431 u32 hw_pattern;
432
433 bool flash_mode:1;
434 bool has_eht:1;
435
436 struct {
437 struct {
438 void *ptr;
439 dma_addr_t phy_addr;
440 } ba_bitmap[MT7996_RRO_BA_BITMAP_LEN];
441 struct {
442 void *ptr;
443 dma_addr_t phy_addr;
444 } addr_elem[MT7996_RRO_ADDR_ELEM_LEN];
445 struct {
446 void *ptr;
447 dma_addr_t phy_addr;
448 } session;
449 struct {
450 void *ptr;
451 dma_addr_t phy_addr;
452 } msdu_pg[MT7996_RRO_MSDU_PG_CR_CNT];
453 struct {
454 struct mt7996_rro_queue_regs_emi *ptr;
455 dma_addr_t phy_addr;
456 } emi_rings_cpu;
457 struct {
458 struct mt7996_rro_queue_regs_emi *ptr;
459 dma_addr_t phy_addr;
460 } emi_rings_dma;
461
462 struct work_struct work;
463 struct list_head poll_list;
464 spinlock_t lock;
465
466 struct list_head page_cache;
467 struct list_head page_map[MT7996_RRO_MSDU_PG_HASH_SIZE];
468 } wed_rro;
469
470 bool ibf;
471 u8 fw_debug_wm;
472 u8 fw_debug_wa;
473 u8 fw_debug_bin;
474 u16 fw_debug_seq;
475
476 struct dentry *debugfs_dir;
477 struct rchan *relay_fwlog;
478
479 struct {
480 u16 table_mask;
481 u8 n_agrt;
482 } twt;
483
484 spinlock_t reg_lock;
485
486 u8 wtbl_size_group;
487 struct {
488 u8 type:4;
489 u8 fem:4;
490 } var;
491 };
492
493 enum {
494 WFDMA0 = 0x0,
495 WFDMA1,
496 WFDMA_EXT,
497 __MT_WFDMA_MAX,
498 };
499
500 enum rdd_idx {
501 MT_RDD_IDX_BAND2, /* RDD idx for band idx 2 */
502 MT_RDD_IDX_BAND1, /* RDD idx for band idx 1 */
503 MT_RDD_IDX_BACKGROUND, /* RDD idx for background chain */
504 };
505
506 enum mt7996_rdd_cmd {
507 RDD_STOP,
508 RDD_START,
509 RDD_DET_MODE,
510 RDD_RADAR_EMULATE,
511 RDD_START_TXQ = 20,
512 RDD_CAC_START = 50,
513 RDD_CAC_END,
514 RDD_NORMAL_START,
515 RDD_DISABLE_DFS_CAL,
516 RDD_PULSE_DBG,
517 RDD_READ_PULSE,
518 RDD_RESUME_BF,
519 RDD_IRQ_OFF,
520 };
521
522 static inline int
mt7996_get_rdd_idx(struct mt7996_phy * phy,bool is_background)523 mt7996_get_rdd_idx(struct mt7996_phy *phy, bool is_background)
524 {
525 if (!phy->mt76->cap.has_5ghz)
526 return -1;
527
528 if (is_background)
529 return MT_RDD_IDX_BACKGROUND;
530
531 if (phy->mt76->band_idx == MT_BAND2)
532 return MT_RDD_IDX_BAND2;
533
534 return MT_RDD_IDX_BAND1;
535 }
536
537 static inline struct mt7996_dev *
mt7996_hw_dev(struct ieee80211_hw * hw)538 mt7996_hw_dev(struct ieee80211_hw *hw)
539 {
540 struct mt76_phy *phy = hw->priv;
541
542 return container_of(phy->dev, struct mt7996_dev, mt76);
543 }
544
545 static inline struct mt7996_phy *
__mt7996_phy(struct mt7996_dev * dev,enum mt76_band_id band)546 __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band)
547 {
548 struct mt76_phy *phy = dev->mt76.phys[band];
549
550 if (!phy)
551 return NULL;
552
553 return phy->priv;
554 }
555
556 static inline struct mt7996_phy *
mt7996_phy2(struct mt7996_dev * dev)557 mt7996_phy2(struct mt7996_dev *dev)
558 {
559 return __mt7996_phy(dev, MT_BAND1);
560 }
561
562 static inline struct mt7996_phy *
mt7996_phy3(struct mt7996_dev * dev)563 mt7996_phy3(struct mt7996_dev *dev)
564 {
565 return __mt7996_phy(dev, MT_BAND2);
566 }
567
568 static inline bool
mt7996_band_valid(struct mt7996_dev * dev,u8 band)569 mt7996_band_valid(struct mt7996_dev *dev, u8 band)
570 {
571 if (!is_mt7996(&dev->mt76))
572 return band <= MT_BAND1;
573
574 return band <= MT_BAND2;
575 }
576
577 static inline struct mt7996_phy *
mt7996_band_phy(struct mt7996_dev * dev,enum nl80211_band band)578 mt7996_band_phy(struct mt7996_dev *dev, enum nl80211_band band)
579 {
580 struct mt76_phy *mphy;
581
582 mphy = dev->mt76.band_phys[band];
583 if (!mphy)
584 return NULL;
585
586 return mphy->priv;
587 }
588
589 static inline struct mt7996_vif_link *
mt7996_vif_link(struct mt7996_dev * dev,struct ieee80211_vif * vif,int link_id)590 mt7996_vif_link(struct mt7996_dev *dev, struct ieee80211_vif *vif, int link_id)
591 {
592 return (struct mt7996_vif_link *)mt76_vif_link(&dev->mt76, vif, link_id);
593 }
594
595 static inline struct mt7996_phy *
mt7996_vif_link_phy(struct mt7996_vif_link * link)596 mt7996_vif_link_phy(struct mt7996_vif_link *link)
597 {
598 struct mt76_phy *mphy = mt76_vif_link_phy(&link->mt76);
599
600 if (!mphy)
601 return NULL;
602
603 return mphy->priv;
604 }
605
606 static inline struct mt7996_vif_link *
mt7996_vif_conf_link(struct mt7996_dev * dev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * link_conf)607 mt7996_vif_conf_link(struct mt7996_dev *dev, struct ieee80211_vif *vif,
608 struct ieee80211_bss_conf *link_conf)
609 {
610 return (struct mt7996_vif_link *)mt76_vif_conf_link(&dev->mt76, vif,
611 link_conf);
612 }
613
614 #define mt7996_for_each_phy(dev, phy) \
615 for (int __i = 0; __i < ARRAY_SIZE((dev)->radio_phy); __i++) \
616 if (((phy) = (dev)->radio_phy[__i]) != NULL)
617
618 extern const struct ieee80211_ops mt7996_ops;
619 extern struct pci_driver mt7996_pci_driver;
620 extern struct pci_driver mt7996_hif_driver;
621
622 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev,
623 void __iomem *mem_base, u32 device_id);
624 void mt7996_rro_hw_init(struct mt7996_dev *dev);
625 void mt7996_wfsys_reset(struct mt7996_dev *dev);
626 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance);
627 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif_link *link);
628 int mt7996_register_device(struct mt7996_dev *dev);
629 void mt7996_unregister_device(struct mt7996_dev *dev);
630 int mt7996_vif_link_add(struct mt76_phy *mphy, struct ieee80211_vif *vif,
631 struct ieee80211_bss_conf *link_conf,
632 struct mt76_vif_link *mlink);
633 void mt7996_vif_link_remove(struct mt76_phy *mphy, struct ieee80211_vif *vif,
634 struct ieee80211_bss_conf *link_conf,
635 struct mt76_vif_link *mlink);
636 int mt7996_eeprom_init(struct mt7996_dev *dev);
637 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy);
638 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev,
639 struct ieee80211_channel *chan);
640 s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band);
641 bool mt7996_eeprom_has_background_radar(struct mt7996_dev *dev);
642 int mt7996_dma_init(struct mt7996_dev *dev);
643 void mt7996_dma_reset(struct mt7996_dev *dev, bool force);
644 void mt7996_dma_prefetch(struct mt7996_dev *dev);
645 void mt7996_dma_cleanup(struct mt7996_dev *dev);
646 void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset);
647 int mt7996_init_tx_queues(struct mt7996_phy *phy, int idx,
648 int n_desc, int ring_base, struct mtk_wed_device *wed);
649 void mt7996_init_txpower(struct mt7996_phy *phy);
650 int mt7996_txbf_init(struct mt7996_dev *dev);
651 void mt7996_reset(struct mt7996_dev *dev);
652 int mt7996_run(struct mt7996_phy *phy);
653 int mt7996_mcu_init(struct mt7996_dev *dev);
654 int mt7996_mcu_init_firmware(struct mt7996_dev *dev);
655 int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev,
656 struct mt7996_vif_link *link,
657 struct mt7996_twt_flow *flow,
658 int cmd);
659 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, struct ieee80211_vif *vif,
660 struct ieee80211_bss_conf *link_conf,
661 struct mt76_vif_link *mlink, bool enable);
662 int mt7996_mcu_add_bss_info(struct mt7996_phy *phy, struct ieee80211_vif *vif,
663 struct ieee80211_bss_conf *link_conf,
664 struct mt76_vif_link *mlink,
665 struct mt7996_sta_link *msta_link, int enable);
666 int mt7996_mcu_add_sta(struct mt7996_dev *dev,
667 struct ieee80211_bss_conf *link_conf,
668 struct ieee80211_link_sta *link_sta,
669 struct mt7996_vif_link *link,
670 struct mt7996_sta_link *msta_link,
671 int conn_state, bool newly);
672 int mt7996_mcu_teardown_mld_sta(struct mt7996_dev *dev,
673 struct mt7996_vif_link *link,
674 struct mt7996_sta_link *msta_link);
675 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev,
676 struct ieee80211_ampdu_params *params,
677 struct ieee80211_vif *vif, bool enable);
678 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev,
679 struct ieee80211_ampdu_params *params,
680 struct ieee80211_vif *vif, bool enable);
681 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev,
682 struct mt76_vif_link *mlink,
683 struct cfg80211_he_bss_color *he_bss_color);
684 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
685 struct ieee80211_bss_conf *link_conf, bool enabled);
686 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev,
687 struct ieee80211_bss_conf *link_conf,
688 struct mt7996_vif_link *link, u32 changed);
689 int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy,
690 struct mt7996_vif_link *link,
691 struct ieee80211_he_obss_pd *he_obss_pd);
692 int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct mt7996_sta *msta,
693 struct ieee80211_vif *vif, u8 link_id,
694 bool changed);
695 int mt7996_set_channel(struct mt76_phy *mphy);
696 int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag);
697 int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif,
698 struct ieee80211_bss_conf *link_conf);
699 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev,
700 void *data, u16 version);
701 int mt7996_mcu_set_fixed_field(struct mt7996_dev *dev, struct mt7996_sta *msta,
702 void *data, u8 link_id, u32 field);
703 int mt7996_mcu_set_eeprom(struct mt7996_dev *dev);
704 int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset, u8 *buf, u32 buf_len);
705 int mt7996_mcu_get_eeprom_free_block(struct mt7996_dev *dev, u8 *block_num);
706 int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap);
707 int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band);
708 int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action);
709 int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val);
710 int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev,
711 const struct mt7996_dfs_pulse *pulse);
712 int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index,
713 const struct mt7996_dfs_pattern *pattern);
714 int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable);
715 int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val);
716 int mt7996_mcu_set_timing(struct mt7996_phy *phy, struct ieee80211_vif *vif,
717 struct ieee80211_bss_conf *link_conf);
718 int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch);
719 int mt7996_mcu_get_temperature(struct mt7996_phy *phy);
720 int mt7996_mcu_set_thermal_throttling(struct mt7996_phy *phy, u8 state);
721 int mt7996_mcu_set_thermal_protect(struct mt7996_phy *phy, bool enable);
722 int mt7996_mcu_set_txpower_sku(struct mt7996_phy *phy);
723 int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 rdd_idx, u8 val);
724 int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy,
725 struct cfg80211_chan_def *chandef);
726 int mt7996_mcu_set_fixed_rate_table(struct mt7996_phy *phy, u8 table_idx,
727 u16 rate_idx, bool beacon);
728 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set);
729 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans);
730 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val);
731 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);
732 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl);
733 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level);
734 int mt7996_mcu_trigger_assert(struct mt7996_dev *dev);
735 void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb);
736 void mt7996_mcu_exit(struct mt7996_dev *dev);
737 int mt7996_mcu_get_all_sta_info(struct mt7996_phy *phy, u16 tag);
738 int mt7996_mcu_wed_rro_reset_sessions(struct mt7996_dev *dev, u16 id);
739 int mt7996_mcu_set_sniffer_mode(struct mt7996_phy *phy, bool enabled);
740
mt7996_has_hwrro(struct mt7996_dev * dev)741 static inline bool mt7996_has_hwrro(struct mt7996_dev *dev)
742 {
743 return dev->mt76.hwrro_mode != MT76_HWRRO_OFF;
744 }
745
mt7996_max_interface_num(struct mt7996_dev * dev)746 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev)
747 {
748 return min(MT7996_MAX_INTERFACES * (1 + mt7996_band_valid(dev, MT_BAND1) +
749 mt7996_band_valid(dev, MT_BAND2)),
750 MT7996_WTBL_BMC_SIZE);
751 }
752
mt7996_wtbl_size(struct mt7996_dev * dev)753 static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev)
754 {
755 return (dev->wtbl_size_group << 8) + MT7996_WTBL_BMC_SIZE;
756 }
757
758 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg,
759 u32 clear, u32 set);
760
mt7996_irq_enable(struct mt7996_dev * dev,u32 mask)761 static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask)
762 {
763 if (dev->hif2)
764 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask);
765 else
766 mt76_set_irq_mask(&dev->mt76, 0, 0, mask);
767
768 tasklet_schedule(&dev->mt76.irq_tasklet);
769 }
770
mt7996_irq_disable(struct mt7996_dev * dev,u32 mask)771 static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask)
772 {
773 if (dev->hif2)
774 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0);
775 else
776 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
777 }
778
779 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset,
780 size_t len);
781
mt7996_rx_chainmask(struct mt7996_phy * phy)782 static inline u16 mt7996_rx_chainmask(struct mt7996_phy *phy)
783 {
784 int max_nss = hweight8(phy->mt76->hw->wiphy->available_antennas_tx);
785 int cur_nss = hweight8(phy->mt76->antenna_mask);
786 u16 tx_chainmask = phy->mt76->chainmask;
787
788 if (cur_nss != max_nss)
789 return tx_chainmask;
790
791 return tx_chainmask | (BIT(fls(tx_chainmask)) * phy->has_aux_rx);
792 }
793
mt7996_has_wa(struct mt7996_dev * dev)794 static inline bool mt7996_has_wa(struct mt7996_dev *dev)
795 {
796 return !is_mt7990(&dev->mt76);
797 }
798
799 void mt7996_mac_init(struct mt7996_dev *dev);
800 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw);
801 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask);
802 void mt7996_mac_reset_counters(struct mt7996_phy *phy);
803 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy);
804 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band);
805 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
806 struct sk_buff *skb, struct mt76_wcid *wcid,
807 struct ieee80211_key_conf *key, int pid,
808 enum mt76_txq_id qid, u32 changed);
809 void mt7996_mac_update_beacons(struct mt7996_phy *phy);
810 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy);
811 void mt7996_mac_work(struct work_struct *work);
812 void mt7996_mac_reset_work(struct work_struct *work);
813 void mt7996_mac_dump_work(struct work_struct *work);
814 void mt7996_mac_sta_rc_work(struct work_struct *work);
815 void mt7996_mac_update_stats(struct mt7996_phy *phy);
816 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev,
817 struct mt7996_vif_link *link,
818 struct mt7996_sta_link *msta_link,
819 u8 flowid);
820 void mt7996_mac_sta_deinit_link(struct mt7996_dev *dev,
821 struct mt7996_sta_link *msta_link);
822 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw,
823 struct ieee80211_sta *sta,
824 struct ieee80211_twt_setup *twt);
825 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
826 enum mt76_txq_id qid, struct mt76_wcid *wcid,
827 struct ieee80211_sta *sta,
828 struct mt76_tx_info *tx_info);
829 void mt7996_tx_token_put(struct mt7996_dev *dev);
830 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
831 struct sk_buff *skb, u32 *info);
832 void mt7996_rro_msdu_page_map_free(struct mt7996_dev *dev);
833 int mt7996_rro_msdu_page_add(struct mt76_dev *mdev, struct mt76_queue *q,
834 dma_addr_t dma_addr, void *data);
835 void mt7996_rro_rx_process(struct mt76_dev *mdev, void *data);
836 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len);
837 void mt7996_stats_work(struct work_struct *work);
838 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force);
839 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy);
840 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy);
841 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy);
842 void mt7996_update_channel(struct mt76_phy *mphy);
843 int mt7996_init_debugfs(struct mt7996_dev *dev);
844 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len);
845 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len);
846 int mt7996_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
847 struct ieee80211_key_conf *key, int mcu_cmd,
848 struct mt76_wcid *wcid, enum set_key_cmd cmd);
849 int mt7996_mcu_bcn_prot_enable(struct mt7996_dev *dev,
850 struct mt7996_vif_link *link,
851 struct mt7996_sta_link *msta_link,
852 struct ieee80211_key_conf *key);
853 int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev,
854 struct ieee80211_vif *vif,
855 struct mt7996_vif_link *link,
856 struct mt7996_sta_link *msta_link);
857 int mt7996_mcu_cp_support(struct mt7996_dev *dev, u8 mode);
858 #ifdef CONFIG_MAC80211_DEBUGFS
859 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
860 struct ieee80211_sta *sta, struct dentry *dir);
861 #endif
862 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
863 bool hif2, int *irq);
864 u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
865
866 #ifdef CONFIG_MTK_DEBUG
867 int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir);
868 #endif
869
870 int mt7996_dma_rro_init(struct mt7996_dev *dev);
871
872 #endif
873