1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_VIS_SIMULATOR_H 27 #define _SYS_VIS_SIMULATOR_H 28 29 /* 30 * VIS opf codes, instruction type 31 */ 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* kstat structure for reporting kstats */ 38 extern struct visinfo_kstat visinfo; 39 40 typedef /* typical VIS instruction. */ 41 struct { 42 unsigned int op : 2; /* Top two bits. */ 43 unsigned int rd : 5; /* Destination. */ 44 unsigned int op3 : 6; /* Main op code. */ 45 unsigned int rs1 : 5; /* First operand. */ 46 unsigned int opf : 9; /* Floating-point op code. */ 47 unsigned int rs2 : 5; /* Second operand. */ 48 } vis_inst_type; 49 50 enum vis_opf { /* VIS opf codes. */ 51 edge8 = 0x0, 52 edge8n = 0x1, 53 edge8l = 0x2, 54 edge8ln = 0x3, 55 edge16 = 0x4, 56 edge16n = 0x5, 57 edge16l = 0x6, 58 edge16ln = 0x7, 59 edge32 = 0x8, 60 edge32n = 0x9, 61 edge32l = 0xa, 62 edge32ln = 0xb, 63 array8 = 0x10, 64 array16 = 0x12, 65 array32 = 0x14, 66 alignaddr = 0x18, 67 bmask = 0x19, 68 alignaddrl = 0x1a, 69 fcmple16 = 0x20, 70 fcmpne16 = 0x22, 71 fcmple32 = 0x24, 72 fcmpne32 = 0x26, 73 fcmpgt16 = 0x28, 74 fcmpeq16 = 0x2a, 75 fcmpgt32 = 0x2c, 76 fcmpeq32 = 0x2e, 77 fmul8x16 = 0x31, 78 fmul8x16au = 0x33, 79 fmul8x16al = 0x35, 80 fmul8sux16 = 0x36, 81 fmul8ulx16 = 0x37, 82 fmuld8sux16 = 0x38, 83 fmuld8ulx16 = 0x39, 84 fpack32 = 0x3a, 85 fpack16 = 0x3b, 86 fpackfix = 0x3d, 87 pdist = 0x3e, 88 pdistn = 0x3f, 89 faligndata = 0x48, 90 fpmerge = 0x4b, 91 bshuffle = 0x4c, 92 fexpand = 0x4d, 93 fpadd16 = 0x50, 94 fpadd16s = 0x51, 95 fpadd32 = 0x52, 96 fpadd32s = 0x53, 97 fpsub16 = 0x54, 98 fpsub16s = 0x55, 99 fpsub32 = 0x56, 100 fpsub32s = 0x57, 101 fzero = 0x60, 102 fzeros = 0x61, 103 fnor = 0x62, 104 fnors = 0x63, 105 fandnot2 = 0x64, 106 fandnot2s = 0x65, 107 fnot2 = 0x66, 108 fnot2s = 0x67, 109 fandnot1 = 0x68, 110 fandnot1s = 0x69, 111 fnot1 = 0x6a, 112 fnot1s = 0x6b, 113 fxor = 0x6c, 114 fxors = 0x6d, 115 fnand = 0x6e, 116 fnands = 0x6f, 117 fand = 0x70, 118 fands = 0x71, 119 fxnor = 0x72, 120 fxnors = 0x73, 121 fsrc1 = 0x74, 122 fsrc1s = 0x75, 123 fornot2 = 0x76, 124 fornot2s = 0x77, 125 fsrc2 = 0x78, 126 fsrc2s = 0x79, 127 fornot1 = 0x7a, 128 fornot1s = 0x7b, 129 for_op = 0x7c, /* compiler does not like the use */ 130 fors_op = 0x7d, /* of the key word "for" ! */ 131 fone = 0x7e, 132 fones = 0x7f, 133 siam = 0x81 134 }; 135 136 #define GSR_ALIGN_MASK UINT64_C(0x0000000000000007) 137 #define GSR_ALIGN_SHIFT 0 138 #define GSR_SCALE_MASK UINT64_C(0x00000000000000f8) 139 #define GSR_SCALE_SHIFT 3 140 #define GSR_IRND_MASK UINT64_C(0x0000000006000000) 141 #define GSR_IRND_SHIFT 25 142 #define GSR_IM_MASK UINT64_C(0x0000000008000000) 143 #define GSR_IM_SHIFT 27 144 #define GSR_MASK_MASK UINT64_C(0xffffffff00000000) 145 #define GSR_MASK_SHIFT 32 146 147 #define GSR_IM_IRND_MASK (GSR_IM_MASK | GSR_IRND_MASK) 148 #define GSR_ALIGN(gsr) ((gsr & GSR_ALIGN_MASK) >> GSR_ALIGN_SHIFT) 149 #define GSR_SCALE(gsr) ((gsr & GSR_SCALE_MASK) >> GSR_SCALE_SHIFT) 150 #define GSR_IRND(gsr) ((gsr & GSR_IRND_MASK) >> GSR_IRND_SHIFT) 151 #define GSR_IM(gsr) ((gsr & GSR_IM_MASK) >> GSR_IM_SHIFT) 152 #define GSR_MASK(gsr) ((gsr & GSR_MASK_MASK) >> GSR_MASK_SHIFT) 153 154 /* PUBLIC FUNCTIONS */ 155 156 /* 157 * vis_fpu_simulator simulates VIS FPU instructions only; reads and writes 158 * FPU data registers directly. 159 */ 160 161 extern enum ftt_type vis_fpu_simulator(fp_simd_type *, fp_inst_type, 162 struct regs *, void *, kfpu_t *); 163 164 /* 165 * Simulator for VIS loads and stores between floating-point unit and memory. 166 */ 167 enum ftt_type vis_fldst(fp_simd_type *, fp_inst_type, struct regs *, 168 void *, unsigned); 169 170 /* 171 * Simulator for rd %gsr instruction. 172 */ 173 enum ftt_type vis_rdgsr(fp_simd_type *, fp_inst_type, struct regs *, 174 void *, kfpu_t *); 175 176 /* 177 * Simulator for wr %gsr instruction. 178 */ 179 enum ftt_type vis_wrgsr(fp_simd_type *, fp_inst_type, struct regs *, 180 void *, kfpu_t *); 181 182 #ifdef __cplusplus 183 } 184 #endif 185 186 #endif /* _SYS_VIS_SIMULATOR_H */ 187