1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2016 - Linaro and Columbia University
4 * Author: Jintack Lim <jintack.lim@linaro.org>
5 */
6
7 #include <linux/kvm.h>
8 #include <linux/kvm_host.h>
9
10 #include <asm/kvm_emulate.h>
11 #include <asm/kvm_nested.h>
12
13 #include "hyp/include/hyp/adjust_pc.h"
14
15 #include "trace.h"
16
17 enum trap_behaviour {
18 BEHAVE_HANDLE_LOCALLY = 0,
19
20 BEHAVE_FORWARD_READ = BIT(0),
21 BEHAVE_FORWARD_WRITE = BIT(1),
22 BEHAVE_FORWARD_RW = BEHAVE_FORWARD_READ | BEHAVE_FORWARD_WRITE,
23
24 /* Traps that take effect in Host EL0, this is rare! */
25 BEHAVE_FORWARD_IN_HOST_EL0 = BIT(2),
26 };
27
28 struct trap_bits {
29 const enum vcpu_sysreg index;
30 const enum trap_behaviour behaviour;
31 const u64 value;
32 const u64 mask;
33 };
34
35 /* Coarse Grained Trap definitions */
36 enum cgt_group_id {
37 /* Indicates no coarse trap control */
38 __RESERVED__,
39
40 /*
41 * The first batch of IDs denote coarse trapping that are used
42 * on their own instead of being part of a combination of
43 * trap controls.
44 */
45 CGT_HCR_TID1,
46 CGT_HCR_TID2,
47 CGT_HCR_TID3,
48 CGT_HCR_IMO,
49 CGT_HCR_FMO,
50 CGT_HCR_TIDCP,
51 CGT_HCR_TACR,
52 CGT_HCR_TSW,
53 CGT_HCR_TPC,
54 CGT_HCR_TPU,
55 CGT_HCR_TTLB,
56 CGT_HCR_TVM,
57 CGT_HCR_TDZ,
58 CGT_HCR_TRVM,
59 CGT_HCR_TLOR,
60 CGT_HCR_TERR,
61 CGT_HCR_APK,
62 CGT_HCR_NV,
63 CGT_HCR_NV_nNV2,
64 CGT_HCR_NV1_nNV2,
65 CGT_HCR_AT,
66 CGT_HCR_nFIEN,
67 CGT_HCR_TID4,
68 CGT_HCR_TICAB,
69 CGT_HCR_TOCU,
70 CGT_HCR_ENSCXT,
71 CGT_HCR_TTLBIS,
72 CGT_HCR_TTLBOS,
73
74 CGT_MDCR_TPMCR,
75 CGT_MDCR_TPM,
76 CGT_MDCR_TDE,
77 CGT_MDCR_TDA,
78 CGT_MDCR_TDOSA,
79 CGT_MDCR_TDRA,
80 CGT_MDCR_E2PB,
81 CGT_MDCR_TPMS,
82 CGT_MDCR_TTRF,
83 CGT_MDCR_E2TB,
84 CGT_MDCR_TDCC,
85
86 CGT_CPTR_TAM,
87 CGT_CPTR_TCPAC,
88
89 CGT_HCRX_EnFPM,
90 CGT_HCRX_TCR2En,
91
92 CGT_CNTHCTL_EL1TVT,
93 CGT_CNTHCTL_EL1TVCT,
94
95 CGT_ICH_HCR_TC,
96 CGT_ICH_HCR_TALL0,
97 CGT_ICH_HCR_TALL1,
98 CGT_ICH_HCR_TDIR,
99
100 /*
101 * Anything after this point is a combination of coarse trap
102 * controls, which must all be evaluated to decide what to do.
103 */
104 __MULTIPLE_CONTROL_BITS__,
105 CGT_HCR_IMO_FMO_ICH_HCR_TC = __MULTIPLE_CONTROL_BITS__,
106 CGT_HCR_TID2_TID4,
107 CGT_HCR_TTLB_TTLBIS,
108 CGT_HCR_TTLB_TTLBOS,
109 CGT_HCR_TVM_TRVM,
110 CGT_HCR_TVM_TRVM_HCRX_TCR2En,
111 CGT_HCR_TPU_TICAB,
112 CGT_HCR_TPU_TOCU,
113 CGT_HCR_NV1_nNV2_ENSCXT,
114 CGT_MDCR_TPM_TPMCR,
115 CGT_MDCR_TPM_HPMN,
116 CGT_MDCR_TDE_TDA,
117 CGT_MDCR_TDE_TDOSA,
118 CGT_MDCR_TDE_TDRA,
119 CGT_MDCR_TDCC_TDE_TDA,
120
121 CGT_ICH_HCR_TC_TDIR,
122
123 /*
124 * Anything after this point requires a callback evaluating a
125 * complex trap condition. Ugly stuff.
126 */
127 __COMPLEX_CONDITIONS__,
128 CGT_CNTHCTL_EL1PCTEN = __COMPLEX_CONDITIONS__,
129 CGT_CNTHCTL_EL1PTEN,
130 CGT_CNTHCTL_EL1NVPCT,
131 CGT_CNTHCTL_EL1NVVCT,
132
133 CGT_CPTR_TTA,
134 CGT_MDCR_HPMN,
135
136 /* Must be last */
137 __NR_CGT_GROUP_IDS__
138 };
139
140 static const struct trap_bits coarse_trap_bits[] = {
141 [CGT_HCR_TID1] = {
142 .index = HCR_EL2,
143 .value = HCR_TID1,
144 .mask = HCR_TID1,
145 .behaviour = BEHAVE_FORWARD_READ,
146 },
147 [CGT_HCR_TID2] = {
148 .index = HCR_EL2,
149 .value = HCR_TID2,
150 .mask = HCR_TID2,
151 .behaviour = BEHAVE_FORWARD_RW,
152 },
153 [CGT_HCR_TID3] = {
154 .index = HCR_EL2,
155 .value = HCR_TID3,
156 .mask = HCR_TID3,
157 .behaviour = BEHAVE_FORWARD_READ,
158 },
159 [CGT_HCR_IMO] = {
160 .index = HCR_EL2,
161 .value = HCR_IMO,
162 .mask = HCR_IMO,
163 .behaviour = BEHAVE_FORWARD_WRITE,
164 },
165 [CGT_HCR_FMO] = {
166 .index = HCR_EL2,
167 .value = HCR_FMO,
168 .mask = HCR_FMO,
169 .behaviour = BEHAVE_FORWARD_WRITE,
170 },
171 [CGT_HCR_TIDCP] = {
172 .index = HCR_EL2,
173 .value = HCR_TIDCP,
174 .mask = HCR_TIDCP,
175 .behaviour = BEHAVE_FORWARD_RW,
176 },
177 [CGT_HCR_TACR] = {
178 .index = HCR_EL2,
179 .value = HCR_TACR,
180 .mask = HCR_TACR,
181 .behaviour = BEHAVE_FORWARD_RW,
182 },
183 [CGT_HCR_TSW] = {
184 .index = HCR_EL2,
185 .value = HCR_TSW,
186 .mask = HCR_TSW,
187 .behaviour = BEHAVE_FORWARD_RW,
188 },
189 [CGT_HCR_TPC] = { /* Also called TCPC when FEAT_DPB is implemented */
190 .index = HCR_EL2,
191 .value = HCR_TPC,
192 .mask = HCR_TPC,
193 .behaviour = BEHAVE_FORWARD_RW,
194 },
195 [CGT_HCR_TPU] = {
196 .index = HCR_EL2,
197 .value = HCR_TPU,
198 .mask = HCR_TPU,
199 .behaviour = BEHAVE_FORWARD_RW,
200 },
201 [CGT_HCR_TTLB] = {
202 .index = HCR_EL2,
203 .value = HCR_TTLB,
204 .mask = HCR_TTLB,
205 .behaviour = BEHAVE_FORWARD_RW,
206 },
207 [CGT_HCR_TVM] = {
208 .index = HCR_EL2,
209 .value = HCR_TVM,
210 .mask = HCR_TVM,
211 .behaviour = BEHAVE_FORWARD_WRITE,
212 },
213 [CGT_HCR_TDZ] = {
214 .index = HCR_EL2,
215 .value = HCR_TDZ,
216 .mask = HCR_TDZ,
217 .behaviour = BEHAVE_FORWARD_RW,
218 },
219 [CGT_HCR_TRVM] = {
220 .index = HCR_EL2,
221 .value = HCR_TRVM,
222 .mask = HCR_TRVM,
223 .behaviour = BEHAVE_FORWARD_READ,
224 },
225 [CGT_HCR_TLOR] = {
226 .index = HCR_EL2,
227 .value = HCR_TLOR,
228 .mask = HCR_TLOR,
229 .behaviour = BEHAVE_FORWARD_RW,
230 },
231 [CGT_HCR_TERR] = {
232 .index = HCR_EL2,
233 .value = HCR_TERR,
234 .mask = HCR_TERR,
235 .behaviour = BEHAVE_FORWARD_RW,
236 },
237 [CGT_HCR_APK] = {
238 .index = HCR_EL2,
239 .value = 0,
240 .mask = HCR_APK,
241 .behaviour = BEHAVE_FORWARD_RW,
242 },
243 [CGT_HCR_NV] = {
244 .index = HCR_EL2,
245 .value = HCR_NV,
246 .mask = HCR_NV,
247 .behaviour = BEHAVE_FORWARD_RW,
248 },
249 [CGT_HCR_NV_nNV2] = {
250 .index = HCR_EL2,
251 .value = HCR_NV,
252 .mask = HCR_NV | HCR_NV2,
253 .behaviour = BEHAVE_FORWARD_RW,
254 },
255 [CGT_HCR_NV1_nNV2] = {
256 .index = HCR_EL2,
257 .value = HCR_NV | HCR_NV1,
258 .mask = HCR_NV | HCR_NV1 | HCR_NV2,
259 .behaviour = BEHAVE_FORWARD_RW,
260 },
261 [CGT_HCR_AT] = {
262 .index = HCR_EL2,
263 .value = HCR_AT,
264 .mask = HCR_AT,
265 .behaviour = BEHAVE_FORWARD_RW,
266 },
267 [CGT_HCR_nFIEN] = {
268 .index = HCR_EL2,
269 .value = 0,
270 .mask = HCR_FIEN,
271 .behaviour = BEHAVE_FORWARD_RW,
272 },
273 [CGT_HCR_TID4] = {
274 .index = HCR_EL2,
275 .value = HCR_TID4,
276 .mask = HCR_TID4,
277 .behaviour = BEHAVE_FORWARD_RW,
278 },
279 [CGT_HCR_TICAB] = {
280 .index = HCR_EL2,
281 .value = HCR_TICAB,
282 .mask = HCR_TICAB,
283 .behaviour = BEHAVE_FORWARD_RW,
284 },
285 [CGT_HCR_TOCU] = {
286 .index = HCR_EL2,
287 .value = HCR_TOCU,
288 .mask = HCR_TOCU,
289 .behaviour = BEHAVE_FORWARD_RW,
290 },
291 [CGT_HCR_ENSCXT] = {
292 .index = HCR_EL2,
293 .value = 0,
294 .mask = HCR_ENSCXT,
295 .behaviour = BEHAVE_FORWARD_RW,
296 },
297 [CGT_HCR_TTLBIS] = {
298 .index = HCR_EL2,
299 .value = HCR_TTLBIS,
300 .mask = HCR_TTLBIS,
301 .behaviour = BEHAVE_FORWARD_RW,
302 },
303 [CGT_HCR_TTLBOS] = {
304 .index = HCR_EL2,
305 .value = HCR_TTLBOS,
306 .mask = HCR_TTLBOS,
307 .behaviour = BEHAVE_FORWARD_RW,
308 },
309 [CGT_MDCR_TPMCR] = {
310 .index = MDCR_EL2,
311 .value = MDCR_EL2_TPMCR,
312 .mask = MDCR_EL2_TPMCR,
313 .behaviour = BEHAVE_FORWARD_RW |
314 BEHAVE_FORWARD_IN_HOST_EL0,
315 },
316 [CGT_MDCR_TPM] = {
317 .index = MDCR_EL2,
318 .value = MDCR_EL2_TPM,
319 .mask = MDCR_EL2_TPM,
320 .behaviour = BEHAVE_FORWARD_RW |
321 BEHAVE_FORWARD_IN_HOST_EL0,
322 },
323 [CGT_MDCR_TDE] = {
324 .index = MDCR_EL2,
325 .value = MDCR_EL2_TDE,
326 .mask = MDCR_EL2_TDE,
327 .behaviour = BEHAVE_FORWARD_RW,
328 },
329 [CGT_MDCR_TDA] = {
330 .index = MDCR_EL2,
331 .value = MDCR_EL2_TDA,
332 .mask = MDCR_EL2_TDA,
333 .behaviour = BEHAVE_FORWARD_RW,
334 },
335 [CGT_MDCR_TDOSA] = {
336 .index = MDCR_EL2,
337 .value = MDCR_EL2_TDOSA,
338 .mask = MDCR_EL2_TDOSA,
339 .behaviour = BEHAVE_FORWARD_RW,
340 },
341 [CGT_MDCR_TDRA] = {
342 .index = MDCR_EL2,
343 .value = MDCR_EL2_TDRA,
344 .mask = MDCR_EL2_TDRA,
345 .behaviour = BEHAVE_FORWARD_RW,
346 },
347 [CGT_MDCR_E2PB] = {
348 .index = MDCR_EL2,
349 .value = 0,
350 .mask = BIT(MDCR_EL2_E2PB_SHIFT),
351 .behaviour = BEHAVE_FORWARD_RW,
352 },
353 [CGT_MDCR_TPMS] = {
354 .index = MDCR_EL2,
355 .value = MDCR_EL2_TPMS,
356 .mask = MDCR_EL2_TPMS,
357 .behaviour = BEHAVE_FORWARD_RW,
358 },
359 [CGT_MDCR_TTRF] = {
360 .index = MDCR_EL2,
361 .value = MDCR_EL2_TTRF,
362 .mask = MDCR_EL2_TTRF,
363 .behaviour = BEHAVE_FORWARD_RW,
364 },
365 [CGT_MDCR_E2TB] = {
366 .index = MDCR_EL2,
367 .value = 0,
368 .mask = BIT(MDCR_EL2_E2TB_SHIFT),
369 .behaviour = BEHAVE_FORWARD_RW,
370 },
371 [CGT_MDCR_TDCC] = {
372 .index = MDCR_EL2,
373 .value = MDCR_EL2_TDCC,
374 .mask = MDCR_EL2_TDCC,
375 .behaviour = BEHAVE_FORWARD_RW,
376 },
377 [CGT_CPTR_TAM] = {
378 .index = CPTR_EL2,
379 .value = CPTR_EL2_TAM,
380 .mask = CPTR_EL2_TAM,
381 .behaviour = BEHAVE_FORWARD_RW,
382 },
383 [CGT_CPTR_TCPAC] = {
384 .index = CPTR_EL2,
385 .value = CPTR_EL2_TCPAC,
386 .mask = CPTR_EL2_TCPAC,
387 .behaviour = BEHAVE_FORWARD_RW,
388 },
389 [CGT_HCRX_EnFPM] = {
390 .index = HCRX_EL2,
391 .value = 0,
392 .mask = HCRX_EL2_EnFPM,
393 .behaviour = BEHAVE_FORWARD_RW,
394 },
395 [CGT_HCRX_TCR2En] = {
396 .index = HCRX_EL2,
397 .value = 0,
398 .mask = HCRX_EL2_TCR2En,
399 .behaviour = BEHAVE_FORWARD_RW,
400 },
401 [CGT_CNTHCTL_EL1TVT] = {
402 .index = CNTHCTL_EL2,
403 .value = CNTHCTL_EL1TVT,
404 .mask = CNTHCTL_EL1TVT,
405 .behaviour = BEHAVE_FORWARD_RW,
406 },
407 [CGT_CNTHCTL_EL1TVCT] = {
408 .index = CNTHCTL_EL2,
409 .value = CNTHCTL_EL1TVCT,
410 .mask = CNTHCTL_EL1TVCT,
411 .behaviour = BEHAVE_FORWARD_READ,
412 },
413 [CGT_ICH_HCR_TC] = {
414 .index = ICH_HCR_EL2,
415 .value = ICH_HCR_EL2_TC,
416 .mask = ICH_HCR_EL2_TC,
417 .behaviour = BEHAVE_FORWARD_RW,
418 },
419 [CGT_ICH_HCR_TALL0] = {
420 .index = ICH_HCR_EL2,
421 .value = ICH_HCR_EL2_TALL0,
422 .mask = ICH_HCR_EL2_TALL0,
423 .behaviour = BEHAVE_FORWARD_RW,
424 },
425 [CGT_ICH_HCR_TALL1] = {
426 .index = ICH_HCR_EL2,
427 .value = ICH_HCR_EL2_TALL1,
428 .mask = ICH_HCR_EL2_TALL1,
429 .behaviour = BEHAVE_FORWARD_RW,
430 },
431 [CGT_ICH_HCR_TDIR] = {
432 .index = ICH_HCR_EL2,
433 .value = ICH_HCR_EL2_TDIR,
434 .mask = ICH_HCR_EL2_TDIR,
435 .behaviour = BEHAVE_FORWARD_RW,
436 },
437 };
438
439 #define MCB(id, ...) \
440 [id - __MULTIPLE_CONTROL_BITS__] = \
441 (const enum cgt_group_id[]){ \
442 __VA_ARGS__, __RESERVED__ \
443 }
444
445 static const enum cgt_group_id *coarse_control_combo[] = {
446 MCB(CGT_HCR_TID2_TID4, CGT_HCR_TID2, CGT_HCR_TID4),
447 MCB(CGT_HCR_TTLB_TTLBIS, CGT_HCR_TTLB, CGT_HCR_TTLBIS),
448 MCB(CGT_HCR_TTLB_TTLBOS, CGT_HCR_TTLB, CGT_HCR_TTLBOS),
449 MCB(CGT_HCR_TVM_TRVM, CGT_HCR_TVM, CGT_HCR_TRVM),
450 MCB(CGT_HCR_TVM_TRVM_HCRX_TCR2En,
451 CGT_HCR_TVM, CGT_HCR_TRVM, CGT_HCRX_TCR2En),
452 MCB(CGT_HCR_TPU_TICAB, CGT_HCR_TPU, CGT_HCR_TICAB),
453 MCB(CGT_HCR_TPU_TOCU, CGT_HCR_TPU, CGT_HCR_TOCU),
454 MCB(CGT_HCR_NV1_nNV2_ENSCXT, CGT_HCR_NV1_nNV2, CGT_HCR_ENSCXT),
455 MCB(CGT_MDCR_TPM_TPMCR, CGT_MDCR_TPM, CGT_MDCR_TPMCR),
456 MCB(CGT_MDCR_TPM_HPMN, CGT_MDCR_TPM, CGT_MDCR_HPMN),
457 MCB(CGT_MDCR_TDE_TDA, CGT_MDCR_TDE, CGT_MDCR_TDA),
458 MCB(CGT_MDCR_TDE_TDOSA, CGT_MDCR_TDE, CGT_MDCR_TDOSA),
459 MCB(CGT_MDCR_TDE_TDRA, CGT_MDCR_TDE, CGT_MDCR_TDRA),
460 MCB(CGT_MDCR_TDCC_TDE_TDA, CGT_MDCR_TDCC, CGT_MDCR_TDE, CGT_MDCR_TDA),
461
462 MCB(CGT_HCR_IMO_FMO_ICH_HCR_TC, CGT_HCR_IMO, CGT_HCR_FMO, CGT_ICH_HCR_TC),
463 MCB(CGT_ICH_HCR_TC_TDIR, CGT_ICH_HCR_TC, CGT_ICH_HCR_TDIR),
464 };
465
466 typedef enum trap_behaviour (*complex_condition_check)(struct kvm_vcpu *);
467
468 /*
469 * Warning, maximum confusion ahead.
470 *
471 * When E2H=0, CNTHCTL_EL2[1:0] are defined as EL1PCEN:EL1PCTEN
472 * When E2H=1, CNTHCTL_EL2[11:10] are defined as EL1PTEN:EL1PCTEN
473 *
474 * Note the single letter difference? Yet, the bits have the same
475 * function despite a different layout and a different name.
476 *
477 * We don't try to reconcile this mess. We just use the E2H=0 bits
478 * to generate something that is in the E2H=1 format, and live with
479 * it. You're welcome.
480 */
get_sanitized_cnthctl(struct kvm_vcpu * vcpu)481 static u64 get_sanitized_cnthctl(struct kvm_vcpu *vcpu)
482 {
483 u64 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
484
485 if (!vcpu_el2_e2h_is_set(vcpu))
486 val = (val & (CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN)) << 10;
487
488 return val & ((CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN) << 10);
489 }
490
check_cnthctl_el1pcten(struct kvm_vcpu * vcpu)491 static enum trap_behaviour check_cnthctl_el1pcten(struct kvm_vcpu *vcpu)
492 {
493 if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCTEN << 10))
494 return BEHAVE_HANDLE_LOCALLY;
495
496 return BEHAVE_FORWARD_RW;
497 }
498
check_cnthctl_el1pten(struct kvm_vcpu * vcpu)499 static enum trap_behaviour check_cnthctl_el1pten(struct kvm_vcpu *vcpu)
500 {
501 if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCEN << 10))
502 return BEHAVE_HANDLE_LOCALLY;
503
504 return BEHAVE_FORWARD_RW;
505 }
506
is_nested_nv2_guest(struct kvm_vcpu * vcpu)507 static bool is_nested_nv2_guest(struct kvm_vcpu *vcpu)
508 {
509 u64 val;
510
511 val = __vcpu_sys_reg(vcpu, HCR_EL2);
512 return ((val & (HCR_E2H | HCR_TGE | HCR_NV2 | HCR_NV1 | HCR_NV)) == (HCR_E2H | HCR_NV2 | HCR_NV));
513 }
514
check_cnthctl_el1nvpct(struct kvm_vcpu * vcpu)515 static enum trap_behaviour check_cnthctl_el1nvpct(struct kvm_vcpu *vcpu)
516 {
517 if (!is_nested_nv2_guest(vcpu) ||
518 !(__vcpu_sys_reg(vcpu, CNTHCTL_EL2) & CNTHCTL_EL1NVPCT))
519 return BEHAVE_HANDLE_LOCALLY;
520
521 return BEHAVE_FORWARD_RW;
522 }
523
check_cnthctl_el1nvvct(struct kvm_vcpu * vcpu)524 static enum trap_behaviour check_cnthctl_el1nvvct(struct kvm_vcpu *vcpu)
525 {
526 if (!is_nested_nv2_guest(vcpu) ||
527 !(__vcpu_sys_reg(vcpu, CNTHCTL_EL2) & CNTHCTL_EL1NVVCT))
528 return BEHAVE_HANDLE_LOCALLY;
529
530 return BEHAVE_FORWARD_RW;
531 }
532
check_cptr_tta(struct kvm_vcpu * vcpu)533 static enum trap_behaviour check_cptr_tta(struct kvm_vcpu *vcpu)
534 {
535 u64 val = __vcpu_sys_reg(vcpu, CPTR_EL2);
536
537 if (!vcpu_el2_e2h_is_set(vcpu))
538 val = translate_cptr_el2_to_cpacr_el1(val);
539
540 if (val & CPACR_EL1_TTA)
541 return BEHAVE_FORWARD_RW;
542
543 return BEHAVE_HANDLE_LOCALLY;
544 }
545
check_mdcr_hpmn(struct kvm_vcpu * vcpu)546 static enum trap_behaviour check_mdcr_hpmn(struct kvm_vcpu *vcpu)
547 {
548 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
549 unsigned int idx;
550
551
552 switch (sysreg) {
553 case SYS_PMEVTYPERn_EL0(0) ... SYS_PMEVTYPERn_EL0(30):
554 case SYS_PMEVCNTRn_EL0(0) ... SYS_PMEVCNTRn_EL0(30):
555 idx = (sys_reg_CRm(sysreg) & 0x3) << 3 | sys_reg_Op2(sysreg);
556 break;
557 case SYS_PMXEVTYPER_EL0:
558 case SYS_PMXEVCNTR_EL0:
559 idx = SYS_FIELD_GET(PMSELR_EL0, SEL,
560 __vcpu_sys_reg(vcpu, PMSELR_EL0));
561 break;
562 default:
563 /* Someone used this trap helper for something else... */
564 KVM_BUG_ON(1, vcpu->kvm);
565 return BEHAVE_HANDLE_LOCALLY;
566 }
567
568 if (kvm_pmu_counter_is_hyp(vcpu, idx))
569 return BEHAVE_FORWARD_RW | BEHAVE_FORWARD_IN_HOST_EL0;
570
571 return BEHAVE_HANDLE_LOCALLY;
572 }
573
574 #define CCC(id, fn) \
575 [id - __COMPLEX_CONDITIONS__] = fn
576
577 static const complex_condition_check ccc[] = {
578 CCC(CGT_CNTHCTL_EL1PCTEN, check_cnthctl_el1pcten),
579 CCC(CGT_CNTHCTL_EL1PTEN, check_cnthctl_el1pten),
580 CCC(CGT_CNTHCTL_EL1NVPCT, check_cnthctl_el1nvpct),
581 CCC(CGT_CNTHCTL_EL1NVVCT, check_cnthctl_el1nvvct),
582 CCC(CGT_CPTR_TTA, check_cptr_tta),
583 CCC(CGT_MDCR_HPMN, check_mdcr_hpmn),
584 };
585
586 /*
587 * Bit assignment for the trap controls. We use a 64bit word with the
588 * following layout for each trapped sysreg:
589 *
590 * [9:0] enum cgt_group_id (10 bits)
591 * [13:10] enum fgt_group_id (4 bits)
592 * [19:14] bit number in the FGT register (6 bits)
593 * [20] trap polarity (1 bit)
594 * [25:21] FG filter (5 bits)
595 * [35:26] Main SysReg table index (10 bits)
596 * [62:36] Unused (27 bits)
597 * [63] RES0 - Must be zero, as lost on insertion in the xarray
598 */
599 #define TC_CGT_BITS 10
600 #define TC_FGT_BITS 4
601 #define TC_FGF_BITS 5
602 #define TC_SRI_BITS 10
603
604 union trap_config {
605 u64 val;
606 struct {
607 unsigned long cgt:TC_CGT_BITS; /* Coarse Grained Trap id */
608 unsigned long fgt:TC_FGT_BITS; /* Fine Grained Trap id */
609 unsigned long bit:6; /* Bit number */
610 unsigned long pol:1; /* Polarity */
611 unsigned long fgf:TC_FGF_BITS; /* Fine Grained Filter */
612 unsigned long sri:TC_SRI_BITS; /* SysReg Index */
613 unsigned long unused:27; /* Unused, should be zero */
614 unsigned long mbz:1; /* Must Be Zero */
615 };
616 };
617
618 struct encoding_to_trap_config {
619 const u32 encoding;
620 const u32 end;
621 const union trap_config tc;
622 const unsigned int line;
623 };
624
625 /*
626 * WARNING: using ranges is a treacherous endeavour, as sysregs that
627 * are part of an architectural range are not necessarily contiguous
628 * in the [Op0,Op1,CRn,CRm,Ops] space. Tread carefully.
629 */
630 #define SR_RANGE_TRAP(sr_start, sr_end, trap_id) \
631 { \
632 .encoding = sr_start, \
633 .end = sr_end, \
634 .tc = { \
635 .cgt = trap_id, \
636 }, \
637 .line = __LINE__, \
638 }
639
640 #define SR_TRAP(sr, trap_id) SR_RANGE_TRAP(sr, sr, trap_id)
641
642 /*
643 * Map encoding to trap bits for exception reported with EC=0x18.
644 * These must only be evaluated when running a nested hypervisor, but
645 * that the current context is not a hypervisor context. When the
646 * trapped access matches one of the trap controls, the exception is
647 * re-injected in the nested hypervisor.
648 */
649 static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
650 SR_TRAP(SYS_REVIDR_EL1, CGT_HCR_TID1),
651 SR_TRAP(SYS_AIDR_EL1, CGT_HCR_TID1),
652 SR_TRAP(SYS_SMIDR_EL1, CGT_HCR_TID1),
653 SR_TRAP(SYS_CTR_EL0, CGT_HCR_TID2),
654 SR_TRAP(SYS_CCSIDR_EL1, CGT_HCR_TID2_TID4),
655 SR_TRAP(SYS_CCSIDR2_EL1, CGT_HCR_TID2_TID4),
656 SR_TRAP(SYS_CLIDR_EL1, CGT_HCR_TID2_TID4),
657 SR_TRAP(SYS_CSSELR_EL1, CGT_HCR_TID2_TID4),
658 SR_RANGE_TRAP(SYS_ID_PFR0_EL1,
659 sys_reg(3, 0, 0, 7, 7), CGT_HCR_TID3),
660 SR_TRAP(SYS_ICC_SGI0R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC),
661 SR_TRAP(SYS_ICC_ASGI1R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC),
662 SR_TRAP(SYS_ICC_SGI1R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC),
663 SR_RANGE_TRAP(sys_reg(3, 0, 11, 0, 0),
664 sys_reg(3, 0, 11, 15, 7), CGT_HCR_TIDCP),
665 SR_RANGE_TRAP(sys_reg(3, 1, 11, 0, 0),
666 sys_reg(3, 1, 11, 15, 7), CGT_HCR_TIDCP),
667 SR_RANGE_TRAP(sys_reg(3, 2, 11, 0, 0),
668 sys_reg(3, 2, 11, 15, 7), CGT_HCR_TIDCP),
669 SR_RANGE_TRAP(sys_reg(3, 3, 11, 0, 0),
670 sys_reg(3, 3, 11, 15, 7), CGT_HCR_TIDCP),
671 SR_RANGE_TRAP(sys_reg(3, 4, 11, 0, 0),
672 sys_reg(3, 4, 11, 15, 7), CGT_HCR_TIDCP),
673 SR_RANGE_TRAP(sys_reg(3, 5, 11, 0, 0),
674 sys_reg(3, 5, 11, 15, 7), CGT_HCR_TIDCP),
675 SR_RANGE_TRAP(sys_reg(3, 6, 11, 0, 0),
676 sys_reg(3, 6, 11, 15, 7), CGT_HCR_TIDCP),
677 SR_RANGE_TRAP(sys_reg(3, 7, 11, 0, 0),
678 sys_reg(3, 7, 11, 15, 7), CGT_HCR_TIDCP),
679 SR_RANGE_TRAP(sys_reg(3, 0, 15, 0, 0),
680 sys_reg(3, 0, 15, 15, 7), CGT_HCR_TIDCP),
681 SR_RANGE_TRAP(sys_reg(3, 1, 15, 0, 0),
682 sys_reg(3, 1, 15, 15, 7), CGT_HCR_TIDCP),
683 SR_RANGE_TRAP(sys_reg(3, 2, 15, 0, 0),
684 sys_reg(3, 2, 15, 15, 7), CGT_HCR_TIDCP),
685 SR_RANGE_TRAP(sys_reg(3, 3, 15, 0, 0),
686 sys_reg(3, 3, 15, 15, 7), CGT_HCR_TIDCP),
687 SR_RANGE_TRAP(sys_reg(3, 4, 15, 0, 0),
688 sys_reg(3, 4, 15, 15, 7), CGT_HCR_TIDCP),
689 SR_RANGE_TRAP(sys_reg(3, 5, 15, 0, 0),
690 sys_reg(3, 5, 15, 15, 7), CGT_HCR_TIDCP),
691 SR_RANGE_TRAP(sys_reg(3, 6, 15, 0, 0),
692 sys_reg(3, 6, 15, 15, 7), CGT_HCR_TIDCP),
693 SR_RANGE_TRAP(sys_reg(3, 7, 15, 0, 0),
694 sys_reg(3, 7, 15, 15, 7), CGT_HCR_TIDCP),
695 SR_TRAP(SYS_ACTLR_EL1, CGT_HCR_TACR),
696 SR_TRAP(SYS_DC_ISW, CGT_HCR_TSW),
697 SR_TRAP(SYS_DC_CSW, CGT_HCR_TSW),
698 SR_TRAP(SYS_DC_CISW, CGT_HCR_TSW),
699 SR_TRAP(SYS_DC_IGSW, CGT_HCR_TSW),
700 SR_TRAP(SYS_DC_IGDSW, CGT_HCR_TSW),
701 SR_TRAP(SYS_DC_CGSW, CGT_HCR_TSW),
702 SR_TRAP(SYS_DC_CGDSW, CGT_HCR_TSW),
703 SR_TRAP(SYS_DC_CIGSW, CGT_HCR_TSW),
704 SR_TRAP(SYS_DC_CIGDSW, CGT_HCR_TSW),
705 SR_TRAP(SYS_DC_CIVAC, CGT_HCR_TPC),
706 SR_TRAP(SYS_DC_CVAC, CGT_HCR_TPC),
707 SR_TRAP(SYS_DC_CVAP, CGT_HCR_TPC),
708 SR_TRAP(SYS_DC_CVADP, CGT_HCR_TPC),
709 SR_TRAP(SYS_DC_IVAC, CGT_HCR_TPC),
710 SR_TRAP(SYS_DC_CIGVAC, CGT_HCR_TPC),
711 SR_TRAP(SYS_DC_CIGDVAC, CGT_HCR_TPC),
712 SR_TRAP(SYS_DC_IGVAC, CGT_HCR_TPC),
713 SR_TRAP(SYS_DC_IGDVAC, CGT_HCR_TPC),
714 SR_TRAP(SYS_DC_CGVAC, CGT_HCR_TPC),
715 SR_TRAP(SYS_DC_CGDVAC, CGT_HCR_TPC),
716 SR_TRAP(SYS_DC_CGVAP, CGT_HCR_TPC),
717 SR_TRAP(SYS_DC_CGDVAP, CGT_HCR_TPC),
718 SR_TRAP(SYS_DC_CGVADP, CGT_HCR_TPC),
719 SR_TRAP(SYS_DC_CGDVADP, CGT_HCR_TPC),
720 SR_TRAP(SYS_IC_IVAU, CGT_HCR_TPU_TOCU),
721 SR_TRAP(SYS_IC_IALLU, CGT_HCR_TPU_TOCU),
722 SR_TRAP(SYS_IC_IALLUIS, CGT_HCR_TPU_TICAB),
723 SR_TRAP(SYS_DC_CVAU, CGT_HCR_TPU_TOCU),
724 SR_TRAP(OP_TLBI_RVAE1, CGT_HCR_TTLB),
725 SR_TRAP(OP_TLBI_RVAAE1, CGT_HCR_TTLB),
726 SR_TRAP(OP_TLBI_RVALE1, CGT_HCR_TTLB),
727 SR_TRAP(OP_TLBI_RVAALE1, CGT_HCR_TTLB),
728 SR_TRAP(OP_TLBI_VMALLE1, CGT_HCR_TTLB),
729 SR_TRAP(OP_TLBI_VAE1, CGT_HCR_TTLB),
730 SR_TRAP(OP_TLBI_ASIDE1, CGT_HCR_TTLB),
731 SR_TRAP(OP_TLBI_VAAE1, CGT_HCR_TTLB),
732 SR_TRAP(OP_TLBI_VALE1, CGT_HCR_TTLB),
733 SR_TRAP(OP_TLBI_VAALE1, CGT_HCR_TTLB),
734 SR_TRAP(OP_TLBI_RVAE1NXS, CGT_HCR_TTLB),
735 SR_TRAP(OP_TLBI_RVAAE1NXS, CGT_HCR_TTLB),
736 SR_TRAP(OP_TLBI_RVALE1NXS, CGT_HCR_TTLB),
737 SR_TRAP(OP_TLBI_RVAALE1NXS, CGT_HCR_TTLB),
738 SR_TRAP(OP_TLBI_VMALLE1NXS, CGT_HCR_TTLB),
739 SR_TRAP(OP_TLBI_VAE1NXS, CGT_HCR_TTLB),
740 SR_TRAP(OP_TLBI_ASIDE1NXS, CGT_HCR_TTLB),
741 SR_TRAP(OP_TLBI_VAAE1NXS, CGT_HCR_TTLB),
742 SR_TRAP(OP_TLBI_VALE1NXS, CGT_HCR_TTLB),
743 SR_TRAP(OP_TLBI_VAALE1NXS, CGT_HCR_TTLB),
744 SR_TRAP(OP_TLBI_RVAE1IS, CGT_HCR_TTLB_TTLBIS),
745 SR_TRAP(OP_TLBI_RVAAE1IS, CGT_HCR_TTLB_TTLBIS),
746 SR_TRAP(OP_TLBI_RVALE1IS, CGT_HCR_TTLB_TTLBIS),
747 SR_TRAP(OP_TLBI_RVAALE1IS, CGT_HCR_TTLB_TTLBIS),
748 SR_TRAP(OP_TLBI_VMALLE1IS, CGT_HCR_TTLB_TTLBIS),
749 SR_TRAP(OP_TLBI_VAE1IS, CGT_HCR_TTLB_TTLBIS),
750 SR_TRAP(OP_TLBI_ASIDE1IS, CGT_HCR_TTLB_TTLBIS),
751 SR_TRAP(OP_TLBI_VAAE1IS, CGT_HCR_TTLB_TTLBIS),
752 SR_TRAP(OP_TLBI_VALE1IS, CGT_HCR_TTLB_TTLBIS),
753 SR_TRAP(OP_TLBI_VAALE1IS, CGT_HCR_TTLB_TTLBIS),
754 SR_TRAP(OP_TLBI_RVAE1ISNXS, CGT_HCR_TTLB_TTLBIS),
755 SR_TRAP(OP_TLBI_RVAAE1ISNXS, CGT_HCR_TTLB_TTLBIS),
756 SR_TRAP(OP_TLBI_RVALE1ISNXS, CGT_HCR_TTLB_TTLBIS),
757 SR_TRAP(OP_TLBI_RVAALE1ISNXS, CGT_HCR_TTLB_TTLBIS),
758 SR_TRAP(OP_TLBI_VMALLE1ISNXS, CGT_HCR_TTLB_TTLBIS),
759 SR_TRAP(OP_TLBI_VAE1ISNXS, CGT_HCR_TTLB_TTLBIS),
760 SR_TRAP(OP_TLBI_ASIDE1ISNXS, CGT_HCR_TTLB_TTLBIS),
761 SR_TRAP(OP_TLBI_VAAE1ISNXS, CGT_HCR_TTLB_TTLBIS),
762 SR_TRAP(OP_TLBI_VALE1ISNXS, CGT_HCR_TTLB_TTLBIS),
763 SR_TRAP(OP_TLBI_VAALE1ISNXS, CGT_HCR_TTLB_TTLBIS),
764 SR_TRAP(OP_TLBI_VMALLE1OS, CGT_HCR_TTLB_TTLBOS),
765 SR_TRAP(OP_TLBI_VAE1OS, CGT_HCR_TTLB_TTLBOS),
766 SR_TRAP(OP_TLBI_ASIDE1OS, CGT_HCR_TTLB_TTLBOS),
767 SR_TRAP(OP_TLBI_VAAE1OS, CGT_HCR_TTLB_TTLBOS),
768 SR_TRAP(OP_TLBI_VALE1OS, CGT_HCR_TTLB_TTLBOS),
769 SR_TRAP(OP_TLBI_VAALE1OS, CGT_HCR_TTLB_TTLBOS),
770 SR_TRAP(OP_TLBI_RVAE1OS, CGT_HCR_TTLB_TTLBOS),
771 SR_TRAP(OP_TLBI_RVAAE1OS, CGT_HCR_TTLB_TTLBOS),
772 SR_TRAP(OP_TLBI_RVALE1OS, CGT_HCR_TTLB_TTLBOS),
773 SR_TRAP(OP_TLBI_RVAALE1OS, CGT_HCR_TTLB_TTLBOS),
774 SR_TRAP(OP_TLBI_VMALLE1OSNXS, CGT_HCR_TTLB_TTLBOS),
775 SR_TRAP(OP_TLBI_VAE1OSNXS, CGT_HCR_TTLB_TTLBOS),
776 SR_TRAP(OP_TLBI_ASIDE1OSNXS, CGT_HCR_TTLB_TTLBOS),
777 SR_TRAP(OP_TLBI_VAAE1OSNXS, CGT_HCR_TTLB_TTLBOS),
778 SR_TRAP(OP_TLBI_VALE1OSNXS, CGT_HCR_TTLB_TTLBOS),
779 SR_TRAP(OP_TLBI_VAALE1OSNXS, CGT_HCR_TTLB_TTLBOS),
780 SR_TRAP(OP_TLBI_RVAE1OSNXS, CGT_HCR_TTLB_TTLBOS),
781 SR_TRAP(OP_TLBI_RVAAE1OSNXS, CGT_HCR_TTLB_TTLBOS),
782 SR_TRAP(OP_TLBI_RVALE1OSNXS, CGT_HCR_TTLB_TTLBOS),
783 SR_TRAP(OP_TLBI_RVAALE1OSNXS, CGT_HCR_TTLB_TTLBOS),
784 SR_TRAP(SYS_SCTLR_EL1, CGT_HCR_TVM_TRVM),
785 SR_TRAP(SYS_TTBR0_EL1, CGT_HCR_TVM_TRVM),
786 SR_TRAP(SYS_TTBR1_EL1, CGT_HCR_TVM_TRVM),
787 SR_TRAP(SYS_TCR_EL1, CGT_HCR_TVM_TRVM),
788 SR_TRAP(SYS_ESR_EL1, CGT_HCR_TVM_TRVM),
789 SR_TRAP(SYS_FAR_EL1, CGT_HCR_TVM_TRVM),
790 SR_TRAP(SYS_AFSR0_EL1, CGT_HCR_TVM_TRVM),
791 SR_TRAP(SYS_AFSR1_EL1, CGT_HCR_TVM_TRVM),
792 SR_TRAP(SYS_MAIR_EL1, CGT_HCR_TVM_TRVM),
793 SR_TRAP(SYS_AMAIR_EL1, CGT_HCR_TVM_TRVM),
794 SR_TRAP(SYS_CONTEXTIDR_EL1, CGT_HCR_TVM_TRVM),
795 SR_TRAP(SYS_PIR_EL1, CGT_HCR_TVM_TRVM),
796 SR_TRAP(SYS_PIRE0_EL1, CGT_HCR_TVM_TRVM),
797 SR_TRAP(SYS_POR_EL0, CGT_HCR_TVM_TRVM),
798 SR_TRAP(SYS_POR_EL1, CGT_HCR_TVM_TRVM),
799 SR_TRAP(SYS_TCR2_EL1, CGT_HCR_TVM_TRVM_HCRX_TCR2En),
800 SR_TRAP(SYS_DC_ZVA, CGT_HCR_TDZ),
801 SR_TRAP(SYS_DC_GVA, CGT_HCR_TDZ),
802 SR_TRAP(SYS_DC_GZVA, CGT_HCR_TDZ),
803 SR_TRAP(SYS_LORSA_EL1, CGT_HCR_TLOR),
804 SR_TRAP(SYS_LOREA_EL1, CGT_HCR_TLOR),
805 SR_TRAP(SYS_LORN_EL1, CGT_HCR_TLOR),
806 SR_TRAP(SYS_LORC_EL1, CGT_HCR_TLOR),
807 SR_TRAP(SYS_LORID_EL1, CGT_HCR_TLOR),
808 SR_TRAP(SYS_ERRIDR_EL1, CGT_HCR_TERR),
809 SR_TRAP(SYS_ERRSELR_EL1, CGT_HCR_TERR),
810 SR_TRAP(SYS_ERXADDR_EL1, CGT_HCR_TERR),
811 SR_TRAP(SYS_ERXCTLR_EL1, CGT_HCR_TERR),
812 SR_TRAP(SYS_ERXFR_EL1, CGT_HCR_TERR),
813 SR_TRAP(SYS_ERXMISC0_EL1, CGT_HCR_TERR),
814 SR_TRAP(SYS_ERXMISC1_EL1, CGT_HCR_TERR),
815 SR_TRAP(SYS_ERXMISC2_EL1, CGT_HCR_TERR),
816 SR_TRAP(SYS_ERXMISC3_EL1, CGT_HCR_TERR),
817 SR_TRAP(SYS_ERXSTATUS_EL1, CGT_HCR_TERR),
818 SR_TRAP(SYS_APIAKEYLO_EL1, CGT_HCR_APK),
819 SR_TRAP(SYS_APIAKEYHI_EL1, CGT_HCR_APK),
820 SR_TRAP(SYS_APIBKEYLO_EL1, CGT_HCR_APK),
821 SR_TRAP(SYS_APIBKEYHI_EL1, CGT_HCR_APK),
822 SR_TRAP(SYS_APDAKEYLO_EL1, CGT_HCR_APK),
823 SR_TRAP(SYS_APDAKEYHI_EL1, CGT_HCR_APK),
824 SR_TRAP(SYS_APDBKEYLO_EL1, CGT_HCR_APK),
825 SR_TRAP(SYS_APDBKEYHI_EL1, CGT_HCR_APK),
826 SR_TRAP(SYS_APGAKEYLO_EL1, CGT_HCR_APK),
827 SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK),
828 /* All _EL2 registers */
829 SR_TRAP(SYS_BRBCR_EL2, CGT_HCR_NV),
830 SR_TRAP(SYS_VPIDR_EL2, CGT_HCR_NV),
831 SR_TRAP(SYS_VMPIDR_EL2, CGT_HCR_NV),
832 SR_TRAP(SYS_SCTLR_EL2, CGT_HCR_NV),
833 SR_TRAP(SYS_ACTLR_EL2, CGT_HCR_NV),
834 SR_TRAP(SYS_SCTLR2_EL2, CGT_HCR_NV),
835 SR_RANGE_TRAP(SYS_HCR_EL2,
836 SYS_HCRX_EL2, CGT_HCR_NV),
837 SR_TRAP(SYS_SMPRIMAP_EL2, CGT_HCR_NV),
838 SR_TRAP(SYS_SMCR_EL2, CGT_HCR_NV),
839 SR_RANGE_TRAP(SYS_TTBR0_EL2,
840 SYS_TCR2_EL2, CGT_HCR_NV),
841 SR_TRAP(SYS_VTTBR_EL2, CGT_HCR_NV),
842 SR_TRAP(SYS_VTCR_EL2, CGT_HCR_NV),
843 SR_TRAP(SYS_VNCR_EL2, CGT_HCR_NV),
844 SR_RANGE_TRAP(SYS_HDFGRTR_EL2,
845 SYS_HAFGRTR_EL2, CGT_HCR_NV),
846 /* Skip the SP_EL1 encoding... */
847 SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV),
848 SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV),
849 /* Skip SPSR_irq, SPSR_abt, SPSR_und, SPSR_fiq */
850 SR_TRAP(SYS_AFSR0_EL2, CGT_HCR_NV),
851 SR_TRAP(SYS_AFSR1_EL2, CGT_HCR_NV),
852 SR_TRAP(SYS_ESR_EL2, CGT_HCR_NV),
853 SR_TRAP(SYS_VSESR_EL2, CGT_HCR_NV),
854 SR_TRAP(SYS_TFSR_EL2, CGT_HCR_NV),
855 SR_TRAP(SYS_FAR_EL2, CGT_HCR_NV),
856 SR_TRAP(SYS_HPFAR_EL2, CGT_HCR_NV),
857 SR_TRAP(SYS_PMSCR_EL2, CGT_HCR_NV),
858 SR_TRAP(SYS_MAIR_EL2, CGT_HCR_NV),
859 SR_TRAP(SYS_AMAIR_EL2, CGT_HCR_NV),
860 SR_TRAP(SYS_MPAMHCR_EL2, CGT_HCR_NV),
861 SR_TRAP(SYS_MPAMVPMV_EL2, CGT_HCR_NV),
862 SR_TRAP(SYS_MPAM2_EL2, CGT_HCR_NV),
863 SR_RANGE_TRAP(SYS_MPAMVPM0_EL2,
864 SYS_MPAMVPM7_EL2, CGT_HCR_NV),
865 /*
866 * Note that the spec. describes a group of MEC registers
867 * whose access should not trap, therefore skip the following:
868 * MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2,
869 * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2,
870 * VMECID_P_EL2.
871 */
872 SR_RANGE_TRAP(SYS_VBAR_EL2,
873 SYS_RMR_EL2, CGT_HCR_NV),
874 SR_TRAP(SYS_VDISR_EL2, CGT_HCR_NV),
875 /* ICH_AP0R<m>_EL2 */
876 SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2,
877 SYS_ICH_AP0R3_EL2, CGT_HCR_NV),
878 /* ICH_AP1R<m>_EL2 */
879 SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2,
880 SYS_ICH_AP1R3_EL2, CGT_HCR_NV),
881 SR_TRAP(SYS_ICC_SRE_EL2, CGT_HCR_NV),
882 SR_RANGE_TRAP(SYS_ICH_HCR_EL2,
883 SYS_ICH_EISR_EL2, CGT_HCR_NV),
884 SR_TRAP(SYS_ICH_ELRSR_EL2, CGT_HCR_NV),
885 SR_TRAP(SYS_ICH_VMCR_EL2, CGT_HCR_NV),
886 /* ICH_LR<m>_EL2 */
887 SR_RANGE_TRAP(SYS_ICH_LR0_EL2,
888 SYS_ICH_LR15_EL2, CGT_HCR_NV),
889 SR_TRAP(SYS_CONTEXTIDR_EL2, CGT_HCR_NV),
890 SR_TRAP(SYS_TPIDR_EL2, CGT_HCR_NV),
891 SR_TRAP(SYS_SCXTNUM_EL2, CGT_HCR_NV),
892 /* AMEVCNTVOFF0<n>_EL2, AMEVCNTVOFF1<n>_EL2 */
893 SR_RANGE_TRAP(SYS_AMEVCNTVOFF0n_EL2(0),
894 SYS_AMEVCNTVOFF1n_EL2(15), CGT_HCR_NV),
895 /* CNT*_EL2 */
896 SR_TRAP(SYS_CNTVOFF_EL2, CGT_HCR_NV),
897 SR_TRAP(SYS_CNTPOFF_EL2, CGT_HCR_NV),
898 SR_TRAP(SYS_CNTHCTL_EL2, CGT_HCR_NV),
899 SR_RANGE_TRAP(SYS_CNTHP_TVAL_EL2,
900 SYS_CNTHP_CVAL_EL2, CGT_HCR_NV),
901 SR_RANGE_TRAP(SYS_CNTHV_TVAL_EL2,
902 SYS_CNTHV_CVAL_EL2, CGT_HCR_NV),
903 /* All _EL02, _EL12 registers up to CNTKCTL_EL12*/
904 SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),
905 sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),
906 SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0),
907 sys_reg(3, 5, 14, 1, 0), CGT_HCR_NV),
908 SR_TRAP(SYS_CNTP_CTL_EL02, CGT_CNTHCTL_EL1NVPCT),
909 SR_TRAP(SYS_CNTP_CVAL_EL02, CGT_CNTHCTL_EL1NVPCT),
910 SR_TRAP(SYS_CNTV_CTL_EL02, CGT_CNTHCTL_EL1NVVCT),
911 SR_TRAP(SYS_CNTV_CVAL_EL02, CGT_CNTHCTL_EL1NVVCT),
912 SR_TRAP(OP_AT_S1E2R, CGT_HCR_NV),
913 SR_TRAP(OP_AT_S1E2W, CGT_HCR_NV),
914 SR_TRAP(OP_AT_S12E1R, CGT_HCR_NV),
915 SR_TRAP(OP_AT_S12E1W, CGT_HCR_NV),
916 SR_TRAP(OP_AT_S12E0R, CGT_HCR_NV),
917 SR_TRAP(OP_AT_S12E0W, CGT_HCR_NV),
918 SR_TRAP(OP_AT_S1E2A, CGT_HCR_NV),
919 SR_TRAP(OP_TLBI_IPAS2E1, CGT_HCR_NV),
920 SR_TRAP(OP_TLBI_RIPAS2E1, CGT_HCR_NV),
921 SR_TRAP(OP_TLBI_IPAS2LE1, CGT_HCR_NV),
922 SR_TRAP(OP_TLBI_RIPAS2LE1, CGT_HCR_NV),
923 SR_TRAP(OP_TLBI_RVAE2, CGT_HCR_NV),
924 SR_TRAP(OP_TLBI_RVALE2, CGT_HCR_NV),
925 SR_TRAP(OP_TLBI_ALLE2, CGT_HCR_NV),
926 SR_TRAP(OP_TLBI_VAE2, CGT_HCR_NV),
927 SR_TRAP(OP_TLBI_ALLE1, CGT_HCR_NV),
928 SR_TRAP(OP_TLBI_VALE2, CGT_HCR_NV),
929 SR_TRAP(OP_TLBI_VMALLS12E1, CGT_HCR_NV),
930 SR_TRAP(OP_TLBI_IPAS2E1NXS, CGT_HCR_NV),
931 SR_TRAP(OP_TLBI_RIPAS2E1NXS, CGT_HCR_NV),
932 SR_TRAP(OP_TLBI_IPAS2LE1NXS, CGT_HCR_NV),
933 SR_TRAP(OP_TLBI_RIPAS2LE1NXS, CGT_HCR_NV),
934 SR_TRAP(OP_TLBI_RVAE2NXS, CGT_HCR_NV),
935 SR_TRAP(OP_TLBI_RVALE2NXS, CGT_HCR_NV),
936 SR_TRAP(OP_TLBI_ALLE2NXS, CGT_HCR_NV),
937 SR_TRAP(OP_TLBI_VAE2NXS, CGT_HCR_NV),
938 SR_TRAP(OP_TLBI_ALLE1NXS, CGT_HCR_NV),
939 SR_TRAP(OP_TLBI_VALE2NXS, CGT_HCR_NV),
940 SR_TRAP(OP_TLBI_VMALLS12E1NXS, CGT_HCR_NV),
941 SR_TRAP(OP_TLBI_IPAS2E1IS, CGT_HCR_NV),
942 SR_TRAP(OP_TLBI_RIPAS2E1IS, CGT_HCR_NV),
943 SR_TRAP(OP_TLBI_IPAS2LE1IS, CGT_HCR_NV),
944 SR_TRAP(OP_TLBI_RIPAS2LE1IS, CGT_HCR_NV),
945 SR_TRAP(OP_TLBI_RVAE2IS, CGT_HCR_NV),
946 SR_TRAP(OP_TLBI_RVALE2IS, CGT_HCR_NV),
947 SR_TRAP(OP_TLBI_ALLE2IS, CGT_HCR_NV),
948 SR_TRAP(OP_TLBI_VAE2IS, CGT_HCR_NV),
949 SR_TRAP(OP_TLBI_ALLE1IS, CGT_HCR_NV),
950 SR_TRAP(OP_TLBI_VALE2IS, CGT_HCR_NV),
951 SR_TRAP(OP_TLBI_VMALLS12E1IS, CGT_HCR_NV),
952 SR_TRAP(OP_TLBI_IPAS2E1ISNXS, CGT_HCR_NV),
953 SR_TRAP(OP_TLBI_RIPAS2E1ISNXS, CGT_HCR_NV),
954 SR_TRAP(OP_TLBI_IPAS2LE1ISNXS, CGT_HCR_NV),
955 SR_TRAP(OP_TLBI_RIPAS2LE1ISNXS, CGT_HCR_NV),
956 SR_TRAP(OP_TLBI_RVAE2ISNXS, CGT_HCR_NV),
957 SR_TRAP(OP_TLBI_RVALE2ISNXS, CGT_HCR_NV),
958 SR_TRAP(OP_TLBI_ALLE2ISNXS, CGT_HCR_NV),
959 SR_TRAP(OP_TLBI_VAE2ISNXS, CGT_HCR_NV),
960 SR_TRAP(OP_TLBI_ALLE1ISNXS, CGT_HCR_NV),
961 SR_TRAP(OP_TLBI_VALE2ISNXS, CGT_HCR_NV),
962 SR_TRAP(OP_TLBI_VMALLS12E1ISNXS,CGT_HCR_NV),
963 SR_TRAP(OP_TLBI_ALLE2OS, CGT_HCR_NV),
964 SR_TRAP(OP_TLBI_VAE2OS, CGT_HCR_NV),
965 SR_TRAP(OP_TLBI_ALLE1OS, CGT_HCR_NV),
966 SR_TRAP(OP_TLBI_VALE2OS, CGT_HCR_NV),
967 SR_TRAP(OP_TLBI_VMALLS12E1OS, CGT_HCR_NV),
968 SR_TRAP(OP_TLBI_IPAS2E1OS, CGT_HCR_NV),
969 SR_TRAP(OP_TLBI_RIPAS2E1OS, CGT_HCR_NV),
970 SR_TRAP(OP_TLBI_IPAS2LE1OS, CGT_HCR_NV),
971 SR_TRAP(OP_TLBI_RIPAS2LE1OS, CGT_HCR_NV),
972 SR_TRAP(OP_TLBI_RVAE2OS, CGT_HCR_NV),
973 SR_TRAP(OP_TLBI_RVALE2OS, CGT_HCR_NV),
974 SR_TRAP(OP_TLBI_ALLE2OSNXS, CGT_HCR_NV),
975 SR_TRAP(OP_TLBI_VAE2OSNXS, CGT_HCR_NV),
976 SR_TRAP(OP_TLBI_ALLE1OSNXS, CGT_HCR_NV),
977 SR_TRAP(OP_TLBI_VALE2OSNXS, CGT_HCR_NV),
978 SR_TRAP(OP_TLBI_VMALLS12E1OSNXS,CGT_HCR_NV),
979 SR_TRAP(OP_TLBI_IPAS2E1OSNXS, CGT_HCR_NV),
980 SR_TRAP(OP_TLBI_RIPAS2E1OSNXS, CGT_HCR_NV),
981 SR_TRAP(OP_TLBI_IPAS2LE1OSNXS, CGT_HCR_NV),
982 SR_TRAP(OP_TLBI_RIPAS2LE1OSNXS, CGT_HCR_NV),
983 SR_TRAP(OP_TLBI_RVAE2OSNXS, CGT_HCR_NV),
984 SR_TRAP(OP_TLBI_RVALE2OSNXS, CGT_HCR_NV),
985 SR_TRAP(OP_CPP_RCTX, CGT_HCR_NV),
986 SR_TRAP(OP_DVP_RCTX, CGT_HCR_NV),
987 SR_TRAP(OP_CFP_RCTX, CGT_HCR_NV),
988 SR_TRAP(SYS_SP_EL1, CGT_HCR_NV_nNV2),
989 SR_TRAP(SYS_VBAR_EL1, CGT_HCR_NV1_nNV2),
990 SR_TRAP(SYS_ELR_EL1, CGT_HCR_NV1_nNV2),
991 SR_TRAP(SYS_SPSR_EL1, CGT_HCR_NV1_nNV2),
992 SR_TRAP(SYS_SCXTNUM_EL1, CGT_HCR_NV1_nNV2_ENSCXT),
993 SR_TRAP(SYS_SCXTNUM_EL0, CGT_HCR_ENSCXT),
994 SR_TRAP(OP_AT_S1E1R, CGT_HCR_AT),
995 SR_TRAP(OP_AT_S1E1W, CGT_HCR_AT),
996 SR_TRAP(OP_AT_S1E0R, CGT_HCR_AT),
997 SR_TRAP(OP_AT_S1E0W, CGT_HCR_AT),
998 SR_TRAP(OP_AT_S1E1RP, CGT_HCR_AT),
999 SR_TRAP(OP_AT_S1E1WP, CGT_HCR_AT),
1000 SR_TRAP(OP_AT_S1E1A, CGT_HCR_AT),
1001 SR_TRAP(SYS_ERXPFGF_EL1, CGT_HCR_nFIEN),
1002 SR_TRAP(SYS_ERXPFGCTL_EL1, CGT_HCR_nFIEN),
1003 SR_TRAP(SYS_ERXPFGCDN_EL1, CGT_HCR_nFIEN),
1004 SR_TRAP(SYS_PMCR_EL0, CGT_MDCR_TPM_TPMCR),
1005 SR_TRAP(SYS_PMCNTENSET_EL0, CGT_MDCR_TPM),
1006 SR_TRAP(SYS_PMCNTENCLR_EL0, CGT_MDCR_TPM),
1007 SR_TRAP(SYS_PMOVSSET_EL0, CGT_MDCR_TPM),
1008 SR_TRAP(SYS_PMOVSCLR_EL0, CGT_MDCR_TPM),
1009 SR_TRAP(SYS_PMCEID0_EL0, CGT_MDCR_TPM),
1010 SR_TRAP(SYS_PMCEID1_EL0, CGT_MDCR_TPM),
1011 SR_TRAP(SYS_PMXEVTYPER_EL0, CGT_MDCR_TPM_HPMN),
1012 SR_TRAP(SYS_PMSWINC_EL0, CGT_MDCR_TPM),
1013 SR_TRAP(SYS_PMSELR_EL0, CGT_MDCR_TPM),
1014 SR_TRAP(SYS_PMXEVCNTR_EL0, CGT_MDCR_TPM_HPMN),
1015 SR_TRAP(SYS_PMCCNTR_EL0, CGT_MDCR_TPM),
1016 SR_TRAP(SYS_PMUSERENR_EL0, CGT_MDCR_TPM),
1017 SR_TRAP(SYS_PMINTENSET_EL1, CGT_MDCR_TPM),
1018 SR_TRAP(SYS_PMINTENCLR_EL1, CGT_MDCR_TPM),
1019 SR_TRAP(SYS_PMMIR_EL1, CGT_MDCR_TPM),
1020 SR_TRAP(SYS_PMEVCNTRn_EL0(0), CGT_MDCR_TPM_HPMN),
1021 SR_TRAP(SYS_PMEVCNTRn_EL0(1), CGT_MDCR_TPM_HPMN),
1022 SR_TRAP(SYS_PMEVCNTRn_EL0(2), CGT_MDCR_TPM_HPMN),
1023 SR_TRAP(SYS_PMEVCNTRn_EL0(3), CGT_MDCR_TPM_HPMN),
1024 SR_TRAP(SYS_PMEVCNTRn_EL0(4), CGT_MDCR_TPM_HPMN),
1025 SR_TRAP(SYS_PMEVCNTRn_EL0(5), CGT_MDCR_TPM_HPMN),
1026 SR_TRAP(SYS_PMEVCNTRn_EL0(6), CGT_MDCR_TPM_HPMN),
1027 SR_TRAP(SYS_PMEVCNTRn_EL0(7), CGT_MDCR_TPM_HPMN),
1028 SR_TRAP(SYS_PMEVCNTRn_EL0(8), CGT_MDCR_TPM_HPMN),
1029 SR_TRAP(SYS_PMEVCNTRn_EL0(9), CGT_MDCR_TPM_HPMN),
1030 SR_TRAP(SYS_PMEVCNTRn_EL0(10), CGT_MDCR_TPM_HPMN),
1031 SR_TRAP(SYS_PMEVCNTRn_EL0(11), CGT_MDCR_TPM_HPMN),
1032 SR_TRAP(SYS_PMEVCNTRn_EL0(12), CGT_MDCR_TPM_HPMN),
1033 SR_TRAP(SYS_PMEVCNTRn_EL0(13), CGT_MDCR_TPM_HPMN),
1034 SR_TRAP(SYS_PMEVCNTRn_EL0(14), CGT_MDCR_TPM_HPMN),
1035 SR_TRAP(SYS_PMEVCNTRn_EL0(15), CGT_MDCR_TPM_HPMN),
1036 SR_TRAP(SYS_PMEVCNTRn_EL0(16), CGT_MDCR_TPM_HPMN),
1037 SR_TRAP(SYS_PMEVCNTRn_EL0(17), CGT_MDCR_TPM_HPMN),
1038 SR_TRAP(SYS_PMEVCNTRn_EL0(18), CGT_MDCR_TPM_HPMN),
1039 SR_TRAP(SYS_PMEVCNTRn_EL0(19), CGT_MDCR_TPM_HPMN),
1040 SR_TRAP(SYS_PMEVCNTRn_EL0(20), CGT_MDCR_TPM_HPMN),
1041 SR_TRAP(SYS_PMEVCNTRn_EL0(21), CGT_MDCR_TPM_HPMN),
1042 SR_TRAP(SYS_PMEVCNTRn_EL0(22), CGT_MDCR_TPM_HPMN),
1043 SR_TRAP(SYS_PMEVCNTRn_EL0(23), CGT_MDCR_TPM_HPMN),
1044 SR_TRAP(SYS_PMEVCNTRn_EL0(24), CGT_MDCR_TPM_HPMN),
1045 SR_TRAP(SYS_PMEVCNTRn_EL0(25), CGT_MDCR_TPM_HPMN),
1046 SR_TRAP(SYS_PMEVCNTRn_EL0(26), CGT_MDCR_TPM_HPMN),
1047 SR_TRAP(SYS_PMEVCNTRn_EL0(27), CGT_MDCR_TPM_HPMN),
1048 SR_TRAP(SYS_PMEVCNTRn_EL0(28), CGT_MDCR_TPM_HPMN),
1049 SR_TRAP(SYS_PMEVCNTRn_EL0(29), CGT_MDCR_TPM_HPMN),
1050 SR_TRAP(SYS_PMEVCNTRn_EL0(30), CGT_MDCR_TPM_HPMN),
1051 SR_TRAP(SYS_PMEVTYPERn_EL0(0), CGT_MDCR_TPM_HPMN),
1052 SR_TRAP(SYS_PMEVTYPERn_EL0(1), CGT_MDCR_TPM_HPMN),
1053 SR_TRAP(SYS_PMEVTYPERn_EL0(2), CGT_MDCR_TPM_HPMN),
1054 SR_TRAP(SYS_PMEVTYPERn_EL0(3), CGT_MDCR_TPM_HPMN),
1055 SR_TRAP(SYS_PMEVTYPERn_EL0(4), CGT_MDCR_TPM_HPMN),
1056 SR_TRAP(SYS_PMEVTYPERn_EL0(5), CGT_MDCR_TPM_HPMN),
1057 SR_TRAP(SYS_PMEVTYPERn_EL0(6), CGT_MDCR_TPM_HPMN),
1058 SR_TRAP(SYS_PMEVTYPERn_EL0(7), CGT_MDCR_TPM_HPMN),
1059 SR_TRAP(SYS_PMEVTYPERn_EL0(8), CGT_MDCR_TPM_HPMN),
1060 SR_TRAP(SYS_PMEVTYPERn_EL0(9), CGT_MDCR_TPM_HPMN),
1061 SR_TRAP(SYS_PMEVTYPERn_EL0(10), CGT_MDCR_TPM_HPMN),
1062 SR_TRAP(SYS_PMEVTYPERn_EL0(11), CGT_MDCR_TPM_HPMN),
1063 SR_TRAP(SYS_PMEVTYPERn_EL0(12), CGT_MDCR_TPM_HPMN),
1064 SR_TRAP(SYS_PMEVTYPERn_EL0(13), CGT_MDCR_TPM_HPMN),
1065 SR_TRAP(SYS_PMEVTYPERn_EL0(14), CGT_MDCR_TPM_HPMN),
1066 SR_TRAP(SYS_PMEVTYPERn_EL0(15), CGT_MDCR_TPM_HPMN),
1067 SR_TRAP(SYS_PMEVTYPERn_EL0(16), CGT_MDCR_TPM_HPMN),
1068 SR_TRAP(SYS_PMEVTYPERn_EL0(17), CGT_MDCR_TPM_HPMN),
1069 SR_TRAP(SYS_PMEVTYPERn_EL0(18), CGT_MDCR_TPM_HPMN),
1070 SR_TRAP(SYS_PMEVTYPERn_EL0(19), CGT_MDCR_TPM_HPMN),
1071 SR_TRAP(SYS_PMEVTYPERn_EL0(20), CGT_MDCR_TPM_HPMN),
1072 SR_TRAP(SYS_PMEVTYPERn_EL0(21), CGT_MDCR_TPM_HPMN),
1073 SR_TRAP(SYS_PMEVTYPERn_EL0(22), CGT_MDCR_TPM_HPMN),
1074 SR_TRAP(SYS_PMEVTYPERn_EL0(23), CGT_MDCR_TPM_HPMN),
1075 SR_TRAP(SYS_PMEVTYPERn_EL0(24), CGT_MDCR_TPM_HPMN),
1076 SR_TRAP(SYS_PMEVTYPERn_EL0(25), CGT_MDCR_TPM_HPMN),
1077 SR_TRAP(SYS_PMEVTYPERn_EL0(26), CGT_MDCR_TPM_HPMN),
1078 SR_TRAP(SYS_PMEVTYPERn_EL0(27), CGT_MDCR_TPM_HPMN),
1079 SR_TRAP(SYS_PMEVTYPERn_EL0(28), CGT_MDCR_TPM_HPMN),
1080 SR_TRAP(SYS_PMEVTYPERn_EL0(29), CGT_MDCR_TPM_HPMN),
1081 SR_TRAP(SYS_PMEVTYPERn_EL0(30), CGT_MDCR_TPM_HPMN),
1082 SR_TRAP(SYS_PMCCFILTR_EL0, CGT_MDCR_TPM),
1083 SR_TRAP(SYS_MDCCSR_EL0, CGT_MDCR_TDCC_TDE_TDA),
1084 SR_TRAP(SYS_MDCCINT_EL1, CGT_MDCR_TDCC_TDE_TDA),
1085 SR_TRAP(SYS_OSDTRRX_EL1, CGT_MDCR_TDCC_TDE_TDA),
1086 SR_TRAP(SYS_OSDTRTX_EL1, CGT_MDCR_TDCC_TDE_TDA),
1087 SR_TRAP(SYS_DBGDTR_EL0, CGT_MDCR_TDCC_TDE_TDA),
1088 /*
1089 * Also covers DBGDTRRX_EL0, which has the same encoding as
1090 * SYS_DBGDTRTX_EL0...
1091 */
1092 SR_TRAP(SYS_DBGDTRTX_EL0, CGT_MDCR_TDCC_TDE_TDA),
1093 SR_TRAP(SYS_MDSCR_EL1, CGT_MDCR_TDE_TDA),
1094 SR_TRAP(SYS_OSECCR_EL1, CGT_MDCR_TDE_TDA),
1095 SR_TRAP(SYS_DBGBVRn_EL1(0), CGT_MDCR_TDE_TDA),
1096 SR_TRAP(SYS_DBGBVRn_EL1(1), CGT_MDCR_TDE_TDA),
1097 SR_TRAP(SYS_DBGBVRn_EL1(2), CGT_MDCR_TDE_TDA),
1098 SR_TRAP(SYS_DBGBVRn_EL1(3), CGT_MDCR_TDE_TDA),
1099 SR_TRAP(SYS_DBGBVRn_EL1(4), CGT_MDCR_TDE_TDA),
1100 SR_TRAP(SYS_DBGBVRn_EL1(5), CGT_MDCR_TDE_TDA),
1101 SR_TRAP(SYS_DBGBVRn_EL1(6), CGT_MDCR_TDE_TDA),
1102 SR_TRAP(SYS_DBGBVRn_EL1(7), CGT_MDCR_TDE_TDA),
1103 SR_TRAP(SYS_DBGBVRn_EL1(8), CGT_MDCR_TDE_TDA),
1104 SR_TRAP(SYS_DBGBVRn_EL1(9), CGT_MDCR_TDE_TDA),
1105 SR_TRAP(SYS_DBGBVRn_EL1(10), CGT_MDCR_TDE_TDA),
1106 SR_TRAP(SYS_DBGBVRn_EL1(11), CGT_MDCR_TDE_TDA),
1107 SR_TRAP(SYS_DBGBVRn_EL1(12), CGT_MDCR_TDE_TDA),
1108 SR_TRAP(SYS_DBGBVRn_EL1(13), CGT_MDCR_TDE_TDA),
1109 SR_TRAP(SYS_DBGBVRn_EL1(14), CGT_MDCR_TDE_TDA),
1110 SR_TRAP(SYS_DBGBVRn_EL1(15), CGT_MDCR_TDE_TDA),
1111 SR_TRAP(SYS_DBGBCRn_EL1(0), CGT_MDCR_TDE_TDA),
1112 SR_TRAP(SYS_DBGBCRn_EL1(1), CGT_MDCR_TDE_TDA),
1113 SR_TRAP(SYS_DBGBCRn_EL1(2), CGT_MDCR_TDE_TDA),
1114 SR_TRAP(SYS_DBGBCRn_EL1(3), CGT_MDCR_TDE_TDA),
1115 SR_TRAP(SYS_DBGBCRn_EL1(4), CGT_MDCR_TDE_TDA),
1116 SR_TRAP(SYS_DBGBCRn_EL1(5), CGT_MDCR_TDE_TDA),
1117 SR_TRAP(SYS_DBGBCRn_EL1(6), CGT_MDCR_TDE_TDA),
1118 SR_TRAP(SYS_DBGBCRn_EL1(7), CGT_MDCR_TDE_TDA),
1119 SR_TRAP(SYS_DBGBCRn_EL1(8), CGT_MDCR_TDE_TDA),
1120 SR_TRAP(SYS_DBGBCRn_EL1(9), CGT_MDCR_TDE_TDA),
1121 SR_TRAP(SYS_DBGBCRn_EL1(10), CGT_MDCR_TDE_TDA),
1122 SR_TRAP(SYS_DBGBCRn_EL1(11), CGT_MDCR_TDE_TDA),
1123 SR_TRAP(SYS_DBGBCRn_EL1(12), CGT_MDCR_TDE_TDA),
1124 SR_TRAP(SYS_DBGBCRn_EL1(13), CGT_MDCR_TDE_TDA),
1125 SR_TRAP(SYS_DBGBCRn_EL1(14), CGT_MDCR_TDE_TDA),
1126 SR_TRAP(SYS_DBGBCRn_EL1(15), CGT_MDCR_TDE_TDA),
1127 SR_TRAP(SYS_DBGWVRn_EL1(0), CGT_MDCR_TDE_TDA),
1128 SR_TRAP(SYS_DBGWVRn_EL1(1), CGT_MDCR_TDE_TDA),
1129 SR_TRAP(SYS_DBGWVRn_EL1(2), CGT_MDCR_TDE_TDA),
1130 SR_TRAP(SYS_DBGWVRn_EL1(3), CGT_MDCR_TDE_TDA),
1131 SR_TRAP(SYS_DBGWVRn_EL1(4), CGT_MDCR_TDE_TDA),
1132 SR_TRAP(SYS_DBGWVRn_EL1(5), CGT_MDCR_TDE_TDA),
1133 SR_TRAP(SYS_DBGWVRn_EL1(6), CGT_MDCR_TDE_TDA),
1134 SR_TRAP(SYS_DBGWVRn_EL1(7), CGT_MDCR_TDE_TDA),
1135 SR_TRAP(SYS_DBGWVRn_EL1(8), CGT_MDCR_TDE_TDA),
1136 SR_TRAP(SYS_DBGWVRn_EL1(9), CGT_MDCR_TDE_TDA),
1137 SR_TRAP(SYS_DBGWVRn_EL1(10), CGT_MDCR_TDE_TDA),
1138 SR_TRAP(SYS_DBGWVRn_EL1(11), CGT_MDCR_TDE_TDA),
1139 SR_TRAP(SYS_DBGWVRn_EL1(12), CGT_MDCR_TDE_TDA),
1140 SR_TRAP(SYS_DBGWVRn_EL1(13), CGT_MDCR_TDE_TDA),
1141 SR_TRAP(SYS_DBGWVRn_EL1(14), CGT_MDCR_TDE_TDA),
1142 SR_TRAP(SYS_DBGWVRn_EL1(15), CGT_MDCR_TDE_TDA),
1143 SR_TRAP(SYS_DBGWCRn_EL1(0), CGT_MDCR_TDE_TDA),
1144 SR_TRAP(SYS_DBGWCRn_EL1(1), CGT_MDCR_TDE_TDA),
1145 SR_TRAP(SYS_DBGWCRn_EL1(2), CGT_MDCR_TDE_TDA),
1146 SR_TRAP(SYS_DBGWCRn_EL1(3), CGT_MDCR_TDE_TDA),
1147 SR_TRAP(SYS_DBGWCRn_EL1(4), CGT_MDCR_TDE_TDA),
1148 SR_TRAP(SYS_DBGWCRn_EL1(5), CGT_MDCR_TDE_TDA),
1149 SR_TRAP(SYS_DBGWCRn_EL1(6), CGT_MDCR_TDE_TDA),
1150 SR_TRAP(SYS_DBGWCRn_EL1(7), CGT_MDCR_TDE_TDA),
1151 SR_TRAP(SYS_DBGWCRn_EL1(8), CGT_MDCR_TDE_TDA),
1152 SR_TRAP(SYS_DBGWCRn_EL1(9), CGT_MDCR_TDE_TDA),
1153 SR_TRAP(SYS_DBGWCRn_EL1(10), CGT_MDCR_TDE_TDA),
1154 SR_TRAP(SYS_DBGWCRn_EL1(11), CGT_MDCR_TDE_TDA),
1155 SR_TRAP(SYS_DBGWCRn_EL1(12), CGT_MDCR_TDE_TDA),
1156 SR_TRAP(SYS_DBGWCRn_EL1(13), CGT_MDCR_TDE_TDA),
1157 SR_TRAP(SYS_DBGWCRn_EL1(14), CGT_MDCR_TDE_TDA),
1158 SR_TRAP(SYS_DBGCLAIMSET_EL1, CGT_MDCR_TDE_TDA),
1159 SR_TRAP(SYS_DBGCLAIMCLR_EL1, CGT_MDCR_TDE_TDA),
1160 SR_TRAP(SYS_DBGAUTHSTATUS_EL1, CGT_MDCR_TDE_TDA),
1161 SR_TRAP(SYS_OSLAR_EL1, CGT_MDCR_TDE_TDOSA),
1162 SR_TRAP(SYS_OSLSR_EL1, CGT_MDCR_TDE_TDOSA),
1163 SR_TRAP(SYS_OSDLR_EL1, CGT_MDCR_TDE_TDOSA),
1164 SR_TRAP(SYS_DBGPRCR_EL1, CGT_MDCR_TDE_TDOSA),
1165 SR_TRAP(SYS_MDRAR_EL1, CGT_MDCR_TDE_TDRA),
1166 SR_TRAP(SYS_PMBLIMITR_EL1, CGT_MDCR_E2PB),
1167 SR_TRAP(SYS_PMBPTR_EL1, CGT_MDCR_E2PB),
1168 SR_TRAP(SYS_PMBSR_EL1, CGT_MDCR_E2PB),
1169 SR_TRAP(SYS_PMSCR_EL1, CGT_MDCR_TPMS),
1170 SR_TRAP(SYS_PMSEVFR_EL1, CGT_MDCR_TPMS),
1171 SR_TRAP(SYS_PMSFCR_EL1, CGT_MDCR_TPMS),
1172 SR_TRAP(SYS_PMSICR_EL1, CGT_MDCR_TPMS),
1173 SR_TRAP(SYS_PMSIDR_EL1, CGT_MDCR_TPMS),
1174 SR_TRAP(SYS_PMSIRR_EL1, CGT_MDCR_TPMS),
1175 SR_TRAP(SYS_PMSLATFR_EL1, CGT_MDCR_TPMS),
1176 SR_TRAP(SYS_PMSNEVFR_EL1, CGT_MDCR_TPMS),
1177 SR_TRAP(SYS_TRFCR_EL1, CGT_MDCR_TTRF),
1178 SR_TRAP(SYS_TRBBASER_EL1, CGT_MDCR_E2TB),
1179 SR_TRAP(SYS_TRBLIMITR_EL1, CGT_MDCR_E2TB),
1180 SR_TRAP(SYS_TRBMAR_EL1, CGT_MDCR_E2TB),
1181 SR_TRAP(SYS_TRBPTR_EL1, CGT_MDCR_E2TB),
1182 SR_TRAP(SYS_TRBSR_EL1, CGT_MDCR_E2TB),
1183 SR_TRAP(SYS_TRBTRG_EL1, CGT_MDCR_E2TB),
1184 SR_TRAP(SYS_CPACR_EL1, CGT_CPTR_TCPAC),
1185 SR_TRAP(SYS_AMUSERENR_EL0, CGT_CPTR_TAM),
1186 SR_TRAP(SYS_AMCFGR_EL0, CGT_CPTR_TAM),
1187 SR_TRAP(SYS_AMCGCR_EL0, CGT_CPTR_TAM),
1188 SR_TRAP(SYS_AMCNTENCLR0_EL0, CGT_CPTR_TAM),
1189 SR_TRAP(SYS_AMCNTENCLR1_EL0, CGT_CPTR_TAM),
1190 SR_TRAP(SYS_AMCNTENSET0_EL0, CGT_CPTR_TAM),
1191 SR_TRAP(SYS_AMCNTENSET1_EL0, CGT_CPTR_TAM),
1192 SR_TRAP(SYS_AMCR_EL0, CGT_CPTR_TAM),
1193 SR_TRAP(SYS_AMEVCNTR0_EL0(0), CGT_CPTR_TAM),
1194 SR_TRAP(SYS_AMEVCNTR0_EL0(1), CGT_CPTR_TAM),
1195 SR_TRAP(SYS_AMEVCNTR0_EL0(2), CGT_CPTR_TAM),
1196 SR_TRAP(SYS_AMEVCNTR0_EL0(3), CGT_CPTR_TAM),
1197 SR_TRAP(SYS_AMEVCNTR1_EL0(0), CGT_CPTR_TAM),
1198 SR_TRAP(SYS_AMEVCNTR1_EL0(1), CGT_CPTR_TAM),
1199 SR_TRAP(SYS_AMEVCNTR1_EL0(2), CGT_CPTR_TAM),
1200 SR_TRAP(SYS_AMEVCNTR1_EL0(3), CGT_CPTR_TAM),
1201 SR_TRAP(SYS_AMEVCNTR1_EL0(4), CGT_CPTR_TAM),
1202 SR_TRAP(SYS_AMEVCNTR1_EL0(5), CGT_CPTR_TAM),
1203 SR_TRAP(SYS_AMEVCNTR1_EL0(6), CGT_CPTR_TAM),
1204 SR_TRAP(SYS_AMEVCNTR1_EL0(7), CGT_CPTR_TAM),
1205 SR_TRAP(SYS_AMEVCNTR1_EL0(8), CGT_CPTR_TAM),
1206 SR_TRAP(SYS_AMEVCNTR1_EL0(9), CGT_CPTR_TAM),
1207 SR_TRAP(SYS_AMEVCNTR1_EL0(10), CGT_CPTR_TAM),
1208 SR_TRAP(SYS_AMEVCNTR1_EL0(11), CGT_CPTR_TAM),
1209 SR_TRAP(SYS_AMEVCNTR1_EL0(12), CGT_CPTR_TAM),
1210 SR_TRAP(SYS_AMEVCNTR1_EL0(13), CGT_CPTR_TAM),
1211 SR_TRAP(SYS_AMEVCNTR1_EL0(14), CGT_CPTR_TAM),
1212 SR_TRAP(SYS_AMEVCNTR1_EL0(15), CGT_CPTR_TAM),
1213 SR_TRAP(SYS_AMEVTYPER0_EL0(0), CGT_CPTR_TAM),
1214 SR_TRAP(SYS_AMEVTYPER0_EL0(1), CGT_CPTR_TAM),
1215 SR_TRAP(SYS_AMEVTYPER0_EL0(2), CGT_CPTR_TAM),
1216 SR_TRAP(SYS_AMEVTYPER0_EL0(3), CGT_CPTR_TAM),
1217 SR_TRAP(SYS_AMEVTYPER1_EL0(0), CGT_CPTR_TAM),
1218 SR_TRAP(SYS_AMEVTYPER1_EL0(1), CGT_CPTR_TAM),
1219 SR_TRAP(SYS_AMEVTYPER1_EL0(2), CGT_CPTR_TAM),
1220 SR_TRAP(SYS_AMEVTYPER1_EL0(3), CGT_CPTR_TAM),
1221 SR_TRAP(SYS_AMEVTYPER1_EL0(4), CGT_CPTR_TAM),
1222 SR_TRAP(SYS_AMEVTYPER1_EL0(5), CGT_CPTR_TAM),
1223 SR_TRAP(SYS_AMEVTYPER1_EL0(6), CGT_CPTR_TAM),
1224 SR_TRAP(SYS_AMEVTYPER1_EL0(7), CGT_CPTR_TAM),
1225 SR_TRAP(SYS_AMEVTYPER1_EL0(8), CGT_CPTR_TAM),
1226 SR_TRAP(SYS_AMEVTYPER1_EL0(9), CGT_CPTR_TAM),
1227 SR_TRAP(SYS_AMEVTYPER1_EL0(10), CGT_CPTR_TAM),
1228 SR_TRAP(SYS_AMEVTYPER1_EL0(11), CGT_CPTR_TAM),
1229 SR_TRAP(SYS_AMEVTYPER1_EL0(12), CGT_CPTR_TAM),
1230 SR_TRAP(SYS_AMEVTYPER1_EL0(13), CGT_CPTR_TAM),
1231 SR_TRAP(SYS_AMEVTYPER1_EL0(14), CGT_CPTR_TAM),
1232 SR_TRAP(SYS_AMEVTYPER1_EL0(15), CGT_CPTR_TAM),
1233 /* op0=2, op1=1, and CRn<0b1000 */
1234 SR_RANGE_TRAP(sys_reg(2, 1, 0, 0, 0),
1235 sys_reg(2, 1, 7, 15, 7), CGT_CPTR_TTA),
1236 SR_TRAP(SYS_CNTP_TVAL_EL0, CGT_CNTHCTL_EL1PTEN),
1237 SR_TRAP(SYS_CNTP_CVAL_EL0, CGT_CNTHCTL_EL1PTEN),
1238 SR_TRAP(SYS_CNTP_CTL_EL0, CGT_CNTHCTL_EL1PTEN),
1239 SR_TRAP(SYS_CNTPCT_EL0, CGT_CNTHCTL_EL1PCTEN),
1240 SR_TRAP(SYS_CNTPCTSS_EL0, CGT_CNTHCTL_EL1PCTEN),
1241 SR_TRAP(SYS_CNTV_TVAL_EL0, CGT_CNTHCTL_EL1TVT),
1242 SR_TRAP(SYS_CNTV_CVAL_EL0, CGT_CNTHCTL_EL1TVT),
1243 SR_TRAP(SYS_CNTV_CTL_EL0, CGT_CNTHCTL_EL1TVT),
1244 SR_TRAP(SYS_CNTVCT_EL0, CGT_CNTHCTL_EL1TVCT),
1245 SR_TRAP(SYS_CNTVCTSS_EL0, CGT_CNTHCTL_EL1TVCT),
1246 SR_TRAP(SYS_FPMR, CGT_HCRX_EnFPM),
1247 /*
1248 * IMPDEF choice:
1249 * We treat ICC_SRE_EL2.{SRE,Enable) and ICV_SRE_EL1.SRE as
1250 * RAO/WI. We therefore never consider ICC_SRE_EL2.Enable for
1251 * ICC_SRE_EL1 access, and always handle it locally.
1252 */
1253 SR_TRAP(SYS_ICC_AP0R0_EL1, CGT_ICH_HCR_TALL0),
1254 SR_TRAP(SYS_ICC_AP0R1_EL1, CGT_ICH_HCR_TALL0),
1255 SR_TRAP(SYS_ICC_AP0R2_EL1, CGT_ICH_HCR_TALL0),
1256 SR_TRAP(SYS_ICC_AP0R3_EL1, CGT_ICH_HCR_TALL0),
1257 SR_TRAP(SYS_ICC_AP1R0_EL1, CGT_ICH_HCR_TALL1),
1258 SR_TRAP(SYS_ICC_AP1R1_EL1, CGT_ICH_HCR_TALL1),
1259 SR_TRAP(SYS_ICC_AP1R2_EL1, CGT_ICH_HCR_TALL1),
1260 SR_TRAP(SYS_ICC_AP1R3_EL1, CGT_ICH_HCR_TALL1),
1261 SR_TRAP(SYS_ICC_BPR0_EL1, CGT_ICH_HCR_TALL0),
1262 SR_TRAP(SYS_ICC_BPR1_EL1, CGT_ICH_HCR_TALL1),
1263 SR_TRAP(SYS_ICC_CTLR_EL1, CGT_ICH_HCR_TC),
1264 SR_TRAP(SYS_ICC_DIR_EL1, CGT_ICH_HCR_TC_TDIR),
1265 SR_TRAP(SYS_ICC_EOIR0_EL1, CGT_ICH_HCR_TALL0),
1266 SR_TRAP(SYS_ICC_EOIR1_EL1, CGT_ICH_HCR_TALL1),
1267 SR_TRAP(SYS_ICC_HPPIR0_EL1, CGT_ICH_HCR_TALL0),
1268 SR_TRAP(SYS_ICC_HPPIR1_EL1, CGT_ICH_HCR_TALL1),
1269 SR_TRAP(SYS_ICC_IAR0_EL1, CGT_ICH_HCR_TALL0),
1270 SR_TRAP(SYS_ICC_IAR1_EL1, CGT_ICH_HCR_TALL1),
1271 SR_TRAP(SYS_ICC_IGRPEN0_EL1, CGT_ICH_HCR_TALL0),
1272 SR_TRAP(SYS_ICC_IGRPEN1_EL1, CGT_ICH_HCR_TALL1),
1273 SR_TRAP(SYS_ICC_PMR_EL1, CGT_ICH_HCR_TC),
1274 SR_TRAP(SYS_ICC_RPR_EL1, CGT_ICH_HCR_TC),
1275 };
1276
1277 static DEFINE_XARRAY(sr_forward_xa);
1278
1279 enum fg_filter_id {
1280 __NO_FGF__,
1281 HCRX_FGTnXS,
1282
1283 /* Must be last */
1284 __NR_FG_FILTER_IDS__
1285 };
1286
1287 #define __FGT(g, b, p, f) \
1288 { \
1289 .fgt = g ## _GROUP, \
1290 .bit = g ## _EL2_ ## b ## _SHIFT, \
1291 .pol = p, \
1292 .fgf = f, \
1293 }
1294
1295 #define FGT(g, b, p) __FGT(g, b, p, __NO_FGF__)
1296
1297 /*
1298 * See the warning next to SR_RANGE_TRAP(), and apply the same
1299 * level of caution.
1300 */
1301 #define SR_FGF_RANGE(sr, e, g, b, p, f) \
1302 { \
1303 .encoding = sr, \
1304 .end = e, \
1305 .tc = __FGT(g, b, p, f), \
1306 .line = __LINE__, \
1307 }
1308
1309 #define SR_FGF(sr, g, b, p, f) SR_FGF_RANGE(sr, sr, g, b, p, f)
1310 #define SR_FGT(sr, g, b, p) SR_FGF_RANGE(sr, sr, g, b, p, __NO_FGF__)
1311 #define SR_FGT_RANGE(sr, end, g, b, p) \
1312 SR_FGF_RANGE(sr, end, g, b, p, __NO_FGF__)
1313
1314 static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {
1315 /* HFGRTR_EL2, HFGWTR_EL2 */
1316 SR_FGT(SYS_AMAIR2_EL1, HFGRTR, nAMAIR2_EL1, 0),
1317 SR_FGT(SYS_MAIR2_EL1, HFGRTR, nMAIR2_EL1, 0),
1318 SR_FGT(SYS_S2POR_EL1, HFGRTR, nS2POR_EL1, 0),
1319 SR_FGT(SYS_POR_EL1, HFGRTR, nPOR_EL1, 0),
1320 SR_FGT(SYS_POR_EL0, HFGRTR, nPOR_EL0, 0),
1321 SR_FGT(SYS_PIR_EL1, HFGRTR, nPIR_EL1, 0),
1322 SR_FGT(SYS_PIRE0_EL1, HFGRTR, nPIRE0_EL1, 0),
1323 SR_FGT(SYS_RCWMASK_EL1, HFGRTR, nRCWMASK_EL1, 0),
1324 SR_FGT(SYS_TPIDR2_EL0, HFGRTR, nTPIDR2_EL0, 0),
1325 SR_FGT(SYS_SMPRI_EL1, HFGRTR, nSMPRI_EL1, 0),
1326 SR_FGT(SYS_GCSCR_EL1, HFGRTR, nGCS_EL1, 0),
1327 SR_FGT(SYS_GCSPR_EL1, HFGRTR, nGCS_EL1, 0),
1328 SR_FGT(SYS_GCSCRE0_EL1, HFGRTR, nGCS_EL0, 0),
1329 SR_FGT(SYS_GCSPR_EL0, HFGRTR, nGCS_EL0, 0),
1330 SR_FGT(SYS_ACCDATA_EL1, HFGRTR, nACCDATA_EL1, 0),
1331 SR_FGT(SYS_ERXADDR_EL1, HFGRTR, ERXADDR_EL1, 1),
1332 SR_FGT(SYS_ERXPFGCDN_EL1, HFGRTR, ERXPFGCDN_EL1, 1),
1333 SR_FGT(SYS_ERXPFGCTL_EL1, HFGRTR, ERXPFGCTL_EL1, 1),
1334 SR_FGT(SYS_ERXPFGF_EL1, HFGRTR, ERXPFGF_EL1, 1),
1335 SR_FGT(SYS_ERXMISC0_EL1, HFGRTR, ERXMISCn_EL1, 1),
1336 SR_FGT(SYS_ERXMISC1_EL1, HFGRTR, ERXMISCn_EL1, 1),
1337 SR_FGT(SYS_ERXMISC2_EL1, HFGRTR, ERXMISCn_EL1, 1),
1338 SR_FGT(SYS_ERXMISC3_EL1, HFGRTR, ERXMISCn_EL1, 1),
1339 SR_FGT(SYS_ERXSTATUS_EL1, HFGRTR, ERXSTATUS_EL1, 1),
1340 SR_FGT(SYS_ERXCTLR_EL1, HFGRTR, ERXCTLR_EL1, 1),
1341 SR_FGT(SYS_ERXFR_EL1, HFGRTR, ERXFR_EL1, 1),
1342 SR_FGT(SYS_ERRSELR_EL1, HFGRTR, ERRSELR_EL1, 1),
1343 SR_FGT(SYS_ERRIDR_EL1, HFGRTR, ERRIDR_EL1, 1),
1344 SR_FGT(SYS_ICC_IGRPEN0_EL1, HFGRTR, ICC_IGRPENn_EL1, 1),
1345 SR_FGT(SYS_ICC_IGRPEN1_EL1, HFGRTR, ICC_IGRPENn_EL1, 1),
1346 SR_FGT(SYS_VBAR_EL1, HFGRTR, VBAR_EL1, 1),
1347 SR_FGT(SYS_TTBR1_EL1, HFGRTR, TTBR1_EL1, 1),
1348 SR_FGT(SYS_TTBR0_EL1, HFGRTR, TTBR0_EL1, 1),
1349 SR_FGT(SYS_TPIDR_EL0, HFGRTR, TPIDR_EL0, 1),
1350 SR_FGT(SYS_TPIDRRO_EL0, HFGRTR, TPIDRRO_EL0, 1),
1351 SR_FGT(SYS_TPIDR_EL1, HFGRTR, TPIDR_EL1, 1),
1352 SR_FGT(SYS_TCR_EL1, HFGRTR, TCR_EL1, 1),
1353 SR_FGT(SYS_TCR2_EL1, HFGRTR, TCR_EL1, 1),
1354 SR_FGT(SYS_SCXTNUM_EL0, HFGRTR, SCXTNUM_EL0, 1),
1355 SR_FGT(SYS_SCXTNUM_EL1, HFGRTR, SCXTNUM_EL1, 1),
1356 SR_FGT(SYS_SCTLR_EL1, HFGRTR, SCTLR_EL1, 1),
1357 SR_FGT(SYS_REVIDR_EL1, HFGRTR, REVIDR_EL1, 1),
1358 SR_FGT(SYS_PAR_EL1, HFGRTR, PAR_EL1, 1),
1359 SR_FGT(SYS_MPIDR_EL1, HFGRTR, MPIDR_EL1, 1),
1360 SR_FGT(SYS_MIDR_EL1, HFGRTR, MIDR_EL1, 1),
1361 SR_FGT(SYS_MAIR_EL1, HFGRTR, MAIR_EL1, 1),
1362 SR_FGT(SYS_LORSA_EL1, HFGRTR, LORSA_EL1, 1),
1363 SR_FGT(SYS_LORN_EL1, HFGRTR, LORN_EL1, 1),
1364 SR_FGT(SYS_LORID_EL1, HFGRTR, LORID_EL1, 1),
1365 SR_FGT(SYS_LOREA_EL1, HFGRTR, LOREA_EL1, 1),
1366 SR_FGT(SYS_LORC_EL1, HFGRTR, LORC_EL1, 1),
1367 SR_FGT(SYS_ISR_EL1, HFGRTR, ISR_EL1, 1),
1368 SR_FGT(SYS_FAR_EL1, HFGRTR, FAR_EL1, 1),
1369 SR_FGT(SYS_ESR_EL1, HFGRTR, ESR_EL1, 1),
1370 SR_FGT(SYS_DCZID_EL0, HFGRTR, DCZID_EL0, 1),
1371 SR_FGT(SYS_CTR_EL0, HFGRTR, CTR_EL0, 1),
1372 SR_FGT(SYS_CSSELR_EL1, HFGRTR, CSSELR_EL1, 1),
1373 SR_FGT(SYS_CPACR_EL1, HFGRTR, CPACR_EL1, 1),
1374 SR_FGT(SYS_CONTEXTIDR_EL1, HFGRTR, CONTEXTIDR_EL1, 1),
1375 SR_FGT(SYS_CLIDR_EL1, HFGRTR, CLIDR_EL1, 1),
1376 SR_FGT(SYS_CCSIDR_EL1, HFGRTR, CCSIDR_EL1, 1),
1377 SR_FGT(SYS_APIBKEYLO_EL1, HFGRTR, APIBKey, 1),
1378 SR_FGT(SYS_APIBKEYHI_EL1, HFGRTR, APIBKey, 1),
1379 SR_FGT(SYS_APIAKEYLO_EL1, HFGRTR, APIAKey, 1),
1380 SR_FGT(SYS_APIAKEYHI_EL1, HFGRTR, APIAKey, 1),
1381 SR_FGT(SYS_APGAKEYLO_EL1, HFGRTR, APGAKey, 1),
1382 SR_FGT(SYS_APGAKEYHI_EL1, HFGRTR, APGAKey, 1),
1383 SR_FGT(SYS_APDBKEYLO_EL1, HFGRTR, APDBKey, 1),
1384 SR_FGT(SYS_APDBKEYHI_EL1, HFGRTR, APDBKey, 1),
1385 SR_FGT(SYS_APDAKEYLO_EL1, HFGRTR, APDAKey, 1),
1386 SR_FGT(SYS_APDAKEYHI_EL1, HFGRTR, APDAKey, 1),
1387 SR_FGT(SYS_AMAIR_EL1, HFGRTR, AMAIR_EL1, 1),
1388 SR_FGT(SYS_AIDR_EL1, HFGRTR, AIDR_EL1, 1),
1389 SR_FGT(SYS_AFSR1_EL1, HFGRTR, AFSR1_EL1, 1),
1390 SR_FGT(SYS_AFSR0_EL1, HFGRTR, AFSR0_EL1, 1),
1391
1392 /* HFGRTR2_EL2, HFGWTR2_EL2 */
1393 SR_FGT(SYS_ACTLRALIAS_EL1, HFGRTR2, nACTLRALIAS_EL1, 0),
1394 SR_FGT(SYS_ACTLRMASK_EL1, HFGRTR2, nACTLRMASK_EL1, 0),
1395 SR_FGT(SYS_CPACRALIAS_EL1, HFGRTR2, nCPACRALIAS_EL1, 0),
1396 SR_FGT(SYS_CPACRMASK_EL1, HFGRTR2, nCPACRMASK_EL1, 0),
1397 SR_FGT(SYS_PFAR_EL1, HFGRTR2, nPFAR_EL1, 0),
1398 SR_FGT(SYS_RCWSMASK_EL1, HFGRTR2, nRCWSMASK_EL1, 0),
1399 SR_FGT(SYS_SCTLR2ALIAS_EL1, HFGRTR2, nSCTLRALIAS2_EL1, 0),
1400 SR_FGT(SYS_SCTLR2MASK_EL1, HFGRTR2, nSCTLR2MASK_EL1, 0),
1401 SR_FGT(SYS_SCTLRALIAS_EL1, HFGRTR2, nSCTLRALIAS_EL1, 0),
1402 SR_FGT(SYS_SCTLRMASK_EL1, HFGRTR2, nSCTLRMASK_EL1, 0),
1403 SR_FGT(SYS_TCR2ALIAS_EL1, HFGRTR2, nTCR2ALIAS_EL1, 0),
1404 SR_FGT(SYS_TCR2MASK_EL1, HFGRTR2, nTCR2MASK_EL1, 0),
1405 SR_FGT(SYS_TCRALIAS_EL1, HFGRTR2, nTCRALIAS_EL1, 0),
1406 SR_FGT(SYS_TCRMASK_EL1, HFGRTR2, nTCRMASK_EL1, 0),
1407 SR_FGT(SYS_ERXGSR_EL1, HFGRTR2, nERXGSR_EL1, 0),
1408
1409 /* HFGITR_EL2 */
1410 SR_FGT(OP_AT_S1E1A, HFGITR, ATS1E1A, 1),
1411 SR_FGT(OP_COSP_RCTX, HFGITR, COSPRCTX, 1),
1412 SR_FGT(OP_GCSPUSHX, HFGITR, nGCSEPP, 0),
1413 SR_FGT(OP_GCSPOPX, HFGITR, nGCSEPP, 0),
1414 SR_FGT(OP_GCSPUSHM, HFGITR, nGCSPUSHM_EL1, 0),
1415 SR_FGT(OP_BRB_IALL, HFGITR, nBRBIALL, 0),
1416 SR_FGT(OP_BRB_INJ, HFGITR, nBRBINJ, 0),
1417 SR_FGT(SYS_DC_CVAC, HFGITR, DCCVAC, 1),
1418 SR_FGT(SYS_DC_CGVAC, HFGITR, DCCVAC, 1),
1419 SR_FGT(SYS_DC_CGDVAC, HFGITR, DCCVAC, 1),
1420 SR_FGT(OP_CPP_RCTX, HFGITR, CPPRCTX, 1),
1421 SR_FGT(OP_DVP_RCTX, HFGITR, DVPRCTX, 1),
1422 SR_FGT(OP_CFP_RCTX, HFGITR, CFPRCTX, 1),
1423 SR_FGT(OP_TLBI_VAALE1, HFGITR, TLBIVAALE1, 1),
1424 SR_FGT(OP_TLBI_VALE1, HFGITR, TLBIVALE1, 1),
1425 SR_FGT(OP_TLBI_VAAE1, HFGITR, TLBIVAAE1, 1),
1426 SR_FGT(OP_TLBI_ASIDE1, HFGITR, TLBIASIDE1, 1),
1427 SR_FGT(OP_TLBI_VAE1, HFGITR, TLBIVAE1, 1),
1428 SR_FGT(OP_TLBI_VMALLE1, HFGITR, TLBIVMALLE1, 1),
1429 SR_FGT(OP_TLBI_RVAALE1, HFGITR, TLBIRVAALE1, 1),
1430 SR_FGT(OP_TLBI_RVALE1, HFGITR, TLBIRVALE1, 1),
1431 SR_FGT(OP_TLBI_RVAAE1, HFGITR, TLBIRVAAE1, 1),
1432 SR_FGT(OP_TLBI_RVAE1, HFGITR, TLBIRVAE1, 1),
1433 SR_FGT(OP_TLBI_RVAALE1IS, HFGITR, TLBIRVAALE1IS, 1),
1434 SR_FGT(OP_TLBI_RVALE1IS, HFGITR, TLBIRVALE1IS, 1),
1435 SR_FGT(OP_TLBI_RVAAE1IS, HFGITR, TLBIRVAAE1IS, 1),
1436 SR_FGT(OP_TLBI_RVAE1IS, HFGITR, TLBIRVAE1IS, 1),
1437 SR_FGT(OP_TLBI_VAALE1IS, HFGITR, TLBIVAALE1IS, 1),
1438 SR_FGT(OP_TLBI_VALE1IS, HFGITR, TLBIVALE1IS, 1),
1439 SR_FGT(OP_TLBI_VAAE1IS, HFGITR, TLBIVAAE1IS, 1),
1440 SR_FGT(OP_TLBI_ASIDE1IS, HFGITR, TLBIASIDE1IS, 1),
1441 SR_FGT(OP_TLBI_VAE1IS, HFGITR, TLBIVAE1IS, 1),
1442 SR_FGT(OP_TLBI_VMALLE1IS, HFGITR, TLBIVMALLE1IS, 1),
1443 SR_FGT(OP_TLBI_RVAALE1OS, HFGITR, TLBIRVAALE1OS, 1),
1444 SR_FGT(OP_TLBI_RVALE1OS, HFGITR, TLBIRVALE1OS, 1),
1445 SR_FGT(OP_TLBI_RVAAE1OS, HFGITR, TLBIRVAAE1OS, 1),
1446 SR_FGT(OP_TLBI_RVAE1OS, HFGITR, TLBIRVAE1OS, 1),
1447 SR_FGT(OP_TLBI_VAALE1OS, HFGITR, TLBIVAALE1OS, 1),
1448 SR_FGT(OP_TLBI_VALE1OS, HFGITR, TLBIVALE1OS, 1),
1449 SR_FGT(OP_TLBI_VAAE1OS, HFGITR, TLBIVAAE1OS, 1),
1450 SR_FGT(OP_TLBI_ASIDE1OS, HFGITR, TLBIASIDE1OS, 1),
1451 SR_FGT(OP_TLBI_VAE1OS, HFGITR, TLBIVAE1OS, 1),
1452 SR_FGT(OP_TLBI_VMALLE1OS, HFGITR, TLBIVMALLE1OS, 1),
1453 /* nXS variants must be checked against HCRX_EL2.FGTnXS */
1454 SR_FGF(OP_TLBI_VAALE1NXS, HFGITR, TLBIVAALE1, 1, HCRX_FGTnXS),
1455 SR_FGF(OP_TLBI_VALE1NXS, HFGITR, TLBIVALE1, 1, HCRX_FGTnXS),
1456 SR_FGF(OP_TLBI_VAAE1NXS, HFGITR, TLBIVAAE1, 1, HCRX_FGTnXS),
1457 SR_FGF(OP_TLBI_ASIDE1NXS, HFGITR, TLBIASIDE1, 1, HCRX_FGTnXS),
1458 SR_FGF(OP_TLBI_VAE1NXS, HFGITR, TLBIVAE1, 1, HCRX_FGTnXS),
1459 SR_FGF(OP_TLBI_VMALLE1NXS, HFGITR, TLBIVMALLE1, 1, HCRX_FGTnXS),
1460 SR_FGF(OP_TLBI_RVAALE1NXS, HFGITR, TLBIRVAALE1, 1, HCRX_FGTnXS),
1461 SR_FGF(OP_TLBI_RVALE1NXS, HFGITR, TLBIRVALE1, 1, HCRX_FGTnXS),
1462 SR_FGF(OP_TLBI_RVAAE1NXS, HFGITR, TLBIRVAAE1, 1, HCRX_FGTnXS),
1463 SR_FGF(OP_TLBI_RVAE1NXS, HFGITR, TLBIRVAE1, 1, HCRX_FGTnXS),
1464 SR_FGF(OP_TLBI_RVAALE1ISNXS, HFGITR, TLBIRVAALE1IS, 1, HCRX_FGTnXS),
1465 SR_FGF(OP_TLBI_RVALE1ISNXS, HFGITR, TLBIRVALE1IS, 1, HCRX_FGTnXS),
1466 SR_FGF(OP_TLBI_RVAAE1ISNXS, HFGITR, TLBIRVAAE1IS, 1, HCRX_FGTnXS),
1467 SR_FGF(OP_TLBI_RVAE1ISNXS, HFGITR, TLBIRVAE1IS, 1, HCRX_FGTnXS),
1468 SR_FGF(OP_TLBI_VAALE1ISNXS, HFGITR, TLBIVAALE1IS, 1, HCRX_FGTnXS),
1469 SR_FGF(OP_TLBI_VALE1ISNXS, HFGITR, TLBIVALE1IS, 1, HCRX_FGTnXS),
1470 SR_FGF(OP_TLBI_VAAE1ISNXS, HFGITR, TLBIVAAE1IS, 1, HCRX_FGTnXS),
1471 SR_FGF(OP_TLBI_ASIDE1ISNXS, HFGITR, TLBIASIDE1IS, 1, HCRX_FGTnXS),
1472 SR_FGF(OP_TLBI_VAE1ISNXS, HFGITR, TLBIVAE1IS, 1, HCRX_FGTnXS),
1473 SR_FGF(OP_TLBI_VMALLE1ISNXS, HFGITR, TLBIVMALLE1IS, 1, HCRX_FGTnXS),
1474 SR_FGF(OP_TLBI_RVAALE1OSNXS, HFGITR, TLBIRVAALE1OS, 1, HCRX_FGTnXS),
1475 SR_FGF(OP_TLBI_RVALE1OSNXS, HFGITR, TLBIRVALE1OS, 1, HCRX_FGTnXS),
1476 SR_FGF(OP_TLBI_RVAAE1OSNXS, HFGITR, TLBIRVAAE1OS, 1, HCRX_FGTnXS),
1477 SR_FGF(OP_TLBI_RVAE1OSNXS, HFGITR, TLBIRVAE1OS, 1, HCRX_FGTnXS),
1478 SR_FGF(OP_TLBI_VAALE1OSNXS, HFGITR, TLBIVAALE1OS, 1, HCRX_FGTnXS),
1479 SR_FGF(OP_TLBI_VALE1OSNXS, HFGITR, TLBIVALE1OS, 1, HCRX_FGTnXS),
1480 SR_FGF(OP_TLBI_VAAE1OSNXS, HFGITR, TLBIVAAE1OS, 1, HCRX_FGTnXS),
1481 SR_FGF(OP_TLBI_ASIDE1OSNXS, HFGITR, TLBIASIDE1OS, 1, HCRX_FGTnXS),
1482 SR_FGF(OP_TLBI_VAE1OSNXS, HFGITR, TLBIVAE1OS, 1, HCRX_FGTnXS),
1483 SR_FGF(OP_TLBI_VMALLE1OSNXS, HFGITR, TLBIVMALLE1OS, 1, HCRX_FGTnXS),
1484 SR_FGT(OP_AT_S1E1WP, HFGITR, ATS1E1WP, 1),
1485 SR_FGT(OP_AT_S1E1RP, HFGITR, ATS1E1RP, 1),
1486 SR_FGT(OP_AT_S1E0W, HFGITR, ATS1E0W, 1),
1487 SR_FGT(OP_AT_S1E0R, HFGITR, ATS1E0R, 1),
1488 SR_FGT(OP_AT_S1E1W, HFGITR, ATS1E1W, 1),
1489 SR_FGT(OP_AT_S1E1R, HFGITR, ATS1E1R, 1),
1490 SR_FGT(SYS_DC_ZVA, HFGITR, DCZVA, 1),
1491 SR_FGT(SYS_DC_GVA, HFGITR, DCZVA, 1),
1492 SR_FGT(SYS_DC_GZVA, HFGITR, DCZVA, 1),
1493 SR_FGT(SYS_DC_CIVAC, HFGITR, DCCIVAC, 1),
1494 SR_FGT(SYS_DC_CIGVAC, HFGITR, DCCIVAC, 1),
1495 SR_FGT(SYS_DC_CIGDVAC, HFGITR, DCCIVAC, 1),
1496 SR_FGT(SYS_DC_CVADP, HFGITR, DCCVADP, 1),
1497 SR_FGT(SYS_DC_CGVADP, HFGITR, DCCVADP, 1),
1498 SR_FGT(SYS_DC_CGDVADP, HFGITR, DCCVADP, 1),
1499 SR_FGT(SYS_DC_CVAP, HFGITR, DCCVAP, 1),
1500 SR_FGT(SYS_DC_CGVAP, HFGITR, DCCVAP, 1),
1501 SR_FGT(SYS_DC_CGDVAP, HFGITR, DCCVAP, 1),
1502 SR_FGT(SYS_DC_CVAU, HFGITR, DCCVAU, 1),
1503 SR_FGT(SYS_DC_CISW, HFGITR, DCCISW, 1),
1504 SR_FGT(SYS_DC_CIGSW, HFGITR, DCCISW, 1),
1505 SR_FGT(SYS_DC_CIGDSW, HFGITR, DCCISW, 1),
1506 SR_FGT(SYS_DC_CSW, HFGITR, DCCSW, 1),
1507 SR_FGT(SYS_DC_CGSW, HFGITR, DCCSW, 1),
1508 SR_FGT(SYS_DC_CGDSW, HFGITR, DCCSW, 1),
1509 SR_FGT(SYS_DC_ISW, HFGITR, DCISW, 1),
1510 SR_FGT(SYS_DC_IGSW, HFGITR, DCISW, 1),
1511 SR_FGT(SYS_DC_IGDSW, HFGITR, DCISW, 1),
1512 SR_FGT(SYS_DC_IVAC, HFGITR, DCIVAC, 1),
1513 SR_FGT(SYS_DC_IGVAC, HFGITR, DCIVAC, 1),
1514 SR_FGT(SYS_DC_IGDVAC, HFGITR, DCIVAC, 1),
1515 SR_FGT(SYS_IC_IVAU, HFGITR, ICIVAU, 1),
1516 SR_FGT(SYS_IC_IALLU, HFGITR, ICIALLU, 1),
1517 SR_FGT(SYS_IC_IALLUIS, HFGITR, ICIALLUIS, 1),
1518
1519 /* HFGITR2_EL2 */
1520 SR_FGT(SYS_DC_CIGDVAPS, HFGITR2, nDCCIVAPS, 0),
1521 SR_FGT(SYS_DC_CIVAPS, HFGITR2, nDCCIVAPS, 0),
1522
1523 /* HDFGRTR_EL2 */
1524 SR_FGT(SYS_PMBIDR_EL1, HDFGRTR, PMBIDR_EL1, 1),
1525 SR_FGT(SYS_PMSNEVFR_EL1, HDFGRTR, nPMSNEVFR_EL1, 0),
1526 SR_FGT(SYS_BRBINF_EL1(0), HDFGRTR, nBRBDATA, 0),
1527 SR_FGT(SYS_BRBINF_EL1(1), HDFGRTR, nBRBDATA, 0),
1528 SR_FGT(SYS_BRBINF_EL1(2), HDFGRTR, nBRBDATA, 0),
1529 SR_FGT(SYS_BRBINF_EL1(3), HDFGRTR, nBRBDATA, 0),
1530 SR_FGT(SYS_BRBINF_EL1(4), HDFGRTR, nBRBDATA, 0),
1531 SR_FGT(SYS_BRBINF_EL1(5), HDFGRTR, nBRBDATA, 0),
1532 SR_FGT(SYS_BRBINF_EL1(6), HDFGRTR, nBRBDATA, 0),
1533 SR_FGT(SYS_BRBINF_EL1(7), HDFGRTR, nBRBDATA, 0),
1534 SR_FGT(SYS_BRBINF_EL1(8), HDFGRTR, nBRBDATA, 0),
1535 SR_FGT(SYS_BRBINF_EL1(9), HDFGRTR, nBRBDATA, 0),
1536 SR_FGT(SYS_BRBINF_EL1(10), HDFGRTR, nBRBDATA, 0),
1537 SR_FGT(SYS_BRBINF_EL1(11), HDFGRTR, nBRBDATA, 0),
1538 SR_FGT(SYS_BRBINF_EL1(12), HDFGRTR, nBRBDATA, 0),
1539 SR_FGT(SYS_BRBINF_EL1(13), HDFGRTR, nBRBDATA, 0),
1540 SR_FGT(SYS_BRBINF_EL1(14), HDFGRTR, nBRBDATA, 0),
1541 SR_FGT(SYS_BRBINF_EL1(15), HDFGRTR, nBRBDATA, 0),
1542 SR_FGT(SYS_BRBINF_EL1(16), HDFGRTR, nBRBDATA, 0),
1543 SR_FGT(SYS_BRBINF_EL1(17), HDFGRTR, nBRBDATA, 0),
1544 SR_FGT(SYS_BRBINF_EL1(18), HDFGRTR, nBRBDATA, 0),
1545 SR_FGT(SYS_BRBINF_EL1(19), HDFGRTR, nBRBDATA, 0),
1546 SR_FGT(SYS_BRBINF_EL1(20), HDFGRTR, nBRBDATA, 0),
1547 SR_FGT(SYS_BRBINF_EL1(21), HDFGRTR, nBRBDATA, 0),
1548 SR_FGT(SYS_BRBINF_EL1(22), HDFGRTR, nBRBDATA, 0),
1549 SR_FGT(SYS_BRBINF_EL1(23), HDFGRTR, nBRBDATA, 0),
1550 SR_FGT(SYS_BRBINF_EL1(24), HDFGRTR, nBRBDATA, 0),
1551 SR_FGT(SYS_BRBINF_EL1(25), HDFGRTR, nBRBDATA, 0),
1552 SR_FGT(SYS_BRBINF_EL1(26), HDFGRTR, nBRBDATA, 0),
1553 SR_FGT(SYS_BRBINF_EL1(27), HDFGRTR, nBRBDATA, 0),
1554 SR_FGT(SYS_BRBINF_EL1(28), HDFGRTR, nBRBDATA, 0),
1555 SR_FGT(SYS_BRBINF_EL1(29), HDFGRTR, nBRBDATA, 0),
1556 SR_FGT(SYS_BRBINF_EL1(30), HDFGRTR, nBRBDATA, 0),
1557 SR_FGT(SYS_BRBINF_EL1(31), HDFGRTR, nBRBDATA, 0),
1558 SR_FGT(SYS_BRBINFINJ_EL1, HDFGRTR, nBRBDATA, 0),
1559 SR_FGT(SYS_BRBSRC_EL1(0), HDFGRTR, nBRBDATA, 0),
1560 SR_FGT(SYS_BRBSRC_EL1(1), HDFGRTR, nBRBDATA, 0),
1561 SR_FGT(SYS_BRBSRC_EL1(2), HDFGRTR, nBRBDATA, 0),
1562 SR_FGT(SYS_BRBSRC_EL1(3), HDFGRTR, nBRBDATA, 0),
1563 SR_FGT(SYS_BRBSRC_EL1(4), HDFGRTR, nBRBDATA, 0),
1564 SR_FGT(SYS_BRBSRC_EL1(5), HDFGRTR, nBRBDATA, 0),
1565 SR_FGT(SYS_BRBSRC_EL1(6), HDFGRTR, nBRBDATA, 0),
1566 SR_FGT(SYS_BRBSRC_EL1(7), HDFGRTR, nBRBDATA, 0),
1567 SR_FGT(SYS_BRBSRC_EL1(8), HDFGRTR, nBRBDATA, 0),
1568 SR_FGT(SYS_BRBSRC_EL1(9), HDFGRTR, nBRBDATA, 0),
1569 SR_FGT(SYS_BRBSRC_EL1(10), HDFGRTR, nBRBDATA, 0),
1570 SR_FGT(SYS_BRBSRC_EL1(11), HDFGRTR, nBRBDATA, 0),
1571 SR_FGT(SYS_BRBSRC_EL1(12), HDFGRTR, nBRBDATA, 0),
1572 SR_FGT(SYS_BRBSRC_EL1(13), HDFGRTR, nBRBDATA, 0),
1573 SR_FGT(SYS_BRBSRC_EL1(14), HDFGRTR, nBRBDATA, 0),
1574 SR_FGT(SYS_BRBSRC_EL1(15), HDFGRTR, nBRBDATA, 0),
1575 SR_FGT(SYS_BRBSRC_EL1(16), HDFGRTR, nBRBDATA, 0),
1576 SR_FGT(SYS_BRBSRC_EL1(17), HDFGRTR, nBRBDATA, 0),
1577 SR_FGT(SYS_BRBSRC_EL1(18), HDFGRTR, nBRBDATA, 0),
1578 SR_FGT(SYS_BRBSRC_EL1(19), HDFGRTR, nBRBDATA, 0),
1579 SR_FGT(SYS_BRBSRC_EL1(20), HDFGRTR, nBRBDATA, 0),
1580 SR_FGT(SYS_BRBSRC_EL1(21), HDFGRTR, nBRBDATA, 0),
1581 SR_FGT(SYS_BRBSRC_EL1(22), HDFGRTR, nBRBDATA, 0),
1582 SR_FGT(SYS_BRBSRC_EL1(23), HDFGRTR, nBRBDATA, 0),
1583 SR_FGT(SYS_BRBSRC_EL1(24), HDFGRTR, nBRBDATA, 0),
1584 SR_FGT(SYS_BRBSRC_EL1(25), HDFGRTR, nBRBDATA, 0),
1585 SR_FGT(SYS_BRBSRC_EL1(26), HDFGRTR, nBRBDATA, 0),
1586 SR_FGT(SYS_BRBSRC_EL1(27), HDFGRTR, nBRBDATA, 0),
1587 SR_FGT(SYS_BRBSRC_EL1(28), HDFGRTR, nBRBDATA, 0),
1588 SR_FGT(SYS_BRBSRC_EL1(29), HDFGRTR, nBRBDATA, 0),
1589 SR_FGT(SYS_BRBSRC_EL1(30), HDFGRTR, nBRBDATA, 0),
1590 SR_FGT(SYS_BRBSRC_EL1(31), HDFGRTR, nBRBDATA, 0),
1591 SR_FGT(SYS_BRBSRCINJ_EL1, HDFGRTR, nBRBDATA, 0),
1592 SR_FGT(SYS_BRBTGT_EL1(0), HDFGRTR, nBRBDATA, 0),
1593 SR_FGT(SYS_BRBTGT_EL1(1), HDFGRTR, nBRBDATA, 0),
1594 SR_FGT(SYS_BRBTGT_EL1(2), HDFGRTR, nBRBDATA, 0),
1595 SR_FGT(SYS_BRBTGT_EL1(3), HDFGRTR, nBRBDATA, 0),
1596 SR_FGT(SYS_BRBTGT_EL1(4), HDFGRTR, nBRBDATA, 0),
1597 SR_FGT(SYS_BRBTGT_EL1(5), HDFGRTR, nBRBDATA, 0),
1598 SR_FGT(SYS_BRBTGT_EL1(6), HDFGRTR, nBRBDATA, 0),
1599 SR_FGT(SYS_BRBTGT_EL1(7), HDFGRTR, nBRBDATA, 0),
1600 SR_FGT(SYS_BRBTGT_EL1(8), HDFGRTR, nBRBDATA, 0),
1601 SR_FGT(SYS_BRBTGT_EL1(9), HDFGRTR, nBRBDATA, 0),
1602 SR_FGT(SYS_BRBTGT_EL1(10), HDFGRTR, nBRBDATA, 0),
1603 SR_FGT(SYS_BRBTGT_EL1(11), HDFGRTR, nBRBDATA, 0),
1604 SR_FGT(SYS_BRBTGT_EL1(12), HDFGRTR, nBRBDATA, 0),
1605 SR_FGT(SYS_BRBTGT_EL1(13), HDFGRTR, nBRBDATA, 0),
1606 SR_FGT(SYS_BRBTGT_EL1(14), HDFGRTR, nBRBDATA, 0),
1607 SR_FGT(SYS_BRBTGT_EL1(15), HDFGRTR, nBRBDATA, 0),
1608 SR_FGT(SYS_BRBTGT_EL1(16), HDFGRTR, nBRBDATA, 0),
1609 SR_FGT(SYS_BRBTGT_EL1(17), HDFGRTR, nBRBDATA, 0),
1610 SR_FGT(SYS_BRBTGT_EL1(18), HDFGRTR, nBRBDATA, 0),
1611 SR_FGT(SYS_BRBTGT_EL1(19), HDFGRTR, nBRBDATA, 0),
1612 SR_FGT(SYS_BRBTGT_EL1(20), HDFGRTR, nBRBDATA, 0),
1613 SR_FGT(SYS_BRBTGT_EL1(21), HDFGRTR, nBRBDATA, 0),
1614 SR_FGT(SYS_BRBTGT_EL1(22), HDFGRTR, nBRBDATA, 0),
1615 SR_FGT(SYS_BRBTGT_EL1(23), HDFGRTR, nBRBDATA, 0),
1616 SR_FGT(SYS_BRBTGT_EL1(24), HDFGRTR, nBRBDATA, 0),
1617 SR_FGT(SYS_BRBTGT_EL1(25), HDFGRTR, nBRBDATA, 0),
1618 SR_FGT(SYS_BRBTGT_EL1(26), HDFGRTR, nBRBDATA, 0),
1619 SR_FGT(SYS_BRBTGT_EL1(27), HDFGRTR, nBRBDATA, 0),
1620 SR_FGT(SYS_BRBTGT_EL1(28), HDFGRTR, nBRBDATA, 0),
1621 SR_FGT(SYS_BRBTGT_EL1(29), HDFGRTR, nBRBDATA, 0),
1622 SR_FGT(SYS_BRBTGT_EL1(30), HDFGRTR, nBRBDATA, 0),
1623 SR_FGT(SYS_BRBTGT_EL1(31), HDFGRTR, nBRBDATA, 0),
1624 SR_FGT(SYS_BRBTGTINJ_EL1, HDFGRTR, nBRBDATA, 0),
1625 SR_FGT(SYS_BRBTS_EL1, HDFGRTR, nBRBDATA, 0),
1626 SR_FGT(SYS_BRBCR_EL1, HDFGRTR, nBRBCTL, 0),
1627 SR_FGT(SYS_BRBFCR_EL1, HDFGRTR, nBRBCTL, 0),
1628 SR_FGT(SYS_BRBIDR0_EL1, HDFGRTR, nBRBIDR, 0),
1629 SR_FGT(SYS_PMCEID0_EL0, HDFGRTR, PMCEIDn_EL0, 1),
1630 SR_FGT(SYS_PMCEID1_EL0, HDFGRTR, PMCEIDn_EL0, 1),
1631 SR_FGT(SYS_PMUSERENR_EL0, HDFGRTR, PMUSERENR_EL0, 1),
1632 SR_FGT(SYS_TRBTRG_EL1, HDFGRTR, TRBTRG_EL1, 1),
1633 SR_FGT(SYS_TRBSR_EL1, HDFGRTR, TRBSR_EL1, 1),
1634 SR_FGT(SYS_TRBPTR_EL1, HDFGRTR, TRBPTR_EL1, 1),
1635 SR_FGT(SYS_TRBMAR_EL1, HDFGRTR, TRBMAR_EL1, 1),
1636 SR_FGT(SYS_TRBLIMITR_EL1, HDFGRTR, TRBLIMITR_EL1, 1),
1637 SR_FGT(SYS_TRBIDR_EL1, HDFGRTR, TRBIDR_EL1, 1),
1638 SR_FGT(SYS_TRBBASER_EL1, HDFGRTR, TRBBASER_EL1, 1),
1639 SR_FGT(SYS_TRCVICTLR, HDFGRTR, TRCVICTLR, 1),
1640 SR_FGT(SYS_TRCSTATR, HDFGRTR, TRCSTATR, 1),
1641 SR_FGT(SYS_TRCSSCSR(0), HDFGRTR, TRCSSCSRn, 1),
1642 SR_FGT(SYS_TRCSSCSR(1), HDFGRTR, TRCSSCSRn, 1),
1643 SR_FGT(SYS_TRCSSCSR(2), HDFGRTR, TRCSSCSRn, 1),
1644 SR_FGT(SYS_TRCSSCSR(3), HDFGRTR, TRCSSCSRn, 1),
1645 SR_FGT(SYS_TRCSSCSR(4), HDFGRTR, TRCSSCSRn, 1),
1646 SR_FGT(SYS_TRCSSCSR(5), HDFGRTR, TRCSSCSRn, 1),
1647 SR_FGT(SYS_TRCSSCSR(6), HDFGRTR, TRCSSCSRn, 1),
1648 SR_FGT(SYS_TRCSSCSR(7), HDFGRTR, TRCSSCSRn, 1),
1649 SR_FGT(SYS_TRCSEQSTR, HDFGRTR, TRCSEQSTR, 1),
1650 SR_FGT(SYS_TRCPRGCTLR, HDFGRTR, TRCPRGCTLR, 1),
1651 SR_FGT(SYS_TRCOSLSR, HDFGRTR, TRCOSLSR, 1),
1652 SR_FGT(SYS_TRCIMSPEC(0), HDFGRTR, TRCIMSPECn, 1),
1653 SR_FGT(SYS_TRCIMSPEC(1), HDFGRTR, TRCIMSPECn, 1),
1654 SR_FGT(SYS_TRCIMSPEC(2), HDFGRTR, TRCIMSPECn, 1),
1655 SR_FGT(SYS_TRCIMSPEC(3), HDFGRTR, TRCIMSPECn, 1),
1656 SR_FGT(SYS_TRCIMSPEC(4), HDFGRTR, TRCIMSPECn, 1),
1657 SR_FGT(SYS_TRCIMSPEC(5), HDFGRTR, TRCIMSPECn, 1),
1658 SR_FGT(SYS_TRCIMSPEC(6), HDFGRTR, TRCIMSPECn, 1),
1659 SR_FGT(SYS_TRCIMSPEC(7), HDFGRTR, TRCIMSPECn, 1),
1660 SR_FGT(SYS_TRCDEVARCH, HDFGRTR, TRCID, 1),
1661 SR_FGT(SYS_TRCDEVID, HDFGRTR, TRCID, 1),
1662 SR_FGT(SYS_TRCIDR0, HDFGRTR, TRCID, 1),
1663 SR_FGT(SYS_TRCIDR1, HDFGRTR, TRCID, 1),
1664 SR_FGT(SYS_TRCIDR2, HDFGRTR, TRCID, 1),
1665 SR_FGT(SYS_TRCIDR3, HDFGRTR, TRCID, 1),
1666 SR_FGT(SYS_TRCIDR4, HDFGRTR, TRCID, 1),
1667 SR_FGT(SYS_TRCIDR5, HDFGRTR, TRCID, 1),
1668 SR_FGT(SYS_TRCIDR6, HDFGRTR, TRCID, 1),
1669 SR_FGT(SYS_TRCIDR7, HDFGRTR, TRCID, 1),
1670 SR_FGT(SYS_TRCIDR8, HDFGRTR, TRCID, 1),
1671 SR_FGT(SYS_TRCIDR9, HDFGRTR, TRCID, 1),
1672 SR_FGT(SYS_TRCIDR10, HDFGRTR, TRCID, 1),
1673 SR_FGT(SYS_TRCIDR11, HDFGRTR, TRCID, 1),
1674 SR_FGT(SYS_TRCIDR12, HDFGRTR, TRCID, 1),
1675 SR_FGT(SYS_TRCIDR13, HDFGRTR, TRCID, 1),
1676 SR_FGT(SYS_TRCCNTVR(0), HDFGRTR, TRCCNTVRn, 1),
1677 SR_FGT(SYS_TRCCNTVR(1), HDFGRTR, TRCCNTVRn, 1),
1678 SR_FGT(SYS_TRCCNTVR(2), HDFGRTR, TRCCNTVRn, 1),
1679 SR_FGT(SYS_TRCCNTVR(3), HDFGRTR, TRCCNTVRn, 1),
1680 SR_FGT(SYS_TRCCLAIMCLR, HDFGRTR, TRCCLAIM, 1),
1681 SR_FGT(SYS_TRCCLAIMSET, HDFGRTR, TRCCLAIM, 1),
1682 SR_FGT(SYS_TRCAUXCTLR, HDFGRTR, TRCAUXCTLR, 1),
1683 SR_FGT(SYS_TRCAUTHSTATUS, HDFGRTR, TRCAUTHSTATUS, 1),
1684 SR_FGT(SYS_TRCACATR(0), HDFGRTR, TRC, 1),
1685 SR_FGT(SYS_TRCACATR(1), HDFGRTR, TRC, 1),
1686 SR_FGT(SYS_TRCACATR(2), HDFGRTR, TRC, 1),
1687 SR_FGT(SYS_TRCACATR(3), HDFGRTR, TRC, 1),
1688 SR_FGT(SYS_TRCACATR(4), HDFGRTR, TRC, 1),
1689 SR_FGT(SYS_TRCACATR(5), HDFGRTR, TRC, 1),
1690 SR_FGT(SYS_TRCACATR(6), HDFGRTR, TRC, 1),
1691 SR_FGT(SYS_TRCACATR(7), HDFGRTR, TRC, 1),
1692 SR_FGT(SYS_TRCACATR(8), HDFGRTR, TRC, 1),
1693 SR_FGT(SYS_TRCACATR(9), HDFGRTR, TRC, 1),
1694 SR_FGT(SYS_TRCACATR(10), HDFGRTR, TRC, 1),
1695 SR_FGT(SYS_TRCACATR(11), HDFGRTR, TRC, 1),
1696 SR_FGT(SYS_TRCACATR(12), HDFGRTR, TRC, 1),
1697 SR_FGT(SYS_TRCACATR(13), HDFGRTR, TRC, 1),
1698 SR_FGT(SYS_TRCACATR(14), HDFGRTR, TRC, 1),
1699 SR_FGT(SYS_TRCACATR(15), HDFGRTR, TRC, 1),
1700 SR_FGT(SYS_TRCACVR(0), HDFGRTR, TRC, 1),
1701 SR_FGT(SYS_TRCACVR(1), HDFGRTR, TRC, 1),
1702 SR_FGT(SYS_TRCACVR(2), HDFGRTR, TRC, 1),
1703 SR_FGT(SYS_TRCACVR(3), HDFGRTR, TRC, 1),
1704 SR_FGT(SYS_TRCACVR(4), HDFGRTR, TRC, 1),
1705 SR_FGT(SYS_TRCACVR(5), HDFGRTR, TRC, 1),
1706 SR_FGT(SYS_TRCACVR(6), HDFGRTR, TRC, 1),
1707 SR_FGT(SYS_TRCACVR(7), HDFGRTR, TRC, 1),
1708 SR_FGT(SYS_TRCACVR(8), HDFGRTR, TRC, 1),
1709 SR_FGT(SYS_TRCACVR(9), HDFGRTR, TRC, 1),
1710 SR_FGT(SYS_TRCACVR(10), HDFGRTR, TRC, 1),
1711 SR_FGT(SYS_TRCACVR(11), HDFGRTR, TRC, 1),
1712 SR_FGT(SYS_TRCACVR(12), HDFGRTR, TRC, 1),
1713 SR_FGT(SYS_TRCACVR(13), HDFGRTR, TRC, 1),
1714 SR_FGT(SYS_TRCACVR(14), HDFGRTR, TRC, 1),
1715 SR_FGT(SYS_TRCACVR(15), HDFGRTR, TRC, 1),
1716 SR_FGT(SYS_TRCBBCTLR, HDFGRTR, TRC, 1),
1717 SR_FGT(SYS_TRCCCCTLR, HDFGRTR, TRC, 1),
1718 SR_FGT(SYS_TRCCIDCCTLR0, HDFGRTR, TRC, 1),
1719 SR_FGT(SYS_TRCCIDCCTLR1, HDFGRTR, TRC, 1),
1720 SR_FGT(SYS_TRCCIDCVR(0), HDFGRTR, TRC, 1),
1721 SR_FGT(SYS_TRCCIDCVR(1), HDFGRTR, TRC, 1),
1722 SR_FGT(SYS_TRCCIDCVR(2), HDFGRTR, TRC, 1),
1723 SR_FGT(SYS_TRCCIDCVR(3), HDFGRTR, TRC, 1),
1724 SR_FGT(SYS_TRCCIDCVR(4), HDFGRTR, TRC, 1),
1725 SR_FGT(SYS_TRCCIDCVR(5), HDFGRTR, TRC, 1),
1726 SR_FGT(SYS_TRCCIDCVR(6), HDFGRTR, TRC, 1),
1727 SR_FGT(SYS_TRCCIDCVR(7), HDFGRTR, TRC, 1),
1728 SR_FGT(SYS_TRCCNTCTLR(0), HDFGRTR, TRC, 1),
1729 SR_FGT(SYS_TRCCNTCTLR(1), HDFGRTR, TRC, 1),
1730 SR_FGT(SYS_TRCCNTCTLR(2), HDFGRTR, TRC, 1),
1731 SR_FGT(SYS_TRCCNTCTLR(3), HDFGRTR, TRC, 1),
1732 SR_FGT(SYS_TRCCNTRLDVR(0), HDFGRTR, TRC, 1),
1733 SR_FGT(SYS_TRCCNTRLDVR(1), HDFGRTR, TRC, 1),
1734 SR_FGT(SYS_TRCCNTRLDVR(2), HDFGRTR, TRC, 1),
1735 SR_FGT(SYS_TRCCNTRLDVR(3), HDFGRTR, TRC, 1),
1736 SR_FGT(SYS_TRCCONFIGR, HDFGRTR, TRC, 1),
1737 SR_FGT(SYS_TRCEVENTCTL0R, HDFGRTR, TRC, 1),
1738 SR_FGT(SYS_TRCEVENTCTL1R, HDFGRTR, TRC, 1),
1739 SR_FGT(SYS_TRCEXTINSELR(0), HDFGRTR, TRC, 1),
1740 SR_FGT(SYS_TRCEXTINSELR(1), HDFGRTR, TRC, 1),
1741 SR_FGT(SYS_TRCEXTINSELR(2), HDFGRTR, TRC, 1),
1742 SR_FGT(SYS_TRCEXTINSELR(3), HDFGRTR, TRC, 1),
1743 SR_FGT(SYS_TRCQCTLR, HDFGRTR, TRC, 1),
1744 SR_FGT(SYS_TRCRSCTLR(2), HDFGRTR, TRC, 1),
1745 SR_FGT(SYS_TRCRSCTLR(3), HDFGRTR, TRC, 1),
1746 SR_FGT(SYS_TRCRSCTLR(4), HDFGRTR, TRC, 1),
1747 SR_FGT(SYS_TRCRSCTLR(5), HDFGRTR, TRC, 1),
1748 SR_FGT(SYS_TRCRSCTLR(6), HDFGRTR, TRC, 1),
1749 SR_FGT(SYS_TRCRSCTLR(7), HDFGRTR, TRC, 1),
1750 SR_FGT(SYS_TRCRSCTLR(8), HDFGRTR, TRC, 1),
1751 SR_FGT(SYS_TRCRSCTLR(9), HDFGRTR, TRC, 1),
1752 SR_FGT(SYS_TRCRSCTLR(10), HDFGRTR, TRC, 1),
1753 SR_FGT(SYS_TRCRSCTLR(11), HDFGRTR, TRC, 1),
1754 SR_FGT(SYS_TRCRSCTLR(12), HDFGRTR, TRC, 1),
1755 SR_FGT(SYS_TRCRSCTLR(13), HDFGRTR, TRC, 1),
1756 SR_FGT(SYS_TRCRSCTLR(14), HDFGRTR, TRC, 1),
1757 SR_FGT(SYS_TRCRSCTLR(15), HDFGRTR, TRC, 1),
1758 SR_FGT(SYS_TRCRSCTLR(16), HDFGRTR, TRC, 1),
1759 SR_FGT(SYS_TRCRSCTLR(17), HDFGRTR, TRC, 1),
1760 SR_FGT(SYS_TRCRSCTLR(18), HDFGRTR, TRC, 1),
1761 SR_FGT(SYS_TRCRSCTLR(19), HDFGRTR, TRC, 1),
1762 SR_FGT(SYS_TRCRSCTLR(20), HDFGRTR, TRC, 1),
1763 SR_FGT(SYS_TRCRSCTLR(21), HDFGRTR, TRC, 1),
1764 SR_FGT(SYS_TRCRSCTLR(22), HDFGRTR, TRC, 1),
1765 SR_FGT(SYS_TRCRSCTLR(23), HDFGRTR, TRC, 1),
1766 SR_FGT(SYS_TRCRSCTLR(24), HDFGRTR, TRC, 1),
1767 SR_FGT(SYS_TRCRSCTLR(25), HDFGRTR, TRC, 1),
1768 SR_FGT(SYS_TRCRSCTLR(26), HDFGRTR, TRC, 1),
1769 SR_FGT(SYS_TRCRSCTLR(27), HDFGRTR, TRC, 1),
1770 SR_FGT(SYS_TRCRSCTLR(28), HDFGRTR, TRC, 1),
1771 SR_FGT(SYS_TRCRSCTLR(29), HDFGRTR, TRC, 1),
1772 SR_FGT(SYS_TRCRSCTLR(30), HDFGRTR, TRC, 1),
1773 SR_FGT(SYS_TRCRSCTLR(31), HDFGRTR, TRC, 1),
1774 SR_FGT(SYS_TRCRSR, HDFGRTR, TRC, 1),
1775 SR_FGT(SYS_TRCSEQEVR(0), HDFGRTR, TRC, 1),
1776 SR_FGT(SYS_TRCSEQEVR(1), HDFGRTR, TRC, 1),
1777 SR_FGT(SYS_TRCSEQEVR(2), HDFGRTR, TRC, 1),
1778 SR_FGT(SYS_TRCSEQRSTEVR, HDFGRTR, TRC, 1),
1779 SR_FGT(SYS_TRCSSCCR(0), HDFGRTR, TRC, 1),
1780 SR_FGT(SYS_TRCSSCCR(1), HDFGRTR, TRC, 1),
1781 SR_FGT(SYS_TRCSSCCR(2), HDFGRTR, TRC, 1),
1782 SR_FGT(SYS_TRCSSCCR(3), HDFGRTR, TRC, 1),
1783 SR_FGT(SYS_TRCSSCCR(4), HDFGRTR, TRC, 1),
1784 SR_FGT(SYS_TRCSSCCR(5), HDFGRTR, TRC, 1),
1785 SR_FGT(SYS_TRCSSCCR(6), HDFGRTR, TRC, 1),
1786 SR_FGT(SYS_TRCSSCCR(7), HDFGRTR, TRC, 1),
1787 SR_FGT(SYS_TRCSSPCICR(0), HDFGRTR, TRC, 1),
1788 SR_FGT(SYS_TRCSSPCICR(1), HDFGRTR, TRC, 1),
1789 SR_FGT(SYS_TRCSSPCICR(2), HDFGRTR, TRC, 1),
1790 SR_FGT(SYS_TRCSSPCICR(3), HDFGRTR, TRC, 1),
1791 SR_FGT(SYS_TRCSSPCICR(4), HDFGRTR, TRC, 1),
1792 SR_FGT(SYS_TRCSSPCICR(5), HDFGRTR, TRC, 1),
1793 SR_FGT(SYS_TRCSSPCICR(6), HDFGRTR, TRC, 1),
1794 SR_FGT(SYS_TRCSSPCICR(7), HDFGRTR, TRC, 1),
1795 SR_FGT(SYS_TRCSTALLCTLR, HDFGRTR, TRC, 1),
1796 SR_FGT(SYS_TRCSYNCPR, HDFGRTR, TRC, 1),
1797 SR_FGT(SYS_TRCTRACEIDR, HDFGRTR, TRC, 1),
1798 SR_FGT(SYS_TRCTSCTLR, HDFGRTR, TRC, 1),
1799 SR_FGT(SYS_TRCVIIECTLR, HDFGRTR, TRC, 1),
1800 SR_FGT(SYS_TRCVIPCSSCTLR, HDFGRTR, TRC, 1),
1801 SR_FGT(SYS_TRCVISSCTLR, HDFGRTR, TRC, 1),
1802 SR_FGT(SYS_TRCVMIDCCTLR0, HDFGRTR, TRC, 1),
1803 SR_FGT(SYS_TRCVMIDCCTLR1, HDFGRTR, TRC, 1),
1804 SR_FGT(SYS_TRCVMIDCVR(0), HDFGRTR, TRC, 1),
1805 SR_FGT(SYS_TRCVMIDCVR(1), HDFGRTR, TRC, 1),
1806 SR_FGT(SYS_TRCVMIDCVR(2), HDFGRTR, TRC, 1),
1807 SR_FGT(SYS_TRCVMIDCVR(3), HDFGRTR, TRC, 1),
1808 SR_FGT(SYS_TRCVMIDCVR(4), HDFGRTR, TRC, 1),
1809 SR_FGT(SYS_TRCVMIDCVR(5), HDFGRTR, TRC, 1),
1810 SR_FGT(SYS_TRCVMIDCVR(6), HDFGRTR, TRC, 1),
1811 SR_FGT(SYS_TRCVMIDCVR(7), HDFGRTR, TRC, 1),
1812 SR_FGT(SYS_PMSLATFR_EL1, HDFGRTR, PMSLATFR_EL1, 1),
1813 SR_FGT(SYS_PMSIRR_EL1, HDFGRTR, PMSIRR_EL1, 1),
1814 SR_FGT(SYS_PMSIDR_EL1, HDFGRTR, PMSIDR_EL1, 1),
1815 SR_FGT(SYS_PMSICR_EL1, HDFGRTR, PMSICR_EL1, 1),
1816 SR_FGT(SYS_PMSFCR_EL1, HDFGRTR, PMSFCR_EL1, 1),
1817 SR_FGT(SYS_PMSEVFR_EL1, HDFGRTR, PMSEVFR_EL1, 1),
1818 SR_FGT(SYS_PMSCR_EL1, HDFGRTR, PMSCR_EL1, 1),
1819 SR_FGT(SYS_PMBSR_EL1, HDFGRTR, PMBSR_EL1, 1),
1820 SR_FGT(SYS_PMBPTR_EL1, HDFGRTR, PMBPTR_EL1, 1),
1821 SR_FGT(SYS_PMBLIMITR_EL1, HDFGRTR, PMBLIMITR_EL1, 1),
1822 SR_FGT(SYS_PMMIR_EL1, HDFGRTR, PMMIR_EL1, 1),
1823 SR_FGT(SYS_PMSELR_EL0, HDFGRTR, PMSELR_EL0, 1),
1824 SR_FGT(SYS_PMOVSCLR_EL0, HDFGRTR, PMOVS, 1),
1825 SR_FGT(SYS_PMOVSSET_EL0, HDFGRTR, PMOVS, 1),
1826 SR_FGT(SYS_PMINTENCLR_EL1, HDFGRTR, PMINTEN, 1),
1827 SR_FGT(SYS_PMINTENSET_EL1, HDFGRTR, PMINTEN, 1),
1828 SR_FGT(SYS_PMCNTENCLR_EL0, HDFGRTR, PMCNTEN, 1),
1829 SR_FGT(SYS_PMCNTENSET_EL0, HDFGRTR, PMCNTEN, 1),
1830 SR_FGT(SYS_PMCCNTR_EL0, HDFGRTR, PMCCNTR_EL0, 1),
1831 SR_FGT(SYS_PMCCFILTR_EL0, HDFGRTR, PMCCFILTR_EL0, 1),
1832 SR_FGT_RANGE(SYS_PMEVTYPERn_EL0(0),
1833 SYS_PMEVTYPERn_EL0(30),
1834 HDFGRTR, PMEVTYPERn_EL0, 1),
1835 SR_FGT_RANGE(SYS_PMEVCNTRn_EL0(0),
1836 SYS_PMEVCNTRn_EL0(30),
1837 HDFGRTR, PMEVCNTRn_EL0, 1),
1838 SR_FGT(SYS_OSDLR_EL1, HDFGRTR, OSDLR_EL1, 1),
1839 SR_FGT(SYS_OSECCR_EL1, HDFGRTR, OSECCR_EL1, 1),
1840 SR_FGT(SYS_OSLSR_EL1, HDFGRTR, OSLSR_EL1, 1),
1841 SR_FGT(SYS_DBGPRCR_EL1, HDFGRTR, DBGPRCR_EL1, 1),
1842 SR_FGT(SYS_DBGAUTHSTATUS_EL1, HDFGRTR, DBGAUTHSTATUS_EL1, 1),
1843 SR_FGT(SYS_DBGCLAIMSET_EL1, HDFGRTR, DBGCLAIM, 1),
1844 SR_FGT(SYS_DBGCLAIMCLR_EL1, HDFGRTR, DBGCLAIM, 1),
1845 SR_FGT(SYS_MDSCR_EL1, HDFGRTR, MDSCR_EL1, 1),
1846 /*
1847 * The trap bits capture *64* debug registers per bit, but the
1848 * ARM ARM only describes the encoding for the first 16, and
1849 * we don't really support more than that anyway.
1850 */
1851 SR_FGT(SYS_DBGWVRn_EL1(0), HDFGRTR, DBGWVRn_EL1, 1),
1852 SR_FGT(SYS_DBGWVRn_EL1(1), HDFGRTR, DBGWVRn_EL1, 1),
1853 SR_FGT(SYS_DBGWVRn_EL1(2), HDFGRTR, DBGWVRn_EL1, 1),
1854 SR_FGT(SYS_DBGWVRn_EL1(3), HDFGRTR, DBGWVRn_EL1, 1),
1855 SR_FGT(SYS_DBGWVRn_EL1(4), HDFGRTR, DBGWVRn_EL1, 1),
1856 SR_FGT(SYS_DBGWVRn_EL1(5), HDFGRTR, DBGWVRn_EL1, 1),
1857 SR_FGT(SYS_DBGWVRn_EL1(6), HDFGRTR, DBGWVRn_EL1, 1),
1858 SR_FGT(SYS_DBGWVRn_EL1(7), HDFGRTR, DBGWVRn_EL1, 1),
1859 SR_FGT(SYS_DBGWVRn_EL1(8), HDFGRTR, DBGWVRn_EL1, 1),
1860 SR_FGT(SYS_DBGWVRn_EL1(9), HDFGRTR, DBGWVRn_EL1, 1),
1861 SR_FGT(SYS_DBGWVRn_EL1(10), HDFGRTR, DBGWVRn_EL1, 1),
1862 SR_FGT(SYS_DBGWVRn_EL1(11), HDFGRTR, DBGWVRn_EL1, 1),
1863 SR_FGT(SYS_DBGWVRn_EL1(12), HDFGRTR, DBGWVRn_EL1, 1),
1864 SR_FGT(SYS_DBGWVRn_EL1(13), HDFGRTR, DBGWVRn_EL1, 1),
1865 SR_FGT(SYS_DBGWVRn_EL1(14), HDFGRTR, DBGWVRn_EL1, 1),
1866 SR_FGT(SYS_DBGWVRn_EL1(15), HDFGRTR, DBGWVRn_EL1, 1),
1867 SR_FGT(SYS_DBGWCRn_EL1(0), HDFGRTR, DBGWCRn_EL1, 1),
1868 SR_FGT(SYS_DBGWCRn_EL1(1), HDFGRTR, DBGWCRn_EL1, 1),
1869 SR_FGT(SYS_DBGWCRn_EL1(2), HDFGRTR, DBGWCRn_EL1, 1),
1870 SR_FGT(SYS_DBGWCRn_EL1(3), HDFGRTR, DBGWCRn_EL1, 1),
1871 SR_FGT(SYS_DBGWCRn_EL1(4), HDFGRTR, DBGWCRn_EL1, 1),
1872 SR_FGT(SYS_DBGWCRn_EL1(5), HDFGRTR, DBGWCRn_EL1, 1),
1873 SR_FGT(SYS_DBGWCRn_EL1(6), HDFGRTR, DBGWCRn_EL1, 1),
1874 SR_FGT(SYS_DBGWCRn_EL1(7), HDFGRTR, DBGWCRn_EL1, 1),
1875 SR_FGT(SYS_DBGWCRn_EL1(8), HDFGRTR, DBGWCRn_EL1, 1),
1876 SR_FGT(SYS_DBGWCRn_EL1(9), HDFGRTR, DBGWCRn_EL1, 1),
1877 SR_FGT(SYS_DBGWCRn_EL1(10), HDFGRTR, DBGWCRn_EL1, 1),
1878 SR_FGT(SYS_DBGWCRn_EL1(11), HDFGRTR, DBGWCRn_EL1, 1),
1879 SR_FGT(SYS_DBGWCRn_EL1(12), HDFGRTR, DBGWCRn_EL1, 1),
1880 SR_FGT(SYS_DBGWCRn_EL1(13), HDFGRTR, DBGWCRn_EL1, 1),
1881 SR_FGT(SYS_DBGWCRn_EL1(14), HDFGRTR, DBGWCRn_EL1, 1),
1882 SR_FGT(SYS_DBGWCRn_EL1(15), HDFGRTR, DBGWCRn_EL1, 1),
1883 SR_FGT(SYS_DBGBVRn_EL1(0), HDFGRTR, DBGBVRn_EL1, 1),
1884 SR_FGT(SYS_DBGBVRn_EL1(1), HDFGRTR, DBGBVRn_EL1, 1),
1885 SR_FGT(SYS_DBGBVRn_EL1(2), HDFGRTR, DBGBVRn_EL1, 1),
1886 SR_FGT(SYS_DBGBVRn_EL1(3), HDFGRTR, DBGBVRn_EL1, 1),
1887 SR_FGT(SYS_DBGBVRn_EL1(4), HDFGRTR, DBGBVRn_EL1, 1),
1888 SR_FGT(SYS_DBGBVRn_EL1(5), HDFGRTR, DBGBVRn_EL1, 1),
1889 SR_FGT(SYS_DBGBVRn_EL1(6), HDFGRTR, DBGBVRn_EL1, 1),
1890 SR_FGT(SYS_DBGBVRn_EL1(7), HDFGRTR, DBGBVRn_EL1, 1),
1891 SR_FGT(SYS_DBGBVRn_EL1(8), HDFGRTR, DBGBVRn_EL1, 1),
1892 SR_FGT(SYS_DBGBVRn_EL1(9), HDFGRTR, DBGBVRn_EL1, 1),
1893 SR_FGT(SYS_DBGBVRn_EL1(10), HDFGRTR, DBGBVRn_EL1, 1),
1894 SR_FGT(SYS_DBGBVRn_EL1(11), HDFGRTR, DBGBVRn_EL1, 1),
1895 SR_FGT(SYS_DBGBVRn_EL1(12), HDFGRTR, DBGBVRn_EL1, 1),
1896 SR_FGT(SYS_DBGBVRn_EL1(13), HDFGRTR, DBGBVRn_EL1, 1),
1897 SR_FGT(SYS_DBGBVRn_EL1(14), HDFGRTR, DBGBVRn_EL1, 1),
1898 SR_FGT(SYS_DBGBVRn_EL1(15), HDFGRTR, DBGBVRn_EL1, 1),
1899 SR_FGT(SYS_DBGBCRn_EL1(0), HDFGRTR, DBGBCRn_EL1, 1),
1900 SR_FGT(SYS_DBGBCRn_EL1(1), HDFGRTR, DBGBCRn_EL1, 1),
1901 SR_FGT(SYS_DBGBCRn_EL1(2), HDFGRTR, DBGBCRn_EL1, 1),
1902 SR_FGT(SYS_DBGBCRn_EL1(3), HDFGRTR, DBGBCRn_EL1, 1),
1903 SR_FGT(SYS_DBGBCRn_EL1(4), HDFGRTR, DBGBCRn_EL1, 1),
1904 SR_FGT(SYS_DBGBCRn_EL1(5), HDFGRTR, DBGBCRn_EL1, 1),
1905 SR_FGT(SYS_DBGBCRn_EL1(6), HDFGRTR, DBGBCRn_EL1, 1),
1906 SR_FGT(SYS_DBGBCRn_EL1(7), HDFGRTR, DBGBCRn_EL1, 1),
1907 SR_FGT(SYS_DBGBCRn_EL1(8), HDFGRTR, DBGBCRn_EL1, 1),
1908 SR_FGT(SYS_DBGBCRn_EL1(9), HDFGRTR, DBGBCRn_EL1, 1),
1909 SR_FGT(SYS_DBGBCRn_EL1(10), HDFGRTR, DBGBCRn_EL1, 1),
1910 SR_FGT(SYS_DBGBCRn_EL1(11), HDFGRTR, DBGBCRn_EL1, 1),
1911 SR_FGT(SYS_DBGBCRn_EL1(12), HDFGRTR, DBGBCRn_EL1, 1),
1912 SR_FGT(SYS_DBGBCRn_EL1(13), HDFGRTR, DBGBCRn_EL1, 1),
1913 SR_FGT(SYS_DBGBCRn_EL1(14), HDFGRTR, DBGBCRn_EL1, 1),
1914 SR_FGT(SYS_DBGBCRn_EL1(15), HDFGRTR, DBGBCRn_EL1, 1),
1915
1916 /* HDFGRTR2_EL2 */
1917 SR_FGT(SYS_MDSELR_EL1, HDFGRTR2, nMDSELR_EL1, 0),
1918 SR_FGT(SYS_MDSTEPOP_EL1, HDFGRTR2, nMDSTEPOP_EL1, 0),
1919 SR_FGT(SYS_PMCCNTSVR_EL1, HDFGRTR2, nPMSSDATA, 0),
1920 SR_FGT_RANGE(SYS_PMEVCNTSVRn_EL1(0),
1921 SYS_PMEVCNTSVRn_EL1(30),
1922 HDFGRTR2, nPMSSDATA, 0),
1923 SR_FGT(SYS_PMICNTSVR_EL1, HDFGRTR2, nPMSSDATA, 0),
1924 SR_FGT(SYS_PMECR_EL1, HDFGRTR2, nPMECR_EL1, 0),
1925 SR_FGT(SYS_PMIAR_EL1, HDFGRTR2, nPMIAR_EL1, 0),
1926 SR_FGT(SYS_PMICFILTR_EL0, HDFGRTR2, nPMICFILTR_EL0, 0),
1927 SR_FGT(SYS_PMICNTR_EL0, HDFGRTR2, nPMICNTR_EL0, 0),
1928 SR_FGT(SYS_PMSSCR_EL1, HDFGRTR2, nPMSSCR_EL1, 0),
1929 SR_FGT(SYS_PMUACR_EL1, HDFGRTR2, nPMUACR_EL1, 0),
1930 SR_FGT(SYS_SPMACCESSR_EL1, HDFGRTR2, nSPMACCESSR_EL1, 0),
1931 SR_FGT(SYS_SPMCFGR_EL1, HDFGRTR2, nSPMID, 0),
1932 SR_FGT(SYS_SPMDEVARCH_EL1, HDFGRTR2, nSPMID, 0),
1933 SR_FGT(SYS_SPMCGCRn_EL1(0), HDFGRTR2, nSPMID, 0),
1934 SR_FGT(SYS_SPMCGCRn_EL1(1), HDFGRTR2, nSPMID, 0),
1935 SR_FGT(SYS_SPMIIDR_EL1, HDFGRTR2, nSPMID, 0),
1936 SR_FGT(SYS_SPMCNTENCLR_EL0, HDFGRTR2, nSPMCNTEN, 0),
1937 SR_FGT(SYS_SPMCNTENSET_EL0, HDFGRTR2, nSPMCNTEN, 0),
1938 SR_FGT(SYS_SPMCR_EL0, HDFGRTR2, nSPMCR_EL0, 0),
1939 SR_FGT(SYS_SPMDEVAFF_EL1, HDFGRTR2, nSPMDEVAFF_EL1, 0),
1940 /*
1941 * We have up to 64 of these registers in ranges of 16, banked via
1942 * SPMSELR_EL0.BANK. We're only concerned with the accessors here,
1943 * not the architectural registers.
1944 */
1945 SR_FGT_RANGE(SYS_SPMEVCNTRn_EL0(0),
1946 SYS_SPMEVCNTRn_EL0(15),
1947 HDFGRTR2, nSPMEVCNTRn_EL0, 0),
1948 SR_FGT_RANGE(SYS_SPMEVFILT2Rn_EL0(0),
1949 SYS_SPMEVFILT2Rn_EL0(15),
1950 HDFGRTR2, nSPMEVTYPERn_EL0, 0),
1951 SR_FGT_RANGE(SYS_SPMEVFILTRn_EL0(0),
1952 SYS_SPMEVFILTRn_EL0(15),
1953 HDFGRTR2, nSPMEVTYPERn_EL0, 0),
1954 SR_FGT_RANGE(SYS_SPMEVTYPERn_EL0(0),
1955 SYS_SPMEVTYPERn_EL0(15),
1956 HDFGRTR2, nSPMEVTYPERn_EL0, 0),
1957 SR_FGT(SYS_SPMINTENCLR_EL1, HDFGRTR2, nSPMINTEN, 0),
1958 SR_FGT(SYS_SPMINTENSET_EL1, HDFGRTR2, nSPMINTEN, 0),
1959 SR_FGT(SYS_SPMOVSCLR_EL0, HDFGRTR2, nSPMOVS, 0),
1960 SR_FGT(SYS_SPMOVSSET_EL0, HDFGRTR2, nSPMOVS, 0),
1961 SR_FGT(SYS_SPMSCR_EL1, HDFGRTR2, nSPMSCR_EL1, 0),
1962 SR_FGT(SYS_SPMSELR_EL0, HDFGRTR2, nSPMSELR_EL0, 0),
1963 SR_FGT(SYS_TRCITECR_EL1, HDFGRTR2, nTRCITECR_EL1, 0),
1964 SR_FGT(SYS_PMBMAR_EL1, HDFGRTR2, nPMBMAR_EL1, 0),
1965 SR_FGT(SYS_PMSDSFR_EL1, HDFGRTR2, nPMSDSFR_EL1, 0),
1966 SR_FGT(SYS_TRBMPAM_EL1, HDFGRTR2, nTRBMPAM_EL1, 0),
1967
1968 /*
1969 * HDFGWTR_EL2
1970 *
1971 * Although HDFGRTR_EL2 and HDFGWTR_EL2 registers largely
1972 * overlap in their bit assignment, there are a number of bits
1973 * that are RES0 on one side, and an actual trap bit on the
1974 * other. The policy chosen here is to describe all the
1975 * read-side mappings, and only the write-side mappings that
1976 * differ from the read side, and the trap handler will pick
1977 * the correct shadow register based on the access type.
1978 *
1979 * Same model applies to the FEAT_FGT2 registers.
1980 */
1981 SR_FGT(SYS_TRFCR_EL1, HDFGWTR, TRFCR_EL1, 1),
1982 SR_FGT(SYS_TRCOSLAR, HDFGWTR, TRCOSLAR, 1),
1983 SR_FGT(SYS_PMCR_EL0, HDFGWTR, PMCR_EL0, 1),
1984 SR_FGT(SYS_PMSWINC_EL0, HDFGWTR, PMSWINC_EL0, 1),
1985 SR_FGT(SYS_OSLAR_EL1, HDFGWTR, OSLAR_EL1, 1),
1986
1987 /* HDFGWTR2_EL2 */
1988 SR_FGT(SYS_PMZR_EL0, HDFGWTR2, nPMZR_EL0, 0),
1989 SR_FGT(SYS_SPMZR_EL0, HDFGWTR2, nSPMEVCNTRn_EL0, 0),
1990
1991 /*
1992 * HAFGRTR_EL2
1993 */
1994 SR_FGT(SYS_AMEVTYPER1_EL0(15), HAFGRTR, AMEVTYPER115_EL0, 1),
1995 SR_FGT(SYS_AMEVTYPER1_EL0(14), HAFGRTR, AMEVTYPER114_EL0, 1),
1996 SR_FGT(SYS_AMEVTYPER1_EL0(13), HAFGRTR, AMEVTYPER113_EL0, 1),
1997 SR_FGT(SYS_AMEVTYPER1_EL0(12), HAFGRTR, AMEVTYPER112_EL0, 1),
1998 SR_FGT(SYS_AMEVTYPER1_EL0(11), HAFGRTR, AMEVTYPER111_EL0, 1),
1999 SR_FGT(SYS_AMEVTYPER1_EL0(10), HAFGRTR, AMEVTYPER110_EL0, 1),
2000 SR_FGT(SYS_AMEVTYPER1_EL0(9), HAFGRTR, AMEVTYPER19_EL0, 1),
2001 SR_FGT(SYS_AMEVTYPER1_EL0(8), HAFGRTR, AMEVTYPER18_EL0, 1),
2002 SR_FGT(SYS_AMEVTYPER1_EL0(7), HAFGRTR, AMEVTYPER17_EL0, 1),
2003 SR_FGT(SYS_AMEVTYPER1_EL0(6), HAFGRTR, AMEVTYPER16_EL0, 1),
2004 SR_FGT(SYS_AMEVTYPER1_EL0(5), HAFGRTR, AMEVTYPER15_EL0, 1),
2005 SR_FGT(SYS_AMEVTYPER1_EL0(4), HAFGRTR, AMEVTYPER14_EL0, 1),
2006 SR_FGT(SYS_AMEVTYPER1_EL0(3), HAFGRTR, AMEVTYPER13_EL0, 1),
2007 SR_FGT(SYS_AMEVTYPER1_EL0(2), HAFGRTR, AMEVTYPER12_EL0, 1),
2008 SR_FGT(SYS_AMEVTYPER1_EL0(1), HAFGRTR, AMEVTYPER11_EL0, 1),
2009 SR_FGT(SYS_AMEVTYPER1_EL0(0), HAFGRTR, AMEVTYPER10_EL0, 1),
2010 SR_FGT(SYS_AMEVCNTR1_EL0(15), HAFGRTR, AMEVCNTR115_EL0, 1),
2011 SR_FGT(SYS_AMEVCNTR1_EL0(14), HAFGRTR, AMEVCNTR114_EL0, 1),
2012 SR_FGT(SYS_AMEVCNTR1_EL0(13), HAFGRTR, AMEVCNTR113_EL0, 1),
2013 SR_FGT(SYS_AMEVCNTR1_EL0(12), HAFGRTR, AMEVCNTR112_EL0, 1),
2014 SR_FGT(SYS_AMEVCNTR1_EL0(11), HAFGRTR, AMEVCNTR111_EL0, 1),
2015 SR_FGT(SYS_AMEVCNTR1_EL0(10), HAFGRTR, AMEVCNTR110_EL0, 1),
2016 SR_FGT(SYS_AMEVCNTR1_EL0(9), HAFGRTR, AMEVCNTR19_EL0, 1),
2017 SR_FGT(SYS_AMEVCNTR1_EL0(8), HAFGRTR, AMEVCNTR18_EL0, 1),
2018 SR_FGT(SYS_AMEVCNTR1_EL0(7), HAFGRTR, AMEVCNTR17_EL0, 1),
2019 SR_FGT(SYS_AMEVCNTR1_EL0(6), HAFGRTR, AMEVCNTR16_EL0, 1),
2020 SR_FGT(SYS_AMEVCNTR1_EL0(5), HAFGRTR, AMEVCNTR15_EL0, 1),
2021 SR_FGT(SYS_AMEVCNTR1_EL0(4), HAFGRTR, AMEVCNTR14_EL0, 1),
2022 SR_FGT(SYS_AMEVCNTR1_EL0(3), HAFGRTR, AMEVCNTR13_EL0, 1),
2023 SR_FGT(SYS_AMEVCNTR1_EL0(2), HAFGRTR, AMEVCNTR12_EL0, 1),
2024 SR_FGT(SYS_AMEVCNTR1_EL0(1), HAFGRTR, AMEVCNTR11_EL0, 1),
2025 SR_FGT(SYS_AMEVCNTR1_EL0(0), HAFGRTR, AMEVCNTR10_EL0, 1),
2026 SR_FGT(SYS_AMCNTENCLR1_EL0, HAFGRTR, AMCNTEN1, 1),
2027 SR_FGT(SYS_AMCNTENSET1_EL0, HAFGRTR, AMCNTEN1, 1),
2028 SR_FGT(SYS_AMCNTENCLR0_EL0, HAFGRTR, AMCNTEN0, 1),
2029 SR_FGT(SYS_AMCNTENSET0_EL0, HAFGRTR, AMCNTEN0, 1),
2030 SR_FGT(SYS_AMEVCNTR0_EL0(3), HAFGRTR, AMEVCNTR03_EL0, 1),
2031 SR_FGT(SYS_AMEVCNTR0_EL0(2), HAFGRTR, AMEVCNTR02_EL0, 1),
2032 SR_FGT(SYS_AMEVCNTR0_EL0(1), HAFGRTR, AMEVCNTR01_EL0, 1),
2033 SR_FGT(SYS_AMEVCNTR0_EL0(0), HAFGRTR, AMEVCNTR00_EL0, 1),
2034 };
2035
2036 /*
2037 * Additional FGTs that do not fire with ESR_EL2.EC==0x18. This table
2038 * isn't used for exception routing, but only as a promise that the
2039 * trap is handled somewhere else.
2040 */
2041 static const union trap_config non_0x18_fgt[] __initconst = {
2042 FGT(HFGITR, PSBCSYNC, 1),
2043 FGT(HFGITR, nGCSSTR_EL1, 0),
2044 FGT(HFGITR, SVC_EL1, 1),
2045 FGT(HFGITR, SVC_EL0, 1),
2046 FGT(HFGITR, ERET, 1),
2047 FGT(HFGITR2, TSBCSYNC, 1),
2048 };
2049
get_trap_config(u32 sysreg)2050 static union trap_config get_trap_config(u32 sysreg)
2051 {
2052 return (union trap_config) {
2053 .val = xa_to_value(xa_load(&sr_forward_xa, sysreg)),
2054 };
2055 }
2056
print_nv_trap_error(const struct encoding_to_trap_config * tc,const char * type,int err)2057 static __init void print_nv_trap_error(const struct encoding_to_trap_config *tc,
2058 const char *type, int err)
2059 {
2060 kvm_err("%s line %d encoding range "
2061 "(%d, %d, %d, %d, %d) - (%d, %d, %d, %d, %d) (err=%d)\n",
2062 type, tc->line,
2063 sys_reg_Op0(tc->encoding), sys_reg_Op1(tc->encoding),
2064 sys_reg_CRn(tc->encoding), sys_reg_CRm(tc->encoding),
2065 sys_reg_Op2(tc->encoding),
2066 sys_reg_Op0(tc->end), sys_reg_Op1(tc->end),
2067 sys_reg_CRn(tc->end), sys_reg_CRm(tc->end),
2068 sys_reg_Op2(tc->end),
2069 err);
2070 }
2071
encoding_next(u32 encoding)2072 static u32 encoding_next(u32 encoding)
2073 {
2074 u8 op0, op1, crn, crm, op2;
2075
2076 op0 = sys_reg_Op0(encoding);
2077 op1 = sys_reg_Op1(encoding);
2078 crn = sys_reg_CRn(encoding);
2079 crm = sys_reg_CRm(encoding);
2080 op2 = sys_reg_Op2(encoding);
2081
2082 if (op2 < Op2_mask)
2083 return sys_reg(op0, op1, crn, crm, op2 + 1);
2084 if (crm < CRm_mask)
2085 return sys_reg(op0, op1, crn, crm + 1, 0);
2086 if (crn < CRn_mask)
2087 return sys_reg(op0, op1, crn + 1, 0, 0);
2088 if (op1 < Op1_mask)
2089 return sys_reg(op0, op1 + 1, 0, 0, 0);
2090
2091 return sys_reg(op0 + 1, 0, 0, 0, 0);
2092 }
2093
2094 #define FGT_MASKS(__n, __m) \
2095 struct fgt_masks __n = { .str = #__m, .res0 = __m, }
2096
2097 FGT_MASKS(hfgrtr_masks, HFGRTR_EL2_RES0);
2098 FGT_MASKS(hfgwtr_masks, HFGWTR_EL2_RES0);
2099 FGT_MASKS(hfgitr_masks, HFGITR_EL2_RES0);
2100 FGT_MASKS(hdfgrtr_masks, HDFGRTR_EL2_RES0);
2101 FGT_MASKS(hdfgwtr_masks, HDFGWTR_EL2_RES0);
2102 FGT_MASKS(hafgrtr_masks, HAFGRTR_EL2_RES0);
2103 FGT_MASKS(hfgrtr2_masks, HFGRTR2_EL2_RES0);
2104 FGT_MASKS(hfgwtr2_masks, HFGWTR2_EL2_RES0);
2105 FGT_MASKS(hfgitr2_masks, HFGITR2_EL2_RES0);
2106 FGT_MASKS(hdfgrtr2_masks, HDFGRTR2_EL2_RES0);
2107 FGT_MASKS(hdfgwtr2_masks, HDFGWTR2_EL2_RES0);
2108
aggregate_fgt(union trap_config tc)2109 static __init bool aggregate_fgt(union trap_config tc)
2110 {
2111 struct fgt_masks *rmasks, *wmasks;
2112
2113 switch (tc.fgt) {
2114 case HFGRTR_GROUP:
2115 rmasks = &hfgrtr_masks;
2116 wmasks = &hfgwtr_masks;
2117 break;
2118 case HDFGRTR_GROUP:
2119 rmasks = &hdfgrtr_masks;
2120 wmasks = &hdfgwtr_masks;
2121 break;
2122 case HAFGRTR_GROUP:
2123 rmasks = &hafgrtr_masks;
2124 wmasks = NULL;
2125 break;
2126 case HFGITR_GROUP:
2127 rmasks = &hfgitr_masks;
2128 wmasks = NULL;
2129 break;
2130 case HFGRTR2_GROUP:
2131 rmasks = &hfgrtr2_masks;
2132 wmasks = &hfgwtr2_masks;
2133 break;
2134 case HDFGRTR2_GROUP:
2135 rmasks = &hdfgrtr2_masks;
2136 wmasks = &hdfgwtr2_masks;
2137 break;
2138 case HFGITR2_GROUP:
2139 rmasks = &hfgitr2_masks;
2140 wmasks = NULL;
2141 break;
2142 }
2143
2144 /*
2145 * A bit can be reserved in either the R or W register, but
2146 * not both.
2147 */
2148 if ((BIT(tc.bit) & rmasks->res0) &&
2149 (!wmasks || (BIT(tc.bit) & wmasks->res0)))
2150 return false;
2151
2152 if (tc.pol)
2153 rmasks->mask |= BIT(tc.bit) & ~rmasks->res0;
2154 else
2155 rmasks->nmask |= BIT(tc.bit) & ~rmasks->res0;
2156
2157 if (wmasks) {
2158 if (tc.pol)
2159 wmasks->mask |= BIT(tc.bit) & ~wmasks->res0;
2160 else
2161 wmasks->nmask |= BIT(tc.bit) & ~wmasks->res0;
2162 }
2163
2164 return true;
2165 }
2166
check_fgt_masks(struct fgt_masks * masks)2167 static __init int check_fgt_masks(struct fgt_masks *masks)
2168 {
2169 unsigned long duplicate = masks->mask & masks->nmask;
2170 u64 res0 = masks->res0;
2171 int ret = 0;
2172
2173 if (duplicate) {
2174 int i;
2175
2176 for_each_set_bit(i, &duplicate, 64) {
2177 kvm_err("%s[%d] bit has both polarities\n",
2178 masks->str, i);
2179 }
2180
2181 ret = -EINVAL;
2182 }
2183
2184 masks->res0 = ~(masks->mask | masks->nmask);
2185 if (masks->res0 != res0)
2186 kvm_info("Implicit %s = %016llx, expecting %016llx\n",
2187 masks->str, masks->res0, res0);
2188
2189 return ret;
2190 }
2191
check_all_fgt_masks(int ret)2192 static __init int check_all_fgt_masks(int ret)
2193 {
2194 static struct fgt_masks * const masks[] __initconst = {
2195 &hfgrtr_masks,
2196 &hfgwtr_masks,
2197 &hfgitr_masks,
2198 &hdfgrtr_masks,
2199 &hdfgwtr_masks,
2200 &hafgrtr_masks,
2201 &hfgrtr2_masks,
2202 &hfgwtr2_masks,
2203 &hfgitr2_masks,
2204 &hdfgrtr2_masks,
2205 &hdfgwtr2_masks,
2206 };
2207 int err = 0;
2208
2209 for (int i = 0; i < ARRAY_SIZE(masks); i++)
2210 err |= check_fgt_masks(masks[i]);
2211
2212 return ret ?: err;
2213 }
2214
2215 #define for_each_encoding_in(__x, __s, __e) \
2216 for (u32 __x = __s; __x <= __e; __x = encoding_next(__x))
2217
populate_nv_trap_config(void)2218 int __init populate_nv_trap_config(void)
2219 {
2220 int ret = 0;
2221
2222 BUILD_BUG_ON(sizeof(union trap_config) != sizeof(void *));
2223 BUILD_BUG_ON(__NR_CGT_GROUP_IDS__ > BIT(TC_CGT_BITS));
2224 BUILD_BUG_ON(__NR_FGT_GROUP_IDS__ > BIT(TC_FGT_BITS));
2225 BUILD_BUG_ON(__NR_FG_FILTER_IDS__ > BIT(TC_FGF_BITS));
2226 BUILD_BUG_ON(__HCRX_EL2_MASK & __HCRX_EL2_nMASK);
2227
2228 for (int i = 0; i < ARRAY_SIZE(encoding_to_cgt); i++) {
2229 const struct encoding_to_trap_config *cgt = &encoding_to_cgt[i];
2230 void *prev;
2231
2232 if (cgt->tc.val & BIT(63)) {
2233 kvm_err("CGT[%d] has MBZ bit set\n", i);
2234 ret = -EINVAL;
2235 }
2236
2237 for_each_encoding_in(enc, cgt->encoding, cgt->end) {
2238 prev = xa_store(&sr_forward_xa, enc,
2239 xa_mk_value(cgt->tc.val), GFP_KERNEL);
2240 if (prev && !xa_is_err(prev)) {
2241 ret = -EINVAL;
2242 print_nv_trap_error(cgt, "Duplicate CGT", ret);
2243 }
2244
2245 if (xa_is_err(prev)) {
2246 ret = xa_err(prev);
2247 print_nv_trap_error(cgt, "Failed CGT insertion", ret);
2248 }
2249 }
2250 }
2251
2252 if (__HCRX_EL2_RES0 != HCRX_EL2_RES0)
2253 kvm_info("Sanitised HCR_EL2_RES0 = %016llx, expecting %016llx\n",
2254 __HCRX_EL2_RES0, HCRX_EL2_RES0);
2255
2256 kvm_info("nv: %ld coarse grained trap handlers\n",
2257 ARRAY_SIZE(encoding_to_cgt));
2258
2259 if (!cpus_have_final_cap(ARM64_HAS_FGT))
2260 goto check_mcb;
2261
2262 for (int i = 0; i < ARRAY_SIZE(encoding_to_fgt); i++) {
2263 const struct encoding_to_trap_config *fgt = &encoding_to_fgt[i];
2264 union trap_config tc;
2265 void *prev;
2266
2267 if (fgt->tc.fgt >= __NR_FGT_GROUP_IDS__) {
2268 ret = -EINVAL;
2269 print_nv_trap_error(fgt, "Invalid FGT", ret);
2270 }
2271
2272 for_each_encoding_in(enc, fgt->encoding, fgt->end) {
2273 tc = get_trap_config(enc);
2274
2275 if (tc.fgt) {
2276 ret = -EINVAL;
2277 print_nv_trap_error(fgt, "Duplicate FGT", ret);
2278 }
2279
2280 tc.val |= fgt->tc.val;
2281 prev = xa_store(&sr_forward_xa, enc,
2282 xa_mk_value(tc.val), GFP_KERNEL);
2283
2284 if (xa_is_err(prev)) {
2285 ret = xa_err(prev);
2286 print_nv_trap_error(fgt, "Failed FGT insertion", ret);
2287 }
2288
2289 if (!aggregate_fgt(tc)) {
2290 ret = -EINVAL;
2291 print_nv_trap_error(fgt, "FGT bit is reserved", ret);
2292 }
2293 }
2294 }
2295
2296 for (int i = 0; i < ARRAY_SIZE(non_0x18_fgt); i++) {
2297 if (!aggregate_fgt(non_0x18_fgt[i])) {
2298 ret = -EINVAL;
2299 kvm_err("non_0x18_fgt[%d] is reserved\n", i);
2300 }
2301 }
2302
2303 ret = check_all_fgt_masks(ret);
2304
2305 kvm_info("nv: %ld fine grained trap handlers\n",
2306 ARRAY_SIZE(encoding_to_fgt));
2307
2308 check_mcb:
2309 for (int id = __MULTIPLE_CONTROL_BITS__; id < __COMPLEX_CONDITIONS__; id++) {
2310 const enum cgt_group_id *cgids;
2311
2312 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__];
2313
2314 for (int i = 0; cgids[i] != __RESERVED__; i++) {
2315 if (cgids[i] >= __MULTIPLE_CONTROL_BITS__ &&
2316 cgids[i] < __COMPLEX_CONDITIONS__) {
2317 kvm_err("Recursive MCB %d/%d\n", id, cgids[i]);
2318 ret = -EINVAL;
2319 }
2320 }
2321 }
2322
2323 if (ret)
2324 xa_destroy(&sr_forward_xa);
2325
2326 return ret;
2327 }
2328
populate_sysreg_config(const struct sys_reg_desc * sr,unsigned int idx)2329 int __init populate_sysreg_config(const struct sys_reg_desc *sr,
2330 unsigned int idx)
2331 {
2332 union trap_config tc;
2333 u32 encoding;
2334 void *ret;
2335
2336 /*
2337 * 0 is a valid value for the index, but not for the storage.
2338 * We'll store (idx+1), so check against an offset'd limit.
2339 */
2340 if (idx >= (BIT(TC_SRI_BITS) - 1)) {
2341 kvm_err("sysreg %s (%d) out of range\n", sr->name, idx);
2342 return -EINVAL;
2343 }
2344
2345 encoding = sys_reg(sr->Op0, sr->Op1, sr->CRn, sr->CRm, sr->Op2);
2346 tc = get_trap_config(encoding);
2347
2348 if (tc.sri) {
2349 kvm_err("sysreg %s (%d) duplicate entry (%d)\n",
2350 sr->name, idx - 1, tc.sri);
2351 return -EINVAL;
2352 }
2353
2354 tc.sri = idx + 1;
2355 ret = xa_store(&sr_forward_xa, encoding,
2356 xa_mk_value(tc.val), GFP_KERNEL);
2357
2358 return xa_err(ret);
2359 }
2360
get_behaviour(struct kvm_vcpu * vcpu,const struct trap_bits * tb)2361 static enum trap_behaviour get_behaviour(struct kvm_vcpu *vcpu,
2362 const struct trap_bits *tb)
2363 {
2364 enum trap_behaviour b = BEHAVE_HANDLE_LOCALLY;
2365 u64 val;
2366
2367 val = __vcpu_sys_reg(vcpu, tb->index);
2368 if ((val & tb->mask) == tb->value)
2369 b |= tb->behaviour;
2370
2371 return b;
2372 }
2373
__compute_trap_behaviour(struct kvm_vcpu * vcpu,const enum cgt_group_id id,enum trap_behaviour b)2374 static enum trap_behaviour __compute_trap_behaviour(struct kvm_vcpu *vcpu,
2375 const enum cgt_group_id id,
2376 enum trap_behaviour b)
2377 {
2378 switch (id) {
2379 const enum cgt_group_id *cgids;
2380
2381 case __RESERVED__ ... __MULTIPLE_CONTROL_BITS__ - 1:
2382 if (likely(id != __RESERVED__))
2383 b |= get_behaviour(vcpu, &coarse_trap_bits[id]);
2384 break;
2385 case __MULTIPLE_CONTROL_BITS__ ... __COMPLEX_CONDITIONS__ - 1:
2386 /* Yes, this is recursive. Don't do anything stupid. */
2387 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__];
2388 for (int i = 0; cgids[i] != __RESERVED__; i++)
2389 b |= __compute_trap_behaviour(vcpu, cgids[i], b);
2390 break;
2391 default:
2392 if (ARRAY_SIZE(ccc))
2393 b |= ccc[id - __COMPLEX_CONDITIONS__](vcpu);
2394 break;
2395 }
2396
2397 return b;
2398 }
2399
compute_trap_behaviour(struct kvm_vcpu * vcpu,const union trap_config tc)2400 static enum trap_behaviour compute_trap_behaviour(struct kvm_vcpu *vcpu,
2401 const union trap_config tc)
2402 {
2403 enum trap_behaviour b = BEHAVE_HANDLE_LOCALLY;
2404
2405 return __compute_trap_behaviour(vcpu, tc.cgt, b);
2406 }
2407
kvm_get_sysreg_res0(struct kvm * kvm,enum vcpu_sysreg sr)2408 static u64 kvm_get_sysreg_res0(struct kvm *kvm, enum vcpu_sysreg sr)
2409 {
2410 struct kvm_sysreg_masks *masks;
2411
2412 /* Only handle the VNCR-backed regs for now */
2413 if (sr < __VNCR_START__)
2414 return 0;
2415
2416 masks = kvm->arch.sysreg_masks;
2417
2418 return masks->mask[sr - __VNCR_START__].res0;
2419 }
2420
check_fgt_bit(struct kvm_vcpu * vcpu,enum vcpu_sysreg sr,const union trap_config tc)2421 static bool check_fgt_bit(struct kvm_vcpu *vcpu, enum vcpu_sysreg sr,
2422 const union trap_config tc)
2423 {
2424 struct kvm *kvm = vcpu->kvm;
2425 u64 val;
2426
2427 /*
2428 * KVM doesn't know about any FGTs that apply to the host, and hopefully
2429 * that'll remain the case.
2430 */
2431 if (is_hyp_ctxt(vcpu))
2432 return false;
2433
2434 val = __vcpu_sys_reg(vcpu, sr);
2435
2436 if (tc.pol)
2437 return (val & BIT(tc.bit));
2438
2439 /*
2440 * FGTs with negative polarities are an absolute nightmare, as
2441 * we need to evaluate the bit in the light of the feature
2442 * that defines it. WTF were they thinking?
2443 *
2444 * So let's check if the bit has been earmarked as RES0, as
2445 * this indicates an unimplemented feature.
2446 */
2447 if (val & BIT(tc.bit))
2448 return false;
2449
2450 return !(kvm_get_sysreg_res0(kvm, sr) & BIT(tc.bit));
2451 }
2452
triage_sysreg_trap(struct kvm_vcpu * vcpu,int * sr_index)2453 bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int *sr_index)
2454 {
2455 enum vcpu_sysreg fgtreg;
2456 union trap_config tc;
2457 enum trap_behaviour b;
2458 bool is_read;
2459 u32 sysreg;
2460 u64 esr;
2461
2462 esr = kvm_vcpu_get_esr(vcpu);
2463 sysreg = esr_sys64_to_sysreg(esr);
2464 is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ;
2465
2466 tc = get_trap_config(sysreg);
2467
2468 /*
2469 * A value of 0 for the whole entry means that we know nothing
2470 * for this sysreg, and that it cannot be re-injected into the
2471 * nested hypervisor. In this situation, let's cut it short.
2472 */
2473 if (!tc.val)
2474 goto local;
2475
2476 /*
2477 * If a sysreg can be trapped using a FGT, first check whether we
2478 * trap for the purpose of forbidding the feature. In that case,
2479 * inject an UNDEF.
2480 */
2481 if (tc.fgt != __NO_FGT_GROUP__ &&
2482 (vcpu->kvm->arch.fgu[tc.fgt] & BIT(tc.bit))) {
2483 kvm_inject_undefined(vcpu);
2484 return true;
2485 }
2486
2487 /*
2488 * If we're not nesting, immediately return to the caller, with the
2489 * sysreg index, should we have it.
2490 */
2491 if (!vcpu_has_nv(vcpu))
2492 goto local;
2493
2494 /*
2495 * There are a few traps that take effect InHost, but are constrained
2496 * to EL0. Don't bother with computing the trap behaviour if the vCPU
2497 * isn't in EL0.
2498 */
2499 if (is_hyp_ctxt(vcpu) && !vcpu_is_host_el0(vcpu))
2500 goto local;
2501
2502 switch ((enum fgt_group_id)tc.fgt) {
2503 case __NO_FGT_GROUP__:
2504 break;
2505
2506 case HFGRTR_GROUP:
2507 fgtreg = is_read ? HFGRTR_EL2 : HFGWTR_EL2;
2508 break;
2509
2510 case HDFGRTR_GROUP:
2511 fgtreg = is_read ? HDFGRTR_EL2 : HDFGWTR_EL2;
2512 break;
2513
2514 case HAFGRTR_GROUP:
2515 fgtreg = HAFGRTR_EL2;
2516 break;
2517
2518 case HFGITR_GROUP:
2519 fgtreg = HFGITR_EL2;
2520 switch (tc.fgf) {
2521 u64 tmp;
2522
2523 case __NO_FGF__:
2524 break;
2525
2526 case HCRX_FGTnXS:
2527 tmp = __vcpu_sys_reg(vcpu, HCRX_EL2);
2528 if (tmp & HCRX_EL2_FGTnXS)
2529 tc.fgt = __NO_FGT_GROUP__;
2530 }
2531 break;
2532
2533 case HFGRTR2_GROUP:
2534 fgtreg = is_read ? HFGRTR2_EL2 : HFGWTR2_EL2;
2535 break;
2536
2537 case HDFGRTR2_GROUP:
2538 fgtreg = is_read ? HDFGRTR2_EL2 : HDFGWTR2_EL2;
2539 break;
2540
2541 case HFGITR2_GROUP:
2542 fgtreg = HFGITR2_EL2;
2543 break;
2544
2545 default:
2546 /* Something is really wrong, bail out */
2547 WARN_ONCE(1, "Bad FGT group (encoding %08x, config %016llx)\n",
2548 sysreg, tc.val);
2549 goto local;
2550 }
2551
2552 if (tc.fgt != __NO_FGT_GROUP__ && check_fgt_bit(vcpu, fgtreg, tc))
2553 goto inject;
2554
2555 b = compute_trap_behaviour(vcpu, tc);
2556
2557 if (!(b & BEHAVE_FORWARD_IN_HOST_EL0) && vcpu_is_host_el0(vcpu))
2558 goto local;
2559
2560 if (((b & BEHAVE_FORWARD_READ) && is_read) ||
2561 ((b & BEHAVE_FORWARD_WRITE) && !is_read))
2562 goto inject;
2563
2564 local:
2565 if (!tc.sri) {
2566 struct sys_reg_params params;
2567
2568 params = esr_sys64_to_params(esr);
2569
2570 /*
2571 * Check for the IMPDEF range, as per DDI0487 J.a,
2572 * D18.3.2 Reserved encodings for IMPLEMENTATION
2573 * DEFINED registers.
2574 */
2575 if (!(params.Op0 == 3 && (params.CRn & 0b1011) == 0b1011))
2576 print_sys_reg_msg(¶ms,
2577 "Unsupported guest access at: %lx\n",
2578 *vcpu_pc(vcpu));
2579 kvm_inject_undefined(vcpu);
2580 return true;
2581 }
2582
2583 *sr_index = tc.sri - 1;
2584 return false;
2585
2586 inject:
2587 trace_kvm_forward_sysreg_trap(vcpu, sysreg, is_read);
2588
2589 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu));
2590 return true;
2591 }
2592
__forward_traps(struct kvm_vcpu * vcpu,unsigned int reg,u64 control_bit)2593 static bool __forward_traps(struct kvm_vcpu *vcpu, unsigned int reg, u64 control_bit)
2594 {
2595 bool control_bit_set;
2596
2597 if (!vcpu_has_nv(vcpu))
2598 return false;
2599
2600 control_bit_set = __vcpu_sys_reg(vcpu, reg) & control_bit;
2601 if (!is_hyp_ctxt(vcpu) && control_bit_set) {
2602 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu));
2603 return true;
2604 }
2605 return false;
2606 }
2607
forward_hcr_traps(struct kvm_vcpu * vcpu,u64 control_bit)2608 static bool forward_hcr_traps(struct kvm_vcpu *vcpu, u64 control_bit)
2609 {
2610 return __forward_traps(vcpu, HCR_EL2, control_bit);
2611 }
2612
forward_smc_trap(struct kvm_vcpu * vcpu)2613 bool forward_smc_trap(struct kvm_vcpu *vcpu)
2614 {
2615 return forward_hcr_traps(vcpu, HCR_TSC);
2616 }
2617
forward_mdcr_traps(struct kvm_vcpu * vcpu,u64 control_bit)2618 static bool forward_mdcr_traps(struct kvm_vcpu *vcpu, u64 control_bit)
2619 {
2620 return __forward_traps(vcpu, MDCR_EL2, control_bit);
2621 }
2622
forward_debug_exception(struct kvm_vcpu * vcpu)2623 bool forward_debug_exception(struct kvm_vcpu *vcpu)
2624 {
2625 return forward_mdcr_traps(vcpu, MDCR_EL2_TDE);
2626 }
2627
kvm_check_illegal_exception_return(struct kvm_vcpu * vcpu,u64 spsr)2628 static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr)
2629 {
2630 u64 mode = spsr & PSR_MODE_MASK;
2631
2632 /*
2633 * Possible causes for an Illegal Exception Return from EL2:
2634 * - trying to return to EL3
2635 * - trying to return to an illegal M value
2636 * - trying to return to a 32bit EL
2637 * - trying to return to EL1 with HCR_EL2.TGE set
2638 */
2639 if (mode == PSR_MODE_EL3t || mode == PSR_MODE_EL3h ||
2640 mode == 0b00001 || (mode & BIT(1)) ||
2641 (spsr & PSR_MODE32_BIT) ||
2642 (vcpu_el2_tge_is_set(vcpu) && (mode == PSR_MODE_EL1t ||
2643 mode == PSR_MODE_EL1h))) {
2644 /*
2645 * The guest is playing with our nerves. Preserve EL, SP,
2646 * masks, flags from the existing PSTATE, and set IL.
2647 * The HW will then generate an Illegal State Exception
2648 * immediately after ERET.
2649 */
2650 spsr = *vcpu_cpsr(vcpu);
2651
2652 spsr &= (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT |
2653 PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT |
2654 PSR_MODE_MASK | PSR_MODE32_BIT);
2655 spsr |= PSR_IL_BIT;
2656 }
2657
2658 return spsr;
2659 }
2660
kvm_emulate_nested_eret(struct kvm_vcpu * vcpu)2661 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu)
2662 {
2663 u64 spsr, elr, esr;
2664
2665 spsr = vcpu_read_sys_reg(vcpu, SPSR_EL2);
2666 spsr = kvm_check_illegal_exception_return(vcpu, spsr);
2667
2668 /* Check for an ERETAx */
2669 esr = kvm_vcpu_get_esr(vcpu);
2670 if (esr_iss_is_eretax(esr) && !kvm_auth_eretax(vcpu, &elr)) {
2671 /*
2672 * Oh no, ERETAx failed to authenticate.
2673 *
2674 * If we have FPACCOMBINE and we don't have a pending
2675 * Illegal Execution State exception (which has priority
2676 * over FPAC), deliver an exception right away.
2677 *
2678 * Otherwise, let the mangled ELR value trickle down the
2679 * ERET handling, and the guest will have a little surprise.
2680 */
2681 if (kvm_has_pauth(vcpu->kvm, FPACCOMBINE) && !(spsr & PSR_IL_BIT)) {
2682 esr &= ESR_ELx_ERET_ISS_ERETA;
2683 esr |= FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_FPAC);
2684 kvm_inject_nested_sync(vcpu, esr);
2685 return;
2686 }
2687 }
2688
2689 preempt_disable();
2690 vcpu_set_flag(vcpu, IN_NESTED_ERET);
2691 kvm_arch_vcpu_put(vcpu);
2692
2693 if (!esr_iss_is_eretax(esr))
2694 elr = __vcpu_sys_reg(vcpu, ELR_EL2);
2695
2696 trace_kvm_nested_eret(vcpu, elr, spsr);
2697
2698 *vcpu_pc(vcpu) = elr;
2699 *vcpu_cpsr(vcpu) = spsr;
2700
2701 kvm_arch_vcpu_load(vcpu, smp_processor_id());
2702 vcpu_clear_flag(vcpu, IN_NESTED_ERET);
2703 preempt_enable();
2704
2705 if (kvm_vcpu_has_pmu(vcpu))
2706 kvm_pmu_nested_transition(vcpu);
2707 }
2708
kvm_inject_el2_exception(struct kvm_vcpu * vcpu,u64 esr_el2,enum exception_type type)2709 static void kvm_inject_el2_exception(struct kvm_vcpu *vcpu, u64 esr_el2,
2710 enum exception_type type)
2711 {
2712 trace_kvm_inject_nested_exception(vcpu, esr_el2, type);
2713
2714 switch (type) {
2715 case except_type_sync:
2716 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_SYNC);
2717 vcpu_write_sys_reg(vcpu, esr_el2, ESR_EL2);
2718 break;
2719 case except_type_irq:
2720 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_IRQ);
2721 break;
2722 default:
2723 WARN_ONCE(1, "Unsupported EL2 exception injection %d\n", type);
2724 }
2725 }
2726
2727 /*
2728 * Emulate taking an exception to EL2.
2729 * See ARM ARM J8.1.2 AArch64.TakeException()
2730 */
kvm_inject_nested(struct kvm_vcpu * vcpu,u64 esr_el2,enum exception_type type)2731 static int kvm_inject_nested(struct kvm_vcpu *vcpu, u64 esr_el2,
2732 enum exception_type type)
2733 {
2734 u64 pstate, mode;
2735 bool direct_inject;
2736
2737 if (!vcpu_has_nv(vcpu)) {
2738 kvm_err("Unexpected call to %s for the non-nesting configuration\n",
2739 __func__);
2740 return -EINVAL;
2741 }
2742
2743 /*
2744 * As for ERET, we can avoid doing too much on the injection path by
2745 * checking that we either took the exception from a VHE host
2746 * userspace or from vEL2. In these cases, there is no change in
2747 * translation regime (or anything else), so let's do as little as
2748 * possible.
2749 */
2750 pstate = *vcpu_cpsr(vcpu);
2751 mode = pstate & (PSR_MODE_MASK | PSR_MODE32_BIT);
2752
2753 direct_inject = (mode == PSR_MODE_EL0t &&
2754 vcpu_el2_e2h_is_set(vcpu) &&
2755 vcpu_el2_tge_is_set(vcpu));
2756 direct_inject |= (mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t);
2757
2758 if (direct_inject) {
2759 kvm_inject_el2_exception(vcpu, esr_el2, type);
2760 return 1;
2761 }
2762
2763 preempt_disable();
2764
2765 /*
2766 * We may have an exception or PC update in the EL0/EL1 context.
2767 * Commit it before entering EL2.
2768 */
2769 __kvm_adjust_pc(vcpu);
2770
2771 kvm_arch_vcpu_put(vcpu);
2772
2773 kvm_inject_el2_exception(vcpu, esr_el2, type);
2774
2775 /*
2776 * A hard requirement is that a switch between EL1 and EL2
2777 * contexts has to happen between a put/load, so that we can
2778 * pick the correct timer and interrupt configuration, among
2779 * other things.
2780 *
2781 * Make sure the exception actually took place before we load
2782 * the new context.
2783 */
2784 __kvm_adjust_pc(vcpu);
2785
2786 kvm_arch_vcpu_load(vcpu, smp_processor_id());
2787 preempt_enable();
2788
2789 if (kvm_vcpu_has_pmu(vcpu))
2790 kvm_pmu_nested_transition(vcpu);
2791
2792 return 1;
2793 }
2794
kvm_inject_nested_sync(struct kvm_vcpu * vcpu,u64 esr_el2)2795 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2)
2796 {
2797 return kvm_inject_nested(vcpu, esr_el2, except_type_sync);
2798 }
2799
kvm_inject_nested_irq(struct kvm_vcpu * vcpu)2800 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu)
2801 {
2802 /*
2803 * Do not inject an irq if the:
2804 * - Current exception level is EL2, and
2805 * - virtual HCR_EL2.TGE == 0
2806 * - virtual HCR_EL2.IMO == 0
2807 *
2808 * See Table D1-17 "Physical interrupt target and masking when EL3 is
2809 * not implemented and EL2 is implemented" in ARM DDI 0487C.a.
2810 */
2811
2812 if (vcpu_is_el2(vcpu) && !vcpu_el2_tge_is_set(vcpu) &&
2813 !(__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_IMO))
2814 return 1;
2815
2816 /* esr_el2 value doesn't matter for exits due to irqs. */
2817 return kvm_inject_nested(vcpu, 0, except_type_irq);
2818 }
2819