xref: /titanic_41/usr/src/uts/common/io/e1000api/e1000_hw.h (revision c6a664189ff58eecb65704097a089f0bb4d35523)
1 /******************************************************************************
2 
3   Copyright (c) 2001-2014, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
8 
9    1. Redistributions of source code must retain the above copyright notice,
10       this list of conditions and the following disclaimer.
11 
12    2. Redistributions in binary form must reproduce the above copyright
13       notice, this list of conditions and the following disclaimer in the
14       documentation and/or other materials provided with the distribution.
15 
16    3. Neither the name of the Intel Corporation nor the names of its
17       contributors may be used to endorse or promote products derived from
18       this software without specific prior written permission.
19 
20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30   POSSIBILITY OF SUCH DAMAGE.
31 
32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #ifndef _E1000_HW_H_
36 #define _E1000_HW_H_
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
42 #include "e1000_osdep.h"
43 #include "e1000_regs.h"
44 #include "e1000_defines.h"
45 
46 struct e1000_hw;
47 
48 #define E1000_DEV_ID_82542			0x1000
49 #define E1000_DEV_ID_82543GC_FIBER		0x1001
50 #define E1000_DEV_ID_82543GC_COPPER		0x1004
51 #define E1000_DEV_ID_82544EI_COPPER		0x1008
52 #define E1000_DEV_ID_82544EI_FIBER		0x1009
53 #define E1000_DEV_ID_82544GC_COPPER		0x100C
54 #define E1000_DEV_ID_82544GC_LOM		0x100D
55 #define E1000_DEV_ID_82540EM			0x100E
56 #define E1000_DEV_ID_82540EM_LOM		0x1015
57 #define E1000_DEV_ID_82540EP_LOM		0x1016
58 #define E1000_DEV_ID_82540EP			0x1017
59 #define E1000_DEV_ID_82540EP_LP			0x101E
60 #define E1000_DEV_ID_82545EM_COPPER		0x100F
61 #define E1000_DEV_ID_82545EM_FIBER		0x1011
62 #define E1000_DEV_ID_82545GM_COPPER		0x1026
63 #define E1000_DEV_ID_82545GM_FIBER		0x1027
64 #define E1000_DEV_ID_82545GM_SERDES		0x1028
65 #define E1000_DEV_ID_82546EB_COPPER		0x1010
66 #define E1000_DEV_ID_82546EB_FIBER		0x1012
67 #define E1000_DEV_ID_82546EB_QUAD_COPPER	0x101D
68 #define E1000_DEV_ID_82546GB_COPPER		0x1079
69 #define E1000_DEV_ID_82546GB_FIBER		0x107A
70 #define E1000_DEV_ID_82546GB_SERDES		0x107B
71 #define E1000_DEV_ID_82546GB_PCIE		0x108A
72 #define E1000_DEV_ID_82546GB_QUAD_COPPER	0x1099
73 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3	0x10B5
74 #define E1000_DEV_ID_82541EI			0x1013
75 #define E1000_DEV_ID_82541EI_MOBILE		0x1018
76 #define E1000_DEV_ID_82541ER_LOM		0x1014
77 #define E1000_DEV_ID_82541ER			0x1078
78 #define E1000_DEV_ID_82541GI			0x1076
79 #define E1000_DEV_ID_82541GI_LF			0x107C
80 #define E1000_DEV_ID_82541GI_MOBILE		0x1077
81 #define E1000_DEV_ID_82547EI			0x1019
82 #define E1000_DEV_ID_82547EI_MOBILE		0x101A
83 #define E1000_DEV_ID_82547GI			0x1075
84 #define E1000_DEV_ID_82571EB_COPPER		0x105E
85 #define E1000_DEV_ID_82571EB_FIBER		0x105F
86 #define E1000_DEV_ID_82571EB_SERDES		0x1060
87 #define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9
88 #define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA
89 #define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4
90 #define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5
91 #define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5
92 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC
93 #define E1000_DEV_ID_82572EI_COPPER		0x107D
94 #define E1000_DEV_ID_82572EI_FIBER		0x107E
95 #define E1000_DEV_ID_82572EI_SERDES		0x107F
96 #define E1000_DEV_ID_82572EI			0x10B9
97 #define E1000_DEV_ID_82573E			0x108B
98 #define E1000_DEV_ID_82573E_IAMT		0x108C
99 #define E1000_DEV_ID_82573L			0x109A
100 #define E1000_DEV_ID_82574L			0x10D3
101 #define E1000_DEV_ID_82574LA			0x10F6
102 #define E1000_DEV_ID_82583V			0x150C
103 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096
104 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098
105 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA
106 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB
107 #define E1000_DEV_ID_ICH8_82567V_3		0x1501
108 #define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049
109 #define E1000_DEV_ID_ICH8_IGP_AMT		0x104A
110 #define E1000_DEV_ID_ICH8_IGP_C			0x104B
111 #define E1000_DEV_ID_ICH8_IFE			0x104C
112 #define E1000_DEV_ID_ICH8_IFE_GT		0x10C4
113 #define E1000_DEV_ID_ICH8_IFE_G			0x10C5
114 #define E1000_DEV_ID_ICH8_IGP_M			0x104D
115 #define E1000_DEV_ID_ICH9_IGP_M			0x10BF
116 #define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5
117 #define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB
118 #define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD
119 #define E1000_DEV_ID_ICH9_BM			0x10E5
120 #define E1000_DEV_ID_ICH9_IGP_C			0x294C
121 #define E1000_DEV_ID_ICH9_IFE			0x10C0
122 #define E1000_DEV_ID_ICH9_IFE_GT		0x10C3
123 #define E1000_DEV_ID_ICH9_IFE_G			0x10C2
124 #define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC
125 #define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD
126 #define E1000_DEV_ID_ICH10_R_BM_V		0x10CE
127 #define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE
128 #define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF
129 #define E1000_DEV_ID_ICH10_D_BM_V		0x1525
130 #define E1000_DEV_ID_PCH_M_HV_LM		0x10EA
131 #define E1000_DEV_ID_PCH_M_HV_LC		0x10EB
132 #define E1000_DEV_ID_PCH_D_HV_DM		0x10EF
133 #define E1000_DEV_ID_PCH_D_HV_DC		0x10F0
134 #define E1000_DEV_ID_PCH2_LV_LM			0x1502
135 #define E1000_DEV_ID_PCH2_LV_V			0x1503
136 #define E1000_DEV_ID_PCH_LPT_I217_LM		0x153A
137 #define E1000_DEV_ID_PCH_LPT_I217_V		0x153B
138 #define E1000_DEV_ID_PCH_LPTLP_I218_LM		0x155A
139 #define E1000_DEV_ID_PCH_LPTLP_I218_V		0x1559
140 #define E1000_DEV_ID_PCH_I218_LM2		0x15A0
141 #define E1000_DEV_ID_PCH_I218_V2		0x15A1
142 #define E1000_DEV_ID_PCH_I218_LM3		0x15A2 /* Wildcat Point PCH */
143 #define E1000_DEV_ID_PCH_I218_V3		0x15A3 /* Wildcat Point PCH */
144 #define E1000_DEV_ID_82576			0x10C9
145 #define E1000_DEV_ID_82576_FIBER		0x10E6
146 #define E1000_DEV_ID_82576_SERDES		0x10E7
147 #define E1000_DEV_ID_82576_QUAD_COPPER		0x10E8
148 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2	0x1526
149 #define E1000_DEV_ID_82576_NS			0x150A
150 #define E1000_DEV_ID_82576_NS_SERDES		0x1518
151 #define E1000_DEV_ID_82576_SERDES_QUAD		0x150D
152 #define E1000_DEV_ID_82576_VF			0x10CA
153 #define E1000_DEV_ID_82576_VF_HV		0x152D
154 #define E1000_DEV_ID_I350_VF			0x1520
155 #define E1000_DEV_ID_I350_VF_HV			0x152F
156 #define E1000_DEV_ID_82575EB_COPPER		0x10A7
157 #define E1000_DEV_ID_82575EB_FIBER_SERDES	0x10A9
158 #define E1000_DEV_ID_82575GB_QUAD_COPPER	0x10D6
159 #define E1000_DEV_ID_82580_COPPER		0x150E
160 #define E1000_DEV_ID_82580_FIBER		0x150F
161 #define E1000_DEV_ID_82580_SERDES		0x1510
162 #define E1000_DEV_ID_82580_SGMII		0x1511
163 #define E1000_DEV_ID_82580_COPPER_DUAL		0x1516
164 #define E1000_DEV_ID_82580_QUAD_FIBER		0x1527
165 #define E1000_DEV_ID_I350_COPPER		0x1521
166 #define E1000_DEV_ID_I350_FIBER			0x1522
167 #define E1000_DEV_ID_I350_SERDES		0x1523
168 #define E1000_DEV_ID_I350_SGMII			0x1524
169 #define E1000_DEV_ID_I350_DA4			0x1546
170 #define E1000_DEV_ID_I210_COPPER		0x1533
171 #define E1000_DEV_ID_I210_COPPER_OEM1		0x1534
172 #define E1000_DEV_ID_I210_COPPER_IT		0x1535
173 #define E1000_DEV_ID_I210_FIBER			0x1536
174 #define E1000_DEV_ID_I210_SERDES		0x1537
175 #define E1000_DEV_ID_I210_SGMII			0x1538
176 #define E1000_DEV_ID_I210_COPPER_FLASHLESS	0x157B
177 #define E1000_DEV_ID_I210_SERDES_FLASHLESS	0x157C
178 #define E1000_DEV_ID_I211_COPPER		0x1539
179 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS	0x1F40
180 #define E1000_DEV_ID_I354_SGMII			0x1F41
181 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS	0x1F45
182 #define E1000_DEV_ID_DH89XXCC_SGMII		0x0438
183 #define E1000_DEV_ID_DH89XXCC_SERDES		0x043A
184 #define E1000_DEV_ID_DH89XXCC_BACKPLANE		0x043C
185 #define E1000_DEV_ID_DH89XXCC_SFP		0x0440
186 
187 #define E1000_REVISION_0	0
188 #define E1000_REVISION_1	1
189 #define E1000_REVISION_2	2
190 #define E1000_REVISION_3	3
191 #define E1000_REVISION_4	4
192 
193 #define E1000_FUNC_0		0
194 #define E1000_FUNC_1		1
195 #define E1000_FUNC_2		2
196 #define E1000_FUNC_3		3
197 
198 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0	0
199 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1	3
200 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2	6
201 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3	9
202 
203 enum e1000_mac_type {
204 	e1000_undefined = 0,
205 	e1000_82542,
206 	e1000_82543,
207 	e1000_82544,
208 	e1000_82540,
209 	e1000_82545,
210 	e1000_82545_rev_3,
211 	e1000_82546,
212 	e1000_82546_rev_3,
213 	e1000_82541,
214 	e1000_82541_rev_2,
215 	e1000_82547,
216 	e1000_82547_rev_2,
217 	e1000_82571,
218 	e1000_82572,
219 	e1000_82573,
220 	e1000_82574,
221 	e1000_82583,
222 	e1000_80003es2lan,
223 	e1000_ich8lan,
224 	e1000_ich9lan,
225 	e1000_ich10lan,
226 	e1000_pchlan,
227 	e1000_pch2lan,
228 	e1000_pch_lpt,
229 	e1000_82575,
230 	e1000_82576,
231 	e1000_82580,
232 	e1000_i350,
233 	e1000_i354,
234 	e1000_i210,
235 	e1000_i211,
236 	e1000_vfadapt,
237 	e1000_vfadapt_i350,
238 	e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
239 };
240 
241 enum e1000_media_type {
242 	e1000_media_type_unknown = 0,
243 	e1000_media_type_copper = 1,
244 	e1000_media_type_fiber = 2,
245 	e1000_media_type_internal_serdes = 3,
246 	e1000_num_media_types
247 };
248 
249 enum e1000_nvm_type {
250 	e1000_nvm_unknown = 0,
251 	e1000_nvm_none,
252 	e1000_nvm_eeprom_spi,
253 	e1000_nvm_eeprom_microwire,
254 	e1000_nvm_flash_hw,
255 	e1000_nvm_invm,
256 	e1000_nvm_flash_sw
257 };
258 
259 enum e1000_nvm_override {
260 	e1000_nvm_override_none = 0,
261 	e1000_nvm_override_spi_small,
262 	e1000_nvm_override_spi_large,
263 	e1000_nvm_override_microwire_small,
264 	e1000_nvm_override_microwire_large
265 };
266 
267 enum e1000_phy_type {
268 	e1000_phy_unknown = 0,
269 	e1000_phy_none,
270 	e1000_phy_m88,
271 	e1000_phy_igp,
272 	e1000_phy_igp_2,
273 	e1000_phy_gg82563,
274 	e1000_phy_igp_3,
275 	e1000_phy_ife,
276 	e1000_phy_bm,
277 	e1000_phy_82578,
278 	e1000_phy_82577,
279 	e1000_phy_82579,
280 	e1000_phy_i217,
281 	e1000_phy_82580,
282 	e1000_phy_vf,
283 	e1000_phy_i210,
284 };
285 
286 enum e1000_bus_type {
287 	e1000_bus_type_unknown = 0,
288 	e1000_bus_type_pci,
289 	e1000_bus_type_pcix,
290 	e1000_bus_type_pci_express,
291 	e1000_bus_type_reserved
292 };
293 
294 enum e1000_bus_speed {
295 	e1000_bus_speed_unknown = 0,
296 	e1000_bus_speed_33,
297 	e1000_bus_speed_66,
298 	e1000_bus_speed_100,
299 	e1000_bus_speed_120,
300 	e1000_bus_speed_133,
301 	e1000_bus_speed_2500,
302 	e1000_bus_speed_5000,
303 	e1000_bus_speed_reserved
304 };
305 
306 enum e1000_bus_width {
307 	e1000_bus_width_unknown = 0,
308 	e1000_bus_width_pcie_x1,
309 	e1000_bus_width_pcie_x2,
310 	e1000_bus_width_pcie_x4 = 4,
311 	e1000_bus_width_pcie_x8 = 8,
312 	e1000_bus_width_32,
313 	e1000_bus_width_64,
314 	e1000_bus_width_reserved
315 };
316 
317 enum e1000_1000t_rx_status {
318 	e1000_1000t_rx_status_not_ok = 0,
319 	e1000_1000t_rx_status_ok,
320 	e1000_1000t_rx_status_undefined = 0xFF
321 };
322 
323 enum e1000_rev_polarity {
324 	e1000_rev_polarity_normal = 0,
325 	e1000_rev_polarity_reversed,
326 	e1000_rev_polarity_undefined = 0xFF
327 };
328 
329 enum e1000_fc_mode {
330 	e1000_fc_none = 0,
331 	e1000_fc_rx_pause,
332 	e1000_fc_tx_pause,
333 	e1000_fc_full,
334 	e1000_fc_default = 0xFF
335 };
336 
337 enum e1000_ffe_config {
338 	e1000_ffe_config_enabled = 0,
339 	e1000_ffe_config_active,
340 	e1000_ffe_config_blocked
341 };
342 
343 enum e1000_dsp_config {
344 	e1000_dsp_config_disabled = 0,
345 	e1000_dsp_config_enabled,
346 	e1000_dsp_config_activated,
347 	e1000_dsp_config_undefined = 0xFF
348 };
349 
350 enum e1000_ms_type {
351 	e1000_ms_hw_default = 0,
352 	e1000_ms_force_master,
353 	e1000_ms_force_slave,
354 	e1000_ms_auto
355 };
356 
357 enum e1000_smart_speed {
358 	e1000_smart_speed_default = 0,
359 	e1000_smart_speed_on,
360 	e1000_smart_speed_off
361 };
362 
363 enum e1000_serdes_link_state {
364 	e1000_serdes_link_down = 0,
365 	e1000_serdes_link_autoneg_progress,
366 	e1000_serdes_link_autoneg_complete,
367 	e1000_serdes_link_forced_up
368 };
369 
370 #define __le16 u16
371 #define __le32 u32
372 #define __le64 u64
373 /* Receive Descriptor */
374 struct e1000_rx_desc {
375 	__le64 buffer_addr; /* Address of the descriptor's data buffer */
376 	__le16 length;      /* Length of data DMAed into data buffer */
377 	__le16 csum; /* Packet checksum */
378 	u8  status;  /* Descriptor status */
379 	u8  errors;  /* Descriptor Errors */
380 	__le16 special;
381 };
382 
383 /* Receive Descriptor - Extended */
384 union e1000_rx_desc_extended {
385 	struct {
386 		__le64 buffer_addr;
387 		__le64 reserved;
388 	} read;
389 	struct {
390 		struct {
391 			__le32 mrq; /* Multiple Rx Queues */
392 			union {
393 				__le32 rss; /* RSS Hash */
394 				struct {
395 					__le16 ip_id;  /* IP id */
396 					__le16 csum;   /* Packet Checksum */
397 				} csum_ip;
398 			} hi_dword;
399 		} lower;
400 		struct {
401 			__le32 status_error;  /* ext status/error */
402 			__le16 length;
403 			__le16 vlan; /* VLAN tag */
404 		} upper;
405 	} wb;  /* writeback */
406 };
407 
408 #define MAX_PS_BUFFERS 4
409 
410 /* Number of packet split data buffers (not including the header buffer) */
411 #define PS_PAGE_BUFFERS	(MAX_PS_BUFFERS - 1)
412 
413 /* Receive Descriptor - Packet Split */
414 union e1000_rx_desc_packet_split {
415 	struct {
416 		/* one buffer for protocol header(s), three data buffers */
417 		__le64 buffer_addr[MAX_PS_BUFFERS];
418 	} read;
419 	struct {
420 		struct {
421 			__le32 mrq;  /* Multiple Rx Queues */
422 			union {
423 				__le32 rss; /* RSS Hash */
424 				struct {
425 					__le16 ip_id;    /* IP id */
426 					__le16 csum;     /* Packet Checksum */
427 				} csum_ip;
428 			} hi_dword;
429 		} lower;
430 		struct {
431 			__le32 status_error;  /* ext status/error */
432 			__le16 length0;  /* length of buffer 0 */
433 			__le16 vlan;  /* VLAN tag */
434 		} middle;
435 		struct {
436 			__le16 header_status;
437 			/* length of buffers 1-3 */
438 			__le16 length[PS_PAGE_BUFFERS];
439 		} upper;
440 		__le64 reserved;
441 	} wb; /* writeback */
442 };
443 
444 /* Transmit Descriptor */
445 struct e1000_tx_desc {
446 	__le64 buffer_addr;   /* Address of the descriptor's data buffer */
447 	union {
448 		__le32 data;
449 		struct {
450 			__le16 length;  /* Data buffer length */
451 			u8 cso;  /* Checksum offset */
452 			u8 cmd;  /* Descriptor control */
453 		} flags;
454 	} lower;
455 	union {
456 		__le32 data;
457 		struct {
458 			u8 status; /* Descriptor status */
459 			u8 css;  /* Checksum start */
460 			__le16 special;
461 		} fields;
462 	} upper;
463 };
464 
465 /* Offload Context Descriptor */
466 struct e1000_context_desc {
467 	union {
468 		__le32 ip_config;
469 		struct {
470 			u8 ipcss;  /* IP checksum start */
471 			u8 ipcso;  /* IP checksum offset */
472 			__le16 ipcse;  /* IP checksum end */
473 		} ip_fields;
474 	} lower_setup;
475 	union {
476 		__le32 tcp_config;
477 		struct {
478 			u8 tucss;  /* TCP checksum start */
479 			u8 tucso;  /* TCP checksum offset */
480 			__le16 tucse;  /* TCP checksum end */
481 		} tcp_fields;
482 	} upper_setup;
483 	__le32 cmd_and_length;
484 	union {
485 		__le32 data;
486 		struct {
487 			u8 status;  /* Descriptor status */
488 			u8 hdr_len;  /* Header length */
489 			__le16 mss;  /* Maximum segment size */
490 		} fields;
491 	} tcp_seg_setup;
492 };
493 
494 /* Offload data descriptor */
495 struct e1000_data_desc {
496 	__le64 buffer_addr;  /* Address of the descriptor's buffer address */
497 	union {
498 		__le32 data;
499 		struct {
500 			__le16 length;  /* Data buffer length */
501 			u8 typ_len_ext;
502 			u8 cmd;
503 		} flags;
504 	} lower;
505 	union {
506 		__le32 data;
507 		struct {
508 			u8 status;  /* Descriptor status */
509 			u8 popts;  /* Packet Options */
510 			__le16 special;
511 		} fields;
512 	} upper;
513 };
514 
515 /* Statistics counters collected by the MAC */
516 struct e1000_hw_stats {
517 	u64 crcerrs;
518 	u64 algnerrc;
519 	u64 symerrs;
520 	u64 rxerrc;
521 	u64 mpc;
522 	u64 scc;
523 	u64 ecol;
524 	u64 mcc;
525 	u64 latecol;
526 	u64 colc;
527 	u64 dc;
528 	u64 tncrs;
529 	u64 sec;
530 	u64 cexterr;
531 	u64 rlec;
532 	u64 xonrxc;
533 	u64 xontxc;
534 	u64 xoffrxc;
535 	u64 xofftxc;
536 	u64 fcruc;
537 	u64 prc64;
538 	u64 prc127;
539 	u64 prc255;
540 	u64 prc511;
541 	u64 prc1023;
542 	u64 prc1522;
543 	u64 gprc;
544 	u64 bprc;
545 	u64 mprc;
546 	u64 gptc;
547 	u64 gorc;
548 	u64 gotc;
549 	u64 rnbc;
550 	u64 ruc;
551 	u64 rfc;
552 	u64 roc;
553 	u64 rjc;
554 	u64 mgprc;
555 	u64 mgpdc;
556 	u64 mgptc;
557 	u64 tor;
558 	u64 tot;
559 	u64 tpr;
560 	u64 tpt;
561 	u64 ptc64;
562 	u64 ptc127;
563 	u64 ptc255;
564 	u64 ptc511;
565 	u64 ptc1023;
566 	u64 ptc1522;
567 	u64 mptc;
568 	u64 bptc;
569 	u64 tsctc;
570 	u64 tsctfc;
571 	u64 iac;
572 	u64 icrxptc;
573 	u64 icrxatc;
574 	u64 ictxptc;
575 	u64 ictxatc;
576 	u64 ictxqec;
577 	u64 ictxqmtc;
578 	u64 icrxdmtc;
579 	u64 icrxoc;
580 	u64 cbtmpc;
581 	u64 htdpmc;
582 	u64 cbrdpc;
583 	u64 cbrmpc;
584 	u64 rpthc;
585 	u64 hgptc;
586 	u64 htcbdpc;
587 	u64 hgorc;
588 	u64 hgotc;
589 	u64 lenerrs;
590 	u64 scvpc;
591 	u64 hrmpc;
592 	u64 doosync;
593 	u64 o2bgptc;
594 	u64 o2bspc;
595 	u64 b2ospc;
596 	u64 b2ogprc;
597 };
598 
599 struct e1000_vf_stats {
600 	u64 base_gprc;
601 	u64 base_gptc;
602 	u64 base_gorc;
603 	u64 base_gotc;
604 	u64 base_mprc;
605 	u64 base_gotlbc;
606 	u64 base_gptlbc;
607 	u64 base_gorlbc;
608 	u64 base_gprlbc;
609 
610 	u32 last_gprc;
611 	u32 last_gptc;
612 	u32 last_gorc;
613 	u32 last_gotc;
614 	u32 last_mprc;
615 	u32 last_gotlbc;
616 	u32 last_gptlbc;
617 	u32 last_gorlbc;
618 	u32 last_gprlbc;
619 
620 	u64 gprc;
621 	u64 gptc;
622 	u64 gorc;
623 	u64 gotc;
624 	u64 mprc;
625 	u64 gotlbc;
626 	u64 gptlbc;
627 	u64 gorlbc;
628 	u64 gprlbc;
629 };
630 
631 struct e1000_phy_stats {
632 	u32 idle_errors;
633 	u32 receive_errors;
634 };
635 
636 struct e1000_host_mng_dhcp_cookie {
637 	u32 signature;
638 	u8  status;
639 	u8  reserved0;
640 	u16 vlan_id;
641 	u32 reserved1;
642 	u16 reserved2;
643 	u8  reserved3;
644 	u8  checksum;
645 };
646 
647 /* Host Interface "Rev 1" */
648 struct e1000_host_command_header {
649 	u8 command_id;
650 	u8 command_length;
651 	u8 command_options;
652 	u8 checksum;
653 };
654 
655 #define E1000_HI_MAX_DATA_LENGTH	252
656 struct e1000_host_command_info {
657 	struct e1000_host_command_header command_header;
658 	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
659 };
660 
661 /* Host Interface "Rev 2" */
662 struct e1000_host_mng_command_header {
663 	u8  command_id;
664 	u8  checksum;
665 	u16 reserved1;
666 	u16 reserved2;
667 	u16 command_length;
668 };
669 
670 #define E1000_HI_MAX_MNG_DATA_LENGTH	0x6F8
671 struct e1000_host_mng_command_info {
672 	struct e1000_host_mng_command_header command_header;
673 	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
674 };
675 
676 #include "e1000_mac.h"
677 #include "e1000_phy.h"
678 #include "e1000_nvm.h"
679 #include "e1000_manage.h"
680 #include "e1000_mbx.h"
681 
682 /* Function pointers for the MAC. */
683 struct e1000_mac_operations {
684 	s32  (*init_params)(struct e1000_hw *);
685 	s32  (*id_led_init)(struct e1000_hw *);
686 	s32  (*blink_led)(struct e1000_hw *);
687 	bool (*check_mng_mode)(struct e1000_hw *);
688 	s32  (*check_for_link)(struct e1000_hw *);
689 	s32  (*cleanup_led)(struct e1000_hw *);
690 	void (*clear_hw_cntrs)(struct e1000_hw *);
691 	void (*clear_vfta)(struct e1000_hw *);
692 	s32  (*get_bus_info)(struct e1000_hw *);
693 	void (*set_lan_id)(struct e1000_hw *);
694 	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
695 	s32  (*led_on)(struct e1000_hw *);
696 	s32  (*led_off)(struct e1000_hw *);
697 	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
698 	s32  (*reset_hw)(struct e1000_hw *);
699 	s32  (*init_hw)(struct e1000_hw *);
700 	void (*shutdown_serdes)(struct e1000_hw *);
701 	void (*power_up_serdes)(struct e1000_hw *);
702 	s32  (*setup_link)(struct e1000_hw *);
703 	s32  (*setup_physical_interface)(struct e1000_hw *);
704 	s32  (*setup_led)(struct e1000_hw *);
705 	void (*write_vfta)(struct e1000_hw *, u32, u32);
706 	void (*config_collision_dist)(struct e1000_hw *);
707 	int  (*rar_set)(struct e1000_hw *, u8*, u32);
708 	s32  (*read_mac_addr)(struct e1000_hw *);
709 	s32  (*validate_mdi_setting)(struct e1000_hw *);
710 	s32  (*set_obff_timer)(struct e1000_hw *, u32);
711 	s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
712 	void (*release_swfw_sync)(struct e1000_hw *, u16);
713 };
714 
715 /* When to use various PHY register access functions:
716  *
717  *                 Func   Caller
718  *   Function      Does   Does    When to use
719  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
720  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
721  *   X_reg_locked  P,A    L       for multiple accesses of different regs
722  *                                on different pages
723  *   X_reg_page    A      L,P     for multiple accesses of different regs
724  *                                on the same page
725  *
726  * Where X=[read|write], L=locking, P=sets page, A=register access
727  *
728  */
729 struct e1000_phy_operations {
730 	s32  (*init_params)(struct e1000_hw *);
731 	s32  (*acquire)(struct e1000_hw *);
732 	s32  (*cfg_on_link_up)(struct e1000_hw *);
733 	s32  (*check_polarity)(struct e1000_hw *);
734 	s32  (*check_reset_block)(struct e1000_hw *);
735 	s32  (*commit)(struct e1000_hw *);
736 	s32  (*force_speed_duplex)(struct e1000_hw *);
737 	s32  (*get_cfg_done)(struct e1000_hw *hw);
738 	s32  (*get_cable_length)(struct e1000_hw *);
739 	s32  (*get_info)(struct e1000_hw *);
740 	s32  (*set_page)(struct e1000_hw *, u16);
741 	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
742 	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
743 	s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
744 	void (*release)(struct e1000_hw *);
745 	s32  (*reset)(struct e1000_hw *);
746 	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
747 	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
748 	s32  (*write_reg)(struct e1000_hw *, u32, u16);
749 	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
750 	s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
751 	void (*power_up)(struct e1000_hw *);
752 	void (*power_down)(struct e1000_hw *);
753 	s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
754 	s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
755 };
756 
757 /* Function pointers for the NVM. */
758 struct e1000_nvm_operations {
759 	s32  (*init_params)(struct e1000_hw *);
760 	s32  (*acquire)(struct e1000_hw *);
761 	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
762 	void (*release)(struct e1000_hw *);
763 	void (*reload)(struct e1000_hw *);
764 	s32  (*update)(struct e1000_hw *);
765 	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
766 	s32  (*validate)(struct e1000_hw *);
767 	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
768 };
769 
770 struct e1000_mac_info {
771 	struct e1000_mac_operations ops;
772 	u8 addr[ETH_ADDR_LEN];
773 	u8 perm_addr[ETH_ADDR_LEN];
774 
775 	enum e1000_mac_type type;
776 
777 	u32 collision_delta;
778 	u32 ledctl_default;
779 	u32 ledctl_mode1;
780 	u32 ledctl_mode2;
781 	u32 mc_filter_type;
782 	u32 tx_packet_delta;
783 	u32 txcw;
784 
785 	u16 current_ifs_val;
786 	u16 ifs_max_val;
787 	u16 ifs_min_val;
788 	u16 ifs_ratio;
789 	u16 ifs_step_size;
790 	u16 mta_reg_count;
791 	u16 uta_reg_count;
792 
793 	/* Maximum size of the MTA register table in all supported adapters */
794 	#define MAX_MTA_REG 128
795 	u32 mta_shadow[MAX_MTA_REG];
796 	u16 rar_entry_count;
797 
798 	u8  forced_speed_duplex;
799 
800 	bool adaptive_ifs;
801 	bool has_fwsm;
802 	bool arc_subsystem_valid;
803 	bool asf_firmware_present;
804 	bool autoneg;
805 	bool autoneg_failed;
806 	bool get_link_status;
807 	bool in_ifs_mode;
808 	bool report_tx_early;
809 	enum e1000_serdes_link_state serdes_link_state;
810 	bool serdes_has_link;
811 	bool tx_pkt_filtering;
812 	u32 max_frame_size;
813 };
814 
815 struct e1000_phy_info {
816 	struct e1000_phy_operations ops;
817 	enum e1000_phy_type type;
818 
819 	enum e1000_1000t_rx_status local_rx;
820 	enum e1000_1000t_rx_status remote_rx;
821 	enum e1000_ms_type ms_type;
822 	enum e1000_ms_type original_ms_type;
823 	enum e1000_rev_polarity cable_polarity;
824 	enum e1000_smart_speed smart_speed;
825 
826 	u32 addr;
827 	u32 id;
828 	u32 reset_delay_us; /* in usec */
829 	u32 revision;
830 
831 	enum e1000_media_type media_type;
832 
833 	u16 autoneg_advertised;
834 	u16 autoneg_mask;
835 	u16 cable_length;
836 	u16 max_cable_length;
837 	u16 min_cable_length;
838 
839 	u8 mdix;
840 
841 	bool disable_polarity_correction;
842 	bool is_mdix;
843 	bool polarity_correction;
844 	bool speed_downgraded;
845 	bool autoneg_wait_to_complete;
846 };
847 
848 struct e1000_nvm_info {
849 	struct e1000_nvm_operations ops;
850 	enum e1000_nvm_type type;
851 	enum e1000_nvm_override override;
852 
853 	u32 flash_bank_size;
854 	u32 flash_base_addr;
855 
856 	u16 word_size;
857 	u16 delay_usec;
858 	u16 address_bits;
859 	u16 opcode_bits;
860 	u16 page_size;
861 };
862 
863 struct e1000_bus_info {
864 	enum e1000_bus_type type;
865 	enum e1000_bus_speed speed;
866 	enum e1000_bus_width width;
867 
868 	u16 func;
869 	u16 pci_cmd_word;
870 };
871 
872 struct e1000_fc_info {
873 	u32 high_water;  /* Flow control high-water mark */
874 	u32 low_water;  /* Flow control low-water mark */
875 	u16 pause_time;  /* Flow control pause timer */
876 	u16 refresh_time;  /* Flow control refresh timer */
877 	bool send_xon;  /* Flow control send XON */
878 	bool strict_ieee;  /* Strict IEEE mode */
879 	enum e1000_fc_mode current_mode;  /* FC mode in effect */
880 	enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
881 };
882 
883 struct e1000_mbx_operations {
884 	s32 (*init_params)(struct e1000_hw *hw);
885 	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
886 	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
887 	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
888 	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
889 	s32 (*check_for_msg)(struct e1000_hw *, u16);
890 	s32 (*check_for_ack)(struct e1000_hw *, u16);
891 	s32 (*check_for_rst)(struct e1000_hw *, u16);
892 };
893 
894 struct e1000_mbx_stats {
895 	u32 msgs_tx;
896 	u32 msgs_rx;
897 
898 	u32 acks;
899 	u32 reqs;
900 	u32 rsts;
901 };
902 
903 struct e1000_mbx_info {
904 	struct e1000_mbx_operations ops;
905 	struct e1000_mbx_stats stats;
906 	u32 timeout;
907 	u32 usec_delay;
908 	u16 size;
909 };
910 
911 struct e1000_dev_spec_82541 {
912 	enum e1000_dsp_config dsp_config;
913 	enum e1000_ffe_config ffe_config;
914 	u32 tx_fifo_head;
915 	u32 tx_fifo_start;
916 	u32 tx_fifo_size;
917 	u16 dsp_reset_counter;
918 	u16 spd_default;
919 	bool phy_init_script;
920 	bool ttl_workaround;
921 };
922 
923 struct e1000_dev_spec_82542 {
924 	bool dma_fairness;
925 };
926 
927 struct e1000_dev_spec_82543 {
928 	u32  tbi_compatibility;
929 	bool dma_fairness;
930 	bool init_phy_disabled;
931 };
932 
933 struct e1000_dev_spec_82571 {
934 	bool laa_is_present;
935 	u32 smb_counter;
936 	E1000_MUTEX swflag_mutex;
937 };
938 
939 struct e1000_dev_spec_80003es2lan {
940 	bool  mdic_wa_enable;
941 };
942 
943 struct e1000_shadow_ram {
944 	u16  value;
945 	bool modified;
946 };
947 
948 #define E1000_SHADOW_RAM_WORDS		2048
949 
950 /* I218 PHY Ultra Low Power (ULP) states */
951 enum e1000_ulp_state {
952 	e1000_ulp_state_unknown,
953 	e1000_ulp_state_off,
954 	e1000_ulp_state_on,
955 };
956 
957 struct e1000_dev_spec_ich8lan {
958 	bool kmrn_lock_loss_workaround_enabled;
959 	struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
960 	E1000_MUTEX nvm_mutex;
961 	E1000_MUTEX swflag_mutex;
962 	bool nvm_k1_enabled;
963 	bool eee_disable;
964 	u16 eee_lp_ability;
965 	enum e1000_ulp_state ulp_state;
966 };
967 
968 struct e1000_dev_spec_82575 {
969 	bool sgmii_active;
970 	bool global_device_reset;
971 	bool eee_disable;
972 	bool module_plugged;
973 	bool clear_semaphore_once;
974 	u32 mtu;
975 	struct sfp_e1000_flags eth_flags;
976 	u8 media_port;
977 	bool media_changed;
978 };
979 
980 struct e1000_dev_spec_vf {
981 	u32 vf_number;
982 	u32 v2p_mailbox;
983 };
984 
985 struct e1000_hw {
986 	void *back;
987 
988 	u8 *hw_addr;
989 	u8 *flash_address;
990 	unsigned long io_base;
991 
992 	struct e1000_mac_info  mac;
993 	struct e1000_fc_info   fc;
994 	struct e1000_phy_info  phy;
995 	struct e1000_nvm_info  nvm;
996 	struct e1000_bus_info  bus;
997 	struct e1000_mbx_info mbx;
998 	struct e1000_host_mng_dhcp_cookie mng_cookie;
999 
1000 	union {
1001 		struct e1000_dev_spec_82541 _82541;
1002 		struct e1000_dev_spec_82542 _82542;
1003 		struct e1000_dev_spec_82543 _82543;
1004 		struct e1000_dev_spec_82571 _82571;
1005 		struct e1000_dev_spec_80003es2lan _80003es2lan;
1006 		struct e1000_dev_spec_ich8lan ich8lan;
1007 		struct e1000_dev_spec_82575 _82575;
1008 		struct e1000_dev_spec_vf vf;
1009 	} dev_spec;
1010 
1011 	u16 device_id;
1012 	u16 subsystem_vendor_id;
1013 	u16 subsystem_device_id;
1014 	u16 vendor_id;
1015 
1016 	u8  revision_id;
1017 };
1018 
1019 #include "e1000_82541.h"
1020 #include "e1000_82543.h"
1021 #include "e1000_82571.h"
1022 #include "e1000_80003es2lan.h"
1023 #include "e1000_ich8lan.h"
1024 #include "e1000_82575.h"
1025 #include "e1000_i210.h"
1026 
1027 /* These functions must be implemented by drivers */
1028 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1029 void e1000_pci_set_mwi(struct e1000_hw *hw);
1030 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1031 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1032 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1033 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1034 
1035 #ifdef __cplusplus
1036 }
1037 #endif
1038 
1039 #endif	/* _E1000_HW_H_ */
1040