1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 #include "opt_acpi.h" 33 #include "opt_iommu.h" 34 #include "opt_bus.h" 35 36 #include <sys/param.h> 37 #include <sys/conf.h> 38 #include <sys/endian.h> 39 #include <sys/eventhandler.h> 40 #include <sys/fcntl.h> 41 #include <sys/kernel.h> 42 #include <sys/limits.h> 43 #include <sys/linker.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/queue.h> 47 #include <sys/sbuf.h> 48 #include <sys/stdarg.h> 49 #include <sys/sysctl.h> 50 #include <sys/systm.h> 51 #include <sys/taskqueue.h> 52 #include <sys/tree.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 #include <vm/vm_extern.h> 57 58 #include <sys/bus.h> 59 #include <machine/bus.h> 60 #include <sys/rman.h> 61 #include <machine/resource.h> 62 63 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 64 #include <machine/intr_machdep.h> 65 #endif 66 67 #include <sys/pciio.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pci_private.h> 71 72 #ifdef PCI_IOV 73 #include <sys/nv.h> 74 #include <dev/pci/pci_iov_private.h> 75 #endif 76 77 #include <dev/usb/controller/xhcireg.h> 78 #include <dev/usb/controller/ehcireg.h> 79 #include <dev/usb/controller/ohcireg.h> 80 #include <dev/usb/controller/uhcireg.h> 81 82 #include <dev/iommu/iommu.h> 83 84 #include "pcib_if.h" 85 #include "pci_if.h" 86 87 #define PCIR_IS_BIOS(cfg, reg) \ 88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 90 91 static device_probe_t pci_probe; 92 93 static bus_reset_post_t pci_reset_post; 94 static bus_reset_prepare_t pci_reset_prepare; 95 static bus_reset_child_t pci_reset_child; 96 static bus_hint_device_unit_t pci_hint_device_unit; 97 static bus_remap_intr_t pci_remap_intr_method; 98 99 static pci_get_id_t pci_get_id_method; 100 101 static int pci_has_quirk(uint32_t devid, int quirk); 102 static pci_addr_t pci_mapbase(uint64_t mapreg); 103 static const char *pci_maptype(uint64_t mapreg); 104 static int pci_maprange(uint64_t mapreg); 105 static pci_addr_t pci_rombase(uint64_t mapreg); 106 static int pci_romsize(uint64_t testval); 107 static void pci_fixancient(pcicfgregs *cfg); 108 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 109 110 static int pci_porten(device_t dev); 111 static int pci_memen(device_t dev); 112 static void pci_assign_interrupt(device_t bus, device_t dev, 113 int force_route); 114 static int pci_add_map(device_t bus, device_t dev, int reg, 115 struct resource_list *rl, int force, int prefetch); 116 static void pci_load_vendor_data(void); 117 static int pci_describe_parse_line(char **ptr, int *vendor, 118 int *device, char **desc); 119 static char *pci_describe_device(device_t dev); 120 static int pci_modevent(module_t mod, int what, void *arg); 121 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 122 pcicfgregs *cfg); 123 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 124 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 125 int reg, uint32_t *data); 126 #if 0 127 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 128 int reg, uint32_t data); 129 #endif 130 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 131 static void pci_mask_msix(device_t dev, u_int index); 132 static void pci_unmask_msix(device_t dev, u_int index); 133 static int pci_msi_blacklisted(void); 134 static int pci_msix_blacklisted(void); 135 static void pci_resume_msi(device_t dev); 136 static void pci_resume_msix(device_t dev); 137 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 138 int b, int s, int f, uint16_t vid, uint16_t did); 139 140 static device_method_t pci_methods[] = { 141 /* Device interface */ 142 DEVMETHOD(device_probe, pci_probe), 143 DEVMETHOD(device_attach, pci_attach), 144 DEVMETHOD(device_detach, pci_detach), 145 DEVMETHOD(device_shutdown, bus_generic_shutdown), 146 DEVMETHOD(device_suspend, bus_generic_suspend), 147 DEVMETHOD(device_resume, pci_resume), 148 149 /* Bus interface */ 150 DEVMETHOD(bus_print_child, pci_print_child), 151 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 152 DEVMETHOD(bus_read_ivar, pci_read_ivar), 153 DEVMETHOD(bus_write_ivar, pci_write_ivar), 154 DEVMETHOD(bus_driver_added, pci_driver_added), 155 DEVMETHOD(bus_setup_intr, pci_setup_intr), 156 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 157 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 158 DEVMETHOD(bus_reset_post, pci_reset_post), 159 DEVMETHOD(bus_reset_child, pci_reset_child), 160 161 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 162 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 163 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 164 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 165 DEVMETHOD(bus_delete_resource, pci_delete_resource), 166 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 167 DEVMETHOD(bus_adjust_resource, pci_adjust_resource), 168 DEVMETHOD(bus_release_resource, pci_release_resource), 169 DEVMETHOD(bus_activate_resource, pci_activate_resource), 170 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 171 DEVMETHOD(bus_map_resource, pci_map_resource), 172 DEVMETHOD(bus_unmap_resource, pci_unmap_resource), 173 DEVMETHOD(bus_child_deleted, pci_child_deleted), 174 DEVMETHOD(bus_child_detached, pci_child_detached), 175 DEVMETHOD(bus_child_pnpinfo, pci_child_pnpinfo_method), 176 DEVMETHOD(bus_child_location, pci_child_location_method), 177 DEVMETHOD(bus_get_device_path, pci_get_device_path_method), 178 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 179 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 180 DEVMETHOD(bus_suspend_child, pci_suspend_child), 181 DEVMETHOD(bus_resume_child, pci_resume_child), 182 DEVMETHOD(bus_rescan, pci_rescan_method), 183 184 /* PCI interface */ 185 DEVMETHOD(pci_read_config, pci_read_config_method), 186 DEVMETHOD(pci_write_config, pci_write_config_method), 187 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 188 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 189 DEVMETHOD(pci_enable_io, pci_enable_io_method), 190 DEVMETHOD(pci_disable_io, pci_disable_io_method), 191 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 192 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 193 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 194 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 195 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 196 DEVMETHOD(pci_find_cap, pci_find_cap_method), 197 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 198 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 199 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 200 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 201 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 202 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 203 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 204 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 205 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 206 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 207 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 208 DEVMETHOD(pci_release_msi, pci_release_msi_method), 209 DEVMETHOD(pci_msi_count, pci_msi_count_method), 210 DEVMETHOD(pci_msix_count, pci_msix_count_method), 211 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 212 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 213 DEVMETHOD(pci_get_id, pci_get_id_method), 214 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 215 DEVMETHOD(pci_child_added, pci_child_added_method), 216 #ifdef PCI_IOV 217 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 218 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 219 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 220 #endif 221 222 DEVMETHOD_END 223 }; 224 225 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 226 227 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_modevent, NULL, BUS_PASS_BUS); 228 MODULE_VERSION(pci, 1); 229 230 static char *pci_vendordata; 231 static size_t pci_vendordata_size; 232 233 struct pci_quirk { 234 uint32_t devid; /* Vendor/device of the card */ 235 int type; 236 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 238 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 239 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 241 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 242 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 243 #define PCI_QUIRK_DISABLE_FLR 8 /* Function-Level Reset (FLR) not working. */ 244 int arg1; 245 int arg2; 246 }; 247 248 static const struct pci_quirk pci_quirks[] = { 249 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 250 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 251 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 252 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 253 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 254 255 /* 256 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 257 * or the CMIC-SL (AKA ServerWorks GC_LE). 258 */ 259 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 260 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 261 262 /* 263 * MSI doesn't work on earlier Intel chipsets including 264 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 265 */ 266 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 267 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 268 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 269 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 271 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 272 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 273 274 /* 275 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 276 * bridge. 277 */ 278 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 279 280 /* 281 * Some virtualization environments emulate an older chipset 282 * but support MSI just fine. QEMU uses the Intel 82440. 283 */ 284 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 285 286 /* 287 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 288 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 289 * It prevents us from attaching hpet(4) when the bit is unset. 290 * Note this quirk only affects SB600 revision A13 and earlier. 291 * For SB600 A21 and later, firmware must set the bit to hide it. 292 * For SB700 and later, it is unused and hardcoded to zero. 293 */ 294 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 295 296 /* 297 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 298 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 299 * of the command register is set. 300 */ 301 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 302 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 303 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 304 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 305 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 306 307 /* 308 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 309 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 310 */ 311 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 312 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 313 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 314 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 315 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 316 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 317 318 /* 319 * HPE Gen 10 VGA has a memory range that can't be allocated in the 320 * expected place. 321 */ 322 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 323 324 /* 325 * With some MediaTek mt76 WiFi FLR does not work despite advertised. 326 */ 327 { 0x061614c3, PCI_QUIRK_DISABLE_FLR, 0, 0 }, /* mt76 7922 */ 328 329 /* end of table */ 330 { 0 } 331 }; 332 333 /* map register information */ 334 #define PCI_MAPMEM 0x01 /* memory map */ 335 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 336 #define PCI_MAPPORT 0x04 /* port map */ 337 338 struct devlist pci_devq; 339 uint32_t pci_generation; 340 uint32_t pci_numdevs = 0; 341 static int pcie_chipset, pcix_chipset; 342 343 /* sysctl vars */ 344 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 345 "PCI bus tuning parameters"); 346 347 static int pci_enable_io_modes = 1; 348 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 349 &pci_enable_io_modes, 1, 350 "Enable I/O and memory bits in the config register. Some BIOSes do not" 351 " enable these bits correctly. We'd like to do this all the time, but" 352 " there are some peripherals that this causes problems with."); 353 354 static int pci_do_realloc_bars = 1; 355 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 356 &pci_do_realloc_bars, 0, 357 "Attempt to allocate a new range for any BARs whose original " 358 "firmware-assigned ranges fail to allocate during the initial device scan."); 359 360 static int pci_do_power_nodriver = 0; 361 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 362 &pci_do_power_nodriver, 0, 363 "Place a function into D3 state when no driver attaches to it. 0 means" 364 " disable. 1 means conservatively place function into D3 state. 2 means" 365 " aggressively place function into D3 state. 3 means put absolutely" 366 " everything in D3 state."); 367 368 int pci_do_power_resume = 1; 369 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 370 &pci_do_power_resume, 1, 371 "Transition from D3 -> D0 on resume."); 372 373 int pci_do_power_suspend = 1; 374 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 375 &pci_do_power_suspend, 1, 376 "Transition from D0 -> D3 on suspend."); 377 378 static int pci_do_msi = 1; 379 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 380 "Enable support for MSI interrupts"); 381 382 static int pci_do_msix = 1; 383 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 384 "Enable support for MSI-X interrupts"); 385 386 static int pci_msix_rewrite_table = 0; 387 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 388 &pci_msix_rewrite_table, 0, 389 "Rewrite entire MSI-X table when updating MSI-X entries"); 390 391 static int pci_honor_msi_blacklist = 1; 392 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 393 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 394 395 #if defined(__i386__) || defined(__amd64__) 396 static int pci_usb_takeover = 1; 397 #else 398 static int pci_usb_takeover = 0; 399 #endif 400 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 401 &pci_usb_takeover, 1, 402 "Enable early takeover of USB controllers. Disable this if you depend on" 403 " BIOS emulation of USB devices, that is you use USB devices (like" 404 " keyboard or mouse) but do not load USB drivers"); 405 406 static int pci_clear_bars; 407 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 408 "Ignore firmware-assigned resources for BARs."); 409 410 static int pci_clear_buses; 411 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 412 "Ignore firmware-assigned bus numbers."); 413 414 static int pci_enable_ari = 1; 415 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 416 0, "Enable support for PCIe Alternative RID Interpretation"); 417 418 /* 419 * Some x86 firmware only enables PCIe hotplug if we claim to support aspm, 420 * however enabling it breaks some arm64 firmware as it powers off devices. 421 */ 422 #if defined(__i386__) || defined(__amd64__) 423 int pci_enable_aspm = 1; 424 #else 425 int pci_enable_aspm = 0; 426 #endif 427 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm, 428 0, "Enable support for PCIe Active State Power Management"); 429 430 static int pci_clear_aer_on_attach = 0; 431 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 432 &pci_clear_aer_on_attach, 0, 433 "Clear port and device AER state on driver attach"); 434 435 static bool pci_enable_mps_tune = true; 436 SYSCTL_BOOL(_hw_pci, OID_AUTO, enable_mps_tune, CTLFLAG_RWTUN, 437 &pci_enable_mps_tune, 1, 438 "Enable tuning of MPS(maximum payload size)." ); 439 440 static bool pci_intx_reroute = true; 441 SYSCTL_BOOL(_hw_pci, OID_AUTO, intx_reroute, CTLFLAG_RWTUN, 442 &pci_intx_reroute, 0, "Re-route INTx interrupts when scanning devices"); 443 444 static int 445 pci_has_quirk(uint32_t devid, int quirk) 446 { 447 const struct pci_quirk *q; 448 449 for (q = &pci_quirks[0]; q->devid; q++) { 450 if (q->devid == devid && q->type == quirk) 451 return (1); 452 } 453 return (0); 454 } 455 456 /* Find a device_t by bus/slot/function in domain 0 */ 457 458 device_t 459 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 460 { 461 462 return (pci_find_dbsf(0, bus, slot, func)); 463 } 464 465 /* Find a device_t by domain/bus/slot/function */ 466 467 device_t 468 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 469 { 470 struct pci_devinfo *dinfo = NULL; 471 472 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 473 if ((dinfo->cfg.domain == domain) && 474 (dinfo->cfg.bus == bus) && 475 (dinfo->cfg.slot == slot) && 476 (dinfo->cfg.func == func)) { 477 break; 478 } 479 } 480 481 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 482 } 483 484 /* Find a device_t by vendor/device ID */ 485 486 device_t 487 pci_find_device(uint16_t vendor, uint16_t device) 488 { 489 struct pci_devinfo *dinfo; 490 491 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 492 if ((dinfo->cfg.vendor == vendor) && 493 (dinfo->cfg.device == device)) { 494 return (dinfo->cfg.dev); 495 } 496 } 497 498 return (NULL); 499 } 500 501 device_t 502 pci_find_class(uint8_t class, uint8_t subclass) 503 { 504 struct pci_devinfo *dinfo; 505 506 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 507 if (dinfo->cfg.baseclass == class && 508 dinfo->cfg.subclass == subclass) { 509 return (dinfo->cfg.dev); 510 } 511 } 512 513 return (NULL); 514 } 515 516 device_t 517 pci_find_class_from(uint8_t class, uint8_t subclass, device_t from) 518 { 519 struct pci_devinfo *dinfo; 520 bool found = false; 521 522 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 523 if (from != NULL && found == false) { 524 if (from != dinfo->cfg.dev) 525 continue; 526 found = true; 527 continue; 528 } 529 if (dinfo->cfg.baseclass == class && 530 dinfo->cfg.subclass == subclass) { 531 return (dinfo->cfg.dev); 532 } 533 } 534 535 return (NULL); 536 } 537 538 device_t 539 pci_find_base_class_from(uint8_t class, device_t from) 540 { 541 struct pci_devinfo *dinfo; 542 bool found = false; 543 544 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 545 if (from != NULL && found == false) { 546 if (from != dinfo->cfg.dev) 547 continue; 548 found = true; 549 continue; 550 } 551 if (dinfo->cfg.baseclass == class) { 552 return (dinfo->cfg.dev); 553 } 554 } 555 556 return (NULL); 557 } 558 559 static int 560 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 561 { 562 va_list ap; 563 int retval; 564 565 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 566 cfg->func); 567 va_start(ap, fmt); 568 retval += vprintf(fmt, ap); 569 va_end(ap); 570 return (retval); 571 } 572 573 /* return base address of memory or port map */ 574 575 static pci_addr_t 576 pci_mapbase(uint64_t mapreg) 577 { 578 579 if (PCI_BAR_MEM(mapreg)) 580 return (mapreg & PCIM_BAR_MEM_BASE); 581 else 582 return (mapreg & PCIM_BAR_IO_BASE); 583 } 584 585 /* return map type of memory or port map */ 586 587 static const char * 588 pci_maptype(uint64_t mapreg) 589 { 590 591 if (PCI_BAR_IO(mapreg)) 592 return ("I/O Port"); 593 if (mapreg & PCIM_BAR_MEM_PREFETCH) 594 return ("Prefetchable Memory"); 595 return ("Memory"); 596 } 597 598 /* return log2 of map size decoded for memory or port map */ 599 600 int 601 pci_mapsize(uint64_t testval) 602 { 603 int ln2size; 604 605 testval = pci_mapbase(testval); 606 ln2size = 0; 607 if (testval != 0) { 608 while ((testval & 1) == 0) 609 { 610 ln2size++; 611 testval >>= 1; 612 } 613 } 614 return (ln2size); 615 } 616 617 /* return base address of device ROM */ 618 619 static pci_addr_t 620 pci_rombase(uint64_t mapreg) 621 { 622 623 return (mapreg & PCIM_BIOS_ADDR_MASK); 624 } 625 626 /* return log2 of map size decided for device ROM */ 627 628 static int 629 pci_romsize(uint64_t testval) 630 { 631 int ln2size; 632 633 testval = pci_rombase(testval); 634 ln2size = 0; 635 if (testval != 0) { 636 while ((testval & 1) == 0) 637 { 638 ln2size++; 639 testval >>= 1; 640 } 641 } 642 return (ln2size); 643 } 644 645 /* return log2 of address range supported by map register */ 646 647 static int 648 pci_maprange(uint64_t mapreg) 649 { 650 int ln2range = 0; 651 652 if (PCI_BAR_IO(mapreg)) 653 ln2range = 32; 654 else 655 switch (mapreg & PCIM_BAR_MEM_TYPE) { 656 case PCIM_BAR_MEM_32: 657 ln2range = 32; 658 break; 659 case PCIM_BAR_MEM_1MB: 660 ln2range = 20; 661 break; 662 case PCIM_BAR_MEM_64: 663 ln2range = 64; 664 break; 665 } 666 return (ln2range); 667 } 668 669 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 670 671 static void 672 pci_fixancient(pcicfgregs *cfg) 673 { 674 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 675 return; 676 677 /* PCI to PCI bridges use header type 1 */ 678 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 679 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 680 } 681 682 /* extract header type specific config data */ 683 684 static void 685 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 686 { 687 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 688 switch (cfg->hdrtype & PCIM_HDRTYPE) { 689 case PCIM_HDRTYPE_NORMAL: 690 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 691 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 692 cfg->mingnt = REG(PCIR_MINGNT, 1); 693 cfg->maxlat = REG(PCIR_MAXLAT, 1); 694 cfg->nummaps = PCI_MAXMAPS_0; 695 break; 696 case PCIM_HDRTYPE_BRIDGE: 697 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 698 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 699 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 700 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 701 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 702 cfg->nummaps = PCI_MAXMAPS_1; 703 break; 704 case PCIM_HDRTYPE_CARDBUS: 705 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 706 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 707 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 708 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 709 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 710 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 711 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 712 cfg->nummaps = PCI_MAXMAPS_2; 713 break; 714 } 715 #undef REG 716 } 717 718 /* read configuration header into pcicfgregs structure */ 719 struct pci_devinfo * 720 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 721 { 722 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 723 uint16_t vid, did; 724 725 vid = REG(PCIR_VENDOR, 2); 726 if (vid == PCIV_INVALID) 727 return (NULL); 728 729 did = REG(PCIR_DEVICE, 2); 730 731 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 732 } 733 734 struct pci_devinfo * 735 pci_alloc_devinfo_method(device_t dev) 736 { 737 738 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 739 M_WAITOK | M_ZERO)); 740 } 741 742 static struct pci_devinfo * 743 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 744 uint16_t vid, uint16_t did) 745 { 746 struct pci_devinfo *devlist_entry; 747 pcicfgregs *cfg; 748 749 devlist_entry = PCI_ALLOC_DEVINFO(bus); 750 751 cfg = &devlist_entry->cfg; 752 753 cfg->domain = d; 754 cfg->bus = b; 755 cfg->slot = s; 756 cfg->func = f; 757 cfg->vendor = vid; 758 cfg->device = did; 759 cfg->cmdreg = REG(PCIR_COMMAND, 2); 760 cfg->statreg = REG(PCIR_STATUS, 2); 761 cfg->baseclass = REG(PCIR_CLASS, 1); 762 cfg->subclass = REG(PCIR_SUBCLASS, 1); 763 cfg->progif = REG(PCIR_PROGIF, 1); 764 cfg->revid = REG(PCIR_REVID, 1); 765 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 766 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 767 cfg->lattimer = REG(PCIR_LATTIMER, 1); 768 cfg->intpin = REG(PCIR_INTPIN, 1); 769 cfg->intline = REG(PCIR_INTLINE, 1); 770 771 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 772 cfg->hdrtype &= ~PCIM_MFDEV; 773 STAILQ_INIT(&cfg->maps); 774 775 cfg->iov = NULL; 776 777 pci_fixancient(cfg); 778 pci_hdrtypedata(pcib, b, s, f, cfg); 779 780 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 781 pci_read_cap(pcib, cfg); 782 783 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 784 785 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 786 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 787 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 788 devlist_entry->conf.pc_sel.pc_func = cfg->func; 789 devlist_entry->conf.pc_hdr = cfg->hdrtype; 790 791 devlist_entry->conf.pc_subvendor = cfg->subvendor; 792 devlist_entry->conf.pc_subdevice = cfg->subdevice; 793 devlist_entry->conf.pc_vendor = cfg->vendor; 794 devlist_entry->conf.pc_device = cfg->device; 795 796 devlist_entry->conf.pc_class = cfg->baseclass; 797 devlist_entry->conf.pc_subclass = cfg->subclass; 798 devlist_entry->conf.pc_progif = cfg->progif; 799 devlist_entry->conf.pc_revid = cfg->revid; 800 801 pci_numdevs++; 802 pci_generation++; 803 804 return (devlist_entry); 805 } 806 #undef REG 807 808 static void 809 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 810 { 811 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 812 cfg->ea.ea_location + (n), w) 813 int num_ent; 814 int ptr; 815 int a, b; 816 uint32_t val; 817 int ent_size; 818 uint32_t dw[4]; 819 uint64_t base, max_offset; 820 struct pci_ea_entry *eae; 821 822 if (cfg->ea.ea_location == 0) 823 return; 824 825 STAILQ_INIT(&cfg->ea.ea_entries); 826 827 /* Determine the number of entries */ 828 num_ent = REG(PCIR_EA_NUM_ENT, 2); 829 num_ent &= PCIM_EA_NUM_ENT_MASK; 830 831 /* Find the first entry to care of */ 832 ptr = PCIR_EA_FIRST_ENT; 833 834 /* Skip DWORD 2 for type 1 functions */ 835 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 836 ptr += 4; 837 838 for (a = 0; a < num_ent; a++) { 839 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 840 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 841 842 /* Read a number of dwords in the entry */ 843 val = REG(ptr, 4); 844 ptr += 4; 845 ent_size = (val & PCIM_EA_ES); 846 847 for (b = 0; b < ent_size; b++) { 848 dw[b] = REG(ptr, 4); 849 ptr += 4; 850 } 851 852 eae->eae_flags = val; 853 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 854 855 base = dw[0] & PCIM_EA_FIELD_MASK; 856 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 857 b = 2; 858 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 859 base |= (uint64_t)dw[b] << 32UL; 860 b++; 861 } 862 if (((dw[1] & PCIM_EA_IS_64) != 0) 863 && (b < ent_size)) { 864 max_offset |= (uint64_t)dw[b] << 32UL; 865 b++; 866 } 867 868 eae->eae_base = base; 869 eae->eae_max_offset = max_offset; 870 871 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 872 873 if (bootverbose) { 874 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 875 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 876 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 877 } 878 } 879 } 880 #undef REG 881 882 static void 883 pci_read_cap(device_t pcib, pcicfgregs *cfg) 884 { 885 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 886 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 887 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 888 uint64_t addr; 889 #endif 890 uint32_t val; 891 int ptr, nextptr, ptrptr; 892 893 switch (cfg->hdrtype & PCIM_HDRTYPE) { 894 case PCIM_HDRTYPE_NORMAL: 895 case PCIM_HDRTYPE_BRIDGE: 896 ptrptr = PCIR_CAP_PTR; 897 break; 898 case PCIM_HDRTYPE_CARDBUS: 899 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 900 break; 901 default: 902 return; /* no extended capabilities support */ 903 } 904 nextptr = REG(ptrptr, 1); /* sanity check? */ 905 906 /* 907 * Read capability entries. 908 */ 909 while (nextptr != 0) { 910 /* Sanity check */ 911 if (nextptr > 255) { 912 printf("illegal PCI extended capability offset %d\n", 913 nextptr); 914 return; 915 } 916 /* Find the next entry */ 917 ptr = nextptr; 918 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 919 920 /* Process this entry */ 921 switch (REG(ptr + PCICAP_ID, 1)) { 922 case PCIY_PMG: /* PCI power management */ 923 cfg->pp.pp_location = ptr; 924 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 925 break; 926 case PCIY_HT: /* HyperTransport */ 927 /* Determine HT-specific capability type. */ 928 val = REG(ptr + PCIR_HT_COMMAND, 2); 929 930 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 931 cfg->ht.ht_slave = ptr; 932 933 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 934 switch (val & PCIM_HTCMD_CAP_MASK) { 935 case PCIM_HTCAP_MSI_MAPPING: 936 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 937 /* Sanity check the mapping window. */ 938 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 939 4); 940 addr <<= 32; 941 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 942 4); 943 if (addr != MSI_INTEL_ADDR_BASE) 944 device_printf(pcib, 945 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 946 cfg->domain, cfg->bus, 947 cfg->slot, cfg->func, 948 (long long)addr); 949 } else 950 addr = MSI_INTEL_ADDR_BASE; 951 952 cfg->ht.ht_msimap = ptr; 953 cfg->ht.ht_msictrl = val; 954 cfg->ht.ht_msiaddr = addr; 955 break; 956 } 957 #endif 958 break; 959 case PCIY_MSI: /* PCI MSI */ 960 cfg->msi.msi_location = ptr; 961 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 962 break; 963 case PCIY_MSIX: /* PCI MSI-X */ 964 cfg->msix.msix_location = ptr; 965 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 966 val = REG(ptr + PCIR_MSIX_TABLE, 4); 967 cfg->msix.msix_table_bar = PCIR_BAR(val & 968 PCIM_MSIX_BIR_MASK); 969 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 970 val = REG(ptr + PCIR_MSIX_PBA, 4); 971 cfg->msix.msix_pba_bar = PCIR_BAR(val & 972 PCIM_MSIX_BIR_MASK); 973 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 974 break; 975 case PCIY_VPD: /* PCI Vital Product Data */ 976 cfg->vpd.vpd_reg = ptr; 977 break; 978 case PCIY_SUBVENDOR: 979 /* Should always be true. */ 980 if ((cfg->hdrtype & PCIM_HDRTYPE) == 981 PCIM_HDRTYPE_BRIDGE) { 982 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 983 cfg->subvendor = val & 0xffff; 984 cfg->subdevice = val >> 16; 985 } 986 break; 987 case PCIY_PCIX: /* PCI-X */ 988 /* 989 * Assume we have a PCI-X chipset if we have 990 * at least one PCI-PCI bridge with a PCI-X 991 * capability. Note that some systems with 992 * PCI-express or HT chipsets might match on 993 * this check as well. 994 */ 995 if ((cfg->hdrtype & PCIM_HDRTYPE) == 996 PCIM_HDRTYPE_BRIDGE) 997 pcix_chipset = 1; 998 cfg->pcix.pcix_location = ptr; 999 break; 1000 case PCIY_EXPRESS: /* PCI-express */ 1001 /* 1002 * Assume we have a PCI-express chipset if we have 1003 * at least one PCI-express device. 1004 */ 1005 pcie_chipset = 1; 1006 cfg->pcie.pcie_location = ptr; 1007 val = REG(ptr + PCIER_FLAGS, 2); 1008 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 1009 break; 1010 case PCIY_EA: /* Enhanced Allocation */ 1011 cfg->ea.ea_location = ptr; 1012 pci_ea_fill_info(pcib, cfg); 1013 break; 1014 default: 1015 break; 1016 } 1017 } 1018 1019 #if defined(__powerpc__) 1020 /* 1021 * Enable the MSI mapping window for all HyperTransport 1022 * slaves. PCI-PCI bridges have their windows enabled via 1023 * PCIB_MAP_MSI(). 1024 */ 1025 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 1026 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 1027 device_printf(pcib, 1028 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 1029 cfg->domain, cfg->bus, cfg->slot, cfg->func); 1030 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 1031 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 1032 2); 1033 } 1034 #endif 1035 /* REG and WREG use carry through to next functions */ 1036 } 1037 1038 /* 1039 * PCI Vital Product Data 1040 */ 1041 1042 #define PCI_VPD_TIMEOUT 1000000 1043 1044 static int 1045 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 1046 { 1047 int count = PCI_VPD_TIMEOUT; 1048 1049 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1050 1051 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 1052 1053 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 1054 if (--count < 0) 1055 return (ENXIO); 1056 DELAY(1); /* limit looping */ 1057 } 1058 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 1059 1060 return (0); 1061 } 1062 1063 #if 0 1064 static int 1065 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1066 { 1067 int count = PCI_VPD_TIMEOUT; 1068 1069 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1070 1071 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1072 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1073 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1074 if (--count < 0) 1075 return (ENXIO); 1076 DELAY(1); /* limit looping */ 1077 } 1078 1079 return (0); 1080 } 1081 #endif 1082 1083 #undef PCI_VPD_TIMEOUT 1084 1085 struct vpd_readstate { 1086 device_t pcib; 1087 pcicfgregs *cfg; 1088 uint32_t val; 1089 int bytesinval; 1090 int off; 1091 uint8_t cksum; 1092 }; 1093 1094 /* return 0 and one byte in *data if no read error, -1 else */ 1095 static int 1096 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1097 { 1098 uint32_t reg; 1099 uint8_t byte; 1100 1101 if (vrs->bytesinval == 0) { 1102 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1103 return (-1); 1104 vrs->val = le32toh(reg); 1105 vrs->off += 4; 1106 byte = vrs->val & 0xff; 1107 vrs->bytesinval = 3; 1108 } else { 1109 vrs->val = vrs->val >> 8; 1110 byte = vrs->val & 0xff; 1111 vrs->bytesinval--; 1112 } 1113 1114 vrs->cksum += byte; 1115 *data = byte; 1116 return (0); 1117 } 1118 1119 /* return 0 on match, -1 and "unget" byte on no match */ 1120 static int 1121 vpd_expectbyte(struct vpd_readstate *vrs, uint8_t expected) 1122 { 1123 uint8_t data; 1124 1125 if (vpd_nextbyte(vrs, &data) != 0) 1126 return (-1); 1127 1128 if (data == expected) 1129 return (0); 1130 1131 vrs->cksum -= data; 1132 vrs->val = (vrs->val << 8) + data; 1133 vrs->bytesinval++; 1134 return (-1); 1135 } 1136 1137 /* return size if tag matches, -1 on no match, -2 on read error */ 1138 static int 1139 vpd_read_tag_size(struct vpd_readstate *vrs, uint8_t vpd_tag) 1140 { 1141 uint8_t byte1, byte2; 1142 1143 if (vpd_expectbyte(vrs, vpd_tag) != 0) 1144 return (-1); 1145 1146 if ((vpd_tag & 0x80) == 0) 1147 return (vpd_tag & 0x07); 1148 1149 if (vpd_nextbyte(vrs, &byte1) != 0) 1150 return (-2); 1151 if (vpd_nextbyte(vrs, &byte2) != 0) 1152 return (-2); 1153 1154 return ((byte2 << 8) + byte1); 1155 } 1156 1157 /* (re)allocate buffer in multiples of 8 elements */ 1158 static void* 1159 alloc_buffer(void* buffer, size_t element_size, int needed) 1160 { 1161 int alloc, new_alloc; 1162 1163 alloc = roundup2(needed, 8); 1164 new_alloc = roundup2(needed + 1, 8); 1165 if (alloc != new_alloc) { 1166 buffer = reallocf(buffer, 1167 new_alloc * element_size, M_DEVBUF, M_WAITOK | M_ZERO); 1168 } 1169 1170 return (buffer); 1171 } 1172 1173 /* read VPD keyword and return element size, return -1 on read error */ 1174 static int 1175 vpd_read_elem_head(struct vpd_readstate *vrs, char keyword[2]) 1176 { 1177 uint8_t data; 1178 1179 if (vpd_nextbyte(vrs, &keyword[0]) != 0) 1180 return (-1); 1181 if (vpd_nextbyte(vrs, &keyword[1]) != 0) 1182 return (-1); 1183 if (vpd_nextbyte(vrs, &data) != 0) 1184 return (-1); 1185 1186 return (data); 1187 } 1188 1189 /* read VPD data element of given size into allocated buffer */ 1190 static char * 1191 vpd_read_value(struct vpd_readstate *vrs, int size) 1192 { 1193 int i; 1194 char char1; 1195 char *value; 1196 1197 value = malloc(size + 1, M_DEVBUF, M_WAITOK); 1198 for (i = 0; i < size; i++) { 1199 if (vpd_nextbyte(vrs, &char1) != 0) { 1200 free(value, M_DEVBUF); 1201 return (NULL); 1202 } 1203 value[i] = char1; 1204 } 1205 value[size] = '\0'; 1206 1207 return (value); 1208 } 1209 1210 /* read VPD into *keyword and *value, return length of data element */ 1211 static int 1212 vpd_read_elem_data(struct vpd_readstate *vrs, char keyword[2], char **value, int maxlen) 1213 { 1214 int len; 1215 1216 len = vpd_read_elem_head(vrs, keyword); 1217 if (len < 0 || len > maxlen) 1218 return (-1); 1219 *value = vpd_read_value(vrs, len); 1220 1221 return (len); 1222 } 1223 1224 /* subtract all data following first byte from checksum of RV element */ 1225 static void 1226 vpd_fixup_cksum(struct vpd_readstate *vrs, char *rvstring, int len) 1227 { 1228 int i; 1229 uint8_t fixup; 1230 1231 fixup = 0; 1232 for (i = 1; i < len; i++) 1233 fixup += rvstring[i]; 1234 vrs->cksum -= fixup; 1235 } 1236 1237 /* fetch one read-only element and return size of heading + data */ 1238 static int 1239 next_vpd_ro_elem(struct vpd_readstate *vrs, int maxsize) 1240 { 1241 struct pcicfg_vpd *vpd; 1242 pcicfgregs *cfg; 1243 struct vpd_readonly *vpd_ros; 1244 int len; 1245 1246 cfg = vrs->cfg; 1247 vpd = &cfg->vpd; 1248 1249 if (maxsize < 3) 1250 return (-1); 1251 vpd->vpd_ros = alloc_buffer(vpd->vpd_ros, sizeof(*vpd->vpd_ros), vpd->vpd_rocnt); 1252 vpd_ros = &vpd->vpd_ros[vpd->vpd_rocnt]; 1253 maxsize -= 3; 1254 len = vpd_read_elem_data(vrs, vpd_ros->keyword, &vpd_ros->value, maxsize); 1255 if (vpd_ros->value == NULL) 1256 return (-1); 1257 vpd_ros->len = len; 1258 if (vpd_ros->keyword[0] == 'R' && vpd_ros->keyword[1] == 'V') { 1259 vpd_fixup_cksum(vrs, vpd_ros->value, len); 1260 if (vrs->cksum != 0) { 1261 pci_printf(cfg, 1262 "invalid VPD checksum %#hhx\n", vrs->cksum); 1263 return (-1); 1264 } 1265 } 1266 vpd->vpd_rocnt++; 1267 1268 return (len + 3); 1269 } 1270 1271 /* fetch one writable element and return size of heading + data */ 1272 static int 1273 next_vpd_rw_elem(struct vpd_readstate *vrs, int maxsize) 1274 { 1275 struct pcicfg_vpd *vpd; 1276 pcicfgregs *cfg; 1277 struct vpd_write *vpd_w; 1278 int len; 1279 1280 cfg = vrs->cfg; 1281 vpd = &cfg->vpd; 1282 1283 if (maxsize < 3) 1284 return (-1); 1285 vpd->vpd_w = alloc_buffer(vpd->vpd_w, sizeof(*vpd->vpd_w), vpd->vpd_wcnt); 1286 if (vpd->vpd_w == NULL) { 1287 pci_printf(cfg, "out of memory"); 1288 return (-1); 1289 } 1290 vpd_w = &vpd->vpd_w[vpd->vpd_wcnt]; 1291 maxsize -= 3; 1292 vpd_w->start = vrs->off + 3 - vrs->bytesinval; 1293 len = vpd_read_elem_data(vrs, vpd_w->keyword, &vpd_w->value, maxsize); 1294 if (vpd_w->value == NULL) 1295 return (-1); 1296 vpd_w->len = len; 1297 vpd->vpd_wcnt++; 1298 1299 return (len + 3); 1300 } 1301 1302 /* free all memory allocated for VPD data */ 1303 static void 1304 vpd_free(struct pcicfg_vpd *vpd) 1305 { 1306 int i; 1307 1308 free(vpd->vpd_ident, M_DEVBUF); 1309 for (i = 0; i < vpd->vpd_rocnt; i++) 1310 free(vpd->vpd_ros[i].value, M_DEVBUF); 1311 free(vpd->vpd_ros, M_DEVBUF); 1312 vpd->vpd_rocnt = 0; 1313 for (i = 0; i < vpd->vpd_wcnt; i++) 1314 free(vpd->vpd_w[i].value, M_DEVBUF); 1315 free(vpd->vpd_w, M_DEVBUF); 1316 vpd->vpd_wcnt = 0; 1317 } 1318 1319 #define VPD_TAG_END ((0x0f << 3) | 0) /* small tag, len == 0 */ 1320 #define VPD_TAG_IDENT (0x02 | 0x80) /* large tag */ 1321 #define VPD_TAG_RO (0x10 | 0x80) /* large tag */ 1322 #define VPD_TAG_RW (0x11 | 0x80) /* large tag */ 1323 1324 static int 1325 pci_parse_vpd(device_t pcib, pcicfgregs *cfg) 1326 { 1327 struct vpd_readstate vrs; 1328 int cksumvalid; 1329 int size, elem_size; 1330 1331 /* init vpd reader */ 1332 vrs.bytesinval = 0; 1333 vrs.off = 0; 1334 vrs.pcib = pcib; 1335 vrs.cfg = cfg; 1336 vrs.cksum = 0; 1337 1338 /* read VPD ident element - mandatory */ 1339 size = vpd_read_tag_size(&vrs, VPD_TAG_IDENT); 1340 if (size <= 0) { 1341 pci_printf(cfg, "no VPD ident found\n"); 1342 return (0); 1343 } 1344 cfg->vpd.vpd_ident = vpd_read_value(&vrs, size); 1345 if (cfg->vpd.vpd_ident == NULL) { 1346 pci_printf(cfg, "error accessing VPD ident data\n"); 1347 return (0); 1348 } 1349 1350 /* read VPD RO elements - mandatory */ 1351 size = vpd_read_tag_size(&vrs, VPD_TAG_RO); 1352 if (size <= 0) { 1353 pci_printf(cfg, "no read-only VPD data found\n"); 1354 return (0); 1355 } 1356 while (size > 0) { 1357 elem_size = next_vpd_ro_elem(&vrs, size); 1358 if (elem_size < 0) { 1359 pci_printf(cfg, "error accessing read-only VPD data\n"); 1360 return (-1); 1361 } 1362 size -= elem_size; 1363 } 1364 cksumvalid = (vrs.cksum == 0); 1365 if (!cksumvalid) 1366 return (-1); 1367 1368 /* read VPD RW elements - optional */ 1369 size = vpd_read_tag_size(&vrs, VPD_TAG_RW); 1370 if (size == -2) 1371 return (-1); 1372 while (size > 0) { 1373 elem_size = next_vpd_rw_elem(&vrs, size); 1374 if (elem_size < 0) { 1375 pci_printf(cfg, "error accessing writeable VPD data\n"); 1376 return (-1); 1377 } 1378 size -= elem_size; 1379 } 1380 1381 /* read empty END tag - mandatory */ 1382 size = vpd_read_tag_size(&vrs, VPD_TAG_END); 1383 if (size != 0) { 1384 pci_printf(cfg, "No valid VPD end tag found\n"); 1385 } 1386 return (0); 1387 } 1388 1389 static void 1390 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1391 { 1392 int status; 1393 1394 status = pci_parse_vpd(pcib, cfg); 1395 if (status < 0) 1396 vpd_free(&cfg->vpd); 1397 cfg->vpd.vpd_cached = 1; 1398 #undef REG 1399 #undef WREG 1400 } 1401 1402 int 1403 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1404 { 1405 struct pci_devinfo *dinfo = device_get_ivars(child); 1406 pcicfgregs *cfg = &dinfo->cfg; 1407 1408 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1409 pci_read_vpd(device_get_parent(dev), cfg); 1410 1411 *identptr = cfg->vpd.vpd_ident; 1412 1413 if (*identptr == NULL) 1414 return (ENXIO); 1415 1416 return (0); 1417 } 1418 1419 int 1420 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1421 const char **vptr) 1422 { 1423 struct pci_devinfo *dinfo = device_get_ivars(child); 1424 pcicfgregs *cfg = &dinfo->cfg; 1425 int i; 1426 1427 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1428 pci_read_vpd(device_get_parent(dev), cfg); 1429 1430 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1431 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1432 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1433 *vptr = cfg->vpd.vpd_ros[i].value; 1434 return (0); 1435 } 1436 1437 *vptr = NULL; 1438 return (ENXIO); 1439 } 1440 1441 struct pcicfg_vpd * 1442 pci_fetch_vpd_list(device_t dev) 1443 { 1444 struct pci_devinfo *dinfo = device_get_ivars(dev); 1445 pcicfgregs *cfg = &dinfo->cfg; 1446 1447 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1448 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1449 return (&cfg->vpd); 1450 } 1451 1452 /* 1453 * Find the requested HyperTransport capability and return the offset 1454 * in configuration space via the pointer provided. The function 1455 * returns 0 on success and an error code otherwise. 1456 */ 1457 int 1458 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1459 { 1460 int ptr, error; 1461 uint16_t val; 1462 1463 error = pci_find_cap(child, PCIY_HT, &ptr); 1464 if (error) 1465 return (error); 1466 1467 /* 1468 * Traverse the capabilities list checking each HT capability 1469 * to see if it matches the requested HT capability. 1470 */ 1471 for (;;) { 1472 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1473 if (capability == PCIM_HTCAP_SLAVE || 1474 capability == PCIM_HTCAP_HOST) 1475 val &= 0xe000; 1476 else 1477 val &= PCIM_HTCMD_CAP_MASK; 1478 if (val == capability) { 1479 if (capreg != NULL) 1480 *capreg = ptr; 1481 return (0); 1482 } 1483 1484 /* Skip to the next HT capability. */ 1485 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1486 break; 1487 } 1488 1489 return (ENOENT); 1490 } 1491 1492 /* 1493 * Find the next requested HyperTransport capability after start and return 1494 * the offset in configuration space via the pointer provided. The function 1495 * returns 0 on success and an error code otherwise. 1496 */ 1497 int 1498 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1499 int start, int *capreg) 1500 { 1501 int ptr; 1502 uint16_t val; 1503 1504 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1505 ("start capability is not HyperTransport capability")); 1506 ptr = start; 1507 1508 /* 1509 * Traverse the capabilities list checking each HT capability 1510 * to see if it matches the requested HT capability. 1511 */ 1512 for (;;) { 1513 /* Skip to the next HT capability. */ 1514 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1515 break; 1516 1517 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1518 if (capability == PCIM_HTCAP_SLAVE || 1519 capability == PCIM_HTCAP_HOST) 1520 val &= 0xe000; 1521 else 1522 val &= PCIM_HTCMD_CAP_MASK; 1523 if (val == capability) { 1524 if (capreg != NULL) 1525 *capreg = ptr; 1526 return (0); 1527 } 1528 } 1529 1530 return (ENOENT); 1531 } 1532 1533 /* 1534 * Find the requested capability and return the offset in 1535 * configuration space via the pointer provided. The function returns 1536 * 0 on success and an error code otherwise. 1537 */ 1538 int 1539 pci_find_cap_method(device_t dev, device_t child, int capability, 1540 int *capreg) 1541 { 1542 struct pci_devinfo *dinfo = device_get_ivars(child); 1543 pcicfgregs *cfg = &dinfo->cfg; 1544 uint32_t status; 1545 uint8_t ptr; 1546 int cnt; 1547 1548 /* 1549 * Check the CAP_LIST bit of the PCI status register first. 1550 */ 1551 status = pci_read_config(child, PCIR_STATUS, 2); 1552 if (!(status & PCIM_STATUS_CAPPRESENT)) 1553 return (ENXIO); 1554 1555 /* 1556 * Determine the start pointer of the capabilities list. 1557 */ 1558 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1559 case PCIM_HDRTYPE_NORMAL: 1560 case PCIM_HDRTYPE_BRIDGE: 1561 ptr = PCIR_CAP_PTR; 1562 break; 1563 case PCIM_HDRTYPE_CARDBUS: 1564 ptr = PCIR_CAP_PTR_2; 1565 break; 1566 default: 1567 /* XXX: panic? */ 1568 return (ENXIO); /* no extended capabilities support */ 1569 } 1570 ptr = pci_read_config(child, ptr, 1); 1571 1572 /* 1573 * Traverse the capabilities list. Limit by total theoretical 1574 * maximum number of caps: capability needs at least id and 1575 * next registers, and any type X header cannot contain caps. 1576 */ 1577 for (cnt = 0; ptr != 0 && cnt < (PCIE_REGMAX - 0x40) / 2; cnt++) { 1578 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1579 if (capreg != NULL) 1580 *capreg = ptr; 1581 return (0); 1582 } 1583 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1584 } 1585 1586 return (ENOENT); 1587 } 1588 1589 /* 1590 * Find the next requested capability after start and return the offset in 1591 * configuration space via the pointer provided. The function returns 1592 * 0 on success and an error code otherwise. 1593 */ 1594 int 1595 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1596 int start, int *capreg) 1597 { 1598 uint8_t ptr; 1599 1600 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1601 ("start capability is not expected capability")); 1602 1603 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1604 while (ptr != 0) { 1605 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1606 if (capreg != NULL) 1607 *capreg = ptr; 1608 return (0); 1609 } 1610 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1611 } 1612 1613 return (ENOENT); 1614 } 1615 1616 /* 1617 * Find the requested extended capability and return the offset in 1618 * configuration space via the pointer provided. The function returns 1619 * 0 on success and an error code otherwise. 1620 */ 1621 int 1622 pci_find_extcap_method(device_t dev, device_t child, int capability, 1623 int *capreg) 1624 { 1625 struct pci_devinfo *dinfo = device_get_ivars(child); 1626 pcicfgregs *cfg = &dinfo->cfg; 1627 uint32_t ecap; 1628 uint16_t ptr; 1629 1630 /* Only supported for PCI-express devices. */ 1631 if (cfg->pcie.pcie_location == 0) 1632 return (ENXIO); 1633 1634 ptr = PCIR_EXTCAP; 1635 ecap = pci_read_config(child, ptr, 4); 1636 if (ecap == 0xffffffff || ecap == 0) 1637 return (ENOENT); 1638 for (;;) { 1639 if (PCI_EXTCAP_ID(ecap) == capability) { 1640 if (capreg != NULL) 1641 *capreg = ptr; 1642 return (0); 1643 } 1644 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1645 if (ptr == 0) 1646 break; 1647 ecap = pci_read_config(child, ptr, 4); 1648 } 1649 1650 return (ENOENT); 1651 } 1652 1653 /* 1654 * Find the next requested extended capability after start and return the 1655 * offset in configuration space via the pointer provided. The function 1656 * returns 0 on success and an error code otherwise. 1657 */ 1658 int 1659 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1660 int start, int *capreg) 1661 { 1662 struct pci_devinfo *dinfo = device_get_ivars(child); 1663 pcicfgregs *cfg = &dinfo->cfg; 1664 uint32_t ecap; 1665 uint16_t ptr; 1666 1667 /* Only supported for PCI-express devices. */ 1668 if (cfg->pcie.pcie_location == 0) 1669 return (ENXIO); 1670 1671 ecap = pci_read_config(child, start, 4); 1672 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1673 ("start extended capability is not expected capability")); 1674 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1675 while (ptr != 0) { 1676 ecap = pci_read_config(child, ptr, 4); 1677 if (PCI_EXTCAP_ID(ecap) == capability) { 1678 if (capreg != NULL) 1679 *capreg = ptr; 1680 return (0); 1681 } 1682 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1683 } 1684 1685 return (ENOENT); 1686 } 1687 1688 /* 1689 * Support for MSI-X message interrupts. 1690 */ 1691 static void 1692 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1693 { 1694 struct pci_devinfo *dinfo = device_get_ivars(dev); 1695 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1696 uint32_t offset; 1697 1698 KASSERT(msix->msix_table_len > index, ("bogus index")); 1699 offset = msix->msix_table_offset + index * 16; 1700 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1701 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1702 bus_write_4(msix->msix_table_res, offset + 8, data); 1703 } 1704 1705 void 1706 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1707 uint64_t address, uint32_t data) 1708 { 1709 1710 if (pci_msix_rewrite_table) { 1711 struct pci_devinfo *dinfo = device_get_ivars(child); 1712 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1713 1714 /* 1715 * Some VM hosts require MSIX to be disabled in the 1716 * control register before updating the MSIX table 1717 * entries are allowed. It is not enough to only 1718 * disable MSIX while updating a single entry. MSIX 1719 * must be disabled while updating all entries in the 1720 * table. 1721 */ 1722 pci_write_config(child, 1723 msix->msix_location + PCIR_MSIX_CTRL, 1724 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1725 pci_resume_msix(child); 1726 } else 1727 pci_write_msix_entry(child, index, address, data); 1728 1729 /* Enable MSI -> HT mapping. */ 1730 pci_ht_map_msi(child, address); 1731 } 1732 1733 void 1734 pci_mask_msix(device_t dev, u_int index) 1735 { 1736 struct pci_devinfo *dinfo = device_get_ivars(dev); 1737 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1738 uint32_t offset, val; 1739 1740 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); 1741 offset = msix->msix_table_offset + index * 16 + 12; 1742 val = bus_read_4(msix->msix_table_res, offset); 1743 val |= PCIM_MSIX_VCTRL_MASK; 1744 1745 /* 1746 * Some devices (e.g. Samsung PM961) do not support reads of this 1747 * register, so always write the new value. 1748 */ 1749 bus_write_4(msix->msix_table_res, offset, val); 1750 } 1751 1752 void 1753 pci_unmask_msix(device_t dev, u_int index) 1754 { 1755 struct pci_devinfo *dinfo = device_get_ivars(dev); 1756 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1757 uint32_t offset, val; 1758 1759 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); 1760 offset = msix->msix_table_offset + index * 16 + 12; 1761 val = bus_read_4(msix->msix_table_res, offset); 1762 val &= ~PCIM_MSIX_VCTRL_MASK; 1763 1764 /* 1765 * Some devices (e.g. Samsung PM961) do not support reads of this 1766 * register, so always write the new value. 1767 */ 1768 bus_write_4(msix->msix_table_res, offset, val); 1769 } 1770 1771 int 1772 pci_pending_msix(device_t dev, u_int index) 1773 { 1774 struct pci_devinfo *dinfo = device_get_ivars(dev); 1775 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1776 uint32_t offset, bit; 1777 1778 KASSERT(msix->msix_table_len > index, ("bogus index")); 1779 offset = msix->msix_pba_offset + (index / 32) * 4; 1780 bit = 1 << index % 32; 1781 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1782 } 1783 1784 /* 1785 * Restore MSI-X registers and table during resume. If MSI-X is 1786 * enabled then walk the virtual table to restore the actual MSI-X 1787 * table. 1788 */ 1789 static void 1790 pci_resume_msix(device_t dev) 1791 { 1792 struct pci_devinfo *dinfo = device_get_ivars(dev); 1793 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1794 struct msix_table_entry *mte; 1795 struct msix_vector *mv; 1796 u_int i, msgnum; 1797 1798 if (msix->msix_alloc > 0) { 1799 msgnum = PCI_MSIX_MSGNUM(msix->msix_ctrl); 1800 1801 /* First, mask all vectors. */ 1802 for (i = 0; i < msgnum; i++) 1803 pci_mask_msix(dev, i); 1804 1805 /* Second, program any messages with at least one handler. */ 1806 for (i = 0; i < msix->msix_table_len; i++) { 1807 mte = &msix->msix_table[i]; 1808 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1809 continue; 1810 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1811 pci_write_msix_entry(dev, i, mv->mv_address, 1812 mv->mv_data); 1813 pci_unmask_msix(dev, i); 1814 } 1815 } 1816 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1817 msix->msix_ctrl, 2); 1818 } 1819 1820 /* 1821 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1822 * returned in *count. After this function returns, each message will be 1823 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1824 */ 1825 int 1826 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1827 { 1828 struct pci_devinfo *dinfo = device_get_ivars(child); 1829 pcicfgregs *cfg = &dinfo->cfg; 1830 struct resource_list_entry *rle; 1831 u_int actual, i, max; 1832 int error, irq; 1833 uint16_t ctrl, msgnum; 1834 1835 /* Don't let count == 0 get us into trouble. */ 1836 if (*count < 1) 1837 return (EINVAL); 1838 1839 /* If rid 0 is allocated, then fail. */ 1840 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1841 if (rle != NULL && rle->res != NULL) 1842 return (ENXIO); 1843 1844 /* Already have allocated messages? */ 1845 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1846 return (ENXIO); 1847 1848 /* If MSI-X is blacklisted for this system, fail. */ 1849 if (pci_msix_blacklisted()) 1850 return (ENXIO); 1851 1852 /* MSI-X capability present? */ 1853 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1854 return (ENODEV); 1855 1856 /* Make sure the appropriate BARs are mapped. */ 1857 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1858 cfg->msix.msix_table_bar); 1859 if (rle == NULL || rle->res == NULL || 1860 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1861 return (ENXIO); 1862 cfg->msix.msix_table_res = rle->res; 1863 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1864 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1865 cfg->msix.msix_pba_bar); 1866 if (rle == NULL || rle->res == NULL || 1867 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1868 return (ENXIO); 1869 } 1870 cfg->msix.msix_pba_res = rle->res; 1871 1872 ctrl = pci_read_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1873 2); 1874 msgnum = PCI_MSIX_MSGNUM(ctrl); 1875 if (bootverbose) 1876 device_printf(child, 1877 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1878 *count, msgnum); 1879 max = min(*count, msgnum); 1880 for (i = 0; i < max; i++) { 1881 /* Allocate a message. */ 1882 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1883 if (error) { 1884 if (i == 0) 1885 return (error); 1886 break; 1887 } 1888 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1889 irq, 1); 1890 } 1891 actual = i; 1892 1893 if (bootverbose) { 1894 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1895 if (actual == 1) 1896 device_printf(child, "using IRQ %ju for MSI-X\n", 1897 rle->start); 1898 else { 1899 bool run; 1900 1901 /* 1902 * Be fancy and try to print contiguous runs of 1903 * IRQ values as ranges. 'irq' is the previous IRQ. 1904 * 'run' is true if we are in a range. 1905 */ 1906 device_printf(child, "using IRQs %ju", rle->start); 1907 irq = rle->start; 1908 run = false; 1909 for (i = 1; i < actual; i++) { 1910 rle = resource_list_find(&dinfo->resources, 1911 SYS_RES_IRQ, i + 1); 1912 1913 /* Still in a run? */ 1914 if (rle->start == irq + 1) { 1915 run = true; 1916 irq++; 1917 continue; 1918 } 1919 1920 /* Finish previous range. */ 1921 if (run) { 1922 printf("-%d", irq); 1923 run = false; 1924 } 1925 1926 /* Start new range. */ 1927 printf(",%ju", rle->start); 1928 irq = rle->start; 1929 } 1930 1931 /* Unfinished range? */ 1932 if (run) 1933 printf("-%d", irq); 1934 printf(" for MSI-X\n"); 1935 } 1936 } 1937 1938 /* 1939 * Mask all vectors. Note that the message index assertion in 1940 * pci_mask_msix requires msix_ctrl to be set. 1941 */ 1942 cfg->msix.msix_ctrl = ctrl; 1943 for (i = 0; i < msgnum; i++) 1944 pci_mask_msix(child, i); 1945 1946 /* Allocate and initialize vector data and virtual table. */ 1947 cfg->msix.msix_vectors = mallocarray(actual, sizeof(struct msix_vector), 1948 M_DEVBUF, M_WAITOK | M_ZERO); 1949 cfg->msix.msix_table = mallocarray(actual, 1950 sizeof(struct msix_table_entry), M_DEVBUF, M_WAITOK | M_ZERO); 1951 for (i = 0; i < actual; i++) { 1952 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1953 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1954 cfg->msix.msix_table[i].mte_vector = i + 1; 1955 } 1956 1957 /* Update control register to enable MSI-X. */ 1958 ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1959 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1960 ctrl, 2); 1961 cfg->msix.msix_ctrl = ctrl; 1962 1963 /* Update counts of alloc'd messages. */ 1964 cfg->msix.msix_alloc = actual; 1965 cfg->msix.msix_table_len = actual; 1966 *count = actual; 1967 return (0); 1968 } 1969 1970 /* 1971 * By default, pci_alloc_msix() will assign the allocated IRQ 1972 * resources consecutively to the first N messages in the MSI-X table. 1973 * However, device drivers may want to use different layouts if they 1974 * either receive fewer messages than they asked for, or they wish to 1975 * populate the MSI-X table sparsely. This method allows the driver 1976 * to specify what layout it wants. It must be called after a 1977 * successful pci_alloc_msix() but before any of the associated 1978 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1979 * 1980 * The 'vectors' array contains 'count' message vectors. The array 1981 * maps directly to the MSI-X table in that index 0 in the array 1982 * specifies the vector for the first message in the MSI-X table, etc. 1983 * The vector value in each array index can either be 0 to indicate 1984 * that no vector should be assigned to a message slot, or it can be a 1985 * number from 1 to N (where N is the count returned from a 1986 * succcessful call to pci_alloc_msix()) to indicate which message 1987 * vector (IRQ) to be used for the corresponding message. 1988 * 1989 * On successful return, each message with a non-zero vector will have 1990 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1991 * 1. Additionally, if any of the IRQs allocated via the previous 1992 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1993 * will be freed back to the system automatically. 1994 * 1995 * For example, suppose a driver has a MSI-X table with 6 messages and 1996 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1997 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1998 * C. After the call to pci_alloc_msix(), the device will be setup to 1999 * have an MSI-X table of ABC--- (where - means no vector assigned). 2000 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 2001 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 2002 * be freed back to the system. This device will also have valid 2003 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 2004 * 2005 * In any case, the SYS_RES_IRQ rid X will always map to the message 2006 * at MSI-X table index X - 1 and will only be valid if a vector is 2007 * assigned to that table entry. 2008 */ 2009 int 2010 pci_remap_msix_method(device_t dev, device_t child, int count, 2011 const u_int *vectors) 2012 { 2013 struct pci_devinfo *dinfo = device_get_ivars(child); 2014 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2015 struct resource_list_entry *rle; 2016 u_int i, irq, j; 2017 bool *used; 2018 2019 /* 2020 * Have to have at least one message in the table but the 2021 * table can't be bigger than the actual MSI-X table in the 2022 * device. 2023 */ 2024 if (count < 1 || count > PCI_MSIX_MSGNUM(msix->msix_ctrl)) 2025 return (EINVAL); 2026 2027 /* Sanity check the vectors. */ 2028 for (i = 0; i < count; i++) 2029 if (vectors[i] > msix->msix_alloc) 2030 return (EINVAL); 2031 2032 /* 2033 * Make sure there aren't any holes in the vectors to be used. 2034 * It's a big pain to support it, and it doesn't really make 2035 * sense anyway. Also, at least one vector must be used. 2036 */ 2037 used = mallocarray(msix->msix_alloc, sizeof(*used), M_DEVBUF, M_WAITOK | 2038 M_ZERO); 2039 for (i = 0; i < count; i++) 2040 if (vectors[i] != 0) 2041 used[vectors[i] - 1] = true; 2042 for (i = 0; i < msix->msix_alloc - 1; i++) 2043 if (!used[i] && used[i + 1]) { 2044 free(used, M_DEVBUF); 2045 return (EINVAL); 2046 } 2047 if (!used[0]) { 2048 free(used, M_DEVBUF); 2049 return (EINVAL); 2050 } 2051 2052 /* Make sure none of the resources are allocated. */ 2053 for (i = 0; i < msix->msix_table_len; i++) { 2054 if (msix->msix_table[i].mte_vector == 0) 2055 continue; 2056 if (msix->msix_table[i].mte_handlers > 0) { 2057 free(used, M_DEVBUF); 2058 return (EBUSY); 2059 } 2060 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2061 KASSERT(rle != NULL, ("missing resource")); 2062 if (rle->res != NULL) { 2063 free(used, M_DEVBUF); 2064 return (EBUSY); 2065 } 2066 } 2067 2068 /* Free the existing resource list entries. */ 2069 for (i = 0; i < msix->msix_table_len; i++) { 2070 if (msix->msix_table[i].mte_vector == 0) 2071 continue; 2072 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2073 } 2074 2075 /* 2076 * Build the new virtual table keeping track of which vectors are 2077 * used. 2078 */ 2079 free(msix->msix_table, M_DEVBUF); 2080 msix->msix_table = mallocarray(count, sizeof(struct msix_table_entry), 2081 M_DEVBUF, M_WAITOK | M_ZERO); 2082 for (i = 0; i < count; i++) 2083 msix->msix_table[i].mte_vector = vectors[i]; 2084 msix->msix_table_len = count; 2085 2086 /* Free any unused IRQs and resize the vectors array if necessary. */ 2087 j = msix->msix_alloc - 1; 2088 if (!used[j]) { 2089 struct msix_vector *vec; 2090 2091 while (!used[j]) { 2092 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2093 msix->msix_vectors[j].mv_irq); 2094 j--; 2095 } 2096 vec = mallocarray(j + 1, sizeof(struct msix_vector), M_DEVBUF, 2097 M_WAITOK); 2098 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2099 (j + 1)); 2100 free(msix->msix_vectors, M_DEVBUF); 2101 msix->msix_vectors = vec; 2102 msix->msix_alloc = j + 1; 2103 } 2104 free(used, M_DEVBUF); 2105 2106 /* Map the IRQs onto the rids. */ 2107 for (i = 0; i < count; i++) { 2108 if (vectors[i] == 0) 2109 continue; 2110 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2111 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2112 irq, 1); 2113 } 2114 2115 if (bootverbose) { 2116 device_printf(child, "Remapped MSI-X IRQs as: "); 2117 for (i = 0; i < count; i++) { 2118 if (i != 0) 2119 printf(", "); 2120 if (vectors[i] == 0) 2121 printf("---"); 2122 else 2123 printf("%d", 2124 msix->msix_vectors[vectors[i] - 1].mv_irq); 2125 } 2126 printf("\n"); 2127 } 2128 2129 return (0); 2130 } 2131 2132 static int 2133 pci_release_msix(device_t dev, device_t child) 2134 { 2135 struct pci_devinfo *dinfo = device_get_ivars(child); 2136 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2137 struct resource_list_entry *rle; 2138 u_int i; 2139 2140 /* Do we have any messages to release? */ 2141 if (msix->msix_alloc == 0) 2142 return (ENODEV); 2143 2144 /* Make sure none of the resources are allocated. */ 2145 for (i = 0; i < msix->msix_table_len; i++) { 2146 if (msix->msix_table[i].mte_vector == 0) 2147 continue; 2148 if (msix->msix_table[i].mte_handlers > 0) 2149 return (EBUSY); 2150 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2151 KASSERT(rle != NULL, ("missing resource")); 2152 if (rle->res != NULL) 2153 return (EBUSY); 2154 } 2155 2156 /* Update control register to disable MSI-X. */ 2157 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2158 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2159 msix->msix_ctrl, 2); 2160 2161 /* Free the resource list entries. */ 2162 for (i = 0; i < msix->msix_table_len; i++) { 2163 if (msix->msix_table[i].mte_vector == 0) 2164 continue; 2165 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2166 } 2167 free(msix->msix_table, M_DEVBUF); 2168 msix->msix_table_len = 0; 2169 2170 /* Release the IRQs. */ 2171 for (i = 0; i < msix->msix_alloc; i++) 2172 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2173 msix->msix_vectors[i].mv_irq); 2174 free(msix->msix_vectors, M_DEVBUF); 2175 msix->msix_alloc = 0; 2176 return (0); 2177 } 2178 2179 /* 2180 * Return the max supported MSI-X messages this device supports. 2181 * Basically, assuming the MD code can alloc messages, this function 2182 * should return the maximum value that pci_alloc_msix() can return. 2183 * Thus, it is subject to the tunables, etc. 2184 */ 2185 int 2186 pci_msix_count_method(device_t dev, device_t child) 2187 { 2188 struct pci_devinfo *dinfo = device_get_ivars(child); 2189 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2190 uint16_t ctrl; 2191 2192 if (pci_do_msix && msix->msix_location != 0) { 2193 ctrl = pci_read_config(child, msix->msix_location + 2194 PCIR_MSI_CTRL, 2); 2195 return (PCI_MSIX_MSGNUM(ctrl)); 2196 } 2197 return (0); 2198 } 2199 2200 int 2201 pci_msix_pba_bar_method(device_t dev, device_t child) 2202 { 2203 struct pci_devinfo *dinfo = device_get_ivars(child); 2204 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2205 2206 if (pci_do_msix && msix->msix_location != 0) 2207 return (msix->msix_pba_bar); 2208 return (-1); 2209 } 2210 2211 int 2212 pci_msix_table_bar_method(device_t dev, device_t child) 2213 { 2214 struct pci_devinfo *dinfo = device_get_ivars(child); 2215 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2216 2217 if (pci_do_msix && msix->msix_location != 0) 2218 return (msix->msix_table_bar); 2219 return (-1); 2220 } 2221 2222 /* 2223 * HyperTransport MSI mapping control 2224 */ 2225 void 2226 pci_ht_map_msi(device_t dev, uint64_t addr) 2227 { 2228 struct pci_devinfo *dinfo = device_get_ivars(dev); 2229 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2230 2231 if (!ht->ht_msimap) 2232 return; 2233 2234 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2235 ht->ht_msiaddr >> 20 == addr >> 20) { 2236 /* Enable MSI -> HT mapping. */ 2237 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2238 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2239 ht->ht_msictrl, 2); 2240 } 2241 2242 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2243 /* Disable MSI -> HT mapping. */ 2244 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2245 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2246 ht->ht_msictrl, 2); 2247 } 2248 } 2249 2250 int 2251 pci_get_relaxed_ordering_enabled(device_t dev) 2252 { 2253 struct pci_devinfo *dinfo = device_get_ivars(dev); 2254 int cap; 2255 uint16_t val; 2256 2257 cap = dinfo->cfg.pcie.pcie_location; 2258 if (cap == 0) 2259 return (0); 2260 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2261 val &= PCIEM_CTL_RELAXED_ORD_ENABLE; 2262 return (val != 0); 2263 } 2264 2265 int 2266 pci_get_max_payload(device_t dev) 2267 { 2268 struct pci_devinfo *dinfo = device_get_ivars(dev); 2269 int cap; 2270 uint16_t val; 2271 2272 cap = dinfo->cfg.pcie.pcie_location; 2273 if (cap == 0) 2274 return (0); 2275 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2276 val &= PCIEM_CTL_MAX_PAYLOAD; 2277 val >>= 5; 2278 return (1 << (val + 7)); 2279 } 2280 2281 int 2282 pci_get_max_read_req(device_t dev) 2283 { 2284 struct pci_devinfo *dinfo = device_get_ivars(dev); 2285 int cap; 2286 uint16_t val; 2287 2288 cap = dinfo->cfg.pcie.pcie_location; 2289 if (cap == 0) 2290 return (0); 2291 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2292 val &= PCIEM_CTL_MAX_READ_REQUEST; 2293 val >>= 12; 2294 return (1 << (val + 7)); 2295 } 2296 2297 int 2298 pci_set_max_read_req(device_t dev, int size) 2299 { 2300 struct pci_devinfo *dinfo = device_get_ivars(dev); 2301 int cap; 2302 uint16_t val; 2303 2304 cap = dinfo->cfg.pcie.pcie_location; 2305 if (cap == 0) 2306 return (0); 2307 if (size < 128) 2308 size = 128; 2309 if (size > 4096) 2310 size = 4096; 2311 size = (1 << (fls(size) - 1)); 2312 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2313 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2314 val |= (fls(size) - 8) << 12; 2315 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2316 return (size); 2317 } 2318 2319 uint32_t 2320 pcie_read_config(device_t dev, int reg, int width) 2321 { 2322 struct pci_devinfo *dinfo = device_get_ivars(dev); 2323 int cap; 2324 2325 cap = dinfo->cfg.pcie.pcie_location; 2326 if (cap == 0) { 2327 if (width == 2) 2328 return (0xffff); 2329 return (0xffffffff); 2330 } 2331 2332 return (pci_read_config(dev, cap + reg, width)); 2333 } 2334 2335 void 2336 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2337 { 2338 struct pci_devinfo *dinfo = device_get_ivars(dev); 2339 int cap; 2340 2341 cap = dinfo->cfg.pcie.pcie_location; 2342 if (cap == 0) 2343 return; 2344 pci_write_config(dev, cap + reg, value, width); 2345 } 2346 2347 /* 2348 * Adjusts a PCI-e capability register by clearing the bits in mask 2349 * and setting the bits in (value & mask). Bits not set in mask are 2350 * not adjusted. 2351 * 2352 * Returns the old value on success or all ones on failure. 2353 */ 2354 uint32_t 2355 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2356 int width) 2357 { 2358 struct pci_devinfo *dinfo = device_get_ivars(dev); 2359 uint32_t old, new; 2360 int cap; 2361 2362 cap = dinfo->cfg.pcie.pcie_location; 2363 if (cap == 0) { 2364 if (width == 2) 2365 return (0xffff); 2366 return (0xffffffff); 2367 } 2368 2369 old = pci_read_config(dev, cap + reg, width); 2370 new = old & ~mask; 2371 new |= (value & mask); 2372 pci_write_config(dev, cap + reg, new, width); 2373 return (old); 2374 } 2375 2376 /* 2377 * Support for MSI message signalled interrupts. 2378 */ 2379 void 2380 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2381 uint16_t data) 2382 { 2383 struct pci_devinfo *dinfo = device_get_ivars(child); 2384 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2385 2386 /* Write data and address values. */ 2387 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2388 address & 0xffffffff, 4); 2389 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2390 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2391 address >> 32, 4); 2392 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2393 data, 2); 2394 } else 2395 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2396 2); 2397 2398 /* Enable MSI in the control register. */ 2399 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2400 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2401 msi->msi_ctrl, 2); 2402 2403 /* Enable MSI -> HT mapping. */ 2404 pci_ht_map_msi(child, address); 2405 } 2406 2407 void 2408 pci_disable_msi_method(device_t dev, device_t child) 2409 { 2410 struct pci_devinfo *dinfo = device_get_ivars(child); 2411 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2412 2413 /* Disable MSI -> HT mapping. */ 2414 pci_ht_map_msi(child, 0); 2415 2416 /* Disable MSI in the control register. */ 2417 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2418 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2419 msi->msi_ctrl, 2); 2420 } 2421 2422 /* 2423 * Restore MSI registers during resume. If MSI is enabled then 2424 * restore the data and address registers in addition to the control 2425 * register. 2426 */ 2427 static void 2428 pci_resume_msi(device_t dev) 2429 { 2430 struct pci_devinfo *dinfo = device_get_ivars(dev); 2431 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2432 uint64_t address; 2433 uint16_t data; 2434 2435 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2436 address = msi->msi_addr; 2437 data = msi->msi_data; 2438 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2439 address & 0xffffffff, 4); 2440 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2441 pci_write_config(dev, msi->msi_location + 2442 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2443 pci_write_config(dev, msi->msi_location + 2444 PCIR_MSI_DATA_64BIT, data, 2); 2445 } else 2446 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2447 data, 2); 2448 } 2449 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2450 2); 2451 } 2452 2453 static int 2454 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2455 { 2456 struct pci_devinfo *dinfo = device_get_ivars(dev); 2457 pcicfgregs *cfg = &dinfo->cfg; 2458 struct resource_list_entry *rle; 2459 struct msix_table_entry *mte; 2460 struct msix_vector *mv; 2461 uint64_t addr; 2462 uint32_t data; 2463 u_int i, j; 2464 int error; 2465 2466 /* 2467 * Handle MSI first. We try to find this IRQ among our list 2468 * of MSI IRQs. If we find it, we request updated address and 2469 * data registers and apply the results. 2470 */ 2471 if (cfg->msi.msi_alloc > 0) { 2472 /* If we don't have any active handlers, nothing to do. */ 2473 if (cfg->msi.msi_handlers == 0) 2474 return (0); 2475 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2476 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2477 i + 1); 2478 if (rle->start == irq) { 2479 error = PCIB_MAP_MSI(device_get_parent(bus), 2480 dev, irq, &addr, &data); 2481 if (error) 2482 return (error); 2483 pci_disable_msi(dev); 2484 dinfo->cfg.msi.msi_addr = addr; 2485 dinfo->cfg.msi.msi_data = data; 2486 pci_enable_msi(dev, addr, data); 2487 return (0); 2488 } 2489 } 2490 return (ENOENT); 2491 } 2492 2493 /* 2494 * For MSI-X, we check to see if we have this IRQ. If we do, 2495 * we request the updated mapping info. If that works, we go 2496 * through all the slots that use this IRQ and update them. 2497 */ 2498 if (cfg->msix.msix_alloc > 0) { 2499 bool found = false; 2500 2501 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2502 mv = &cfg->msix.msix_vectors[i]; 2503 if (mv->mv_irq == irq) { 2504 error = PCIB_MAP_MSI(device_get_parent(bus), 2505 dev, irq, &addr, &data); 2506 if (error) 2507 return (error); 2508 mv->mv_address = addr; 2509 mv->mv_data = data; 2510 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2511 mte = &cfg->msix.msix_table[j]; 2512 if (mte->mte_vector != i + 1) 2513 continue; 2514 if (mte->mte_handlers == 0) 2515 continue; 2516 pci_mask_msix(dev, j); 2517 pci_enable_msix(dev, j, addr, data); 2518 pci_unmask_msix(dev, j); 2519 } 2520 found = true; 2521 } 2522 } 2523 return (found ? 0 : ENOENT); 2524 } 2525 2526 return (ENOENT); 2527 } 2528 2529 /* 2530 * Returns true if the specified device is blacklisted because MSI 2531 * doesn't work. 2532 */ 2533 int 2534 pci_msi_device_blacklisted(device_t dev) 2535 { 2536 2537 if (!pci_honor_msi_blacklist) 2538 return (0); 2539 2540 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2541 } 2542 2543 /* 2544 * Determine if MSI is blacklisted globally on this system. Currently, 2545 * we just check for blacklisted chipsets as represented by the 2546 * host-PCI bridge at device 0:0:0. In the future, it may become 2547 * necessary to check other system attributes, such as the kenv values 2548 * that give the motherboard manufacturer and model number. 2549 */ 2550 static int 2551 pci_msi_blacklisted(void) 2552 { 2553 device_t dev; 2554 2555 if (!pci_honor_msi_blacklist) 2556 return (0); 2557 2558 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2559 if (!(pcie_chipset || pcix_chipset)) { 2560 if (vm_guest != VM_GUEST_NO) { 2561 /* 2562 * Whitelist older chipsets in virtual 2563 * machines known to support MSI. 2564 */ 2565 dev = pci_find_bsf(0, 0, 0); 2566 if (dev != NULL) 2567 return (!pci_has_quirk(pci_get_devid(dev), 2568 PCI_QUIRK_ENABLE_MSI_VM)); 2569 } 2570 return (1); 2571 } 2572 2573 dev = pci_find_bsf(0, 0, 0); 2574 if (dev != NULL) 2575 return (pci_msi_device_blacklisted(dev)); 2576 return (0); 2577 } 2578 2579 /* 2580 * Returns true if the specified device is blacklisted because MSI-X 2581 * doesn't work. Note that this assumes that if MSI doesn't work, 2582 * MSI-X doesn't either. 2583 */ 2584 int 2585 pci_msix_device_blacklisted(device_t dev) 2586 { 2587 2588 if (!pci_honor_msi_blacklist) 2589 return (0); 2590 2591 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2592 return (1); 2593 2594 return (pci_msi_device_blacklisted(dev)); 2595 } 2596 2597 /* 2598 * Determine if MSI-X is blacklisted globally on this system. If MSI 2599 * is blacklisted, assume that MSI-X is as well. Check for additional 2600 * chipsets where MSI works but MSI-X does not. 2601 */ 2602 static int 2603 pci_msix_blacklisted(void) 2604 { 2605 device_t dev; 2606 2607 if (!pci_honor_msi_blacklist) 2608 return (0); 2609 2610 dev = pci_find_bsf(0, 0, 0); 2611 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2612 PCI_QUIRK_DISABLE_MSIX)) 2613 return (1); 2614 2615 return (pci_msi_blacklisted()); 2616 } 2617 2618 /* 2619 * Attempt to allocate *count MSI messages. The actual number allocated is 2620 * returned in *count. After this function returns, each message will be 2621 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2622 */ 2623 int 2624 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2625 { 2626 struct pci_devinfo *dinfo = device_get_ivars(child); 2627 pcicfgregs *cfg = &dinfo->cfg; 2628 struct resource_list_entry *rle; 2629 u_int actual, i; 2630 int error, irqs[32]; 2631 uint16_t ctrl, msgnum; 2632 2633 /* Don't let count == 0 get us into trouble. */ 2634 if (*count < 1) 2635 return (EINVAL); 2636 2637 /* If rid 0 is allocated, then fail. */ 2638 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2639 if (rle != NULL && rle->res != NULL) 2640 return (ENXIO); 2641 2642 /* Already have allocated messages? */ 2643 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2644 return (ENXIO); 2645 2646 /* If MSI is blacklisted for this system, fail. */ 2647 if (pci_msi_blacklisted()) 2648 return (ENXIO); 2649 2650 /* MSI capability present? */ 2651 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2652 return (ENODEV); 2653 2654 ctrl = pci_read_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 2); 2655 msgnum = PCI_MSI_MSGNUM(ctrl); 2656 if (bootverbose) 2657 device_printf(child, 2658 "attempting to allocate %d MSI vectors (%u supported)\n", 2659 *count, msgnum); 2660 2661 /* Don't ask for more than the device supports. */ 2662 actual = min(*count, msgnum); 2663 2664 /* Don't ask for more than 32 messages. */ 2665 actual = min(actual, 32); 2666 2667 /* MSI requires power of 2 number of messages. */ 2668 if (!powerof2(actual)) 2669 return (EINVAL); 2670 2671 for (;;) { 2672 /* Try to allocate N messages. */ 2673 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2674 actual, irqs); 2675 if (error == 0) 2676 break; 2677 if (actual == 1) 2678 return (error); 2679 2680 /* Try N / 2. */ 2681 actual >>= 1; 2682 } 2683 2684 /* 2685 * We now have N actual messages mapped onto SYS_RES_IRQ 2686 * resources in the irqs[] array, so add new resources 2687 * starting at rid 1. 2688 */ 2689 for (i = 0; i < actual; i++) 2690 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2691 irqs[i], irqs[i], 1); 2692 2693 if (bootverbose) { 2694 if (actual == 1) 2695 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2696 else { 2697 bool run; 2698 2699 /* 2700 * Be fancy and try to print contiguous runs 2701 * of IRQ values as ranges. 'run' is true if 2702 * we are in a range. 2703 */ 2704 device_printf(child, "using IRQs %d", irqs[0]); 2705 run = false; 2706 for (i = 1; i < actual; i++) { 2707 /* Still in a run? */ 2708 if (irqs[i] == irqs[i - 1] + 1) { 2709 run = true; 2710 continue; 2711 } 2712 2713 /* Finish previous range. */ 2714 if (run) { 2715 printf("-%d", irqs[i - 1]); 2716 run = false; 2717 } 2718 2719 /* Start new range. */ 2720 printf(",%d", irqs[i]); 2721 } 2722 2723 /* Unfinished range? */ 2724 if (run) 2725 printf("-%d", irqs[actual - 1]); 2726 printf(" for MSI\n"); 2727 } 2728 } 2729 2730 /* Update control register with actual count. */ 2731 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2732 ctrl |= (ffs(actual) - 1) << 4; 2733 cfg->msi.msi_ctrl = ctrl; 2734 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2735 2736 /* Update counts of alloc'd messages. */ 2737 cfg->msi.msi_alloc = actual; 2738 cfg->msi.msi_handlers = 0; 2739 *count = actual; 2740 return (0); 2741 } 2742 2743 /* Release the MSI messages associated with this device. */ 2744 int 2745 pci_release_msi_method(device_t dev, device_t child) 2746 { 2747 struct pci_devinfo *dinfo = device_get_ivars(child); 2748 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2749 struct resource_list_entry *rle; 2750 u_int i, irqs[32]; 2751 int error; 2752 2753 /* Try MSI-X first. */ 2754 error = pci_release_msix(dev, child); 2755 if (error != ENODEV) 2756 return (error); 2757 2758 /* Do we have any messages to release? */ 2759 if (msi->msi_alloc == 0) 2760 return (ENODEV); 2761 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2762 2763 /* Make sure none of the resources are allocated. */ 2764 if (msi->msi_handlers > 0) 2765 return (EBUSY); 2766 for (i = 0; i < msi->msi_alloc; i++) { 2767 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2768 KASSERT(rle != NULL, ("missing MSI resource")); 2769 if (rle->res != NULL) 2770 return (EBUSY); 2771 irqs[i] = rle->start; 2772 } 2773 2774 /* Update control register with 0 count. */ 2775 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2776 ("%s: MSI still enabled", __func__)); 2777 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2778 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2779 msi->msi_ctrl, 2); 2780 2781 /* Release the messages. */ 2782 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2783 for (i = 0; i < msi->msi_alloc; i++) 2784 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2785 2786 /* Update alloc count. */ 2787 msi->msi_alloc = 0; 2788 msi->msi_addr = 0; 2789 msi->msi_data = 0; 2790 return (0); 2791 } 2792 2793 /* 2794 * Return the max supported MSI messages this device supports. 2795 * Basically, assuming the MD code can alloc messages, this function 2796 * should return the maximum value that pci_alloc_msi() can return. 2797 * Thus, it is subject to the tunables, etc. 2798 */ 2799 int 2800 pci_msi_count_method(device_t dev, device_t child) 2801 { 2802 struct pci_devinfo *dinfo = device_get_ivars(child); 2803 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2804 uint16_t ctrl; 2805 2806 if (pci_do_msi && msi->msi_location != 0) { 2807 ctrl = pci_read_config(child, msi->msi_location + PCIR_MSI_CTRL, 2808 2); 2809 return (PCI_MSI_MSGNUM(ctrl)); 2810 } 2811 return (0); 2812 } 2813 2814 /* free pcicfgregs structure and all depending data structures */ 2815 2816 int 2817 pci_freecfg(struct pci_devinfo *dinfo) 2818 { 2819 struct devlist *devlist_head; 2820 struct pci_map *pm, *next; 2821 2822 devlist_head = &pci_devq; 2823 2824 if (dinfo->cfg.vpd.vpd_reg) 2825 vpd_free(&dinfo->cfg.vpd); 2826 2827 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2828 free(pm, M_DEVBUF); 2829 } 2830 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2831 free(dinfo, M_DEVBUF); 2832 2833 /* increment the generation count */ 2834 pci_generation++; 2835 2836 /* we're losing one device */ 2837 pci_numdevs--; 2838 return (0); 2839 } 2840 2841 /* 2842 * PCI power manangement 2843 */ 2844 int 2845 pci_set_powerstate_method(device_t dev, device_t child, int state) 2846 { 2847 struct pci_devinfo *dinfo = device_get_ivars(child); 2848 pcicfgregs *cfg = &dinfo->cfg; 2849 uint16_t status; 2850 int oldstate, highest, delay; 2851 2852 if (cfg->pp.pp_location == 0) 2853 return (EOPNOTSUPP); 2854 2855 /* 2856 * Optimize a no state change request away. While it would be OK to 2857 * write to the hardware in theory, some devices have shown odd 2858 * behavior when going from D3 -> D3. 2859 */ 2860 oldstate = pci_get_powerstate(child); 2861 if (oldstate == state) 2862 return (0); 2863 2864 /* 2865 * The PCI power management specification states that after a state 2866 * transition between PCI power states, system software must 2867 * guarantee a minimal delay before the function accesses the device. 2868 * Compute the worst case delay that we need to guarantee before we 2869 * access the device. Many devices will be responsive much more 2870 * quickly than this delay, but there are some that don't respond 2871 * instantly to state changes. Transitions to/from D3 state require 2872 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2873 * is done below with DELAY rather than a sleeper function because 2874 * this function can be called from contexts where we cannot sleep. 2875 */ 2876 highest = (oldstate > state) ? oldstate : state; 2877 if (highest == PCI_POWERSTATE_D3) 2878 delay = 10000; 2879 else if (highest == PCI_POWERSTATE_D2) 2880 delay = 200; 2881 else 2882 delay = 0; 2883 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + 2884 PCIR_POWER_STATUS, 2) & ~PCIM_PSTAT_DMASK; 2885 switch (state) { 2886 case PCI_POWERSTATE_D0: 2887 status |= PCIM_PSTAT_D0; 2888 break; 2889 case PCI_POWERSTATE_D1: 2890 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2891 return (EOPNOTSUPP); 2892 status |= PCIM_PSTAT_D1; 2893 break; 2894 case PCI_POWERSTATE_D2: 2895 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2896 return (EOPNOTSUPP); 2897 status |= PCIM_PSTAT_D2; 2898 break; 2899 case PCI_POWERSTATE_D3: 2900 status |= PCIM_PSTAT_D3; 2901 break; 2902 default: 2903 return (EINVAL); 2904 } 2905 2906 if (bootverbose) 2907 pci_printf(cfg, "Transition from %s to %s\n", 2908 pci_powerstate_to_str(oldstate), 2909 pci_powerstate_to_str(state)); 2910 2911 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_location + PCIR_POWER_STATUS, 2912 status, 2); 2913 if (delay) 2914 DELAY(delay); 2915 return (0); 2916 } 2917 2918 int 2919 pci_get_powerstate_method(device_t dev, device_t child) 2920 { 2921 struct pci_devinfo *dinfo = device_get_ivars(child); 2922 pcicfgregs *cfg = &dinfo->cfg; 2923 uint16_t status; 2924 int result; 2925 2926 if (cfg->pp.pp_location != 0) { 2927 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + 2928 PCIR_POWER_STATUS, 2); 2929 switch (status & PCIM_PSTAT_DMASK) { 2930 case PCIM_PSTAT_D0: 2931 result = PCI_POWERSTATE_D0; 2932 break; 2933 case PCIM_PSTAT_D1: 2934 result = PCI_POWERSTATE_D1; 2935 break; 2936 case PCIM_PSTAT_D2: 2937 result = PCI_POWERSTATE_D2; 2938 break; 2939 case PCIM_PSTAT_D3: 2940 result = PCI_POWERSTATE_D3; 2941 break; 2942 default: 2943 result = PCI_POWERSTATE_UNKNOWN; 2944 break; 2945 } 2946 } else { 2947 /* No support, device is always at D0 */ 2948 result = PCI_POWERSTATE_D0; 2949 } 2950 return (result); 2951 } 2952 2953 /* Clear any active PME# and disable PME# generation. */ 2954 void 2955 pci_clear_pme(device_t dev) 2956 { 2957 struct pci_devinfo *dinfo = device_get_ivars(dev); 2958 pcicfgregs *cfg = &dinfo->cfg; 2959 uint16_t status; 2960 2961 if (cfg->pp.pp_location != 0) { 2962 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + 2963 PCIR_POWER_STATUS, 2); 2964 status &= ~PCIM_PSTAT_PMEENABLE; 2965 status |= PCIM_PSTAT_PME; 2966 pci_write_config(dev, dinfo->cfg.pp.pp_location + 2967 PCIR_POWER_STATUS, status, 2); 2968 } 2969 } 2970 2971 /* Clear any active PME# and enable PME# generation. */ 2972 void 2973 pci_enable_pme(device_t dev) 2974 { 2975 struct pci_devinfo *dinfo = device_get_ivars(dev); 2976 pcicfgregs *cfg = &dinfo->cfg; 2977 uint16_t status; 2978 2979 if (cfg->pp.pp_location != 0) { 2980 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + 2981 PCIR_POWER_STATUS, 2); 2982 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2983 pci_write_config(dev, dinfo->cfg.pp.pp_location + 2984 PCIR_POWER_STATUS, status, 2); 2985 } 2986 } 2987 2988 bool 2989 pci_has_pm(device_t dev) 2990 { 2991 struct pci_devinfo *dinfo = device_get_ivars(dev); 2992 pcicfgregs *cfg = &dinfo->cfg; 2993 2994 return (cfg->pp.pp_location != 0); 2995 } 2996 2997 /* 2998 * Some convenience functions for PCI device drivers. 2999 */ 3000 3001 static __inline void 3002 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 3003 { 3004 uint16_t command; 3005 3006 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 3007 command |= bit; 3008 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 3009 } 3010 3011 static __inline void 3012 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 3013 { 3014 uint16_t command; 3015 3016 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 3017 command &= ~bit; 3018 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 3019 } 3020 3021 int 3022 pci_enable_busmaster_method(device_t dev, device_t child) 3023 { 3024 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 3025 return (0); 3026 } 3027 3028 int 3029 pci_disable_busmaster_method(device_t dev, device_t child) 3030 { 3031 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 3032 return (0); 3033 } 3034 3035 int 3036 pci_enable_io_method(device_t dev, device_t child, int space) 3037 { 3038 uint16_t bit; 3039 3040 switch(space) { 3041 case SYS_RES_IOPORT: 3042 bit = PCIM_CMD_PORTEN; 3043 break; 3044 case SYS_RES_MEMORY: 3045 bit = PCIM_CMD_MEMEN; 3046 break; 3047 default: 3048 return (EINVAL); 3049 } 3050 pci_set_command_bit(dev, child, bit); 3051 return (0); 3052 } 3053 3054 int 3055 pci_disable_io_method(device_t dev, device_t child, int space) 3056 { 3057 uint16_t bit; 3058 3059 switch(space) { 3060 case SYS_RES_IOPORT: 3061 bit = PCIM_CMD_PORTEN; 3062 break; 3063 case SYS_RES_MEMORY: 3064 bit = PCIM_CMD_MEMEN; 3065 break; 3066 default: 3067 return (EINVAL); 3068 } 3069 pci_clear_command_bit(dev, child, bit); 3070 return (0); 3071 } 3072 3073 /* 3074 * New style pci driver. Parent device is either a pci-host-bridge or a 3075 * pci-pci-bridge. Both kinds are represented by instances of pcib. 3076 */ 3077 3078 void 3079 pci_print_verbose(struct pci_devinfo *dinfo) 3080 { 3081 3082 if (bootverbose) { 3083 pcicfgregs *cfg = &dinfo->cfg; 3084 3085 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 3086 cfg->vendor, cfg->device, cfg->revid); 3087 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 3088 cfg->domain, cfg->bus, cfg->slot, cfg->func); 3089 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 3090 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 3091 cfg->mfdev); 3092 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 3093 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 3094 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 3095 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 3096 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 3097 if (cfg->intpin > 0) 3098 printf("\tintpin=%c, irq=%d\n", 3099 cfg->intpin +'a' -1, cfg->intline); 3100 if (cfg->pp.pp_location) { 3101 uint16_t status; 3102 3103 status = pci_read_config(cfg->dev, cfg->pp.pp_location + 3104 PCIR_POWER_STATUS, 2); 3105 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 3106 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 3107 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 3108 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 3109 status & PCIM_PSTAT_DMASK); 3110 } 3111 if (cfg->msi.msi_location) { 3112 uint16_t ctrl, msgnum; 3113 3114 ctrl = cfg->msi.msi_ctrl; 3115 msgnum = PCI_MSI_MSGNUM(ctrl); 3116 printf("\tMSI supports %d message%s%s%s\n", 3117 msgnum, (msgnum == 1) ? "" : "s", 3118 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 3119 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 3120 } 3121 if (cfg->msix.msix_location) { 3122 uint16_t msgnum; 3123 3124 msgnum = PCI_MSIX_MSGNUM(cfg->msix.msix_ctrl); 3125 printf("\tMSI-X supports %d message%s ", 3126 msgnum, (msgnum == 1) ? "" : "s"); 3127 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 3128 printf("in map 0x%x\n", 3129 cfg->msix.msix_table_bar); 3130 else 3131 printf("in maps 0x%x and 0x%x\n", 3132 cfg->msix.msix_table_bar, 3133 cfg->msix.msix_pba_bar); 3134 } 3135 } 3136 } 3137 3138 static int 3139 pci_porten(device_t dev) 3140 { 3141 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 3142 } 3143 3144 static int 3145 pci_memen(device_t dev) 3146 { 3147 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 3148 } 3149 3150 void 3151 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 3152 int *bar64) 3153 { 3154 struct pci_devinfo *dinfo; 3155 pci_addr_t map, testval; 3156 int ln2range; 3157 uint16_t cmd; 3158 3159 /* 3160 * The device ROM BAR is special. It is always a 32-bit 3161 * memory BAR. Bit 0 is special and should not be set when 3162 * sizing the BAR. 3163 */ 3164 dinfo = device_get_ivars(dev); 3165 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3166 map = pci_read_config(dev, reg, 4); 3167 pci_write_config(dev, reg, 0xfffffffe, 4); 3168 testval = pci_read_config(dev, reg, 4); 3169 pci_write_config(dev, reg, map, 4); 3170 *mapp = map; 3171 *testvalp = testval; 3172 if (bar64 != NULL) 3173 *bar64 = 0; 3174 return; 3175 } 3176 3177 map = pci_read_config(dev, reg, 4); 3178 ln2range = pci_maprange(map); 3179 if (ln2range == 64) 3180 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3181 3182 /* 3183 * Disable decoding via the command register before 3184 * determining the BAR's length since we will be placing it in 3185 * a weird state. 3186 */ 3187 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3188 pci_write_config(dev, PCIR_COMMAND, 3189 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3190 3191 /* 3192 * Determine the BAR's length by writing all 1's. The bottom 3193 * log_2(size) bits of the BAR will stick as 0 when we read 3194 * the value back. 3195 * 3196 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3197 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3198 * and combines the result into a 64-bit value." (section 6.2.5.1) 3199 * 3200 * Writes to both registers must be performed before attempting to 3201 * read back the size value. 3202 */ 3203 testval = 0; 3204 pci_write_config(dev, reg, 0xffffffff, 4); 3205 if (ln2range == 64) { 3206 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3207 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3208 } 3209 testval |= pci_read_config(dev, reg, 4); 3210 3211 /* 3212 * Restore the original value of the BAR. We may have reprogrammed 3213 * the BAR of the low-level console device and when booting verbose, 3214 * we need the console device addressable. 3215 */ 3216 pci_write_config(dev, reg, map, 4); 3217 if (ln2range == 64) 3218 pci_write_config(dev, reg + 4, map >> 32, 4); 3219 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3220 3221 *mapp = map; 3222 *testvalp = testval; 3223 if (bar64 != NULL) 3224 *bar64 = (ln2range == 64); 3225 } 3226 3227 static void 3228 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3229 { 3230 struct pci_devinfo *dinfo; 3231 int ln2range; 3232 3233 /* The device ROM BAR is always a 32-bit memory BAR. */ 3234 dinfo = device_get_ivars(dev); 3235 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3236 ln2range = 32; 3237 else 3238 ln2range = pci_maprange(pm->pm_value); 3239 pci_write_config(dev, pm->pm_reg, base, 4); 3240 if (ln2range == 64) 3241 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3242 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3243 if (ln2range == 64) 3244 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3245 pm->pm_reg + 4, 4) << 32; 3246 } 3247 3248 struct pci_map * 3249 pci_find_bar(device_t dev, int reg) 3250 { 3251 struct pci_devinfo *dinfo; 3252 struct pci_map *pm; 3253 3254 dinfo = device_get_ivars(dev); 3255 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3256 if (pm->pm_reg == reg) 3257 return (pm); 3258 } 3259 return (NULL); 3260 } 3261 3262 struct pci_map * 3263 pci_first_bar(device_t dev) 3264 { 3265 struct pci_devinfo *dinfo; 3266 3267 dinfo = device_get_ivars(dev); 3268 return (STAILQ_FIRST(&dinfo->cfg.maps)); 3269 } 3270 3271 struct pci_map * 3272 pci_next_bar(struct pci_map *pm) 3273 { 3274 return (STAILQ_NEXT(pm, pm_link)); 3275 } 3276 3277 int 3278 pci_bar_enabled(device_t dev, struct pci_map *pm) 3279 { 3280 struct pci_devinfo *dinfo; 3281 uint16_t cmd; 3282 3283 dinfo = device_get_ivars(dev); 3284 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3285 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3286 return (0); 3287 #ifdef PCI_IOV 3288 if ((dinfo->cfg.flags & PCICFG_VF) != 0) { 3289 struct pcicfg_iov *iov; 3290 3291 iov = dinfo->cfg.iov; 3292 cmd = pci_read_config(iov->iov_pf, 3293 iov->iov_pos + PCIR_SRIOV_CTL, 2); 3294 return ((cmd & PCIM_SRIOV_VF_MSE) != 0); 3295 } 3296 #endif 3297 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3298 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3299 return ((cmd & PCIM_CMD_MEMEN) != 0); 3300 else 3301 return ((cmd & PCIM_CMD_PORTEN) != 0); 3302 } 3303 3304 struct pci_map * 3305 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3306 { 3307 struct pci_devinfo *dinfo; 3308 struct pci_map *pm, *prev; 3309 3310 dinfo = device_get_ivars(dev); 3311 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3312 pm->pm_reg = reg; 3313 pm->pm_value = value; 3314 pm->pm_size = size; 3315 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3316 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3317 reg)); 3318 if (STAILQ_NEXT(prev, pm_link) == NULL || 3319 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3320 break; 3321 } 3322 if (prev != NULL) 3323 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3324 else 3325 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3326 return (pm); 3327 } 3328 3329 static void 3330 pci_restore_bars(device_t dev) 3331 { 3332 struct pci_devinfo *dinfo; 3333 struct pci_map *pm; 3334 int ln2range; 3335 3336 dinfo = device_get_ivars(dev); 3337 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3338 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3339 ln2range = 32; 3340 else 3341 ln2range = pci_maprange(pm->pm_value); 3342 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3343 if (ln2range == 64) 3344 pci_write_config(dev, pm->pm_reg + 4, 3345 pm->pm_value >> 32, 4); 3346 } 3347 } 3348 3349 /* 3350 * Add a resource based on a pci map register. Return 1 if the map 3351 * register is a 32bit map register or 2 if it is a 64bit register. 3352 */ 3353 static int 3354 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3355 int force, int prefetch) 3356 { 3357 struct pci_map *pm; 3358 pci_addr_t base, map, testval; 3359 pci_addr_t start, end, count; 3360 int barlen, basezero, flags, maprange, mapsize, type; 3361 uint16_t cmd; 3362 struct resource *res; 3363 3364 /* 3365 * The BAR may already exist if the device is a CardBus card 3366 * whose CIS is stored in this BAR. 3367 */ 3368 pm = pci_find_bar(dev, reg); 3369 if (pm != NULL) { 3370 maprange = pci_maprange(pm->pm_value); 3371 barlen = maprange == 64 ? 2 : 1; 3372 return (barlen); 3373 } 3374 3375 pci_read_bar(dev, reg, &map, &testval, NULL); 3376 if (PCI_BAR_MEM(map)) { 3377 type = SYS_RES_MEMORY; 3378 if (map & PCIM_BAR_MEM_PREFETCH) 3379 prefetch = 1; 3380 } else 3381 type = SYS_RES_IOPORT; 3382 mapsize = pci_mapsize(testval); 3383 base = pci_mapbase(map); 3384 #ifdef __PCI_BAR_ZERO_VALID 3385 basezero = 0; 3386 #else 3387 basezero = base == 0; 3388 #endif 3389 maprange = pci_maprange(map); 3390 barlen = maprange == 64 ? 2 : 1; 3391 3392 /* 3393 * For I/O registers, if bottom bit is set, and the next bit up 3394 * isn't clear, we know we have a BAR that doesn't conform to the 3395 * spec, so ignore it. Also, sanity check the size of the data 3396 * areas to the type of memory involved. Memory must be at least 3397 * 16 bytes in size, while I/O ranges must be at least 4. 3398 */ 3399 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3400 return (barlen); 3401 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3402 (type == SYS_RES_IOPORT && mapsize < 2)) 3403 return (barlen); 3404 3405 /* Save a record of this BAR. */ 3406 pm = pci_add_bar(dev, reg, map, mapsize); 3407 if (bootverbose) { 3408 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3409 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3410 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3411 printf(", port disabled\n"); 3412 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3413 printf(", memory disabled\n"); 3414 else 3415 printf(", enabled\n"); 3416 } 3417 3418 /* 3419 * If base is 0, then we have problems if this architecture does 3420 * not allow that. It is best to ignore such entries for the 3421 * moment. These will be allocated later if the driver specifically 3422 * requests them. However, some removable buses look better when 3423 * all resources are allocated, so allow '0' to be overridden. 3424 * 3425 * Similarly treat maps whose values is the same as the test value 3426 * read back. These maps have had all f's written to them by the 3427 * BIOS in an attempt to disable the resources. 3428 */ 3429 if (!force && (basezero || map == testval)) 3430 return (barlen); 3431 if ((u_long)base != base) { 3432 device_printf(bus, 3433 "pci%d:%d:%d:%d bar %#x too many address bits", 3434 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3435 pci_get_function(dev), reg); 3436 return (barlen); 3437 } 3438 3439 /* 3440 * This code theoretically does the right thing, but has 3441 * undesirable side effects in some cases where peripherals 3442 * respond oddly to having these bits enabled. Let the user 3443 * be able to turn them off (since pci_enable_io_modes is 1 by 3444 * default). 3445 */ 3446 if (pci_enable_io_modes) { 3447 /* Turn on resources that have been left off by a lazy BIOS */ 3448 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3449 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3450 cmd |= PCIM_CMD_PORTEN; 3451 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3452 } 3453 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3454 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3455 cmd |= PCIM_CMD_MEMEN; 3456 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3457 } 3458 } else { 3459 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3460 return (barlen); 3461 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3462 return (barlen); 3463 } 3464 3465 count = (pci_addr_t)1 << mapsize; 3466 flags = RF_ALIGNMENT_LOG2(mapsize); 3467 if (prefetch) 3468 flags |= RF_PREFETCHABLE; 3469 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3470 start = 0; /* Let the parent decide. */ 3471 end = ~0; 3472 } else { 3473 start = base; 3474 end = base + count - 1; 3475 } 3476 resource_list_add(rl, type, reg, start, end, count); 3477 3478 /* 3479 * Try to allocate the resource for this BAR from our parent 3480 * so that this resource range is already reserved. The 3481 * driver for this device will later inherit this resource in 3482 * pci_alloc_resource(). 3483 */ 3484 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3485 flags); 3486 if ((pci_do_realloc_bars 3487 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3488 && res == NULL && (start != 0 || end != ~0)) { 3489 /* 3490 * If the allocation fails, try to allocate a resource for 3491 * this BAR using any available range. The firmware felt 3492 * it was important enough to assign a resource, so don't 3493 * disable decoding if we can help it. 3494 */ 3495 resource_list_delete(rl, type, reg); 3496 resource_list_add(rl, type, reg, 0, ~0, count); 3497 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3498 count, flags); 3499 } 3500 if (res == NULL) { 3501 /* 3502 * If the allocation fails, delete the resource list entry 3503 * and disable decoding for this device. 3504 * 3505 * If the driver requests this resource in the future, 3506 * pci_reserve_map() will try to allocate a fresh 3507 * resource range. 3508 */ 3509 resource_list_delete(rl, type, reg); 3510 pci_disable_io(dev, type); 3511 if (bootverbose) 3512 device_printf(bus, 3513 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3514 pci_get_domain(dev), pci_get_bus(dev), 3515 pci_get_slot(dev), pci_get_function(dev), reg); 3516 } else { 3517 start = rman_get_start(res); 3518 pci_write_bar(dev, pm, start); 3519 } 3520 return (barlen); 3521 } 3522 3523 /* 3524 * For ATA devices we need to decide early what addressing mode to use. 3525 * Legacy demands that the primary and secondary ATA ports sits on the 3526 * same addresses that old ISA hardware did. This dictates that we use 3527 * those addresses and ignore the BAR's if we cannot set PCI native 3528 * addressing mode. 3529 */ 3530 static void 3531 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3532 uint32_t prefetchmask) 3533 { 3534 int rid, type, progif; 3535 #if 0 3536 /* if this device supports PCI native addressing use it */ 3537 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3538 if ((progif & 0x8a) == 0x8a) { 3539 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3540 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3541 printf("Trying ATA native PCI addressing mode\n"); 3542 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3543 } 3544 } 3545 #endif 3546 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3547 type = SYS_RES_IOPORT; 3548 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3549 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3550 prefetchmask & (1 << 0)); 3551 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3552 prefetchmask & (1 << 1)); 3553 } else { 3554 rid = PCIR_BAR(0); 3555 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3556 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3557 0x1f7, 8, 0); 3558 rid = PCIR_BAR(1); 3559 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3560 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3561 0x3f6, 1, 0); 3562 } 3563 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3564 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3565 prefetchmask & (1 << 2)); 3566 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3567 prefetchmask & (1 << 3)); 3568 } else { 3569 rid = PCIR_BAR(2); 3570 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3571 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3572 0x177, 8, 0); 3573 rid = PCIR_BAR(3); 3574 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3575 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3576 0x376, 1, 0); 3577 } 3578 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3579 prefetchmask & (1 << 4)); 3580 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3581 prefetchmask & (1 << 5)); 3582 } 3583 3584 static void 3585 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3586 { 3587 struct pci_devinfo *dinfo = device_get_ivars(dev); 3588 pcicfgregs *cfg = &dinfo->cfg; 3589 char tunable_name[64]; 3590 int irq; 3591 3592 /* Has to have an intpin to have an interrupt. */ 3593 if (cfg->intpin == 0) 3594 return; 3595 3596 /* Let the user override the IRQ with a tunable. */ 3597 irq = PCI_INVALID_IRQ; 3598 snprintf(tunable_name, sizeof(tunable_name), 3599 "hw.pci%d.%d.%d.INT%c.irq", 3600 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3601 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3602 irq = PCI_INVALID_IRQ; 3603 3604 /* 3605 * If we didn't get an IRQ via the tunable, then we either use the 3606 * IRQ value in the intline register or we ask the bus to route an 3607 * interrupt for us. If force_route is true, then we only use the 3608 * value in the intline register if the bus was unable to assign an 3609 * IRQ. 3610 */ 3611 if (!PCI_INTERRUPT_VALID(irq)) { 3612 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3613 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3614 if (!PCI_INTERRUPT_VALID(irq)) 3615 irq = cfg->intline; 3616 } 3617 3618 /* If after all that we don't have an IRQ, just bail. */ 3619 if (!PCI_INTERRUPT_VALID(irq)) 3620 return; 3621 3622 /* Update the config register if it changed. */ 3623 if (irq != cfg->intline) { 3624 cfg->intline = irq; 3625 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3626 } 3627 3628 /* Add this IRQ as rid 0 interrupt resource. */ 3629 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3630 } 3631 3632 /* Perform early OHCI takeover from SMM. */ 3633 static void 3634 ohci_early_takeover(device_t self) 3635 { 3636 struct resource *res; 3637 uint32_t ctl; 3638 int rid; 3639 int i; 3640 3641 rid = PCIR_BAR(0); 3642 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3643 if (res == NULL) 3644 return; 3645 3646 ctl = bus_read_4(res, OHCI_CONTROL); 3647 if (ctl & OHCI_IR) { 3648 if (bootverbose) 3649 printf("ohci early: " 3650 "SMM active, request owner change\n"); 3651 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3652 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3653 DELAY(1000); 3654 ctl = bus_read_4(res, OHCI_CONTROL); 3655 } 3656 if (ctl & OHCI_IR) { 3657 if (bootverbose) 3658 printf("ohci early: " 3659 "SMM does not respond, resetting\n"); 3660 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3661 } 3662 /* Disable interrupts */ 3663 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3664 } 3665 3666 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3667 } 3668 3669 /* Perform early UHCI takeover from SMM. */ 3670 static void 3671 uhci_early_takeover(device_t self) 3672 { 3673 struct resource *res; 3674 int rid; 3675 3676 /* 3677 * Set the PIRQD enable bit and switch off all the others. We don't 3678 * want legacy support to interfere with us XXX Does this also mean 3679 * that the BIOS won't touch the keyboard anymore if it is connected 3680 * to the ports of the root hub? 3681 */ 3682 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3683 3684 /* Disable interrupts */ 3685 rid = PCI_UHCI_BASE_REG; 3686 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3687 if (res != NULL) { 3688 bus_write_2(res, UHCI_INTR, 0); 3689 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3690 } 3691 } 3692 3693 /* Perform early EHCI takeover from SMM. */ 3694 static void 3695 ehci_early_takeover(device_t self) 3696 { 3697 struct resource *res; 3698 uint32_t cparams; 3699 uint32_t eec; 3700 uint8_t eecp; 3701 uint8_t bios_sem; 3702 uint8_t offs; 3703 int rid; 3704 int i; 3705 3706 rid = PCIR_BAR(0); 3707 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3708 if (res == NULL) 3709 return; 3710 3711 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3712 3713 /* Synchronise with the BIOS if it owns the controller. */ 3714 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3715 eecp = EHCI_EECP_NEXT(eec)) { 3716 eec = pci_read_config(self, eecp, 4); 3717 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3718 continue; 3719 } 3720 bios_sem = pci_read_config(self, eecp + 3721 EHCI_LEGSUP_BIOS_SEM, 1); 3722 if (bios_sem == 0) { 3723 continue; 3724 } 3725 if (bootverbose) 3726 printf("ehci early: " 3727 "SMM active, request owner change\n"); 3728 3729 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3730 3731 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3732 DELAY(1000); 3733 bios_sem = pci_read_config(self, eecp + 3734 EHCI_LEGSUP_BIOS_SEM, 1); 3735 } 3736 3737 if (bios_sem != 0) { 3738 if (bootverbose) 3739 printf("ehci early: " 3740 "SMM does not respond\n"); 3741 } 3742 /* Disable interrupts */ 3743 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3744 bus_write_4(res, offs + EHCI_USBINTR, 0); 3745 } 3746 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3747 } 3748 3749 /* Perform early XHCI takeover from SMM. */ 3750 static void 3751 xhci_early_takeover(device_t self) 3752 { 3753 struct resource *res; 3754 uint32_t cparams; 3755 uint32_t eec; 3756 uint8_t eecp; 3757 uint8_t bios_sem; 3758 uint8_t offs; 3759 int rid; 3760 int i; 3761 3762 rid = PCIR_BAR(0); 3763 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3764 if (res == NULL) 3765 return; 3766 3767 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3768 3769 eec = -1; 3770 3771 /* Synchronise with the BIOS if it owns the controller. */ 3772 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3773 eecp += XHCI_XECP_NEXT(eec) << 2) { 3774 eec = bus_read_4(res, eecp); 3775 3776 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3777 continue; 3778 3779 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3780 if (bios_sem == 0) 3781 continue; 3782 3783 if (bootverbose) 3784 printf("xhci early: " 3785 "SMM active, request owner change\n"); 3786 3787 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3788 3789 /* wait a maximum of 5 second */ 3790 3791 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3792 DELAY(1000); 3793 bios_sem = bus_read_1(res, eecp + 3794 XHCI_XECP_BIOS_SEM); 3795 } 3796 3797 if (bios_sem != 0) { 3798 if (bootverbose) 3799 printf("xhci early: " 3800 "SMM does not respond\n"); 3801 } 3802 3803 /* Disable interrupts */ 3804 offs = bus_read_1(res, XHCI_CAPLENGTH); 3805 bus_write_4(res, offs + XHCI_USBCMD, 0); 3806 bus_read_4(res, offs + XHCI_USBSTS); 3807 } 3808 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3809 } 3810 3811 static void 3812 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3813 struct resource_list *rl) 3814 { 3815 struct resource *res; 3816 char *cp; 3817 rman_res_t start, end, count; 3818 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3819 3820 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3821 case PCIM_HDRTYPE_BRIDGE: 3822 sec_reg = PCIR_SECBUS_1; 3823 sub_reg = PCIR_SUBBUS_1; 3824 break; 3825 case PCIM_HDRTYPE_CARDBUS: 3826 sec_reg = PCIR_SECBUS_2; 3827 sub_reg = PCIR_SUBBUS_2; 3828 break; 3829 default: 3830 return; 3831 } 3832 3833 /* 3834 * If the existing bus range is valid, attempt to reserve it 3835 * from our parent. If this fails for any reason, clear the 3836 * secbus and subbus registers. 3837 * 3838 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3839 * This would at least preserve the existing sec_bus if it is 3840 * valid. 3841 */ 3842 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3843 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3844 3845 /* Quirk handling. */ 3846 switch (pci_get_devid(dev)) { 3847 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3848 sup_bus = pci_read_config(dev, 0x41, 1); 3849 if (sup_bus != 0xff) { 3850 sec_bus = sup_bus + 1; 3851 sub_bus = sup_bus + 1; 3852 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3853 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3854 } 3855 break; 3856 3857 case 0x00dd10de: 3858 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3859 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3860 break; 3861 if (strncmp(cp, "Compal", 6) != 0) { 3862 freeenv(cp); 3863 break; 3864 } 3865 freeenv(cp); 3866 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3867 break; 3868 if (strncmp(cp, "08A0", 4) != 0) { 3869 freeenv(cp); 3870 break; 3871 } 3872 freeenv(cp); 3873 if (sub_bus < 0xa) { 3874 sub_bus = 0xa; 3875 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3876 } 3877 break; 3878 } 3879 3880 if (bootverbose) 3881 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3882 if (sec_bus > 0 && sub_bus >= sec_bus) { 3883 start = sec_bus; 3884 end = sub_bus; 3885 count = end - start + 1; 3886 3887 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3888 3889 /* 3890 * If requested, clear secondary bus registers in 3891 * bridge devices to force a complete renumbering 3892 * rather than reserving the existing range. However, 3893 * preserve the existing size. 3894 */ 3895 if (pci_clear_buses) 3896 goto clear; 3897 3898 rid = 0; 3899 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3900 start, end, count, 0); 3901 if (res != NULL) 3902 return; 3903 3904 if (bootverbose) 3905 device_printf(bus, 3906 "pci%d:%d:%d:%d secbus failed to allocate\n", 3907 pci_get_domain(dev), pci_get_bus(dev), 3908 pci_get_slot(dev), pci_get_function(dev)); 3909 } 3910 3911 clear: 3912 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3913 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3914 } 3915 3916 static struct resource * 3917 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3918 rman_res_t end, rman_res_t count, u_int flags) 3919 { 3920 struct pci_devinfo *dinfo; 3921 pcicfgregs *cfg; 3922 struct resource_list *rl; 3923 struct resource *res; 3924 int sec_reg, sub_reg; 3925 3926 dinfo = device_get_ivars(child); 3927 cfg = &dinfo->cfg; 3928 rl = &dinfo->resources; 3929 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3930 case PCIM_HDRTYPE_BRIDGE: 3931 sec_reg = PCIR_SECBUS_1; 3932 sub_reg = PCIR_SUBBUS_1; 3933 break; 3934 case PCIM_HDRTYPE_CARDBUS: 3935 sec_reg = PCIR_SECBUS_2; 3936 sub_reg = PCIR_SUBBUS_2; 3937 break; 3938 default: 3939 return (NULL); 3940 } 3941 3942 if (*rid != 0) 3943 return (NULL); 3944 3945 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3946 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3947 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3948 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3949 start, end, count, flags & ~RF_ACTIVE); 3950 if (res == NULL) { 3951 resource_list_delete(rl, PCI_RES_BUS, *rid); 3952 device_printf(child, "allocating %ju bus%s failed\n", 3953 count, count == 1 ? "" : "es"); 3954 return (NULL); 3955 } 3956 if (bootverbose) 3957 device_printf(child, 3958 "Lazy allocation of %ju bus%s at %ju\n", count, 3959 count == 1 ? "" : "es", rman_get_start(res)); 3960 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3961 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3962 } 3963 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3964 end, count, flags)); 3965 } 3966 3967 static int 3968 pci_ea_bei_to_rid(device_t dev, int bei) 3969 { 3970 #ifdef PCI_IOV 3971 struct pci_devinfo *dinfo; 3972 int iov_pos; 3973 struct pcicfg_iov *iov; 3974 3975 dinfo = device_get_ivars(dev); 3976 iov = dinfo->cfg.iov; 3977 if (iov != NULL) 3978 iov_pos = iov->iov_pos; 3979 else 3980 iov_pos = 0; 3981 #endif 3982 3983 /* Check if matches BAR */ 3984 if ((bei >= PCIM_EA_BEI_BAR_0) && 3985 (bei <= PCIM_EA_BEI_BAR_5)) 3986 return (PCIR_BAR(bei)); 3987 3988 /* Check ROM */ 3989 if (bei == PCIM_EA_BEI_ROM) 3990 return (PCIR_BIOS); 3991 3992 #ifdef PCI_IOV 3993 /* Check if matches VF_BAR */ 3994 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3995 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3996 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3997 iov_pos); 3998 #endif 3999 4000 return (-1); 4001 } 4002 4003 int 4004 pci_ea_is_enabled(device_t dev, int rid) 4005 { 4006 struct pci_ea_entry *ea; 4007 struct pci_devinfo *dinfo; 4008 4009 dinfo = device_get_ivars(dev); 4010 4011 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 4012 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 4013 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 4014 } 4015 4016 return (0); 4017 } 4018 4019 void 4020 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 4021 { 4022 struct pci_ea_entry *ea; 4023 struct pci_devinfo *dinfo; 4024 pci_addr_t start, end, count; 4025 struct resource_list *rl; 4026 int type, flags, rid; 4027 struct resource *res; 4028 uint32_t tmp; 4029 #ifdef PCI_IOV 4030 struct pcicfg_iov *iov; 4031 #endif 4032 4033 dinfo = device_get_ivars(dev); 4034 rl = &dinfo->resources; 4035 flags = 0; 4036 4037 #ifdef PCI_IOV 4038 iov = dinfo->cfg.iov; 4039 #endif 4040 4041 if (dinfo->cfg.ea.ea_location == 0) 4042 return; 4043 4044 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 4045 /* 4046 * TODO: Ignore EA-BAR if is not enabled. 4047 * Currently the EA implementation supports 4048 * only situation, where EA structure contains 4049 * predefined entries. In case they are not enabled 4050 * leave them unallocated and proceed with 4051 * a legacy-BAR mechanism. 4052 */ 4053 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 4054 continue; 4055 4056 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 4057 case PCIM_EA_P_MEM_PREFETCH: 4058 case PCIM_EA_P_VF_MEM_PREFETCH: 4059 flags = RF_PREFETCHABLE; 4060 /* FALLTHROUGH */ 4061 case PCIM_EA_P_VF_MEM: 4062 case PCIM_EA_P_MEM: 4063 type = SYS_RES_MEMORY; 4064 break; 4065 case PCIM_EA_P_IO: 4066 type = SYS_RES_IOPORT; 4067 break; 4068 default: 4069 continue; 4070 } 4071 4072 if (alloc_iov != 0) { 4073 #ifdef PCI_IOV 4074 /* Allocating IOV, confirm BEI matches */ 4075 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 4076 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 4077 continue; 4078 #else 4079 continue; 4080 #endif 4081 } else { 4082 /* Allocating BAR, confirm BEI matches */ 4083 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 4084 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 4085 (ea->eae_bei != PCIM_EA_BEI_ROM)) 4086 continue; 4087 } 4088 4089 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 4090 if (rid < 0) 4091 continue; 4092 4093 /* Skip resources already allocated by EA */ 4094 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 4095 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 4096 continue; 4097 4098 start = ea->eae_base; 4099 count = ea->eae_max_offset + 1; 4100 #ifdef PCI_IOV 4101 if (iov != NULL) 4102 count = count * iov->iov_num_vfs; 4103 #endif 4104 end = start + count - 1; 4105 if (count == 0) 4106 continue; 4107 4108 resource_list_add(rl, type, rid, start, end, count); 4109 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 4110 flags); 4111 if (res == NULL) { 4112 resource_list_delete(rl, type, rid); 4113 4114 /* 4115 * Failed to allocate using EA, disable entry. 4116 * Another attempt to allocation will be performed 4117 * further, but this time using legacy BAR registers 4118 */ 4119 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 4120 tmp &= ~PCIM_EA_ENABLE; 4121 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 4122 4123 /* 4124 * Disabling entry might fail in case it is hardwired. 4125 * Read flags again to match current status. 4126 */ 4127 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 4128 4129 continue; 4130 } 4131 4132 /* As per specification, fill BAR with zeros */ 4133 pci_write_config(dev, rid, 0, 4); 4134 } 4135 } 4136 4137 void 4138 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 4139 { 4140 struct pci_devinfo *dinfo; 4141 pcicfgregs *cfg; 4142 struct resource_list *rl; 4143 const struct pci_quirk *q; 4144 uint32_t devid; 4145 int i; 4146 4147 dinfo = device_get_ivars(dev); 4148 cfg = &dinfo->cfg; 4149 rl = &dinfo->resources; 4150 devid = (cfg->device << 16) | cfg->vendor; 4151 4152 /* Allocate resources using Enhanced Allocation */ 4153 pci_add_resources_ea(bus, dev, 0); 4154 4155 /* ATA devices needs special map treatment */ 4156 if ((pci_get_class(dev) == PCIC_STORAGE) && 4157 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 4158 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 4159 (!pci_read_config(dev, PCIR_BAR(0), 4) && 4160 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 4161 pci_ata_maps(bus, dev, rl, force, prefetchmask); 4162 else 4163 for (i = 0; i < cfg->nummaps;) { 4164 /* Skip resources already managed by EA */ 4165 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 4166 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 4167 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 4168 i++; 4169 continue; 4170 } 4171 4172 /* 4173 * Skip quirked resources. 4174 */ 4175 for (q = &pci_quirks[0]; q->devid != 0; q++) 4176 if (q->devid == devid && 4177 q->type == PCI_QUIRK_UNMAP_REG && 4178 q->arg1 == PCIR_BAR(i)) 4179 break; 4180 if (q->devid != 0) { 4181 i++; 4182 continue; 4183 } 4184 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4185 prefetchmask & (1 << i)); 4186 } 4187 4188 /* 4189 * Add additional, quirked resources. 4190 */ 4191 for (q = &pci_quirks[0]; q->devid != 0; q++) 4192 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4193 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4194 4195 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline) && 4196 pci_intx_reroute) { 4197 /* 4198 * Try to re-route interrupts. Sometimes the BIOS or 4199 * firmware may leave bogus values in these registers. 4200 * If the re-route fails, then just stick with what we 4201 * have. 4202 */ 4203 pci_assign_interrupt(bus, dev, 1); 4204 } 4205 4206 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4207 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4208 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4209 xhci_early_takeover(dev); 4210 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4211 ehci_early_takeover(dev); 4212 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4213 ohci_early_takeover(dev); 4214 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4215 uhci_early_takeover(dev); 4216 } 4217 4218 /* 4219 * Reserve resources for secondary bus ranges behind bridge 4220 * devices. 4221 */ 4222 pci_reserve_secbus(bus, dev, cfg, rl); 4223 } 4224 4225 static struct pci_devinfo * 4226 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4227 int slot, int func) 4228 { 4229 struct pci_devinfo *dinfo; 4230 4231 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4232 if (dinfo != NULL) 4233 pci_add_child(dev, dinfo); 4234 4235 return (dinfo); 4236 } 4237 4238 void 4239 pci_add_children(device_t dev, int domain, int busno) 4240 { 4241 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4242 device_t pcib = device_get_parent(dev); 4243 struct pci_devinfo *dinfo; 4244 int maxslots; 4245 int s, f, pcifunchigh; 4246 uint8_t hdrtype; 4247 int first_func; 4248 4249 /* 4250 * Try to detect a device at slot 0, function 0. If it exists, try to 4251 * enable ARI. We must enable ARI before detecting the rest of the 4252 * functions on this bus as ARI changes the set of slots and functions 4253 * that are legal on this bus. 4254 */ 4255 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4256 if (dinfo != NULL && pci_enable_ari) 4257 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4258 4259 /* 4260 * Start looking for new devices on slot 0 at function 1 because we 4261 * just identified the device at slot 0, function 0. 4262 */ 4263 first_func = 1; 4264 4265 maxslots = PCIB_MAXSLOTS(pcib); 4266 for (s = 0; s <= maxslots; s++, first_func = 0) { 4267 pcifunchigh = 0; 4268 f = 0; 4269 DELAY(1); 4270 4271 /* If function 0 is not present, skip to the next slot. */ 4272 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4273 continue; 4274 hdrtype = REG(PCIR_HDRTYPE, 1); 4275 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4276 continue; 4277 if (hdrtype & PCIM_MFDEV) 4278 pcifunchigh = PCIB_MAXFUNCS(pcib); 4279 for (f = first_func; f <= pcifunchigh; f++) 4280 pci_identify_function(pcib, dev, domain, busno, s, f); 4281 } 4282 #undef REG 4283 } 4284 4285 int 4286 pci_rescan_method(device_t dev) 4287 { 4288 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4289 device_t pcib = device_get_parent(dev); 4290 device_t child, *devlist, *unchanged; 4291 int devcount, error, i, j, maxslots, oldcount; 4292 int busno, domain, s, f, pcifunchigh; 4293 uint8_t hdrtype; 4294 4295 /* No need to check for ARI on a rescan. */ 4296 error = device_get_children(dev, &devlist, &devcount); 4297 if (error) 4298 return (error); 4299 if (devcount != 0) { 4300 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4301 M_NOWAIT | M_ZERO); 4302 if (unchanged == NULL) { 4303 free(devlist, M_TEMP); 4304 return (ENOMEM); 4305 } 4306 } else 4307 unchanged = NULL; 4308 4309 domain = pcib_get_domain(dev); 4310 busno = pcib_get_bus(dev); 4311 maxslots = PCIB_MAXSLOTS(pcib); 4312 for (s = 0; s <= maxslots; s++) { 4313 /* If function 0 is not present, skip to the next slot. */ 4314 f = 0; 4315 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4316 continue; 4317 pcifunchigh = 0; 4318 hdrtype = REG(PCIR_HDRTYPE, 1); 4319 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4320 continue; 4321 if (hdrtype & PCIM_MFDEV) 4322 pcifunchigh = PCIB_MAXFUNCS(pcib); 4323 for (f = 0; f <= pcifunchigh; f++) { 4324 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4325 continue; 4326 4327 /* 4328 * Found a valid function. Check if a 4329 * device_t for this device already exists. 4330 */ 4331 for (i = 0; i < devcount; i++) { 4332 child = devlist[i]; 4333 if (child == NULL) 4334 continue; 4335 if (pci_get_slot(child) == s && 4336 pci_get_function(child) == f) { 4337 unchanged[i] = child; 4338 goto next_func; 4339 } 4340 } 4341 4342 pci_identify_function(pcib, dev, domain, busno, s, f); 4343 next_func:; 4344 } 4345 } 4346 4347 /* Remove devices that are no longer present. */ 4348 for (i = 0; i < devcount; i++) { 4349 if (unchanged[i] != NULL) 4350 continue; 4351 device_delete_child(dev, devlist[i]); 4352 } 4353 4354 free(devlist, M_TEMP); 4355 oldcount = devcount; 4356 4357 /* Try to attach the devices just added. */ 4358 error = device_get_children(dev, &devlist, &devcount); 4359 if (error) { 4360 free(unchanged, M_TEMP); 4361 return (error); 4362 } 4363 4364 for (i = 0; i < devcount; i++) { 4365 for (j = 0; j < oldcount; j++) { 4366 if (devlist[i] == unchanged[j]) 4367 goto next_device; 4368 } 4369 4370 device_probe_and_attach(devlist[i]); 4371 next_device:; 4372 } 4373 4374 free(unchanged, M_TEMP); 4375 free(devlist, M_TEMP); 4376 return (0); 4377 #undef REG 4378 } 4379 4380 #ifdef PCI_IOV 4381 device_t 4382 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4383 uint16_t did) 4384 { 4385 struct pci_devinfo *vf_dinfo; 4386 device_t pcib; 4387 int busno, slot, func; 4388 4389 pcib = device_get_parent(bus); 4390 4391 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4392 4393 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4394 slot, func, vid, did); 4395 4396 vf_dinfo->cfg.flags |= PCICFG_VF; 4397 pci_add_child(bus, vf_dinfo); 4398 4399 return (vf_dinfo->cfg.dev); 4400 } 4401 4402 device_t 4403 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4404 uint16_t vid, uint16_t did) 4405 { 4406 4407 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4408 } 4409 #endif 4410 4411 /* 4412 * For PCIe device set Max_Payload_Size to match PCIe root's. 4413 */ 4414 static void 4415 pcie_setup_mps(device_t dev) 4416 { 4417 struct pci_devinfo *dinfo = device_get_ivars(dev); 4418 device_t root; 4419 uint16_t rmps, mmps, mps; 4420 4421 if (dinfo->cfg.pcie.pcie_location == 0) 4422 return; 4423 root = pci_find_pcie_root_port(dev); 4424 if (root == NULL) 4425 return; 4426 /* Check whether the MPS is already configured. */ 4427 rmps = pcie_read_config(root, PCIER_DEVICE_CTL, 2) & 4428 PCIEM_CTL_MAX_PAYLOAD; 4429 mps = pcie_read_config(dev, PCIER_DEVICE_CTL, 2) & 4430 PCIEM_CTL_MAX_PAYLOAD; 4431 if (mps == rmps) 4432 return; 4433 /* Check whether the device is capable of the root's MPS. */ 4434 mmps = (pcie_read_config(dev, PCIER_DEVICE_CAP, 2) & 4435 PCIEM_CAP_MAX_PAYLOAD) << 5; 4436 if (rmps > mmps) { 4437 /* 4438 * The device is unable to handle root's MPS. Limit root. 4439 * XXX: We should traverse through all the tree, applying 4440 * it to all the devices. 4441 */ 4442 pcie_adjust_config(root, PCIER_DEVICE_CTL, 4443 PCIEM_CTL_MAX_PAYLOAD, mmps, 2); 4444 } else { 4445 pcie_adjust_config(dev, PCIER_DEVICE_CTL, 4446 PCIEM_CTL_MAX_PAYLOAD, rmps, 2); 4447 } 4448 } 4449 4450 static void 4451 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4452 { 4453 int aer; 4454 uint32_t r; 4455 uint16_t r2; 4456 4457 if (dinfo->cfg.pcie.pcie_location != 0 && 4458 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4459 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4460 PCIER_ROOT_CTL, 2); 4461 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4462 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4463 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4464 PCIER_ROOT_CTL, r2, 2); 4465 } 4466 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4467 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4468 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4469 if (r != 0 && bootverbose) { 4470 pci_printf(&dinfo->cfg, 4471 "clearing AER UC 0x%08x -> 0x%08x\n", 4472 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4473 4)); 4474 } 4475 4476 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4477 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4478 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4479 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4480 PCIM_AER_UC_POISONED_TLP | 4481 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4482 PCIM_AER_UC_COMPLETION_TIMEOUT | 4483 PCIM_AER_UC_COMPLETER_ABORT | 4484 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4485 PCIM_AER_UC_RECEIVER_OVERFLOW | 4486 PCIM_AER_UC_MALFORMED_TLP | 4487 PCIM_AER_UC_ECRC_ERROR | 4488 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4489 PCIM_AER_UC_ACS_VIOLATION | 4490 PCIM_AER_UC_INTERNAL_ERROR | 4491 PCIM_AER_UC_MC_BLOCKED_TLP | 4492 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4493 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4494 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4495 4496 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4497 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4498 if (r != 0 && bootverbose) { 4499 pci_printf(&dinfo->cfg, 4500 "clearing AER COR 0x%08x -> 0x%08x\n", 4501 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4502 4)); 4503 } 4504 4505 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4506 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4507 PCIM_AER_COR_BAD_TLP | 4508 PCIM_AER_COR_BAD_DLLP | 4509 PCIM_AER_COR_REPLAY_ROLLOVER | 4510 PCIM_AER_COR_REPLAY_TIMEOUT | 4511 PCIM_AER_COR_ADVISORY_NF_ERROR | 4512 PCIM_AER_COR_INTERNAL_ERROR | 4513 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4514 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4515 4516 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4517 PCIER_DEVICE_CTL, 2); 4518 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4519 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4520 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4521 PCIER_DEVICE_CTL, r, 2); 4522 } 4523 } 4524 4525 void 4526 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4527 { 4528 device_t dev; 4529 4530 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY); 4531 device_set_ivars(dev, dinfo); 4532 resource_list_init(&dinfo->resources); 4533 pci_cfg_save(dev, dinfo, 0); 4534 pci_cfg_restore(dev, dinfo); 4535 pci_clear_pme(dev); 4536 pci_print_verbose(dinfo); 4537 pci_add_resources(bus, dev, 0, 0); 4538 if (pci_enable_mps_tune) 4539 pcie_setup_mps(dev); 4540 pci_child_added(dinfo->cfg.dev); 4541 4542 if (pci_clear_aer_on_attach) 4543 pci_add_child_clear_aer(dev, dinfo); 4544 4545 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4546 } 4547 4548 void 4549 pci_child_added_method(device_t dev, device_t child) 4550 { 4551 4552 } 4553 4554 static int 4555 pci_probe(device_t dev) 4556 { 4557 4558 device_set_desc(dev, "PCI bus"); 4559 4560 /* Allow other subclasses to override this driver. */ 4561 return (BUS_PROBE_GENERIC); 4562 } 4563 4564 int 4565 pci_attach_common(device_t dev) 4566 { 4567 struct pci_softc *sc; 4568 int busno, domain; 4569 int rid; 4570 4571 sc = device_get_softc(dev); 4572 domain = pcib_get_domain(dev); 4573 busno = pcib_get_bus(dev); 4574 rid = 0; 4575 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4576 1, 0); 4577 if (sc->sc_bus == NULL) { 4578 device_printf(dev, "failed to allocate bus number\n"); 4579 return (ENXIO); 4580 } 4581 if (bootverbose) 4582 device_printf(dev, "domain=%d, physical bus=%d\n", 4583 domain, busno); 4584 sc->sc_dma_tag = bus_get_dma_tag(dev); 4585 return (0); 4586 } 4587 4588 int 4589 pci_attach(device_t dev) 4590 { 4591 int busno, domain, error; 4592 4593 error = pci_attach_common(dev); 4594 if (error) 4595 return (error); 4596 4597 /* 4598 * Since there can be multiple independently numbered PCI 4599 * buses on systems with multiple PCI domains, we can't use 4600 * the unit number to decide which bus we are probing. We ask 4601 * the parent pcib what our domain and bus numbers are. 4602 */ 4603 domain = pcib_get_domain(dev); 4604 busno = pcib_get_bus(dev); 4605 pci_add_children(dev, domain, busno); 4606 bus_attach_children(dev); 4607 return (0); 4608 } 4609 4610 int 4611 pci_detach(device_t dev) 4612 { 4613 struct pci_softc *sc; 4614 int error; 4615 4616 error = bus_generic_detach(dev); 4617 if (error) 4618 return (error); 4619 sc = device_get_softc(dev); 4620 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4621 return (error); 4622 } 4623 4624 static void 4625 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4626 { 4627 int line, unit; 4628 const char *at; 4629 char me1[24], me2[32]; 4630 uint8_t b, s, f; 4631 uint32_t d; 4632 device_location_cache_t *cache; 4633 4634 d = pci_get_domain(child); 4635 b = pci_get_bus(child); 4636 s = pci_get_slot(child); 4637 f = pci_get_function(child); 4638 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4639 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4640 line = 0; 4641 cache = dev_wired_cache_init(); 4642 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4643 resource_string_value(name, unit, "at", &at); 4644 if (strcmp(at, me1) == 0 || strcmp(at, me2) == 0) { 4645 *unitp = unit; 4646 break; 4647 } 4648 if (dev_wired_cache_match(cache, child, at)) { 4649 *unitp = unit; 4650 break; 4651 } 4652 } 4653 dev_wired_cache_fini(cache); 4654 } 4655 4656 static void 4657 pci_set_power_child(device_t dev, device_t child, int state) 4658 { 4659 device_t pcib; 4660 int dstate; 4661 4662 /* 4663 * Set the device to the given state. If the firmware suggests 4664 * a different power state, use it instead. If power management 4665 * is not present, the firmware is responsible for managing 4666 * device power. Skip children who aren't attached since they 4667 * are handled separately. 4668 */ 4669 pcib = device_get_parent(dev); 4670 dstate = state; 4671 if (device_is_attached(child) && 4672 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4673 pci_set_powerstate(child, dstate); 4674 } 4675 4676 int 4677 pci_suspend_child(device_t dev, device_t child) 4678 { 4679 struct pci_devinfo *dinfo; 4680 struct resource_list_entry *rle; 4681 int error; 4682 4683 dinfo = device_get_ivars(child); 4684 4685 /* 4686 * Save the PCI configuration space for the child and set the 4687 * device in the appropriate power state for this sleep state. 4688 */ 4689 pci_cfg_save(child, dinfo, 0); 4690 4691 /* Suspend devices before potentially powering them down. */ 4692 error = bus_generic_suspend_child(dev, child); 4693 4694 if (error) 4695 return (error); 4696 4697 if (pci_do_power_suspend) { 4698 /* 4699 * Make sure this device's interrupt handler is not invoked 4700 * in the case the device uses a shared interrupt that can 4701 * be raised by some other device. 4702 * This is applicable only to regular (legacy) PCI interrupts 4703 * as MSI/MSI-X interrupts are never shared. 4704 */ 4705 rle = resource_list_find(&dinfo->resources, 4706 SYS_RES_IRQ, 0); 4707 if (rle != NULL && rle->res != NULL) 4708 (void)bus_suspend_intr(child, rle->res); 4709 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4710 } 4711 4712 return (0); 4713 } 4714 4715 int 4716 pci_resume_child(device_t dev, device_t child) 4717 { 4718 struct pci_devinfo *dinfo; 4719 struct resource_list_entry *rle; 4720 4721 if (pci_do_power_resume) 4722 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4723 4724 dinfo = device_get_ivars(child); 4725 pci_cfg_restore(child, dinfo); 4726 pci_clear_pme(child); 4727 if (!device_is_attached(child)) 4728 pci_cfg_save(child, dinfo, 1); 4729 4730 bus_generic_resume_child(dev, child); 4731 4732 /* 4733 * Allow interrupts only after fully resuming the driver and hardware. 4734 */ 4735 if (pci_do_power_suspend) { 4736 /* See pci_suspend_child for details. */ 4737 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4738 if (rle != NULL && rle->res != NULL) 4739 (void)bus_resume_intr(child, rle->res); 4740 } 4741 4742 return (0); 4743 } 4744 4745 int 4746 pci_resume(device_t dev) 4747 { 4748 device_t child, *devlist; 4749 int error, i, numdevs; 4750 4751 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4752 return (error); 4753 4754 /* 4755 * Resume critical devices first, then everything else later. 4756 */ 4757 for (i = 0; i < numdevs; i++) { 4758 child = devlist[i]; 4759 switch (pci_get_class(child)) { 4760 case PCIC_DISPLAY: 4761 case PCIC_MEMORY: 4762 case PCIC_BRIDGE: 4763 case PCIC_BASEPERIPH: 4764 BUS_RESUME_CHILD(dev, child); 4765 break; 4766 } 4767 } 4768 for (i = 0; i < numdevs; i++) { 4769 child = devlist[i]; 4770 switch (pci_get_class(child)) { 4771 case PCIC_DISPLAY: 4772 case PCIC_MEMORY: 4773 case PCIC_BRIDGE: 4774 case PCIC_BASEPERIPH: 4775 break; 4776 default: 4777 BUS_RESUME_CHILD(dev, child); 4778 } 4779 } 4780 free(devlist, M_TEMP); 4781 return (0); 4782 } 4783 4784 static void 4785 pci_load_vendor_data(void) 4786 { 4787 caddr_t data; 4788 void *ptr; 4789 size_t sz; 4790 4791 data = preload_search_by_type("pci_vendor_data"); 4792 if (data != NULL) { 4793 ptr = preload_fetch_addr(data); 4794 sz = preload_fetch_size(data); 4795 if (ptr != NULL && sz != 0) { 4796 pci_vendordata = ptr; 4797 pci_vendordata_size = sz; 4798 /* terminate the database */ 4799 pci_vendordata[pci_vendordata_size] = '\n'; 4800 } 4801 } 4802 } 4803 4804 void 4805 pci_driver_added(device_t dev, driver_t *driver) 4806 { 4807 int numdevs; 4808 device_t *devlist; 4809 device_t child; 4810 struct pci_devinfo *dinfo; 4811 int i; 4812 4813 if (bootverbose) 4814 device_printf(dev, "driver added\n"); 4815 DEVICE_IDENTIFY(driver, dev); 4816 if (device_get_children(dev, &devlist, &numdevs) != 0) 4817 return; 4818 for (i = 0; i < numdevs; i++) { 4819 child = devlist[i]; 4820 if (device_get_state(child) != DS_NOTPRESENT) 4821 continue; 4822 dinfo = device_get_ivars(child); 4823 pci_print_verbose(dinfo); 4824 if (bootverbose) 4825 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4826 pci_cfg_restore(child, dinfo); 4827 if (device_probe_and_attach(child) != 0) 4828 pci_child_detached(dev, child); 4829 } 4830 free(devlist, M_TEMP); 4831 } 4832 4833 int 4834 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4835 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4836 { 4837 struct pci_devinfo *dinfo; 4838 struct msix_table_entry *mte; 4839 struct msix_vector *mv; 4840 uint64_t addr; 4841 uint32_t data; 4842 void *cookie; 4843 int error, rid; 4844 4845 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4846 arg, &cookie); 4847 if (error) 4848 return (error); 4849 4850 /* If this is not a direct child, just bail out. */ 4851 if (device_get_parent(child) != dev) { 4852 *cookiep = cookie; 4853 return(0); 4854 } 4855 4856 rid = rman_get_rid(irq); 4857 if (rid == 0) { 4858 /* Make sure that INTx is enabled */ 4859 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4860 } else { 4861 /* 4862 * Check to see if the interrupt is MSI or MSI-X. 4863 * Ask our parent to map the MSI and give 4864 * us the address and data register values. 4865 * If we fail for some reason, teardown the 4866 * interrupt handler. 4867 */ 4868 dinfo = device_get_ivars(child); 4869 if (dinfo->cfg.msi.msi_alloc > 0) { 4870 if (dinfo->cfg.msi.msi_addr == 0) { 4871 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4872 ("MSI has handlers, but vectors not mapped")); 4873 error = PCIB_MAP_MSI(device_get_parent(dev), 4874 child, rman_get_start(irq), &addr, &data); 4875 if (error) 4876 goto bad; 4877 dinfo->cfg.msi.msi_addr = addr; 4878 dinfo->cfg.msi.msi_data = data; 4879 } 4880 if (dinfo->cfg.msi.msi_handlers == 0) 4881 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4882 dinfo->cfg.msi.msi_data); 4883 dinfo->cfg.msi.msi_handlers++; 4884 } else { 4885 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4886 ("No MSI or MSI-X interrupts allocated")); 4887 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4888 ("MSI-X index too high")); 4889 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4890 KASSERT(mte->mte_vector != 0, ("no message vector")); 4891 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4892 KASSERT(mv->mv_irq == rman_get_start(irq), 4893 ("IRQ mismatch")); 4894 if (mv->mv_address == 0) { 4895 KASSERT(mte->mte_handlers == 0, 4896 ("MSI-X table entry has handlers, but vector not mapped")); 4897 error = PCIB_MAP_MSI(device_get_parent(dev), 4898 child, rman_get_start(irq), &addr, &data); 4899 if (error) 4900 goto bad; 4901 mv->mv_address = addr; 4902 mv->mv_data = data; 4903 } 4904 4905 /* 4906 * The MSIX table entry must be made valid by 4907 * incrementing the mte_handlers before 4908 * calling pci_enable_msix() and 4909 * pci_resume_msix(). Else the MSIX rewrite 4910 * table quirk will not work as expected. 4911 */ 4912 mte->mte_handlers++; 4913 if (mte->mte_handlers == 1) { 4914 pci_enable_msix(child, rid - 1, mv->mv_address, 4915 mv->mv_data); 4916 pci_unmask_msix(child, rid - 1); 4917 } 4918 } 4919 4920 /* 4921 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4922 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4923 * in which case we "enable" INTx so MSI/MSI-X actually works. 4924 */ 4925 if (!pci_has_quirk(pci_get_devid(child), 4926 PCI_QUIRK_MSI_INTX_BUG)) 4927 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4928 else 4929 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4930 bad: 4931 if (error) { 4932 (void)bus_generic_teardown_intr(dev, child, irq, 4933 cookie); 4934 return (error); 4935 } 4936 } 4937 *cookiep = cookie; 4938 return (0); 4939 } 4940 4941 int 4942 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4943 void *cookie) 4944 { 4945 struct msix_table_entry *mte; 4946 struct resource_list_entry *rle; 4947 struct pci_devinfo *dinfo; 4948 int error, rid; 4949 4950 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4951 return (EINVAL); 4952 4953 /* If this isn't a direct child, just bail out */ 4954 if (device_get_parent(child) != dev) 4955 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4956 4957 rid = rman_get_rid(irq); 4958 if (rid == 0) { 4959 /* Mask INTx */ 4960 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4961 } else { 4962 /* 4963 * Check to see if the interrupt is MSI or MSI-X. If so, 4964 * decrement the appropriate handlers count and mask the 4965 * MSI-X message, or disable MSI messages if the count 4966 * drops to 0. 4967 */ 4968 dinfo = device_get_ivars(child); 4969 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4970 if (rle->res != irq) 4971 return (EINVAL); 4972 if (dinfo->cfg.msi.msi_alloc > 0) { 4973 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4974 ("MSI-X index too high")); 4975 if (dinfo->cfg.msi.msi_handlers == 0) 4976 return (EINVAL); 4977 dinfo->cfg.msi.msi_handlers--; 4978 if (dinfo->cfg.msi.msi_handlers == 0) 4979 pci_disable_msi(child); 4980 } else { 4981 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4982 ("No MSI or MSI-X interrupts allocated")); 4983 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4984 ("MSI-X index too high")); 4985 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4986 if (mte->mte_handlers == 0) 4987 return (EINVAL); 4988 mte->mte_handlers--; 4989 if (mte->mte_handlers == 0) 4990 pci_mask_msix(child, rid - 1); 4991 } 4992 } 4993 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4994 if (rid > 0) 4995 KASSERT(error == 0, 4996 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4997 return (error); 4998 } 4999 5000 int 5001 pci_print_child(device_t dev, device_t child) 5002 { 5003 struct pci_devinfo *dinfo; 5004 struct resource_list *rl; 5005 int retval = 0; 5006 5007 dinfo = device_get_ivars(child); 5008 rl = &dinfo->resources; 5009 5010 retval += bus_print_child_header(dev, child); 5011 5012 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 5013 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 5014 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 5015 if (device_get_flags(dev)) 5016 retval += printf(" flags %#x", device_get_flags(dev)); 5017 5018 retval += printf(" at device %d.%d", pci_get_slot(child), 5019 pci_get_function(child)); 5020 5021 retval += bus_print_child_domain(dev, child); 5022 retval += bus_print_child_footer(dev, child); 5023 5024 return (retval); 5025 } 5026 5027 static const struct 5028 { 5029 int class; 5030 int subclass; 5031 int report; /* 0 = bootverbose, 1 = always */ 5032 const char *desc; 5033 } pci_nomatch_tab[] = { 5034 {PCIC_OLD, -1, 1, "old"}, 5035 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 5036 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 5037 {PCIC_STORAGE, -1, 1, "mass storage"}, 5038 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 5039 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 5040 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 5041 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 5042 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 5043 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 5044 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 5045 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 5046 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 5047 {PCIC_NETWORK, -1, 1, "network"}, 5048 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 5049 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 5050 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 5051 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 5052 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 5053 {PCIC_DISPLAY, -1, 1, "display"}, 5054 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 5055 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 5056 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 5057 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 5058 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 5059 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 5060 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 5061 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 5062 {PCIC_MEMORY, -1, 1, "memory"}, 5063 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 5064 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 5065 {PCIC_BRIDGE, -1, 1, "bridge"}, 5066 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 5067 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 5068 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 5069 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 5070 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 5071 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 5072 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 5073 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 5074 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 5075 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 5076 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 5077 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 5078 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 5079 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 5080 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 5081 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 5082 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 5083 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 5084 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 5085 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 5086 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 5087 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 5088 {PCIC_INPUTDEV, -1, 1, "input device"}, 5089 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 5090 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 5091 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 5092 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 5093 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 5094 {PCIC_DOCKING, -1, 1, "docking station"}, 5095 {PCIC_PROCESSOR, -1, 1, "processor"}, 5096 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 5097 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 5098 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 5099 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 5100 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 5101 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 5102 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 5103 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 5104 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 5105 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 5106 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 5107 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 5108 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 5109 {PCIC_SATCOM, -1, 1, "satellite communication"}, 5110 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 5111 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 5112 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 5113 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 5114 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 5115 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 5116 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 5117 {PCIC_DASP, -1, 0, "dasp"}, 5118 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 5119 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 5120 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 5121 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 5122 {PCIC_INSTRUMENT, -1, 0, "non-essential instrumentation"}, 5123 {0, 0, 0, NULL} 5124 }; 5125 5126 void 5127 pci_probe_nomatch(device_t dev, device_t child) 5128 { 5129 int i, report; 5130 const char *cp, *scp; 5131 char *device; 5132 5133 /* 5134 * Look for a listing for this device in a loaded device database. 5135 */ 5136 report = 1; 5137 if ((device = pci_describe_device(child)) != NULL) { 5138 device_printf(dev, "<%s>", device); 5139 free(device, M_DEVBUF); 5140 } else { 5141 /* 5142 * Scan the class/subclass descriptions for a general 5143 * description. 5144 */ 5145 cp = "unknown"; 5146 scp = NULL; 5147 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 5148 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 5149 if (pci_nomatch_tab[i].subclass == -1) { 5150 cp = pci_nomatch_tab[i].desc; 5151 report = pci_nomatch_tab[i].report; 5152 } else if (pci_nomatch_tab[i].subclass == 5153 pci_get_subclass(child)) { 5154 scp = pci_nomatch_tab[i].desc; 5155 report = pci_nomatch_tab[i].report; 5156 } 5157 } 5158 } 5159 if (report || bootverbose) { 5160 device_printf(dev, "<%s%s%s>", 5161 cp ? cp : "", 5162 ((cp != NULL) && (scp != NULL)) ? ", " : "", 5163 scp ? scp : ""); 5164 } 5165 } 5166 if (report || bootverbose) { 5167 printf(" at device %d.%d (no driver attached)\n", 5168 pci_get_slot(child), pci_get_function(child)); 5169 } 5170 pci_cfg_save(child, device_get_ivars(child), 1); 5171 } 5172 5173 void 5174 pci_child_detached(device_t dev, device_t child) 5175 { 5176 struct pci_devinfo *dinfo; 5177 struct resource_list *rl; 5178 5179 dinfo = device_get_ivars(child); 5180 rl = &dinfo->resources; 5181 5182 /* 5183 * Have to deallocate IRQs before releasing any MSI messages and 5184 * have to release MSI messages before deallocating any memory 5185 * BARs. 5186 */ 5187 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 5188 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 5189 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 5190 if (dinfo->cfg.msi.msi_alloc != 0) 5191 pci_printf(&dinfo->cfg, "Device leaked %d MSI " 5192 "vectors\n", dinfo->cfg.msi.msi_alloc); 5193 else 5194 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " 5195 "vectors\n", dinfo->cfg.msix.msix_alloc); 5196 (void)pci_release_msi(child); 5197 } 5198 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 5199 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 5200 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 5201 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 5202 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 5203 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 5204 5205 pci_cfg_save(child, dinfo, 1); 5206 } 5207 5208 /* 5209 * Parse the PCI device database, if loaded, and return a pointer to a 5210 * description of the device. 5211 * 5212 * The database is flat text formatted as follows: 5213 * 5214 * Any line not in a valid format is ignored. 5215 * Lines are terminated with newline '\n' characters. 5216 * 5217 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 5218 * the vendor name. 5219 * 5220 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 5221 * - devices cannot be listed without a corresponding VENDOR line. 5222 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 5223 * another TAB, then the device name. 5224 */ 5225 5226 /* 5227 * Assuming (ptr) points to the beginning of a line in the database, 5228 * return the vendor or device and description of the next entry. 5229 * The value of (vendor) or (device) inappropriate for the entry type 5230 * is set to -1. Returns nonzero at the end of the database. 5231 * 5232 * Note that this is slightly unrobust in the face of corrupt data; 5233 * we attempt to safeguard against this by spamming the end of the 5234 * database with a newline when we initialise. 5235 */ 5236 static int 5237 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5238 { 5239 char *cp = *ptr; 5240 int left; 5241 5242 *device = -1; 5243 *vendor = -1; 5244 **desc = '\0'; 5245 for (;;) { 5246 left = pci_vendordata_size - (cp - pci_vendordata); 5247 if (left <= 0) { 5248 *ptr = cp; 5249 return(1); 5250 } 5251 5252 /* vendor entry? */ 5253 if (*cp != '\t' && 5254 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5255 break; 5256 /* device entry? */ 5257 if (*cp == '\t' && 5258 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5259 break; 5260 5261 /* skip to next line */ 5262 while (*cp != '\n' && left > 0) { 5263 cp++; 5264 left--; 5265 } 5266 if (*cp == '\n') { 5267 cp++; 5268 left--; 5269 } 5270 } 5271 /* skip to next line */ 5272 while (*cp != '\n' && left > 0) { 5273 cp++; 5274 left--; 5275 } 5276 if (*cp == '\n' && left > 0) 5277 cp++; 5278 *ptr = cp; 5279 return(0); 5280 } 5281 5282 static char * 5283 pci_describe_device(device_t dev) 5284 { 5285 int vendor, device; 5286 char *desc, *vp, *dp, *line; 5287 5288 desc = vp = dp = NULL; 5289 5290 /* 5291 * If we have no vendor data, we can't do anything. 5292 */ 5293 if (pci_vendordata == NULL) 5294 goto out; 5295 5296 /* 5297 * Scan the vendor data looking for this device 5298 */ 5299 line = pci_vendordata; 5300 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5301 goto out; 5302 for (;;) { 5303 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5304 goto out; 5305 if (vendor == pci_get_vendor(dev)) 5306 break; 5307 } 5308 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5309 goto out; 5310 for (;;) { 5311 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5312 *dp = 0; 5313 break; 5314 } 5315 if (vendor != -1) { 5316 *dp = 0; 5317 break; 5318 } 5319 if (device == pci_get_device(dev)) 5320 break; 5321 } 5322 if (dp[0] == '\0') 5323 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5324 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5325 NULL) 5326 sprintf(desc, "%s, %s", vp, dp); 5327 out: 5328 if (vp != NULL) 5329 free(vp, M_DEVBUF); 5330 if (dp != NULL) 5331 free(dp, M_DEVBUF); 5332 return(desc); 5333 } 5334 5335 int 5336 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5337 { 5338 struct pci_devinfo *dinfo; 5339 pcicfgregs *cfg; 5340 5341 dinfo = device_get_ivars(child); 5342 cfg = &dinfo->cfg; 5343 5344 switch (which) { 5345 case PCI_IVAR_ETHADDR: 5346 /* 5347 * The generic accessor doesn't deal with failure, so 5348 * we set the return value, then return an error. 5349 */ 5350 *((uint8_t **) result) = NULL; 5351 return (EINVAL); 5352 case PCI_IVAR_SUBVENDOR: 5353 *result = cfg->subvendor; 5354 break; 5355 case PCI_IVAR_SUBDEVICE: 5356 *result = cfg->subdevice; 5357 break; 5358 case PCI_IVAR_VENDOR: 5359 *result = cfg->vendor; 5360 break; 5361 case PCI_IVAR_DEVICE: 5362 *result = cfg->device; 5363 break; 5364 case PCI_IVAR_DEVID: 5365 *result = (cfg->device << 16) | cfg->vendor; 5366 break; 5367 case PCI_IVAR_CLASS: 5368 *result = cfg->baseclass; 5369 break; 5370 case PCI_IVAR_SUBCLASS: 5371 *result = cfg->subclass; 5372 break; 5373 case PCI_IVAR_PROGIF: 5374 *result = cfg->progif; 5375 break; 5376 case PCI_IVAR_REVID: 5377 *result = cfg->revid; 5378 break; 5379 case PCI_IVAR_INTPIN: 5380 *result = cfg->intpin; 5381 break; 5382 case PCI_IVAR_IRQ: 5383 *result = cfg->intline; 5384 break; 5385 case PCI_IVAR_DOMAIN: 5386 *result = cfg->domain; 5387 break; 5388 case PCI_IVAR_BUS: 5389 *result = cfg->bus; 5390 break; 5391 case PCI_IVAR_SLOT: 5392 *result = cfg->slot; 5393 break; 5394 case PCI_IVAR_FUNCTION: 5395 *result = cfg->func; 5396 break; 5397 case PCI_IVAR_CMDREG: 5398 *result = cfg->cmdreg; 5399 break; 5400 case PCI_IVAR_CACHELNSZ: 5401 *result = cfg->cachelnsz; 5402 break; 5403 case PCI_IVAR_MINGNT: 5404 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5405 *result = -1; 5406 return (EINVAL); 5407 } 5408 *result = cfg->mingnt; 5409 break; 5410 case PCI_IVAR_MAXLAT: 5411 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5412 *result = -1; 5413 return (EINVAL); 5414 } 5415 *result = cfg->maxlat; 5416 break; 5417 case PCI_IVAR_LATTIMER: 5418 *result = cfg->lattimer; 5419 break; 5420 default: 5421 return (ENOENT); 5422 } 5423 return (0); 5424 } 5425 5426 int 5427 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5428 { 5429 struct pci_devinfo *dinfo; 5430 5431 dinfo = device_get_ivars(child); 5432 5433 switch (which) { 5434 case PCI_IVAR_INTPIN: 5435 dinfo->cfg.intpin = value; 5436 return (0); 5437 case PCI_IVAR_ETHADDR: 5438 case PCI_IVAR_SUBVENDOR: 5439 case PCI_IVAR_SUBDEVICE: 5440 case PCI_IVAR_VENDOR: 5441 case PCI_IVAR_DEVICE: 5442 case PCI_IVAR_DEVID: 5443 case PCI_IVAR_CLASS: 5444 case PCI_IVAR_SUBCLASS: 5445 case PCI_IVAR_PROGIF: 5446 case PCI_IVAR_REVID: 5447 case PCI_IVAR_IRQ: 5448 case PCI_IVAR_DOMAIN: 5449 case PCI_IVAR_BUS: 5450 case PCI_IVAR_SLOT: 5451 case PCI_IVAR_FUNCTION: 5452 return (EINVAL); /* disallow for now */ 5453 5454 default: 5455 return (ENOENT); 5456 } 5457 } 5458 5459 #include "opt_ddb.h" 5460 #ifdef DDB 5461 #include <ddb/ddb.h> 5462 #include <sys/cons.h> 5463 5464 /* 5465 * List resources based on pci map registers, used for within ddb 5466 */ 5467 5468 DB_SHOW_COMMAND_FLAGS(pciregs, db_pci_dump, DB_CMD_MEMSAFE) 5469 { 5470 struct pci_devinfo *dinfo; 5471 struct devlist *devlist_head; 5472 struct pci_conf *p; 5473 const char *name; 5474 int i, error, none_count; 5475 5476 none_count = 0; 5477 /* get the head of the device queue */ 5478 devlist_head = &pci_devq; 5479 5480 /* 5481 * Go through the list of devices and print out devices 5482 */ 5483 for (error = 0, i = 0, 5484 dinfo = STAILQ_FIRST(devlist_head); 5485 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5486 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5487 /* Populate pd_name and pd_unit */ 5488 name = NULL; 5489 if (dinfo->cfg.dev) 5490 name = device_get_name(dinfo->cfg.dev); 5491 5492 p = &dinfo->conf; 5493 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5494 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5495 (name && *name) ? name : "none", 5496 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5497 none_count++, 5498 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5499 p->pc_sel.pc_func, (p->pc_class << 16) | 5500 (p->pc_subclass << 8) | p->pc_progif, 5501 (p->pc_subdevice << 16) | p->pc_subvendor, 5502 (p->pc_device << 16) | p->pc_vendor, 5503 p->pc_revid, p->pc_hdr); 5504 } 5505 } 5506 #endif /* DDB */ 5507 5508 struct resource * 5509 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5510 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5511 u_int flags) 5512 { 5513 struct pci_devinfo *dinfo = device_get_ivars(child); 5514 struct resource_list *rl = &dinfo->resources; 5515 struct resource *res; 5516 struct pci_map *pm; 5517 uint16_t cmd; 5518 pci_addr_t map, testval; 5519 int mapsize; 5520 5521 res = NULL; 5522 5523 /* If rid is managed by EA, ignore it */ 5524 if (pci_ea_is_enabled(child, *rid)) 5525 goto out; 5526 5527 pm = pci_find_bar(child, *rid); 5528 if (pm != NULL) { 5529 /* This is a BAR that we failed to allocate earlier. */ 5530 mapsize = pm->pm_size; 5531 map = pm->pm_value; 5532 } else { 5533 /* 5534 * Weed out the bogons, and figure out how large the 5535 * BAR/map is. BARs that read back 0 here are bogus 5536 * and unimplemented. Note: atapci in legacy mode are 5537 * special and handled elsewhere in the code. If you 5538 * have a atapci device in legacy mode and it fails 5539 * here, that other code is broken. 5540 */ 5541 pci_read_bar(child, *rid, &map, &testval, NULL); 5542 5543 /* 5544 * Determine the size of the BAR and ignore BARs with a size 5545 * of 0. Device ROM BARs use a different mask value. 5546 */ 5547 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5548 mapsize = pci_romsize(testval); 5549 else 5550 mapsize = pci_mapsize(testval); 5551 if (mapsize == 0) 5552 goto out; 5553 pm = pci_add_bar(child, *rid, map, mapsize); 5554 } 5555 5556 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5557 if (type != SYS_RES_MEMORY) { 5558 if (bootverbose) 5559 device_printf(dev, 5560 "child %s requested type %d for rid %#x," 5561 " but the BAR says it is an memio\n", 5562 device_get_nameunit(child), type, *rid); 5563 goto out; 5564 } 5565 } else { 5566 if (type != SYS_RES_IOPORT) { 5567 if (bootverbose) 5568 device_printf(dev, 5569 "child %s requested type %d for rid %#x," 5570 " but the BAR says it is an ioport\n", 5571 device_get_nameunit(child), type, *rid); 5572 goto out; 5573 } 5574 } 5575 5576 /* 5577 * For real BARs, we need to override the size that 5578 * the driver requests, because that's what the BAR 5579 * actually uses and we would otherwise have a 5580 * situation where we might allocate the excess to 5581 * another driver, which won't work. 5582 */ 5583 count = ((pci_addr_t)1 << mapsize) * num; 5584 if (RF_ALIGNMENT(flags) < mapsize) 5585 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5586 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5587 flags |= RF_PREFETCHABLE; 5588 5589 /* 5590 * Allocate enough resource, and then write back the 5591 * appropriate BAR for that resource. 5592 */ 5593 resource_list_add(rl, type, *rid, start, end, count); 5594 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5595 count, flags & ~RF_ACTIVE); 5596 if (res == NULL) { 5597 resource_list_delete(rl, type, *rid); 5598 device_printf(child, 5599 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5600 count, *rid, type, start, end); 5601 goto out; 5602 } 5603 if (bootverbose) 5604 device_printf(child, 5605 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5606 count, *rid, type, rman_get_start(res)); 5607 5608 /* Disable decoding via the CMD register before updating the BAR */ 5609 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5610 pci_write_config(child, PCIR_COMMAND, 5611 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5612 5613 map = rman_get_start(res); 5614 pci_write_bar(child, pm, map); 5615 5616 /* Restore the original value of the CMD register */ 5617 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5618 out: 5619 return (res); 5620 } 5621 5622 struct resource * 5623 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5624 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5625 u_int flags) 5626 { 5627 struct pci_devinfo *dinfo; 5628 struct resource_list *rl; 5629 struct resource_list_entry *rle; 5630 struct resource *res; 5631 pcicfgregs *cfg; 5632 5633 /* 5634 * Perform lazy resource allocation 5635 */ 5636 dinfo = device_get_ivars(child); 5637 rl = &dinfo->resources; 5638 cfg = &dinfo->cfg; 5639 switch (type) { 5640 case PCI_RES_BUS: 5641 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5642 flags)); 5643 case SYS_RES_IRQ: 5644 /* 5645 * Can't alloc legacy interrupt once MSI messages have 5646 * been allocated. 5647 */ 5648 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5649 cfg->msix.msix_alloc > 0)) 5650 return (NULL); 5651 5652 /* 5653 * If the child device doesn't have an interrupt 5654 * routed and is deserving of an interrupt, try to 5655 * assign it one. 5656 */ 5657 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5658 (cfg->intpin != 0)) 5659 pci_assign_interrupt(dev, child, 0); 5660 break; 5661 case SYS_RES_IOPORT: 5662 case SYS_RES_MEMORY: 5663 /* 5664 * PCI-PCI bridge I/O window resources are not BARs. 5665 * For those allocations just pass the request up the 5666 * tree. 5667 */ 5668 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5669 switch (*rid) { 5670 case PCIR_IOBASEL_1: 5671 case PCIR_MEMBASE_1: 5672 case PCIR_PMBASEL_1: 5673 /* 5674 * XXX: Should we bother creating a resource 5675 * list entry? 5676 */ 5677 return (bus_generic_alloc_resource(dev, child, 5678 type, rid, start, end, count, flags)); 5679 } 5680 } 5681 /* Reserve resources for this BAR if needed. */ 5682 rle = resource_list_find(rl, type, *rid); 5683 if (rle == NULL) { 5684 res = pci_reserve_map(dev, child, type, rid, start, end, 5685 count, num, flags); 5686 if (res == NULL) 5687 return (NULL); 5688 } 5689 } 5690 return (resource_list_alloc(rl, dev, child, type, rid, 5691 start, end, count, flags)); 5692 } 5693 5694 struct resource * 5695 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5696 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5697 { 5698 #ifdef PCI_IOV 5699 struct pci_devinfo *dinfo; 5700 #endif 5701 5702 if (device_get_parent(child) != dev) 5703 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5704 type, rid, start, end, count, flags)); 5705 5706 #ifdef PCI_IOV 5707 dinfo = device_get_ivars(child); 5708 if (dinfo->cfg.flags & PCICFG_VF) { 5709 switch (type) { 5710 /* VFs can't have I/O BARs. */ 5711 case SYS_RES_IOPORT: 5712 return (NULL); 5713 case SYS_RES_MEMORY: 5714 return (pci_vf_alloc_mem_resource(dev, child, rid, 5715 start, end, count, flags)); 5716 } 5717 5718 /* Fall through for other types of resource allocations. */ 5719 } 5720 #endif 5721 5722 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5723 count, 1, flags)); 5724 } 5725 5726 int 5727 pci_release_resource(device_t dev, device_t child, struct resource *r) 5728 { 5729 struct pci_devinfo *dinfo; 5730 struct resource_list *rl; 5731 pcicfgregs *cfg __unused; 5732 5733 if (device_get_parent(child) != dev) 5734 return (bus_generic_release_resource(dev, child, r)); 5735 5736 dinfo = device_get_ivars(child); 5737 cfg = &dinfo->cfg; 5738 5739 #ifdef PCI_IOV 5740 if (cfg->flags & PCICFG_VF) { 5741 switch (rman_get_type(r)) { 5742 /* VFs can't have I/O BARs. */ 5743 case SYS_RES_IOPORT: 5744 return (EDOOFUS); 5745 case SYS_RES_MEMORY: 5746 return (pci_vf_release_mem_resource(dev, child, r)); 5747 } 5748 5749 /* Fall through for other types of resource allocations. */ 5750 } 5751 #endif 5752 5753 /* 5754 * PCI-PCI bridge I/O window resources are not BARs. For 5755 * those allocations just pass the request up the tree. 5756 */ 5757 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5758 (rman_get_type(r) == SYS_RES_IOPORT || 5759 rman_get_type(r) == SYS_RES_MEMORY)) { 5760 switch (rman_get_rid(r)) { 5761 case PCIR_IOBASEL_1: 5762 case PCIR_MEMBASE_1: 5763 case PCIR_PMBASEL_1: 5764 return (bus_generic_release_resource(dev, child, r)); 5765 } 5766 } 5767 5768 rl = &dinfo->resources; 5769 return (resource_list_release(rl, dev, child, r)); 5770 } 5771 5772 int 5773 pci_activate_resource(device_t dev, device_t child, struct resource *r) 5774 { 5775 struct pci_devinfo *dinfo; 5776 int error, rid, type; 5777 5778 if (device_get_parent(child) != dev) 5779 return (bus_generic_activate_resource(dev, child, r)); 5780 5781 dinfo = device_get_ivars(child); 5782 #ifdef PCI_IOV 5783 if (dinfo->cfg.flags & PCICFG_VF) { 5784 switch (rman_get_type(r)) { 5785 /* VFs can't have I/O BARs. */ 5786 case SYS_RES_IOPORT: 5787 error = EINVAL; 5788 break; 5789 case SYS_RES_MEMORY: 5790 error = pci_vf_activate_mem_resource(dev, child, r); 5791 break; 5792 default: 5793 error = bus_generic_activate_resource(dev, child, r); 5794 break; 5795 } 5796 } else 5797 #endif 5798 error = bus_generic_activate_resource(dev, child, r); 5799 if (error) 5800 return (error); 5801 5802 rid = rman_get_rid(r); 5803 type = rman_get_type(r); 5804 5805 /* Device ROMs need their decoding explicitly enabled. */ 5806 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5807 pci_write_bar(child, pci_find_bar(child, rid), 5808 rman_get_start(r) | PCIM_BIOS_ENABLE); 5809 5810 /* Enable decoding in the command register when activating BARs. */ 5811 switch (type) { 5812 case SYS_RES_IOPORT: 5813 case SYS_RES_MEMORY: 5814 error = PCI_ENABLE_IO(dev, child, type); 5815 break; 5816 } 5817 return (error); 5818 } 5819 5820 int 5821 pci_deactivate_resource(device_t dev, device_t child, struct resource *r) 5822 { 5823 struct pci_devinfo *dinfo; 5824 int error, rid, type; 5825 5826 if (device_get_parent(child) != dev) 5827 return (bus_generic_deactivate_resource(dev, child, r)); 5828 5829 dinfo = device_get_ivars(child); 5830 #ifdef PCI_IOV 5831 if (dinfo->cfg.flags & PCICFG_VF) { 5832 switch (rman_get_type(r)) { 5833 /* VFs can't have I/O BARs. */ 5834 case SYS_RES_IOPORT: 5835 error = EINVAL; 5836 break; 5837 case SYS_RES_MEMORY: 5838 error = pci_vf_deactivate_mem_resource(dev, child, r); 5839 break; 5840 default: 5841 error = bus_generic_deactivate_resource(dev, child, r); 5842 break; 5843 } 5844 } else 5845 #endif 5846 error = bus_generic_deactivate_resource(dev, child, r); 5847 if (error) 5848 return (error); 5849 5850 /* Disable decoding for device ROMs. */ 5851 rid = rman_get_rid(r); 5852 type = rman_get_type(r); 5853 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5854 pci_write_bar(child, pci_find_bar(child, rid), 5855 rman_get_start(r)); 5856 return (0); 5857 } 5858 5859 int 5860 pci_adjust_resource(device_t dev, device_t child, struct resource *r, 5861 rman_res_t start, rman_res_t end) 5862 { 5863 #ifdef PCI_IOV 5864 struct pci_devinfo *dinfo; 5865 5866 if (device_get_parent(child) != dev) 5867 return (bus_generic_adjust_resource(dev, child, r, start, 5868 end)); 5869 5870 dinfo = device_get_ivars(child); 5871 if (dinfo->cfg.flags & PCICFG_VF) { 5872 switch (rman_get_type(r)) { 5873 /* VFs can't have I/O BARs. */ 5874 case SYS_RES_IOPORT: 5875 return (EINVAL); 5876 case SYS_RES_MEMORY: 5877 return (pci_vf_adjust_mem_resource(dev, child, r, 5878 start, end)); 5879 } 5880 5881 /* Fall through for other types of resource allocations. */ 5882 } 5883 #endif 5884 5885 return (bus_generic_adjust_resource(dev, child, r, start, end)); 5886 } 5887 5888 int 5889 pci_map_resource(device_t dev, device_t child, struct resource *r, 5890 struct resource_map_request *argsp, struct resource_map *map) 5891 { 5892 #ifdef PCI_IOV 5893 struct pci_devinfo *dinfo; 5894 5895 if (device_get_parent(child) != dev) 5896 return (bus_generic_map_resource(dev, child, r, argsp, 5897 map)); 5898 5899 dinfo = device_get_ivars(child); 5900 if (dinfo->cfg.flags & PCICFG_VF) { 5901 switch (rman_get_type(r)) { 5902 /* VFs can't have I/O BARs. */ 5903 case SYS_RES_IOPORT: 5904 return (EINVAL); 5905 case SYS_RES_MEMORY: 5906 return (pci_vf_map_mem_resource(dev, child, r, argsp, 5907 map)); 5908 } 5909 5910 /* Fall through for other types of resource allocations. */ 5911 } 5912 #endif 5913 5914 return (bus_generic_map_resource(dev, child, r, argsp, map)); 5915 } 5916 5917 int 5918 pci_unmap_resource(device_t dev, device_t child, struct resource *r, 5919 struct resource_map *map) 5920 { 5921 #ifdef PCI_IOV 5922 struct pci_devinfo *dinfo; 5923 5924 if (device_get_parent(child) != dev) 5925 return (bus_generic_unmap_resource(dev, child, r, map)); 5926 5927 dinfo = device_get_ivars(child); 5928 if (dinfo->cfg.flags & PCICFG_VF) { 5929 switch (rman_get_type(r)) { 5930 /* VFs can't have I/O BARs. */ 5931 case SYS_RES_IOPORT: 5932 return (EINVAL); 5933 case SYS_RES_MEMORY: 5934 return (pci_vf_unmap_mem_resource(dev, child, r, map)); 5935 } 5936 5937 /* Fall through for other types of resource allocations. */ 5938 } 5939 #endif 5940 5941 return (bus_generic_unmap_resource(dev, child, r, map)); 5942 } 5943 5944 void 5945 pci_child_deleted(device_t dev, device_t child) 5946 { 5947 struct resource_list_entry *rle; 5948 struct resource_list *rl; 5949 struct pci_devinfo *dinfo; 5950 5951 dinfo = device_get_ivars(child); 5952 rl = &dinfo->resources; 5953 5954 EVENTHANDLER_INVOKE(pci_delete_device, child); 5955 5956 /* Turn off access to resources we're about to free */ 5957 if (bus_child_present(child) != 0) { 5958 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5959 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5960 5961 pci_disable_busmaster(child); 5962 } 5963 5964 /* Free all allocated resources */ 5965 STAILQ_FOREACH(rle, rl, link) { 5966 if (rle->res) { 5967 if (rman_get_flags(rle->res) & RF_ACTIVE || 5968 resource_list_busy(rl, rle->type, rle->rid)) { 5969 pci_printf(&dinfo->cfg, 5970 "Resource still owned, oops. " 5971 "(type=%d, rid=%d, addr=%lx)\n", 5972 rle->type, rle->rid, 5973 rman_get_start(rle->res)); 5974 bus_release_resource(child, rle->type, rle->rid, 5975 rle->res); 5976 } 5977 resource_list_unreserve(rl, dev, child, rle->type, 5978 rle->rid); 5979 } 5980 } 5981 resource_list_free(rl); 5982 5983 pci_freecfg(dinfo); 5984 } 5985 5986 void 5987 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5988 { 5989 struct pci_devinfo *dinfo; 5990 struct resource_list *rl; 5991 struct resource_list_entry *rle; 5992 5993 if (device_get_parent(child) != dev) 5994 return; 5995 5996 dinfo = device_get_ivars(child); 5997 rl = &dinfo->resources; 5998 rle = resource_list_find(rl, type, rid); 5999 if (rle == NULL) 6000 return; 6001 6002 if (rle->res) { 6003 if (rman_get_flags(rle->res) & RF_ACTIVE || 6004 resource_list_busy(rl, type, rid)) { 6005 device_printf(dev, "delete_resource: " 6006 "Resource still owned by child, oops. " 6007 "(type=%d, rid=%d, addr=%jx)\n", 6008 type, rid, rman_get_start(rle->res)); 6009 return; 6010 } 6011 resource_list_unreserve(rl, dev, child, type, rid); 6012 } 6013 resource_list_delete(rl, type, rid); 6014 } 6015 6016 struct resource_list * 6017 pci_get_resource_list (device_t dev, device_t child) 6018 { 6019 struct pci_devinfo *dinfo = device_get_ivars(child); 6020 6021 return (&dinfo->resources); 6022 } 6023 6024 #ifdef IOMMU 6025 bus_dma_tag_t 6026 pci_get_dma_tag(device_t bus, device_t dev) 6027 { 6028 bus_dma_tag_t tag; 6029 struct pci_softc *sc; 6030 6031 if (device_get_parent(dev) == bus) { 6032 /* try iommu and return if it works */ 6033 tag = iommu_get_dma_tag(bus, dev); 6034 } else 6035 tag = NULL; 6036 if (tag == NULL) { 6037 sc = device_get_softc(bus); 6038 tag = sc->sc_dma_tag; 6039 } 6040 return (tag); 6041 } 6042 #else 6043 bus_dma_tag_t 6044 pci_get_dma_tag(device_t bus, device_t dev) 6045 { 6046 struct pci_softc *sc = device_get_softc(bus); 6047 6048 return (sc->sc_dma_tag); 6049 } 6050 #endif 6051 6052 uint32_t 6053 pci_read_config_method(device_t dev, device_t child, int reg, int width) 6054 { 6055 struct pci_devinfo *dinfo = device_get_ivars(child); 6056 pcicfgregs *cfg = &dinfo->cfg; 6057 6058 #ifdef PCI_IOV 6059 /* 6060 * SR-IOV VFs don't implement the VID or DID registers, so we have to 6061 * emulate them here. 6062 */ 6063 if (cfg->flags & PCICFG_VF) { 6064 if (reg == PCIR_VENDOR) { 6065 switch (width) { 6066 case 4: 6067 return (cfg->device << 16 | cfg->vendor); 6068 case 2: 6069 return (cfg->vendor); 6070 case 1: 6071 return (cfg->vendor & 0xff); 6072 default: 6073 return (0xffffffff); 6074 } 6075 } else if (reg == PCIR_DEVICE) { 6076 switch (width) { 6077 /* Note that an unaligned 4-byte read is an error. */ 6078 case 2: 6079 return (cfg->device); 6080 case 1: 6081 return (cfg->device & 0xff); 6082 default: 6083 return (0xffffffff); 6084 } 6085 } 6086 } 6087 #endif 6088 6089 return (PCIB_READ_CONFIG(device_get_parent(dev), 6090 cfg->bus, cfg->slot, cfg->func, reg, width)); 6091 } 6092 6093 void 6094 pci_write_config_method(device_t dev, device_t child, int reg, 6095 uint32_t val, int width) 6096 { 6097 struct pci_devinfo *dinfo = device_get_ivars(child); 6098 pcicfgregs *cfg = &dinfo->cfg; 6099 6100 PCIB_WRITE_CONFIG(device_get_parent(dev), 6101 cfg->bus, cfg->slot, cfg->func, reg, val, width); 6102 } 6103 6104 int 6105 pci_child_location_method(device_t dev, device_t child, struct sbuf *sb) 6106 { 6107 6108 sbuf_printf(sb, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 6109 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 6110 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 6111 return (0); 6112 } 6113 6114 int 6115 pci_child_pnpinfo_method(device_t dev, device_t child, struct sbuf *sb) 6116 { 6117 struct pci_devinfo *dinfo; 6118 pcicfgregs *cfg; 6119 6120 dinfo = device_get_ivars(child); 6121 cfg = &dinfo->cfg; 6122 sbuf_printf(sb, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 6123 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 6124 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 6125 cfg->progif); 6126 return (0); 6127 } 6128 6129 int 6130 pci_get_device_path_method(device_t bus, device_t child, const char *locator, 6131 struct sbuf *sb) 6132 { 6133 device_t parent = device_get_parent(bus); 6134 int rv; 6135 6136 if (strcmp(locator, BUS_LOCATOR_UEFI) == 0) { 6137 rv = bus_generic_get_device_path(parent, bus, locator, sb); 6138 if (rv == 0) { 6139 sbuf_printf(sb, "/Pci(0x%x,0x%x)", pci_get_slot(child), 6140 pci_get_function(child)); 6141 } 6142 return (0); 6143 } 6144 return (bus_generic_get_device_path(bus, child, locator, sb)); 6145 } 6146 6147 int 6148 pci_assign_interrupt_method(device_t dev, device_t child) 6149 { 6150 struct pci_devinfo *dinfo = device_get_ivars(child); 6151 pcicfgregs *cfg = &dinfo->cfg; 6152 6153 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 6154 cfg->intpin)); 6155 } 6156 6157 static void 6158 pci_lookup(void *arg, const char *name, device_t *dev) 6159 { 6160 long val; 6161 char *end; 6162 int domain, bus, slot, func; 6163 6164 if (*dev != NULL) 6165 return; 6166 6167 /* 6168 * Accept pciconf-style selectors of either pciD:B:S:F or 6169 * pciB:S:F. In the latter case, the domain is assumed to 6170 * be zero. 6171 */ 6172 if (strncmp(name, "pci", 3) != 0) 6173 return; 6174 val = strtol(name + 3, &end, 10); 6175 if (val < 0 || val > INT_MAX || *end != ':') 6176 return; 6177 domain = val; 6178 val = strtol(end + 1, &end, 10); 6179 if (val < 0 || val > INT_MAX || *end != ':') 6180 return; 6181 bus = val; 6182 val = strtol(end + 1, &end, 10); 6183 if (val < 0 || val > INT_MAX) 6184 return; 6185 slot = val; 6186 if (*end == ':') { 6187 val = strtol(end + 1, &end, 10); 6188 if (val < 0 || val > INT_MAX || *end != '\0') 6189 return; 6190 func = val; 6191 } else if (*end == '\0') { 6192 func = slot; 6193 slot = bus; 6194 bus = domain; 6195 domain = 0; 6196 } else 6197 return; 6198 6199 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 6200 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 6201 return; 6202 6203 *dev = pci_find_dbsf(domain, bus, slot, func); 6204 } 6205 6206 static int 6207 pci_modevent(module_t mod, int what, void *arg) 6208 { 6209 static struct cdev *pci_cdev; 6210 static eventhandler_tag tag; 6211 6212 switch (what) { 6213 case MOD_LOAD: 6214 STAILQ_INIT(&pci_devq); 6215 pci_generation = 0; 6216 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 6217 "pci"); 6218 pci_load_vendor_data(); 6219 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 6220 1000); 6221 break; 6222 6223 case MOD_UNLOAD: 6224 if (tag != NULL) 6225 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 6226 destroy_dev(pci_cdev); 6227 break; 6228 } 6229 6230 return (0); 6231 } 6232 6233 static void 6234 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 6235 { 6236 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 6237 struct pcicfg_pcie *cfg; 6238 int version, pos; 6239 6240 cfg = &dinfo->cfg.pcie; 6241 pos = cfg->pcie_location; 6242 6243 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6244 6245 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 6246 6247 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6248 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6249 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6250 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 6251 6252 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6253 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6254 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6255 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 6256 6257 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6258 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6259 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 6260 6261 if (version > 1) { 6262 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 6263 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 6264 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 6265 } 6266 #undef WREG 6267 } 6268 6269 static void 6270 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 6271 { 6272 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 6273 dinfo->cfg.pcix.pcix_command, 2); 6274 } 6275 6276 void 6277 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 6278 { 6279 6280 /* 6281 * Restore the device to full power mode. We must do this 6282 * before we restore the registers because moving from D3 to 6283 * D0 will cause the chip's BARs and some other registers to 6284 * be reset to some unknown power on reset values. Cut down 6285 * the noise on boot by doing nothing if we are already in 6286 * state D0. 6287 */ 6288 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 6289 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6290 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 6291 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 6292 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 6293 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 6294 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 6295 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 6296 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6297 case PCIM_HDRTYPE_NORMAL: 6298 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 6299 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 6300 break; 6301 case PCIM_HDRTYPE_BRIDGE: 6302 pci_write_config(dev, PCIR_SECLAT_1, 6303 dinfo->cfg.bridge.br_seclat, 1); 6304 pci_write_config(dev, PCIR_SUBBUS_1, 6305 dinfo->cfg.bridge.br_subbus, 1); 6306 pci_write_config(dev, PCIR_SECBUS_1, 6307 dinfo->cfg.bridge.br_secbus, 1); 6308 pci_write_config(dev, PCIR_PRIBUS_1, 6309 dinfo->cfg.bridge.br_pribus, 1); 6310 pci_write_config(dev, PCIR_BRIDGECTL_1, 6311 dinfo->cfg.bridge.br_control, 2); 6312 break; 6313 case PCIM_HDRTYPE_CARDBUS: 6314 pci_write_config(dev, PCIR_SECLAT_2, 6315 dinfo->cfg.bridge.br_seclat, 1); 6316 pci_write_config(dev, PCIR_SUBBUS_2, 6317 dinfo->cfg.bridge.br_subbus, 1); 6318 pci_write_config(dev, PCIR_SECBUS_2, 6319 dinfo->cfg.bridge.br_secbus, 1); 6320 pci_write_config(dev, PCIR_PRIBUS_2, 6321 dinfo->cfg.bridge.br_pribus, 1); 6322 pci_write_config(dev, PCIR_BRIDGECTL_2, 6323 dinfo->cfg.bridge.br_control, 2); 6324 break; 6325 } 6326 pci_restore_bars(dev); 6327 6328 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) 6329 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 6330 6331 /* 6332 * Restore extended capabilities for PCI-Express and PCI-X 6333 */ 6334 if (dinfo->cfg.pcie.pcie_location != 0) 6335 pci_cfg_restore_pcie(dev, dinfo); 6336 if (dinfo->cfg.pcix.pcix_location != 0) 6337 pci_cfg_restore_pcix(dev, dinfo); 6338 6339 /* Restore MSI and MSI-X configurations if they are present. */ 6340 if (dinfo->cfg.msi.msi_location != 0) 6341 pci_resume_msi(dev); 6342 if (dinfo->cfg.msix.msix_location != 0) 6343 pci_resume_msix(dev); 6344 6345 #ifdef PCI_IOV 6346 if (dinfo->cfg.iov != NULL) 6347 pci_iov_cfg_restore(dev, dinfo); 6348 #endif 6349 } 6350 6351 static void 6352 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 6353 { 6354 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6355 struct pcicfg_pcie *cfg; 6356 int version, pos; 6357 6358 cfg = &dinfo->cfg.pcie; 6359 pos = cfg->pcie_location; 6360 6361 cfg->pcie_flags = RREG(PCIER_FLAGS); 6362 6363 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6364 6365 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6366 6367 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6368 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6369 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6370 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6371 6372 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6373 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6374 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6375 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6376 6377 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6378 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6379 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6380 6381 if (version > 1) { 6382 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6383 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6384 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6385 } 6386 #undef RREG 6387 } 6388 6389 static void 6390 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6391 { 6392 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6393 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6394 } 6395 6396 void 6397 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6398 { 6399 uint32_t cls; 6400 int ps; 6401 6402 /* 6403 * Some drivers apparently write to these registers w/o updating our 6404 * cached copy. No harm happens if we update the copy, so do so here 6405 * so we can restore them. The COMMAND register is modified by the 6406 * bus w/o updating the cache. This should represent the normally 6407 * writable portion of the 'defined' part of type 0/1/2 headers. 6408 */ 6409 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6410 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6411 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6412 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6413 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6414 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6415 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6416 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6417 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6418 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6419 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6420 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6421 case PCIM_HDRTYPE_NORMAL: 6422 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6423 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6424 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6425 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6426 break; 6427 case PCIM_HDRTYPE_BRIDGE: 6428 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6429 PCIR_SECLAT_1, 1); 6430 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6431 PCIR_SUBBUS_1, 1); 6432 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6433 PCIR_SECBUS_1, 1); 6434 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6435 PCIR_PRIBUS_1, 1); 6436 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6437 PCIR_BRIDGECTL_1, 2); 6438 break; 6439 case PCIM_HDRTYPE_CARDBUS: 6440 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6441 PCIR_SECLAT_2, 1); 6442 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6443 PCIR_SUBBUS_2, 1); 6444 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6445 PCIR_SECBUS_2, 1); 6446 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6447 PCIR_PRIBUS_2, 1); 6448 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6449 PCIR_BRIDGECTL_2, 2); 6450 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6451 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6452 break; 6453 } 6454 6455 if (dinfo->cfg.pcie.pcie_location != 0) 6456 pci_cfg_save_pcie(dev, dinfo); 6457 6458 if (dinfo->cfg.pcix.pcix_location != 0) 6459 pci_cfg_save_pcix(dev, dinfo); 6460 6461 #ifdef PCI_IOV 6462 if (dinfo->cfg.iov != NULL) 6463 pci_iov_cfg_save(dev, dinfo); 6464 #endif 6465 6466 /* 6467 * don't set the state for display devices, base peripherals and 6468 * memory devices since bad things happen when they are powered down. 6469 * We should (a) have drivers that can easily detach and (b) use 6470 * generic drivers for these devices so that some device actually 6471 * attaches. We need to make sure that when we implement (a) we don't 6472 * power the device down on a reattach. 6473 */ 6474 cls = pci_get_class(dev); 6475 if (!setstate) 6476 return; 6477 switch (pci_do_power_nodriver) 6478 { 6479 case 0: /* NO powerdown at all */ 6480 return; 6481 case 1: /* Conservative about what to power down */ 6482 if (cls == PCIC_STORAGE) 6483 return; 6484 /*FALLTHROUGH*/ 6485 case 2: /* Aggressive about what to power down */ 6486 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6487 cls == PCIC_BASEPERIPH) 6488 return; 6489 /*FALLTHROUGH*/ 6490 case 3: /* Power down everything */ 6491 break; 6492 } 6493 /* 6494 * PCI spec says we can only go into D3 state from D0 state. 6495 * Transition from D[12] into D0 before going to D3 state. 6496 */ 6497 ps = pci_get_powerstate(dev); 6498 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6499 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6500 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6501 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6502 } 6503 6504 /* Wrapper APIs suitable for device driver use. */ 6505 void 6506 pci_save_state(device_t dev) 6507 { 6508 struct pci_devinfo *dinfo; 6509 6510 dinfo = device_get_ivars(dev); 6511 pci_cfg_save(dev, dinfo, 0); 6512 } 6513 6514 void 6515 pci_restore_state(device_t dev) 6516 { 6517 struct pci_devinfo *dinfo; 6518 6519 dinfo = device_get_ivars(dev); 6520 pci_cfg_restore(dev, dinfo); 6521 } 6522 6523 static int 6524 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6525 uintptr_t *id) 6526 { 6527 6528 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6529 } 6530 6531 /* Find the upstream port of a given PCI device in a root complex. */ 6532 device_t 6533 pci_find_pcie_root_port(device_t dev) 6534 { 6535 struct pci_devinfo *dinfo; 6536 devclass_t pci_class; 6537 device_t pcib, bus; 6538 6539 pci_class = devclass_find("pci"); 6540 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6541 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6542 6543 /* 6544 * Walk the bridge hierarchy until we find a PCI-e root 6545 * port or a non-PCI device. 6546 */ 6547 for (;;) { 6548 bus = device_get_parent(dev); 6549 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6550 device_get_nameunit(dev))); 6551 6552 pcib = device_get_parent(bus); 6553 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6554 device_get_nameunit(bus))); 6555 6556 /* 6557 * pcib's parent must be a PCI bus for this to be a 6558 * PCI-PCI bridge. 6559 */ 6560 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6561 return (NULL); 6562 6563 dinfo = device_get_ivars(pcib); 6564 if (dinfo->cfg.pcie.pcie_location != 0 && 6565 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6566 return (pcib); 6567 6568 dev = pcib; 6569 } 6570 } 6571 6572 /* 6573 * Wait for pending transactions to complete on a PCI-express function. 6574 * 6575 * The maximum delay is specified in milliseconds in max_delay. Note 6576 * that this function may sleep. 6577 * 6578 * Returns true if the function is idle and false if the timeout is 6579 * exceeded. If dev is not a PCI-express function, this returns true. 6580 */ 6581 bool 6582 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6583 { 6584 struct pci_devinfo *dinfo = device_get_ivars(dev); 6585 uint16_t sta; 6586 int cap; 6587 6588 cap = dinfo->cfg.pcie.pcie_location; 6589 if (cap == 0) 6590 return (true); 6591 6592 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6593 while (sta & PCIEM_STA_TRANSACTION_PND) { 6594 if (max_delay == 0) 6595 return (false); 6596 6597 /* Poll once every 100 milliseconds up to the timeout. */ 6598 if (max_delay > 100) { 6599 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6600 max_delay -= 100; 6601 } else { 6602 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6603 C_HARDCLOCK); 6604 max_delay = 0; 6605 } 6606 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6607 } 6608 6609 return (true); 6610 } 6611 6612 /* 6613 * Determine the maximum Completion Timeout in microseconds. 6614 * 6615 * For non-PCI-express functions this returns 0. 6616 */ 6617 int 6618 pcie_get_max_completion_timeout(device_t dev) 6619 { 6620 struct pci_devinfo *dinfo = device_get_ivars(dev); 6621 int cap; 6622 6623 cap = dinfo->cfg.pcie.pcie_location; 6624 if (cap == 0) 6625 return (0); 6626 6627 /* 6628 * Functions using the 1.x spec use the default timeout range of 6629 * 50 microseconds to 50 milliseconds. Functions that do not 6630 * support programmable timeouts also use this range. 6631 */ 6632 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6633 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6634 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6635 return (50 * 1000); 6636 6637 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6638 PCIEM_CTL2_COMP_TIMO_VAL) { 6639 case PCIEM_CTL2_COMP_TIMO_100US: 6640 return (100); 6641 case PCIEM_CTL2_COMP_TIMO_10MS: 6642 return (10 * 1000); 6643 case PCIEM_CTL2_COMP_TIMO_55MS: 6644 return (55 * 1000); 6645 case PCIEM_CTL2_COMP_TIMO_210MS: 6646 return (210 * 1000); 6647 case PCIEM_CTL2_COMP_TIMO_900MS: 6648 return (900 * 1000); 6649 case PCIEM_CTL2_COMP_TIMO_3500MS: 6650 return (3500 * 1000); 6651 case PCIEM_CTL2_COMP_TIMO_13S: 6652 return (13 * 1000 * 1000); 6653 case PCIEM_CTL2_COMP_TIMO_64S: 6654 return (64 * 1000 * 1000); 6655 default: 6656 return (50 * 1000); 6657 } 6658 } 6659 6660 void 6661 pcie_apei_error(device_t dev, int sev, uint8_t *aerp) 6662 { 6663 struct pci_devinfo *dinfo = device_get_ivars(dev); 6664 const char *s; 6665 int aer; 6666 uint32_t r, r1; 6667 uint16_t rs; 6668 6669 if (sev == PCIEM_STA_CORRECTABLE_ERROR) 6670 s = "Correctable"; 6671 else if (sev == PCIEM_STA_NON_FATAL_ERROR) 6672 s = "Uncorrectable (Non-Fatal)"; 6673 else 6674 s = "Uncorrectable (Fatal)"; 6675 device_printf(dev, "%s PCIe error reported by APEI\n", s); 6676 if (aerp) { 6677 if (sev == PCIEM_STA_CORRECTABLE_ERROR) { 6678 r = le32dec(aerp + PCIR_AER_COR_STATUS); 6679 r1 = le32dec(aerp + PCIR_AER_COR_MASK); 6680 } else { 6681 r = le32dec(aerp + PCIR_AER_UC_STATUS); 6682 r1 = le32dec(aerp + PCIR_AER_UC_MASK); 6683 } 6684 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1); 6685 if (sev != PCIEM_STA_CORRECTABLE_ERROR) { 6686 r = le32dec(aerp + PCIR_AER_UC_SEVERITY); 6687 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL); 6688 printf(" severity 0x%08x first %d\n", 6689 r, rs & 0x1f); 6690 } else 6691 printf("\n"); 6692 } 6693 6694 /* As kind of recovery just report and clear the error statuses. */ 6695 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6696 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6697 if (r != 0) { 6698 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6699 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r); 6700 } 6701 6702 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6703 if (r != 0) { 6704 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6705 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r); 6706 } 6707 } 6708 if (dinfo->cfg.pcie.pcie_location != 0) { 6709 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6710 PCIER_DEVICE_STA, 2); 6711 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR | 6712 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6713 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6714 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6715 PCIER_DEVICE_STA, rs, 2); 6716 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs); 6717 } 6718 } 6719 } 6720 6721 /* 6722 * Perform a Function Level Reset (FLR) on a device. 6723 * 6724 * This function first waits for any pending transactions to complete 6725 * within the timeout specified by max_delay. If transactions are 6726 * still pending, the function will return false without attempting a 6727 * reset. 6728 * 6729 * If dev is not a PCI-express function or does not support FLR, this 6730 * function returns false. 6731 * 6732 * Note that no registers are saved or restored. The caller is 6733 * responsible for saving and restoring any registers including 6734 * PCI-standard registers via pci_save_state() and 6735 * pci_restore_state(). 6736 */ 6737 bool 6738 pcie_flr(device_t dev, u_int max_delay, bool force) 6739 { 6740 struct pci_devinfo *dinfo = device_get_ivars(dev); 6741 uint16_t cmd, ctl; 6742 int compl_delay; 6743 int cap; 6744 6745 cap = dinfo->cfg.pcie.pcie_location; 6746 if (cap == 0) 6747 return (false); 6748 6749 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6750 return (false); 6751 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_FLR)) 6752 return (false); 6753 6754 /* 6755 * Disable busmastering to prevent generation of new 6756 * transactions while waiting for the device to go idle. If 6757 * the idle timeout fails, the command register is restored 6758 * which will re-enable busmastering. 6759 */ 6760 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6761 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6762 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6763 if (!force) { 6764 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6765 return (false); 6766 } 6767 pci_printf(&dinfo->cfg, 6768 "Resetting with transactions pending after %d ms\n", 6769 max_delay); 6770 6771 /* 6772 * Extend the post-FLR delay to cover the maximum 6773 * Completion Timeout delay of anything in flight 6774 * during the FLR delay. Enforce a minimum delay of 6775 * at least 10ms. 6776 */ 6777 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6778 if (compl_delay < 10) 6779 compl_delay = 10; 6780 } else 6781 compl_delay = 0; 6782 6783 /* Initiate the reset. */ 6784 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6785 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6786 PCIEM_CTL_INITIATE_FLR, 2); 6787 6788 /* Wait for 100ms. */ 6789 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6790 6791 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6792 PCIEM_STA_TRANSACTION_PND) 6793 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6794 return (true); 6795 } 6796 6797 /* 6798 * Attempt a power-management reset by cycling the device in/out of D3 6799 * state. PCI spec says we can only go into D3 state from D0 state. 6800 * Transition from D[12] into D0 before going to D3 state. 6801 */ 6802 int 6803 pci_power_reset(device_t dev) 6804 { 6805 int ps; 6806 6807 ps = pci_get_powerstate(dev); 6808 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6809 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6810 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6811 pci_set_powerstate(dev, ps); 6812 return (0); 6813 } 6814 6815 /* 6816 * Try link drop and retrain of the downstream port of upstream 6817 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6818 * cause Conventional Hot reset of the device in the slot. 6819 * Alternative, for PCIe, could be the secondary bus reset initiatied 6820 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6821 */ 6822 int 6823 pcie_link_reset(device_t port, int pcie_location) 6824 { 6825 uint16_t v; 6826 6827 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6828 v |= PCIEM_LINK_CTL_LINK_DIS; 6829 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6830 pause_sbt("pcier1", mstosbt(20), 0, 0); 6831 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6832 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6833 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6834 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6835 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6836 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6837 } 6838 6839 static int 6840 pci_reset_post(device_t dev, device_t child) 6841 { 6842 6843 if (dev == device_get_parent(child)) 6844 pci_restore_state(child); 6845 return (0); 6846 } 6847 6848 static int 6849 pci_reset_prepare(device_t dev, device_t child) 6850 { 6851 6852 if (dev == device_get_parent(child)) 6853 pci_save_state(child); 6854 return (0); 6855 } 6856 6857 static int 6858 pci_reset_child(device_t dev, device_t child, int flags) 6859 { 6860 int error; 6861 6862 if (dev == NULL || device_get_parent(child) != dev) 6863 return (0); 6864 if ((flags & DEVF_RESET_DETACH) != 0) { 6865 error = device_get_state(child) == DS_ATTACHED ? 6866 device_detach(child) : 0; 6867 } else { 6868 error = BUS_SUSPEND_CHILD(dev, child); 6869 } 6870 if (error == 0) { 6871 if (!pcie_flr(child, 1000, false)) { 6872 error = BUS_RESET_PREPARE(dev, child); 6873 if (error == 0) 6874 pci_power_reset(child); 6875 BUS_RESET_POST(dev, child); 6876 } 6877 if ((flags & DEVF_RESET_DETACH) != 0) 6878 device_probe_and_attach(child); 6879 else 6880 BUS_RESUME_CHILD(dev, child); 6881 } 6882 return (error); 6883 } 6884 6885 const struct pci_device_table * 6886 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6887 { 6888 bool match; 6889 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6890 6891 vendor = pci_get_vendor(child); 6892 device = pci_get_device(child); 6893 subvendor = pci_get_subvendor(child); 6894 subdevice = pci_get_subdevice(child); 6895 class = pci_get_class(child); 6896 subclass = pci_get_subclass(child); 6897 revid = pci_get_revid(child); 6898 while (nelt-- > 0) { 6899 match = true; 6900 if (id->match_flag_vendor) 6901 match &= vendor == id->vendor; 6902 if (id->match_flag_device) 6903 match &= device == id->device; 6904 if (id->match_flag_subvendor) 6905 match &= subvendor == id->subvendor; 6906 if (id->match_flag_subdevice) 6907 match &= subdevice == id->subdevice; 6908 if (id->match_flag_class) 6909 match &= class == id->class_id; 6910 if (id->match_flag_subclass) 6911 match &= subclass == id->subclass; 6912 if (id->match_flag_revid) 6913 match &= revid == id->revid; 6914 if (match) 6915 return (id); 6916 id++; 6917 } 6918 return (NULL); 6919 } 6920 6921 static void 6922 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6923 { 6924 const char *dev_name; 6925 device_t dev; 6926 6927 dev = dinfo->cfg.dev; 6928 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6929 dinfo->cfg.slot, dinfo->cfg.func); 6930 dev_name = device_get_name(dev); 6931 if (dev_name != NULL) 6932 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6933 } 6934 6935 void 6936 pci_print_faulted_dev(void) 6937 { 6938 struct pci_devinfo *dinfo; 6939 device_t dev; 6940 int aer, i; 6941 uint32_t r1, r2; 6942 uint16_t status; 6943 6944 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6945 dev = dinfo->cfg.dev; 6946 status = pci_read_config(dev, PCIR_STATUS, 2); 6947 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6948 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6949 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6950 if (status != 0) { 6951 pci_print_faulted_dev_name(dinfo); 6952 printf(" error 0x%04x\n", status); 6953 } 6954 if (dinfo->cfg.pcie.pcie_location != 0) { 6955 status = pci_read_config(dev, 6956 dinfo->cfg.pcie.pcie_location + 6957 PCIER_DEVICE_STA, 2); 6958 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6959 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6960 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6961 pci_print_faulted_dev_name(dinfo); 6962 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6963 pci_read_config(dev, 6964 dinfo->cfg.pcie.pcie_location + 6965 PCIER_DEVICE_CTL, 2), 6966 status); 6967 } 6968 } 6969 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6970 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6971 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6972 if (r1 != 0 || r2 != 0) { 6973 pci_print_faulted_dev_name(dinfo); 6974 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6975 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6976 r1, pci_read_config(dev, aer + 6977 PCIR_AER_UC_MASK, 4), 6978 pci_read_config(dev, aer + 6979 PCIR_AER_UC_SEVERITY, 4), 6980 r2, pci_read_config(dev, aer + 6981 PCIR_AER_COR_MASK, 4), 6982 pci_read_config(dev, aer + 6983 PCIR_AER_CAP_CONTROL, 4)); 6984 for (i = 0; i < 4; i++) { 6985 r1 = pci_read_config(dev, aer + 6986 PCIR_AER_HEADER_LOG + i * 4, 4); 6987 printf(" HL%d: 0x%08x\n", i, r1); 6988 } 6989 } 6990 } 6991 } 6992 } 6993 6994 #ifdef DDB 6995 DB_SHOW_COMMAND_FLAGS(pcierr, pci_print_faulted_dev_db, DB_CMD_MEMSAFE) 6996 { 6997 6998 pci_print_faulted_dev(); 6999 } 7000 7001 static void 7002 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 7003 { 7004 device_t dev; 7005 int aer; 7006 uint32_t r; 7007 7008 dev = dinfo->cfg.dev; 7009 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 7010 PCIER_DEVICE_STA, 2); 7011 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 7012 PCIER_DEVICE_STA, r, 2); 7013 7014 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 7015 return; 7016 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 7017 if (r != 0) 7018 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 7019 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 7020 if (r != 0) 7021 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 7022 } 7023 7024 DB_COMMAND_FLAGS(pci_clearerr, db_pci_clearerr, DB_CMD_MEMSAFE) 7025 { 7026 struct pci_devinfo *dinfo; 7027 device_t dev; 7028 uint16_t status, status1; 7029 7030 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 7031 dev = dinfo->cfg.dev; 7032 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 7033 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 7034 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 7035 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 7036 if (status1 != 0) { 7037 status &= ~status1; 7038 pci_write_config(dev, PCIR_STATUS, status, 2); 7039 } 7040 if (dinfo->cfg.pcie.pcie_location != 0) 7041 db_clear_pcie_errors(dinfo); 7042 } 7043 } 7044 #endif 7045