1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * intel_hdmi_audio.c - Intel HDMI audio driver
4 *
5 * Copyright (C) 2016 Intel Corp
6 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
7 * Ramesh Babu K V <ramesh.babu@intel.com>
8 * Vaibhav Agarwal <vaibhav.agarwal@intel.com>
9 * Jerome Anand <jerome.anand@intel.com>
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
13 * ALSA driver for Intel HDMI audio
14 */
15
16 #include <linux/types.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/interrupt.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/delay.h>
25 #include <linux/string.h>
26 #include <sound/core.h>
27 #include <sound/asoundef.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/initval.h>
31 #include <sound/control.h>
32 #include <sound/jack.h>
33 #include <drm/drm_edid.h>
34 #include <drm/drm_eld.h>
35 #include <drm/intel/intel_lpe_audio.h>
36 #include "intel_hdmi_audio.h"
37
38 #define INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS 5000
39
40 #define for_each_pipe(card_ctx, pipe) \
41 for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++)
42 #define for_each_port(card_ctx, port) \
43 for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++)
44
45 /*standard module options for ALSA. This module supports only one card*/
46 static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
47 static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
48 static bool single_port;
49
50 module_param_named(index, hdmi_card_index, int, 0444);
51 MODULE_PARM_DESC(index,
52 "Index value for INTEL Intel HDMI Audio controller.");
53 module_param_named(id, hdmi_card_id, charp, 0444);
54 MODULE_PARM_DESC(id,
55 "ID string for INTEL Intel HDMI Audio controller.");
56 module_param(single_port, bool, 0444);
57 MODULE_PARM_DESC(single_port,
58 "Single-port mode (for compatibility)");
59
60 /*
61 * ELD SA bits in the CEA Speaker Allocation data block
62 */
63 static const int eld_speaker_allocation_bits[] = {
64 [0] = FL | FR,
65 [1] = LFE,
66 [2] = FC,
67 [3] = RL | RR,
68 [4] = RC,
69 [5] = FLC | FRC,
70 [6] = RLC | RRC,
71 /* the following are not defined in ELD yet */
72 [7] = 0,
73 };
74
75 /*
76 * This is an ordered list!
77 *
78 * The preceding ones have better chances to be selected by
79 * hdmi_channel_allocation().
80 */
81 static struct cea_channel_speaker_allocation channel_allocations[] = {
82 /* channel: 7 6 5 4 3 2 1 0 */
83 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
84 /* 2.1 */
85 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
86 /* Dolby Surround */
87 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
88 /* surround40 */
89 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
90 /* surround41 */
91 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
92 /* surround50 */
93 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
94 /* surround51 */
95 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
96 /* 6.1 */
97 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
98 /* surround71 */
99 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
100
101 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
102 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
103 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
104 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
105 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
106 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
107 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
108 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
109 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
110 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
111 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
112 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
113 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
114 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
115 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
116 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
117 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
118 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
119 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
120 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
121 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
122 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
123 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
124 };
125
126 static const struct channel_map_table map_tables[] = {
127 { SNDRV_CHMAP_FL, 0x00, FL },
128 { SNDRV_CHMAP_FR, 0x01, FR },
129 { SNDRV_CHMAP_RL, 0x04, RL },
130 { SNDRV_CHMAP_RR, 0x05, RR },
131 { SNDRV_CHMAP_LFE, 0x02, LFE },
132 { SNDRV_CHMAP_FC, 0x03, FC },
133 { SNDRV_CHMAP_RLC, 0x06, RLC },
134 { SNDRV_CHMAP_RRC, 0x07, RRC },
135 {} /* terminator */
136 };
137
138 /* hardware capability structure */
139 static const struct snd_pcm_hardware had_pcm_hardware = {
140 .info = (SNDRV_PCM_INFO_INTERLEAVED |
141 SNDRV_PCM_INFO_MMAP |
142 SNDRV_PCM_INFO_MMAP_VALID |
143 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
144 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
145 SNDRV_PCM_FMTBIT_S24_LE |
146 SNDRV_PCM_FMTBIT_S32_LE),
147 .rates = SNDRV_PCM_RATE_32000 |
148 SNDRV_PCM_RATE_44100 |
149 SNDRV_PCM_RATE_48000 |
150 SNDRV_PCM_RATE_88200 |
151 SNDRV_PCM_RATE_96000 |
152 SNDRV_PCM_RATE_176400 |
153 SNDRV_PCM_RATE_192000,
154 .rate_min = HAD_MIN_RATE,
155 .rate_max = HAD_MAX_RATE,
156 .channels_min = HAD_MIN_CHANNEL,
157 .channels_max = HAD_MAX_CHANNEL,
158 .buffer_bytes_max = HAD_MAX_BUFFER,
159 .period_bytes_min = HAD_MIN_PERIOD_BYTES,
160 .period_bytes_max = HAD_MAX_PERIOD_BYTES,
161 .periods_min = HAD_MIN_PERIODS,
162 .periods_max = HAD_MAX_PERIODS,
163 .fifo_size = HAD_FIFO_SIZE,
164 };
165
166 /* Get the active PCM substream;
167 * Call had_substream_put() for unreferecing.
168 * Don't call this inside had_spinlock, as it takes by itself
169 */
170 static struct snd_pcm_substream *
had_substream_get(struct snd_intelhad * intelhaddata)171 had_substream_get(struct snd_intelhad *intelhaddata)
172 {
173 struct snd_pcm_substream *substream;
174 unsigned long flags;
175
176 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
177 substream = intelhaddata->stream_info.substream;
178 if (substream)
179 intelhaddata->stream_info.substream_refcount++;
180 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
181 return substream;
182 }
183
184 /* Unref the active PCM substream;
185 * Don't call this inside had_spinlock, as it takes by itself
186 */
had_substream_put(struct snd_intelhad * intelhaddata)187 static void had_substream_put(struct snd_intelhad *intelhaddata)
188 {
189 unsigned long flags;
190
191 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
192 intelhaddata->stream_info.substream_refcount--;
193 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
194 }
195
had_config_offset(int pipe)196 static u32 had_config_offset(int pipe)
197 {
198 switch (pipe) {
199 default:
200 case 0:
201 return AUDIO_HDMI_CONFIG_A;
202 case 1:
203 return AUDIO_HDMI_CONFIG_B;
204 case 2:
205 return AUDIO_HDMI_CONFIG_C;
206 }
207 }
208
209 /* Register access functions */
had_read_register_raw(struct snd_intelhad_card * card_ctx,int pipe,u32 reg)210 static u32 had_read_register_raw(struct snd_intelhad_card *card_ctx,
211 int pipe, u32 reg)
212 {
213 return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg);
214 }
215
had_write_register_raw(struct snd_intelhad_card * card_ctx,int pipe,u32 reg,u32 val)216 static void had_write_register_raw(struct snd_intelhad_card *card_ctx,
217 int pipe, u32 reg, u32 val)
218 {
219 iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg);
220 }
221
had_read_register(struct snd_intelhad * ctx,u32 reg,u32 * val)222 static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val)
223 {
224 if (!ctx->connected)
225 *val = 0;
226 else
227 *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg);
228 }
229
had_write_register(struct snd_intelhad * ctx,u32 reg,u32 val)230 static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val)
231 {
232 if (ctx->connected)
233 had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val);
234 }
235
236 /*
237 * enable / disable audio configuration
238 *
239 * The normal read/modify should not directly be used on VLV2 for
240 * updating AUD_CONFIG register.
241 * This is because:
242 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
243 * HDMI IP. As a result a read-modify of AUD_CONFIG register will always
244 * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
245 * register. This field should be 1xy binary for configuration with 6 or
246 * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
247 * causes the "channels" field to be updated as 0xy binary resulting in
248 * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
249 * appropriate value when doing read-modify of AUD_CONFIG register.
250 */
had_enable_audio(struct snd_intelhad * intelhaddata,bool enable)251 static void had_enable_audio(struct snd_intelhad *intelhaddata,
252 bool enable)
253 {
254 /* update the cached value */
255 intelhaddata->aud_config.regx.aud_en = enable;
256 had_write_register(intelhaddata, AUD_CONFIG,
257 intelhaddata->aud_config.regval);
258 }
259
260 /* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */
had_ack_irqs(struct snd_intelhad * ctx)261 static void had_ack_irqs(struct snd_intelhad *ctx)
262 {
263 u32 status_reg;
264
265 if (!ctx->connected)
266 return;
267 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
268 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
269 had_write_register(ctx, AUD_HDMI_STATUS, status_reg);
270 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
271 }
272
273 /* Reset buffer pointers */
had_reset_audio(struct snd_intelhad * intelhaddata)274 static void had_reset_audio(struct snd_intelhad *intelhaddata)
275 {
276 had_write_register(intelhaddata, AUD_HDMI_STATUS,
277 AUD_HDMI_STATUSG_MASK_FUNCRST);
278 had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
279 }
280
281 /*
282 * initialize audio channel status registers
283 * This function is called in the prepare callback
284 */
had_prog_status_reg(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)285 static int had_prog_status_reg(struct snd_pcm_substream *substream,
286 struct snd_intelhad *intelhaddata)
287 {
288 union aud_ch_status_0 ch_stat0 = {.regval = 0};
289 union aud_ch_status_1 ch_stat1 = {.regval = 0};
290
291 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
292 IEC958_AES0_NONAUDIO) >> 1;
293 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
294 IEC958_AES3_CON_CLOCK) >> 4;
295
296 switch (substream->runtime->rate) {
297 case AUD_SAMPLE_RATE_32:
298 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
299 break;
300
301 case AUD_SAMPLE_RATE_44_1:
302 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
303 break;
304 case AUD_SAMPLE_RATE_48:
305 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
306 break;
307 case AUD_SAMPLE_RATE_88_2:
308 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
309 break;
310 case AUD_SAMPLE_RATE_96:
311 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
312 break;
313 case AUD_SAMPLE_RATE_176_4:
314 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
315 break;
316 case AUD_SAMPLE_RATE_192:
317 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
318 break;
319
320 default:
321 /* control should never come here */
322 return -EINVAL;
323 }
324
325 had_write_register(intelhaddata,
326 AUD_CH_STATUS_0, ch_stat0.regval);
327
328 switch (substream->runtime->format) {
329 case SNDRV_PCM_FORMAT_S16_LE:
330 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
331 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
332 break;
333 case SNDRV_PCM_FORMAT_S24_LE:
334 case SNDRV_PCM_FORMAT_S32_LE:
335 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
336 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
337 break;
338 default:
339 return -EINVAL;
340 }
341
342 had_write_register(intelhaddata,
343 AUD_CH_STATUS_1, ch_stat1.regval);
344 return 0;
345 }
346
347 /*
348 * function to initialize audio
349 * registers and buffer configuration registers
350 * This function is called in the prepare callback
351 */
had_init_audio_ctrl(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)352 static int had_init_audio_ctrl(struct snd_pcm_substream *substream,
353 struct snd_intelhad *intelhaddata)
354 {
355 union aud_cfg cfg_val = {.regval = 0};
356 union aud_buf_config buf_cfg = {.regval = 0};
357 u8 channels;
358
359 had_prog_status_reg(substream, intelhaddata);
360
361 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
362 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
363 buf_cfg.regx.aud_delay = 0;
364 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);
365
366 channels = substream->runtime->channels;
367 cfg_val.regx.num_ch = channels - 2;
368 if (channels <= 2)
369 cfg_val.regx.layout = LAYOUT0;
370 else
371 cfg_val.regx.layout = LAYOUT1;
372
373 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
374 cfg_val.regx.packet_mode = 1;
375
376 if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE)
377 cfg_val.regx.left_align = 1;
378
379 cfg_val.regx.val_bit = 1;
380
381 /* fix up the DP bits */
382 if (intelhaddata->dp_output) {
383 cfg_val.regx.dp_modei = 1;
384 cfg_val.regx.set = 1;
385 }
386
387 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
388 intelhaddata->aud_config = cfg_val;
389 return 0;
390 }
391
392 /*
393 * Compute derived values in channel_allocations[].
394 */
init_channel_allocations(void)395 static void init_channel_allocations(void)
396 {
397 int i, j;
398 struct cea_channel_speaker_allocation *p;
399
400 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
401 p = channel_allocations + i;
402 p->channels = 0;
403 p->spk_mask = 0;
404 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
405 if (p->speakers[j]) {
406 p->channels++;
407 p->spk_mask |= p->speakers[j];
408 }
409 }
410 }
411
412 /*
413 * The transformation takes two steps:
414 *
415 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
416 * spk_mask => (channel_allocations[]) => ai->CA
417 *
418 * TODO: it could select the wrong CA from multiple candidates.
419 */
had_channel_allocation(struct snd_intelhad * intelhaddata,int channels)420 static int had_channel_allocation(struct snd_intelhad *intelhaddata,
421 int channels)
422 {
423 int i;
424 int ca = 0;
425 int spk_mask = 0;
426
427 /*
428 * CA defaults to 0 for basic stereo audio
429 */
430 if (channels <= 2)
431 return 0;
432
433 /*
434 * expand ELD's speaker allocation mask
435 *
436 * ELD tells the speaker mask in a compact(paired) form,
437 * expand ELD's notions to match the ones used by Audio InfoFrame.
438 */
439
440 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
441 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
442 spk_mask |= eld_speaker_allocation_bits[i];
443 }
444
445 /* search for the first working match in the CA table */
446 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
447 if (channels == channel_allocations[i].channels &&
448 (spk_mask & channel_allocations[i].spk_mask) ==
449 channel_allocations[i].spk_mask) {
450 ca = channel_allocations[i].ca_index;
451 break;
452 }
453 }
454
455 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
456
457 return ca;
458 }
459
460 /* from speaker bit mask to ALSA API channel position */
spk_to_chmap(int spk)461 static int spk_to_chmap(int spk)
462 {
463 const struct channel_map_table *t = map_tables;
464
465 for (; t->map; t++) {
466 if (t->spk_mask == spk)
467 return t->map;
468 }
469 return 0;
470 }
471
had_build_channel_allocation_map(struct snd_intelhad * intelhaddata)472 static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
473 {
474 int i, c;
475 int spk_mask = 0;
476 struct snd_pcm_chmap_elem *chmap;
477 u8 eld_high, eld_high_mask = 0xF0;
478 u8 high_msb;
479
480 kfree(intelhaddata->chmap->chmap);
481 intelhaddata->chmap->chmap = NULL;
482
483 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
484 if (!chmap)
485 return;
486
487 dev_dbg(intelhaddata->dev, "eld speaker = %x\n",
488 intelhaddata->eld[DRM_ELD_SPEAKER]);
489
490 /* WA: Fix the max channel supported to 8 */
491
492 /*
493 * Sink may support more than 8 channels, if eld_high has more than
494 * one bit set. SOC supports max 8 channels.
495 * Refer eld_speaker_allocation_bits, for sink speaker allocation
496 */
497
498 /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
499 eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask;
500 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
501 /* eld_high & (eld_high-1): if more than 1 bit set */
502 /* 0x1F: 7 channels */
503 for (i = 1; i < 4; i++) {
504 high_msb = eld_high & (0x80 >> i);
505 if (high_msb) {
506 intelhaddata->eld[DRM_ELD_SPEAKER] &=
507 high_msb | 0xF;
508 break;
509 }
510 }
511 }
512
513 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
514 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
515 spk_mask |= eld_speaker_allocation_bits[i];
516 }
517
518 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
519 if (spk_mask == channel_allocations[i].spk_mask) {
520 for (c = 0; c < channel_allocations[i].channels; c++) {
521 chmap->map[c] = spk_to_chmap(
522 channel_allocations[i].speakers[
523 (MAX_SPEAKERS - 1) - c]);
524 }
525 chmap->channels = channel_allocations[i].channels;
526 intelhaddata->chmap->chmap = chmap;
527 break;
528 }
529 }
530 if (i >= ARRAY_SIZE(channel_allocations))
531 kfree(chmap);
532 }
533
534 /*
535 * ALSA API channel-map control callbacks
536 */
had_chmap_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)537 static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
538 struct snd_ctl_elem_info *uinfo)
539 {
540 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
541 uinfo->count = HAD_MAX_CHANNEL;
542 uinfo->value.integer.min = 0;
543 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
544 return 0;
545 }
546
had_chmap_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)547 static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
548 struct snd_ctl_elem_value *ucontrol)
549 {
550 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
551 struct snd_intelhad *intelhaddata = info->private_data;
552 int i;
553 const struct snd_pcm_chmap_elem *chmap;
554
555 memset(ucontrol->value.integer.value, 0,
556 sizeof(long) * HAD_MAX_CHANNEL);
557 mutex_lock(&intelhaddata->mutex);
558 if (!intelhaddata->chmap->chmap) {
559 mutex_unlock(&intelhaddata->mutex);
560 return 0;
561 }
562
563 chmap = intelhaddata->chmap->chmap;
564 for (i = 0; i < chmap->channels; i++)
565 ucontrol->value.integer.value[i] = chmap->map[i];
566 mutex_unlock(&intelhaddata->mutex);
567
568 return 0;
569 }
570
had_register_chmap_ctls(struct snd_intelhad * intelhaddata,struct snd_pcm * pcm)571 static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
572 struct snd_pcm *pcm)
573 {
574 int err;
575
576 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
577 NULL, 0, (unsigned long)intelhaddata,
578 &intelhaddata->chmap);
579 if (err < 0)
580 return err;
581
582 intelhaddata->chmap->private_data = intelhaddata;
583 intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
584 intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
585 intelhaddata->chmap->chmap = NULL;
586 return 0;
587 }
588
589 /*
590 * Initialize Data Island Packets registers
591 * This function is called in the prepare callback
592 */
had_prog_dip(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)593 static void had_prog_dip(struct snd_pcm_substream *substream,
594 struct snd_intelhad *intelhaddata)
595 {
596 int i;
597 union aud_ctrl_st ctrl_state = {.regval = 0};
598 union aud_info_frame2 frame2 = {.regval = 0};
599 union aud_info_frame3 frame3 = {.regval = 0};
600 u8 checksum = 0;
601 u32 info_frame;
602 int channels;
603 int ca;
604
605 channels = substream->runtime->channels;
606
607 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
608
609 ca = had_channel_allocation(intelhaddata, channels);
610 if (intelhaddata->dp_output) {
611 info_frame = DP_INFO_FRAME_WORD1;
612 frame2.regval = (substream->runtime->channels - 1) | (ca << 24);
613 } else {
614 info_frame = HDMI_INFO_FRAME_WORD1;
615 frame2.regx.chnl_cnt = substream->runtime->channels - 1;
616 frame3.regx.chnl_alloc = ca;
617
618 /* Calculte the byte wide checksum for all valid DIP words */
619 for (i = 0; i < BYTES_PER_WORD; i++)
620 checksum += (info_frame >> (i * 8)) & 0xff;
621 for (i = 0; i < BYTES_PER_WORD; i++)
622 checksum += (frame2.regval >> (i * 8)) & 0xff;
623 for (i = 0; i < BYTES_PER_WORD; i++)
624 checksum += (frame3.regval >> (i * 8)) & 0xff;
625
626 frame2.regx.chksum = -(checksum);
627 }
628
629 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
630 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);
631 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);
632
633 /* program remaining DIP words with zero */
634 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
635 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
636
637 ctrl_state.regx.dip_freq = 1;
638 ctrl_state.regx.dip_en_sta = 1;
639 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
640 }
641
had_calculate_maud_value(u32 aud_samp_freq,u32 link_rate)642 static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
643 {
644 u32 maud_val;
645
646 /* Select maud according to DP 1.2 spec */
647 if (link_rate == DP_2_7_GHZ) {
648 switch (aud_samp_freq) {
649 case AUD_SAMPLE_RATE_32:
650 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
651 break;
652
653 case AUD_SAMPLE_RATE_44_1:
654 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
655 break;
656
657 case AUD_SAMPLE_RATE_48:
658 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
659 break;
660
661 case AUD_SAMPLE_RATE_88_2:
662 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
663 break;
664
665 case AUD_SAMPLE_RATE_96:
666 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
667 break;
668
669 case AUD_SAMPLE_RATE_176_4:
670 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
671 break;
672
673 case HAD_MAX_RATE:
674 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
675 break;
676
677 default:
678 maud_val = -EINVAL;
679 break;
680 }
681 } else if (link_rate == DP_1_62_GHZ) {
682 switch (aud_samp_freq) {
683 case AUD_SAMPLE_RATE_32:
684 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
685 break;
686
687 case AUD_SAMPLE_RATE_44_1:
688 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
689 break;
690
691 case AUD_SAMPLE_RATE_48:
692 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
693 break;
694
695 case AUD_SAMPLE_RATE_88_2:
696 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
697 break;
698
699 case AUD_SAMPLE_RATE_96:
700 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
701 break;
702
703 case AUD_SAMPLE_RATE_176_4:
704 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
705 break;
706
707 case HAD_MAX_RATE:
708 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
709 break;
710
711 default:
712 maud_val = -EINVAL;
713 break;
714 }
715 } else
716 maud_val = -EINVAL;
717
718 return maud_val;
719 }
720
721 /*
722 * Program HDMI audio CTS value
723 *
724 * @aud_samp_freq: sampling frequency of audio data
725 * @tmds: sampling frequency of the display data
726 * @link_rate: DP link rate
727 * @n_param: N value, depends on aud_samp_freq
728 * @intelhaddata: substream private data
729 *
730 * Program CTS register based on the audio and display sampling frequency
731 */
had_prog_cts(u32 aud_samp_freq,u32 tmds,u32 link_rate,u32 n_param,struct snd_intelhad * intelhaddata)732 static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate,
733 u32 n_param, struct snd_intelhad *intelhaddata)
734 {
735 u32 cts_val;
736 u64 dividend, divisor;
737
738 if (intelhaddata->dp_output) {
739 /* Substitute cts_val with Maud according to DP 1.2 spec*/
740 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
741 } else {
742 /* Calculate CTS according to HDMI 1.3a spec*/
743 dividend = (u64)tmds * n_param*1000;
744 divisor = 128 * aud_samp_freq;
745 cts_val = div64_u64(dividend, divisor);
746 }
747 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
748 tmds, n_param, cts_val);
749 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
750 }
751
had_calculate_n_value(u32 aud_samp_freq)752 static int had_calculate_n_value(u32 aud_samp_freq)
753 {
754 int n_val;
755
756 /* Select N according to HDMI 1.3a spec*/
757 switch (aud_samp_freq) {
758 case AUD_SAMPLE_RATE_32:
759 n_val = 4096;
760 break;
761
762 case AUD_SAMPLE_RATE_44_1:
763 n_val = 6272;
764 break;
765
766 case AUD_SAMPLE_RATE_48:
767 n_val = 6144;
768 break;
769
770 case AUD_SAMPLE_RATE_88_2:
771 n_val = 12544;
772 break;
773
774 case AUD_SAMPLE_RATE_96:
775 n_val = 12288;
776 break;
777
778 case AUD_SAMPLE_RATE_176_4:
779 n_val = 25088;
780 break;
781
782 case HAD_MAX_RATE:
783 n_val = 24576;
784 break;
785
786 default:
787 n_val = -EINVAL;
788 break;
789 }
790 return n_val;
791 }
792
793 /*
794 * Program HDMI audio N value
795 *
796 * @aud_samp_freq: sampling frequency of audio data
797 * @n_param: N value, depends on aud_samp_freq
798 * @intelhaddata: substream private data
799 *
800 * This function is called in the prepare callback.
801 * It programs based on the audio and display sampling frequency
802 */
had_prog_n(u32 aud_samp_freq,u32 * n_param,struct snd_intelhad * intelhaddata)803 static int had_prog_n(u32 aud_samp_freq, u32 *n_param,
804 struct snd_intelhad *intelhaddata)
805 {
806 int n_val;
807
808 if (intelhaddata->dp_output) {
809 /*
810 * According to DP specs, Maud and Naud values hold
811 * a relationship, which is stated as:
812 * Maud/Naud = 512 * fs / f_LS_Clk
813 * where, fs is the sampling frequency of the audio stream
814 * and Naud is 32768 for Async clock.
815 */
816
817 n_val = DP_NAUD_VAL;
818 } else
819 n_val = had_calculate_n_value(aud_samp_freq);
820
821 if (n_val < 0)
822 return n_val;
823
824 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
825 *n_param = n_val;
826 return 0;
827 }
828
829 /*
830 * PCM ring buffer handling
831 *
832 * The hardware provides a ring buffer with the fixed 4 buffer descriptors
833 * (BDs). The driver maps these 4 BDs onto the PCM ring buffer. The mapping
834 * moves at each period elapsed. The below illustrates how it works:
835 *
836 * At time=0
837 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
838 * BD | 0 | 1 | 2 | 3 |
839 *
840 * At time=1 (period elapsed)
841 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
842 * BD | 1 | 2 | 3 | 0 |
843 *
844 * At time=2 (second period elapsed)
845 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
846 * BD | 2 | 3 | 0 | 1 |
847 *
848 * The bd_head field points to the index of the BD to be read. It's also the
849 * position to be filled at next. The pcm_head and the pcm_filled fields
850 * point to the indices of the current position and of the next position to
851 * be filled, respectively. For PCM buffer there are both _head and _filled
852 * because they may be difference when nperiods > 4. For example, in the
853 * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5:
854 *
855 * pcm_head (=1) --v v-- pcm_filled (=5)
856 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
857 * BD | 1 | 2 | 3 | 0 |
858 * bd_head (=1) --^ ^-- next to fill (= bd_head)
859 *
860 * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that
861 * the hardware skips those BDs in the loop.
862 *
863 * An exceptional setup is the case with nperiods=1. Since we have to update
864 * BDs after finishing one BD processing, we'd need at least two BDs, where
865 * both BDs point to the same content, the same address, the same size of the
866 * whole PCM buffer.
867 */
868
869 #define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH)
870 #define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH)
871
872 /* Set up a buffer descriptor at the "filled" position */
had_prog_bd(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)873 static void had_prog_bd(struct snd_pcm_substream *substream,
874 struct snd_intelhad *intelhaddata)
875 {
876 int idx = intelhaddata->bd_head;
877 int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes;
878 u32 addr = substream->runtime->dma_addr + ofs;
879
880 addr |= AUD_BUF_VALID;
881 if (!substream->runtime->no_period_wakeup)
882 addr |= AUD_BUF_INTR_EN;
883 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr);
884 had_write_register(intelhaddata, AUD_BUF_LEN(idx),
885 intelhaddata->period_bytes);
886
887 /* advance the indices to the next */
888 intelhaddata->bd_head++;
889 intelhaddata->bd_head %= intelhaddata->num_bds;
890 intelhaddata->pcmbuf_filled++;
891 intelhaddata->pcmbuf_filled %= substream->runtime->periods;
892 }
893
894 /* invalidate a buffer descriptor with the given index */
had_invalidate_bd(struct snd_intelhad * intelhaddata,int idx)895 static void had_invalidate_bd(struct snd_intelhad *intelhaddata,
896 int idx)
897 {
898 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0);
899 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0);
900 }
901
902 /* Initial programming of ring buffer */
had_init_ringbuf(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)903 static void had_init_ringbuf(struct snd_pcm_substream *substream,
904 struct snd_intelhad *intelhaddata)
905 {
906 struct snd_pcm_runtime *runtime = substream->runtime;
907 int i, num_periods;
908
909 num_periods = runtime->periods;
910 intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS);
911 /* set the minimum 2 BDs for num_periods=1 */
912 intelhaddata->num_bds = max(intelhaddata->num_bds, 2U);
913 intelhaddata->period_bytes =
914 frames_to_bytes(runtime, runtime->period_size);
915 WARN_ON(intelhaddata->period_bytes & 0x3f);
916
917 intelhaddata->bd_head = 0;
918 intelhaddata->pcmbuf_head = 0;
919 intelhaddata->pcmbuf_filled = 0;
920
921 for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) {
922 if (i < intelhaddata->num_bds)
923 had_prog_bd(substream, intelhaddata);
924 else /* invalidate the rest */
925 had_invalidate_bd(intelhaddata, i);
926 }
927
928 intelhaddata->bd_head = 0; /* reset at head again before starting */
929 }
930
931 /* process a bd, advance to the next */
had_advance_ringbuf(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)932 static void had_advance_ringbuf(struct snd_pcm_substream *substream,
933 struct snd_intelhad *intelhaddata)
934 {
935 int num_periods = substream->runtime->periods;
936
937 /* reprogram the next buffer */
938 had_prog_bd(substream, intelhaddata);
939
940 /* proceed to next */
941 intelhaddata->pcmbuf_head++;
942 intelhaddata->pcmbuf_head %= num_periods;
943 }
944
945 /* process the current BD(s);
946 * returns the current PCM buffer byte position, or -EPIPE for underrun.
947 */
had_process_ringbuf(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)948 static int had_process_ringbuf(struct snd_pcm_substream *substream,
949 struct snd_intelhad *intelhaddata)
950 {
951 int len, processed;
952 unsigned long flags;
953
954 processed = 0;
955 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
956 for (;;) {
957 /* get the remaining bytes on the buffer */
958 had_read_register(intelhaddata,
959 AUD_BUF_LEN(intelhaddata->bd_head),
960 &len);
961 if (len < 0 || len > intelhaddata->period_bytes) {
962 dev_dbg(intelhaddata->dev, "Invalid buf length %d\n",
963 len);
964 len = -EPIPE;
965 goto out;
966 }
967
968 if (len > 0) /* OK, this is the current buffer */
969 break;
970
971 /* len=0 => already empty, check the next buffer */
972 if (++processed >= intelhaddata->num_bds) {
973 len = -EPIPE; /* all empty? - report underrun */
974 goto out;
975 }
976 had_advance_ringbuf(substream, intelhaddata);
977 }
978
979 len = intelhaddata->period_bytes - len;
980 len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head;
981 out:
982 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
983 return len;
984 }
985
986 /* called from irq handler */
had_process_buffer_done(struct snd_intelhad * intelhaddata)987 static void had_process_buffer_done(struct snd_intelhad *intelhaddata)
988 {
989 struct snd_pcm_substream *substream;
990
991 substream = had_substream_get(intelhaddata);
992 if (!substream)
993 return; /* no stream? - bail out */
994
995 if (!intelhaddata->connected) {
996 snd_pcm_stop_xrun(substream);
997 goto out; /* disconnected? - bail out */
998 }
999
1000 /* process or stop the stream */
1001 if (had_process_ringbuf(substream, intelhaddata) < 0)
1002 snd_pcm_stop_xrun(substream);
1003 else
1004 snd_pcm_period_elapsed(substream);
1005
1006 out:
1007 had_substream_put(intelhaddata);
1008 }
1009
1010 /*
1011 * The interrupt status 'sticky' bits might not be cleared by
1012 * setting '1' to that bit once...
1013 */
wait_clear_underrun_bit(struct snd_intelhad * intelhaddata)1014 static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata)
1015 {
1016 int i;
1017 u32 val;
1018
1019 for (i = 0; i < 100; i++) {
1020 /* clear bit30, 31 AUD_HDMI_STATUS */
1021 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val);
1022 if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN))
1023 return;
1024 udelay(100);
1025 cond_resched();
1026 had_write_register(intelhaddata, AUD_HDMI_STATUS, val);
1027 }
1028 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
1029 }
1030
1031 /* Perform some reset procedure after stopping the stream;
1032 * this is called from prepare or hw_free callbacks once after trigger STOP
1033 * or underrun has been processed in order to settle down the h/w state.
1034 */
had_pcm_sync_stop(struct snd_pcm_substream * substream)1035 static int had_pcm_sync_stop(struct snd_pcm_substream *substream)
1036 {
1037 struct snd_intelhad *intelhaddata = snd_pcm_substream_chip(substream);
1038
1039 if (!intelhaddata->connected)
1040 return 0;
1041
1042 /* Reset buffer pointers */
1043 had_reset_audio(intelhaddata);
1044 wait_clear_underrun_bit(intelhaddata);
1045 return 0;
1046 }
1047
1048 /* called from irq handler */
had_process_buffer_underrun(struct snd_intelhad * intelhaddata)1049 static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
1050 {
1051 struct snd_pcm_substream *substream;
1052
1053 /* Report UNDERRUN error to above layers */
1054 substream = had_substream_get(intelhaddata);
1055 if (substream) {
1056 snd_pcm_stop_xrun(substream);
1057 had_substream_put(intelhaddata);
1058 }
1059 }
1060
1061 /*
1062 * ALSA PCM open callback
1063 */
had_pcm_open(struct snd_pcm_substream * substream)1064 static int had_pcm_open(struct snd_pcm_substream *substream)
1065 {
1066 struct snd_intelhad *intelhaddata;
1067 struct snd_pcm_runtime *runtime;
1068 int retval;
1069
1070 intelhaddata = snd_pcm_substream_chip(substream);
1071 runtime = substream->runtime;
1072
1073 retval = pm_runtime_resume_and_get(intelhaddata->dev);
1074 if (retval < 0)
1075 return retval;
1076
1077 /* set the runtime hw parameter with local snd_pcm_hardware struct */
1078 runtime->hw = had_pcm_hardware;
1079
1080 retval = snd_pcm_hw_constraint_integer(runtime,
1081 SNDRV_PCM_HW_PARAM_PERIODS);
1082 if (retval < 0)
1083 goto error;
1084
1085 /* Make sure, that the period size is always aligned
1086 * 64byte boundary
1087 */
1088 retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1089 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
1090 if (retval < 0)
1091 goto error;
1092
1093 retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1094 if (retval < 0)
1095 goto error;
1096
1097 /* expose PCM substream */
1098 spin_lock_irq(&intelhaddata->had_spinlock);
1099 intelhaddata->stream_info.substream = substream;
1100 intelhaddata->stream_info.substream_refcount++;
1101 spin_unlock_irq(&intelhaddata->had_spinlock);
1102
1103 return retval;
1104 error:
1105 pm_runtime_mark_last_busy(intelhaddata->dev);
1106 pm_runtime_put_autosuspend(intelhaddata->dev);
1107 return retval;
1108 }
1109
1110 /*
1111 * ALSA PCM close callback
1112 */
had_pcm_close(struct snd_pcm_substream * substream)1113 static int had_pcm_close(struct snd_pcm_substream *substream)
1114 {
1115 struct snd_intelhad *intelhaddata;
1116
1117 intelhaddata = snd_pcm_substream_chip(substream);
1118
1119 /* unreference and sync with the pending PCM accesses */
1120 spin_lock_irq(&intelhaddata->had_spinlock);
1121 intelhaddata->stream_info.substream = NULL;
1122 intelhaddata->stream_info.substream_refcount--;
1123 while (intelhaddata->stream_info.substream_refcount > 0) {
1124 spin_unlock_irq(&intelhaddata->had_spinlock);
1125 cpu_relax();
1126 spin_lock_irq(&intelhaddata->had_spinlock);
1127 }
1128 spin_unlock_irq(&intelhaddata->had_spinlock);
1129
1130 pm_runtime_mark_last_busy(intelhaddata->dev);
1131 pm_runtime_put_autosuspend(intelhaddata->dev);
1132 return 0;
1133 }
1134
1135 /*
1136 * ALSA PCM hw_params callback
1137 */
had_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)1138 static int had_pcm_hw_params(struct snd_pcm_substream *substream,
1139 struct snd_pcm_hw_params *hw_params)
1140 {
1141 struct snd_intelhad *intelhaddata;
1142 int buf_size;
1143
1144 intelhaddata = snd_pcm_substream_chip(substream);
1145 buf_size = params_buffer_bytes(hw_params);
1146 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
1147 __func__, buf_size);
1148 return 0;
1149 }
1150
1151 /*
1152 * ALSA PCM trigger callback
1153 */
had_pcm_trigger(struct snd_pcm_substream * substream,int cmd)1154 static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1155 {
1156 int retval = 0;
1157 struct snd_intelhad *intelhaddata;
1158
1159 intelhaddata = snd_pcm_substream_chip(substream);
1160
1161 spin_lock(&intelhaddata->had_spinlock);
1162 switch (cmd) {
1163 case SNDRV_PCM_TRIGGER_START:
1164 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1165 case SNDRV_PCM_TRIGGER_RESUME:
1166 /* Enable Audio */
1167 had_ack_irqs(intelhaddata); /* FIXME: do we need this? */
1168 had_enable_audio(intelhaddata, true);
1169 break;
1170
1171 case SNDRV_PCM_TRIGGER_STOP:
1172 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1173 /* Disable Audio */
1174 had_enable_audio(intelhaddata, false);
1175 break;
1176
1177 default:
1178 retval = -EINVAL;
1179 }
1180 spin_unlock(&intelhaddata->had_spinlock);
1181 return retval;
1182 }
1183
1184 /*
1185 * ALSA PCM prepare callback
1186 */
had_pcm_prepare(struct snd_pcm_substream * substream)1187 static int had_pcm_prepare(struct snd_pcm_substream *substream)
1188 {
1189 int retval;
1190 u32 disp_samp_freq, n_param;
1191 u32 link_rate = 0;
1192 struct snd_intelhad *intelhaddata;
1193 struct snd_pcm_runtime *runtime;
1194
1195 intelhaddata = snd_pcm_substream_chip(substream);
1196 runtime = substream->runtime;
1197
1198 dev_dbg(intelhaddata->dev, "period_size=%d\n",
1199 (int)frames_to_bytes(runtime, runtime->period_size));
1200 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
1201 dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
1202 (int)snd_pcm_lib_buffer_bytes(substream));
1203 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
1204 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
1205
1206 /* Get N value in KHz */
1207 disp_samp_freq = intelhaddata->tmds_clock_speed;
1208
1209 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1210 if (retval) {
1211 dev_err(intelhaddata->dev,
1212 "programming N value failed %#x\n", retval);
1213 goto prep_end;
1214 }
1215
1216 if (intelhaddata->dp_output)
1217 link_rate = intelhaddata->link_rate;
1218
1219 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1220 n_param, intelhaddata);
1221
1222 had_prog_dip(substream, intelhaddata);
1223
1224 retval = had_init_audio_ctrl(substream, intelhaddata);
1225
1226 /* Prog buffer address */
1227 had_init_ringbuf(substream, intelhaddata);
1228
1229 /*
1230 * Program channel mapping in following order:
1231 * FL, FR, C, LFE, RL, RR
1232 */
1233
1234 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
1235
1236 prep_end:
1237 return retval;
1238 }
1239
1240 /*
1241 * ALSA PCM pointer callback
1242 */
had_pcm_pointer(struct snd_pcm_substream * substream)1243 static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream)
1244 {
1245 struct snd_intelhad *intelhaddata;
1246 int len;
1247
1248 intelhaddata = snd_pcm_substream_chip(substream);
1249
1250 if (!intelhaddata->connected)
1251 return SNDRV_PCM_POS_XRUN;
1252
1253 len = had_process_ringbuf(substream, intelhaddata);
1254 if (len < 0)
1255 return SNDRV_PCM_POS_XRUN;
1256 len = bytes_to_frames(substream->runtime, len);
1257 /* wrapping may happen when periods=1 */
1258 len %= substream->runtime->buffer_size;
1259 return len;
1260 }
1261
1262 /*
1263 * ALSA PCM ops
1264 */
1265 static const struct snd_pcm_ops had_pcm_ops = {
1266 .open = had_pcm_open,
1267 .close = had_pcm_close,
1268 .hw_params = had_pcm_hw_params,
1269 .prepare = had_pcm_prepare,
1270 .trigger = had_pcm_trigger,
1271 .sync_stop = had_pcm_sync_stop,
1272 .pointer = had_pcm_pointer,
1273 };
1274
1275 /* process mode change of the running stream; called in mutex */
had_process_mode_change(struct snd_intelhad * intelhaddata)1276 static int had_process_mode_change(struct snd_intelhad *intelhaddata)
1277 {
1278 struct snd_pcm_substream *substream;
1279 int retval = 0;
1280 u32 disp_samp_freq, n_param;
1281 u32 link_rate = 0;
1282
1283 substream = had_substream_get(intelhaddata);
1284 if (!substream)
1285 return 0;
1286
1287 /* Disable Audio */
1288 had_enable_audio(intelhaddata, false);
1289
1290 /* Update CTS value */
1291 disp_samp_freq = intelhaddata->tmds_clock_speed;
1292
1293 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1294 if (retval) {
1295 dev_err(intelhaddata->dev,
1296 "programming N value failed %#x\n", retval);
1297 goto out;
1298 }
1299
1300 if (intelhaddata->dp_output)
1301 link_rate = intelhaddata->link_rate;
1302
1303 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1304 n_param, intelhaddata);
1305
1306 /* Enable Audio */
1307 had_enable_audio(intelhaddata, true);
1308
1309 out:
1310 had_substream_put(intelhaddata);
1311 return retval;
1312 }
1313
1314 /* process hot plug, called from wq with mutex locked */
had_process_hot_plug(struct snd_intelhad * intelhaddata)1315 static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
1316 {
1317 struct snd_pcm_substream *substream;
1318
1319 spin_lock_irq(&intelhaddata->had_spinlock);
1320 if (intelhaddata->connected) {
1321 dev_dbg(intelhaddata->dev, "Device already connected\n");
1322 spin_unlock_irq(&intelhaddata->had_spinlock);
1323 return;
1324 }
1325
1326 /* Disable Audio */
1327 had_enable_audio(intelhaddata, false);
1328
1329 intelhaddata->connected = true;
1330 dev_dbg(intelhaddata->dev,
1331 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
1332 __func__, __LINE__);
1333 spin_unlock_irq(&intelhaddata->had_spinlock);
1334
1335 had_build_channel_allocation_map(intelhaddata);
1336
1337 /* Report to above ALSA layer */
1338 substream = had_substream_get(intelhaddata);
1339 if (substream) {
1340 snd_pcm_stop_xrun(substream);
1341 had_substream_put(intelhaddata);
1342 }
1343
1344 snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT);
1345 }
1346
1347 /* process hot unplug, called from wq with mutex locked */
had_process_hot_unplug(struct snd_intelhad * intelhaddata)1348 static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
1349 {
1350 struct snd_pcm_substream *substream;
1351
1352 spin_lock_irq(&intelhaddata->had_spinlock);
1353 if (!intelhaddata->connected) {
1354 dev_dbg(intelhaddata->dev, "Device already disconnected\n");
1355 spin_unlock_irq(&intelhaddata->had_spinlock);
1356 return;
1357
1358 }
1359
1360 /* Disable Audio */
1361 had_enable_audio(intelhaddata, false);
1362
1363 intelhaddata->connected = false;
1364 dev_dbg(intelhaddata->dev,
1365 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
1366 __func__, __LINE__);
1367 spin_unlock_irq(&intelhaddata->had_spinlock);
1368
1369 kfree(intelhaddata->chmap->chmap);
1370 intelhaddata->chmap->chmap = NULL;
1371
1372 /* Report to above ALSA layer */
1373 substream = had_substream_get(intelhaddata);
1374 if (substream) {
1375 snd_pcm_stop_xrun(substream);
1376 had_substream_put(intelhaddata);
1377 }
1378
1379 snd_jack_report(intelhaddata->jack, 0);
1380 }
1381
1382 /*
1383 * ALSA iec958 and ELD controls
1384 */
1385
had_iec958_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1386 static int had_iec958_info(struct snd_kcontrol *kcontrol,
1387 struct snd_ctl_elem_info *uinfo)
1388 {
1389 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1390 uinfo->count = 1;
1391 return 0;
1392 }
1393
had_iec958_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1394 static int had_iec958_get(struct snd_kcontrol *kcontrol,
1395 struct snd_ctl_elem_value *ucontrol)
1396 {
1397 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1398
1399 mutex_lock(&intelhaddata->mutex);
1400 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1401 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1402 ucontrol->value.iec958.status[2] =
1403 (intelhaddata->aes_bits >> 16) & 0xff;
1404 ucontrol->value.iec958.status[3] =
1405 (intelhaddata->aes_bits >> 24) & 0xff;
1406 mutex_unlock(&intelhaddata->mutex);
1407 return 0;
1408 }
1409
had_iec958_mask_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1410 static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1411 struct snd_ctl_elem_value *ucontrol)
1412 {
1413 ucontrol->value.iec958.status[0] = 0xff;
1414 ucontrol->value.iec958.status[1] = 0xff;
1415 ucontrol->value.iec958.status[2] = 0xff;
1416 ucontrol->value.iec958.status[3] = 0xff;
1417 return 0;
1418 }
1419
had_iec958_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1420 static int had_iec958_put(struct snd_kcontrol *kcontrol,
1421 struct snd_ctl_elem_value *ucontrol)
1422 {
1423 unsigned int val;
1424 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1425 int changed = 0;
1426
1427 val = (ucontrol->value.iec958.status[0] << 0) |
1428 (ucontrol->value.iec958.status[1] << 8) |
1429 (ucontrol->value.iec958.status[2] << 16) |
1430 (ucontrol->value.iec958.status[3] << 24);
1431 mutex_lock(&intelhaddata->mutex);
1432 if (intelhaddata->aes_bits != val) {
1433 intelhaddata->aes_bits = val;
1434 changed = 1;
1435 }
1436 mutex_unlock(&intelhaddata->mutex);
1437 return changed;
1438 }
1439
had_ctl_eld_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1440 static int had_ctl_eld_info(struct snd_kcontrol *kcontrol,
1441 struct snd_ctl_elem_info *uinfo)
1442 {
1443 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1444 uinfo->count = HDMI_MAX_ELD_BYTES;
1445 return 0;
1446 }
1447
had_ctl_eld_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1448 static int had_ctl_eld_get(struct snd_kcontrol *kcontrol,
1449 struct snd_ctl_elem_value *ucontrol)
1450 {
1451 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1452
1453 mutex_lock(&intelhaddata->mutex);
1454 memcpy(ucontrol->value.bytes.data, intelhaddata->eld,
1455 HDMI_MAX_ELD_BYTES);
1456 mutex_unlock(&intelhaddata->mutex);
1457 return 0;
1458 }
1459
1460 static const struct snd_kcontrol_new had_controls[] = {
1461 {
1462 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1463 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1464 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1465 .info = had_iec958_info, /* shared */
1466 .get = had_iec958_mask_get,
1467 },
1468 {
1469 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1470 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1471 .info = had_iec958_info,
1472 .get = had_iec958_get,
1473 .put = had_iec958_put,
1474 },
1475 {
1476 .access = (SNDRV_CTL_ELEM_ACCESS_READ |
1477 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1478 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1479 .name = "ELD",
1480 .info = had_ctl_eld_info,
1481 .get = had_ctl_eld_get,
1482 },
1483 };
1484
1485 /*
1486 * audio interrupt handler
1487 */
display_pipe_interrupt_handler(int irq,void * dev_id)1488 static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1489 {
1490 struct snd_intelhad_card *card_ctx = dev_id;
1491 u32 audio_stat[3] = {};
1492 int pipe, port;
1493
1494 for_each_pipe(card_ctx, pipe) {
1495 /* use raw register access to ack IRQs even while disconnected */
1496 audio_stat[pipe] = had_read_register_raw(card_ctx, pipe,
1497 AUD_HDMI_STATUS) &
1498 (HDMI_AUDIO_UNDERRUN | HDMI_AUDIO_BUFFER_DONE);
1499
1500 if (audio_stat[pipe])
1501 had_write_register_raw(card_ctx, pipe,
1502 AUD_HDMI_STATUS, audio_stat[pipe]);
1503 }
1504
1505 for_each_port(card_ctx, port) {
1506 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1507 int pipe = ctx->pipe;
1508
1509 if (pipe < 0)
1510 continue;
1511
1512 if (audio_stat[pipe] & HDMI_AUDIO_BUFFER_DONE)
1513 had_process_buffer_done(ctx);
1514 if (audio_stat[pipe] & HDMI_AUDIO_UNDERRUN)
1515 had_process_buffer_underrun(ctx);
1516 }
1517
1518 return IRQ_HANDLED;
1519 }
1520
1521 /*
1522 * monitor plug/unplug notification from i915; just kick off the work
1523 */
notify_audio_lpe(struct platform_device * pdev,int port)1524 static void notify_audio_lpe(struct platform_device *pdev, int port)
1525 {
1526 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
1527 struct snd_intelhad *ctx;
1528
1529 ctx = &card_ctx->pcm_ctx[single_port ? 0 : port];
1530 if (single_port)
1531 ctx->port = port;
1532
1533 schedule_work(&ctx->hdmi_audio_wq);
1534 }
1535
1536 /* the work to handle monitor hot plug/unplug */
had_audio_wq(struct work_struct * work)1537 static void had_audio_wq(struct work_struct *work)
1538 {
1539 struct snd_intelhad *ctx =
1540 container_of(work, struct snd_intelhad, hdmi_audio_wq);
1541 struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
1542 struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port];
1543 int ret;
1544
1545 ret = pm_runtime_resume_and_get(ctx->dev);
1546 if (ret < 0)
1547 return;
1548
1549 mutex_lock(&ctx->mutex);
1550 if (ppdata->pipe < 0) {
1551 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n",
1552 __func__, ctx->port);
1553
1554 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */
1555
1556 ctx->dp_output = false;
1557 ctx->tmds_clock_speed = 0;
1558 ctx->link_rate = 0;
1559
1560 /* Shut down the stream */
1561 had_process_hot_unplug(ctx);
1562
1563 ctx->pipe = -1;
1564 } else {
1565 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1566 __func__, ctx->port, ppdata->ls_clock);
1567
1568 memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld));
1569
1570 ctx->dp_output = ppdata->dp_output;
1571 if (ctx->dp_output) {
1572 ctx->tmds_clock_speed = 0;
1573 ctx->link_rate = ppdata->ls_clock;
1574 } else {
1575 ctx->tmds_clock_speed = ppdata->ls_clock;
1576 ctx->link_rate = 0;
1577 }
1578
1579 /*
1580 * Shut down the stream before we change
1581 * the pipe assignment for this pcm device
1582 */
1583 had_process_hot_plug(ctx);
1584
1585 ctx->pipe = ppdata->pipe;
1586
1587 /* Restart the stream if necessary */
1588 had_process_mode_change(ctx);
1589 }
1590
1591 mutex_unlock(&ctx->mutex);
1592 pm_runtime_mark_last_busy(ctx->dev);
1593 pm_runtime_put_autosuspend(ctx->dev);
1594 }
1595
1596 /*
1597 * Jack interface
1598 */
had_create_jack(struct snd_intelhad * ctx,struct snd_pcm * pcm)1599 static int had_create_jack(struct snd_intelhad *ctx,
1600 struct snd_pcm *pcm)
1601 {
1602 char hdmi_str[32];
1603 int err;
1604
1605 snprintf(hdmi_str, sizeof(hdmi_str),
1606 "HDMI/DP,pcm=%d", pcm->device);
1607
1608 err = snd_jack_new(ctx->card_ctx->card, hdmi_str,
1609 SND_JACK_AVOUT, &ctx->jack,
1610 true, false);
1611 if (err < 0)
1612 return err;
1613 ctx->jack->private_data = ctx;
1614 return 0;
1615 }
1616
1617 /*
1618 * PM callbacks
1619 */
1620
hdmi_lpe_audio_suspend(struct device * dev)1621 static int hdmi_lpe_audio_suspend(struct device *dev)
1622 {
1623 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1624
1625 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot);
1626
1627 return 0;
1628 }
1629
hdmi_lpe_audio_resume(struct device * dev)1630 static int hdmi_lpe_audio_resume(struct device *dev)
1631 {
1632 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1633
1634 pm_runtime_mark_last_busy(dev);
1635
1636 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0);
1637
1638 return 0;
1639 }
1640
1641 /* release resources */
hdmi_lpe_audio_free(struct snd_card * card)1642 static void hdmi_lpe_audio_free(struct snd_card *card)
1643 {
1644 struct snd_intelhad_card *card_ctx = card->private_data;
1645 struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data;
1646 int port;
1647
1648 spin_lock_irq(&pdata->lpe_audio_slock);
1649 pdata->notify_audio_lpe = NULL;
1650 spin_unlock_irq(&pdata->lpe_audio_slock);
1651
1652 for_each_port(card_ctx, port) {
1653 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1654
1655 cancel_work_sync(&ctx->hdmi_audio_wq);
1656 }
1657 }
1658
1659 /*
1660 * hdmi_lpe_audio_probe - start bridge with i915
1661 *
1662 * This function is called when the i915 driver creates the
1663 * hdmi-lpe-audio platform device.
1664 */
__hdmi_lpe_audio_probe(struct platform_device * pdev)1665 static int __hdmi_lpe_audio_probe(struct platform_device *pdev)
1666 {
1667 struct snd_card *card;
1668 struct snd_intelhad_card *card_ctx;
1669 struct snd_intelhad *ctx;
1670 struct snd_pcm *pcm;
1671 struct intel_hdmi_lpe_audio_pdata *pdata;
1672 int irq;
1673 struct resource *res_mmio;
1674 int port, ret;
1675
1676 pdata = pdev->dev.platform_data;
1677 if (!pdata) {
1678 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1679 return -EINVAL;
1680 }
1681
1682 /* get resources */
1683 irq = platform_get_irq(pdev, 0);
1684 if (irq < 0)
1685 return irq;
1686
1687 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1688 if (!res_mmio) {
1689 dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
1690 return -ENXIO;
1691 }
1692
1693 /* create a card instance with ALSA framework */
1694 ret = snd_devm_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
1695 THIS_MODULE, sizeof(*card_ctx), &card);
1696 if (ret)
1697 return ret;
1698
1699 card_ctx = card->private_data;
1700 card_ctx->dev = &pdev->dev;
1701 card_ctx->card = card;
1702 strscpy(card->driver, INTEL_HAD);
1703 strscpy(card->shortname, "Intel HDMI/DP LPE Audio");
1704 strscpy(card->longname, "Intel HDMI/DP LPE Audio");
1705
1706 card_ctx->irq = -1;
1707
1708 card->private_free = hdmi_lpe_audio_free;
1709
1710 platform_set_drvdata(pdev, card_ctx);
1711
1712 card_ctx->num_pipes = pdata->num_pipes;
1713 card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
1714
1715 for_each_port(card_ctx, port) {
1716 ctx = &card_ctx->pcm_ctx[port];
1717 ctx->card_ctx = card_ctx;
1718 ctx->dev = card_ctx->dev;
1719 ctx->port = single_port ? -1 : port;
1720 ctx->pipe = -1;
1721
1722 spin_lock_init(&ctx->had_spinlock);
1723 mutex_init(&ctx->mutex);
1724 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
1725 }
1726
1727 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
1728 __func__, (unsigned int)res_mmio->start,
1729 (unsigned int)res_mmio->end);
1730
1731 card_ctx->mmio_start =
1732 devm_ioremap(&pdev->dev, res_mmio->start,
1733 (size_t)(resource_size(res_mmio)));
1734 if (!card_ctx->mmio_start) {
1735 dev_err(&pdev->dev, "Could not get ioremap\n");
1736 return -EACCES;
1737 }
1738
1739 /* setup interrupt handler */
1740 ret = devm_request_irq(&pdev->dev, irq, display_pipe_interrupt_handler,
1741 0, pdev->name, card_ctx);
1742 if (ret < 0) {
1743 dev_err(&pdev->dev, "request_irq failed\n");
1744 return ret;
1745 }
1746
1747 card_ctx->irq = irq;
1748
1749 /* only 32bit addressable */
1750 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1751 if (ret)
1752 return ret;
1753
1754 init_channel_allocations();
1755
1756 card_ctx->num_pipes = pdata->num_pipes;
1757 card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
1758
1759 for_each_port(card_ctx, port) {
1760 int i;
1761
1762 ctx = &card_ctx->pcm_ctx[port];
1763 ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS,
1764 MAX_CAP_STREAMS, &pcm);
1765 if (ret)
1766 return ret;
1767
1768 /* setup private data which can be retrieved when required */
1769 pcm->private_data = ctx;
1770 pcm->info_flags = 0;
1771 strscpy(pcm->name, card->shortname, strlen(card->shortname));
1772 /* setup the ops for playback */
1773 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops);
1774
1775 /* allocate dma pages;
1776 * try to allocate 600k buffer as default which is large enough
1777 */
1778 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_WC,
1779 card->dev, HAD_DEFAULT_BUFFER,
1780 HAD_MAX_BUFFER);
1781
1782 /* create controls */
1783 for (i = 0; i < ARRAY_SIZE(had_controls); i++) {
1784 struct snd_kcontrol *kctl;
1785
1786 kctl = snd_ctl_new1(&had_controls[i], ctx);
1787 if (!kctl)
1788 return -ENOMEM;
1789
1790 kctl->id.device = pcm->device;
1791
1792 ret = snd_ctl_add(card, kctl);
1793 if (ret < 0)
1794 return ret;
1795 }
1796
1797 /* Register channel map controls */
1798 ret = had_register_chmap_ctls(ctx, pcm);
1799 if (ret < 0)
1800 return ret;
1801
1802 ret = had_create_jack(ctx, pcm);
1803 if (ret < 0)
1804 return ret;
1805 }
1806
1807 ret = snd_card_register(card);
1808 if (ret)
1809 return ret;
1810
1811 spin_lock_irq(&pdata->lpe_audio_slock);
1812 pdata->notify_audio_lpe = notify_audio_lpe;
1813 spin_unlock_irq(&pdata->lpe_audio_slock);
1814
1815 pm_runtime_set_autosuspend_delay(&pdev->dev, INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS);
1816 pm_runtime_use_autosuspend(&pdev->dev);
1817 pm_runtime_enable(&pdev->dev);
1818 pm_runtime_mark_last_busy(&pdev->dev);
1819 pm_runtime_idle(&pdev->dev);
1820
1821 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
1822 for_each_port(card_ctx, port) {
1823 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1824
1825 schedule_work(&ctx->hdmi_audio_wq);
1826 }
1827
1828 return 0;
1829 }
1830
hdmi_lpe_audio_probe(struct platform_device * pdev)1831 static int hdmi_lpe_audio_probe(struct platform_device *pdev)
1832 {
1833 return snd_card_free_on_error(&pdev->dev, __hdmi_lpe_audio_probe(pdev));
1834 }
1835
1836 static const struct dev_pm_ops hdmi_lpe_audio_pm = {
1837 SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume)
1838 };
1839
1840 static struct platform_driver hdmi_lpe_audio_driver = {
1841 .driver = {
1842 .name = "hdmi-lpe-audio",
1843 .pm = pm_ptr(&hdmi_lpe_audio_pm),
1844 },
1845 .probe = hdmi_lpe_audio_probe,
1846 };
1847
1848 module_platform_driver(hdmi_lpe_audio_driver);
1849 MODULE_ALIAS("platform:hdmi_lpe_audio");
1850
1851 MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
1852 MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
1853 MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
1854 MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
1855 MODULE_DESCRIPTION("Intel HDMI Audio driver");
1856 MODULE_LICENSE("GPL v2");
1857