xref: /linux/drivers/gpu/drm/i915/display/intel_display.h (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 /*
2  * Copyright © 2006-2019 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #ifndef _INTEL_DISPLAY_H_
26 #define _INTEL_DISPLAY_H_
27 
28 #include <drm/drm_util.h>
29 
30 #include "i915_reg_defs.h"
31 #include "intel_display_limits.h"
32 
33 enum drm_scaling_filter;
34 struct dpll;
35 struct drm_atomic_state;
36 struct drm_connector;
37 struct drm_device;
38 struct drm_display_mode;
39 struct drm_encoder;
40 struct drm_file;
41 struct drm_format_info;
42 struct drm_framebuffer;
43 struct drm_i915_private;
44 struct drm_mode_fb_cmd2;
45 struct drm_modeset_acquire_ctx;
46 struct drm_plane;
47 struct drm_plane_state;
48 struct i915_address_space;
49 struct i915_gtt_view;
50 struct intel_atomic_state;
51 struct intel_crtc;
52 struct intel_crtc_state;
53 struct intel_digital_port;
54 struct intel_display;
55 struct intel_dp;
56 struct intel_encoder;
57 struct intel_initial_plane_config;
58 struct intel_link_m_n;
59 struct intel_plane;
60 struct intel_plane_state;
61 struct intel_power_domain_mask;
62 struct intel_remapped_info;
63 struct intel_rotation_info;
64 struct pci_dev;
65 struct work_struct;
66 
67 
68 #define pipe_name(p) ((p) + 'A')
69 
transcoder_name(enum transcoder transcoder)70 static inline const char *transcoder_name(enum transcoder transcoder)
71 {
72 	switch (transcoder) {
73 	case TRANSCODER_A:
74 		return "A";
75 	case TRANSCODER_B:
76 		return "B";
77 	case TRANSCODER_C:
78 		return "C";
79 	case TRANSCODER_D:
80 		return "D";
81 	case TRANSCODER_EDP:
82 		return "EDP";
83 	case TRANSCODER_DSI_A:
84 		return "DSI A";
85 	case TRANSCODER_DSI_C:
86 		return "DSI C";
87 	default:
88 		return "<invalid>";
89 	}
90 }
91 
transcoder_is_dsi(enum transcoder transcoder)92 static inline bool transcoder_is_dsi(enum transcoder transcoder)
93 {
94 	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
95 }
96 
97 #define plane_name(p) ((p) + 'A')
98 
99 #define for_each_plane_id_on_crtc(__crtc, __p) \
100 	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
101 		for_each_if((__crtc)->plane_ids_mask & BIT(__p))
102 
103 #define for_each_dbuf_slice(__dev_priv, __slice) \
104 	for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
105 		for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
106 
107 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
108 	for_each_dbuf_slice((__dev_priv), (__slice)) \
109 		for_each_if((__mask) & BIT(__slice))
110 
111 #define port_name(p) ((p) + 'A')
112 
113 /*
114  * Ports identifier referenced from other drivers.
115  * Expected to remain stable over time
116  */
port_identifier(enum port port)117 static inline const char *port_identifier(enum port port)
118 {
119 	switch (port) {
120 	case PORT_A:
121 		return "Port A";
122 	case PORT_B:
123 		return "Port B";
124 	case PORT_C:
125 		return "Port C";
126 	case PORT_D:
127 		return "Port D";
128 	case PORT_E:
129 		return "Port E";
130 	case PORT_F:
131 		return "Port F";
132 	case PORT_G:
133 		return "Port G";
134 	case PORT_H:
135 		return "Port H";
136 	case PORT_I:
137 		return "Port I";
138 	default:
139 		return "<invalid>";
140 	}
141 }
142 
143 enum tc_port {
144 	TC_PORT_NONE = -1,
145 
146 	TC_PORT_1 = 0,
147 	TC_PORT_2,
148 	TC_PORT_3,
149 	TC_PORT_4,
150 	TC_PORT_5,
151 	TC_PORT_6,
152 
153 	I915_MAX_TC_PORTS
154 };
155 
156 enum aux_ch {
157 	AUX_CH_NONE = -1,
158 
159 	AUX_CH_A,
160 	AUX_CH_B,
161 	AUX_CH_C,
162 	AUX_CH_D,
163 	AUX_CH_E, /* ICL+ */
164 	AUX_CH_F,
165 	AUX_CH_G,
166 	AUX_CH_H,
167 	AUX_CH_I,
168 
169 	/* tgl+ */
170 	AUX_CH_USBC1 = AUX_CH_D,
171 	AUX_CH_USBC2,
172 	AUX_CH_USBC3,
173 	AUX_CH_USBC4,
174 	AUX_CH_USBC5,
175 	AUX_CH_USBC6,
176 
177 	/* XE_LPD repositions D/E offsets and bitfields */
178 	AUX_CH_D_XELPD = AUX_CH_USBC5,
179 	AUX_CH_E_XELPD,
180 };
181 
182 enum phy {
183 	PHY_NONE = -1,
184 
185 	PHY_A = 0,
186 	PHY_B,
187 	PHY_C,
188 	PHY_D,
189 	PHY_E,
190 	PHY_F,
191 	PHY_G,
192 	PHY_H,
193 	PHY_I,
194 
195 	I915_MAX_PHYS
196 };
197 
198 #define phy_name(a) ((a) + 'A')
199 
200 enum phy_fia {
201 	FIA1,
202 	FIA2,
203 	FIA3,
204 };
205 
206 #define for_each_hpd_pin(__pin) \
207 	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
208 
209 #define for_each_pipe(__dev_priv, __p) \
210 	for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
211 		for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
212 
213 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
214 	for_each_pipe(__dev_priv, __p) \
215 		for_each_if((__mask) & BIT(__p))
216 
217 #define for_each_cpu_transcoder(__dev_priv, __t) \
218 	for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)	\
219 		for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
220 
221 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
222 	for_each_cpu_transcoder(__dev_priv, __t) \
223 		for_each_if ((__mask) & BIT(__t))
224 
225 #define for_each_sprite(__dev_priv, __p, __s)				\
226 	for ((__s) = 0;							\
227 	     (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];	\
228 	     (__s)++)
229 
230 #define for_each_port(__port) \
231 	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
232 
233 #define for_each_port_masked(__port, __ports_mask)			\
234 	for_each_port(__port)						\
235 		for_each_if((__ports_mask) & BIT(__port))
236 
237 #define for_each_phy_masked(__phy, __phys_mask) \
238 	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
239 		for_each_if((__phys_mask) & BIT(__phy))
240 
241 #define for_each_intel_plane(dev, intel_plane) \
242 	list_for_each_entry(intel_plane,			\
243 			    &(dev)->mode_config.plane_list,	\
244 			    base.head)
245 
246 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
247 	list_for_each_entry(intel_plane,				\
248 			    &(dev)->mode_config.plane_list,		\
249 			    base.head)					\
250 		for_each_if((plane_mask) &				\
251 			    drm_plane_mask(&intel_plane->base))
252 
253 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
254 	list_for_each_entry(intel_plane,				\
255 			    &(dev)->mode_config.plane_list,		\
256 			    base.head)					\
257 		for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
258 
259 #define for_each_intel_crtc(dev, intel_crtc)				\
260 	list_for_each_entry(intel_crtc,					\
261 			    &(dev)->mode_config.crtc_list,		\
262 			    base.head)
263 
264 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask)	\
265 	list_for_each_entry(intel_crtc,					\
266 			    &(dev)->mode_config.crtc_list,		\
267 			    base.head)					\
268 		for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
269 
270 #define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask)	\
271 	list_for_each_entry_reverse((intel_crtc),				\
272 				    &(dev)->mode_config.crtc_list,		\
273 				    base.head)					\
274 		for_each_if((pipe_mask) & BIT((intel_crtc)->pipe))
275 
276 #define for_each_intel_encoder(dev, intel_encoder)		\
277 	list_for_each_entry(intel_encoder,			\
278 			    &(dev)->mode_config.encoder_list,	\
279 			    base.head)
280 
281 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask)	\
282 	list_for_each_entry(intel_encoder,				\
283 			    &(dev)->mode_config.encoder_list,		\
284 			    base.head)					\
285 		for_each_if((encoder_mask) &				\
286 			    drm_encoder_mask(&intel_encoder->base))
287 
288 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
289 	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
290 		for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
291 			    intel_encoder_can_psr(intel_encoder))
292 
293 #define for_each_intel_dp(dev, intel_encoder)			\
294 	for_each_intel_encoder(dev, intel_encoder)		\
295 		for_each_if(intel_encoder_is_dp(intel_encoder))
296 
297 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \
298 	for_each_intel_encoder((dev), (intel_encoder)) \
299 		for_each_if(intel_encoder_can_psr(intel_encoder))
300 
301 #define for_each_intel_connector_iter(intel_connector, iter) \
302 	while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
303 
304 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
305 	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
306 		for_each_if((intel_encoder)->base.crtc == (__crtc))
307 
308 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
309 	for ((__i) = 0; \
310 	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
311 		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
312 		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
313 	     (__i)++) \
314 		for_each_if(plane)
315 
316 #define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \
317 	for ((__i) = 0; \
318 	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
319 		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
320 		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \
321 	     (__i)++) \
322 		for_each_if(crtc)
323 
324 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
325 	for ((__i) = 0; \
326 	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
327 		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
328 		      (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
329 	     (__i)++) \
330 		for_each_if(plane)
331 
332 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
333 	for ((__i) = 0; \
334 	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
335 		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
336 		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
337 	     (__i)++) \
338 		for_each_if(crtc)
339 
340 #define for_each_new_intel_crtc_in_state_reverse(__state, crtc, new_crtc_state, __i) \
341 	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
342 	     (__i) >= 0  && \
343 	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
344 	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
345 	     (__i)--) \
346 		for_each_if(crtc)
347 
348 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
349 	for ((__i) = 0; \
350 	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
351 		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
352 		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
353 		      (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
354 	     (__i)++) \
355 		for_each_if(plane)
356 
357 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
358 	for ((__i) = 0; \
359 	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
360 		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
361 		      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
362 		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
363 	     (__i)++) \
364 		for_each_if(crtc)
365 
366 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
367 	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
368 	     (__i) >= 0  && \
369 	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
370 	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
371 	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
372 	     (__i)--) \
373 		for_each_if(crtc)
374 
375 #define intel_atomic_crtc_state_for_each_plane_state( \
376 		  plane, plane_state, \
377 		  crtc_state) \
378 	for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
379 				((crtc_state)->uapi.plane_mask)) \
380 		for_each_if ((plane_state = \
381 			      to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
382 
383 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
384 	for ((__i) = 0; \
385 	     (__i) < (__state)->base.num_connector; \
386 	     (__i)++) \
387 		for_each_if ((__state)->base.connectors[__i].ptr && \
388 			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
389 			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
390 
391 #define for_each_crtc_in_masks(display, crtc, first_pipes, second_pipes, i) \
392 	for ((i) = 0; \
393 	     (i) < (I915_MAX_PIPES * 2) && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
394 	     (i)++) \
395 		for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
396 
397 #define for_each_crtc_in_masks_reverse(display, crtc, first_pipes, second_pipes, i) \
398 	for ((i) = (I915_MAX_PIPES * 2 - 1); \
399 	     (i) >= 0 && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
400 	     (i)--) \
401 		for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
402 
403 #define for_each_pipe_crtc_modeset_disable(display, crtc, crtc_state, i) \
404 	for_each_crtc_in_masks(display, crtc, \
405 			       _intel_modeset_primary_pipes(crtc_state), \
406 			       _intel_modeset_secondary_pipes(crtc_state), \
407 			       i)
408 
409 #define for_each_pipe_crtc_modeset_enable(display, crtc, crtc_state, i) \
410 	for_each_crtc_in_masks_reverse(display, crtc, \
411 				       _intel_modeset_primary_pipes(crtc_state), \
412 				       _intel_modeset_secondary_pipes(crtc_state), \
413 				       i)
414 
415 int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
416 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
417 				     struct intel_crtc *crtc);
418 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
419 			   u8 active_pipes);
420 void intel_link_compute_m_n(u16 bpp, int nlanes,
421 			    int pixel_clock, int link_clock,
422 			    int bw_overhead,
423 			    struct intel_link_m_n *m_n);
424 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
425 			      u32 pixel_format, u64 modifier);
426 enum drm_mode_status
427 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
428 				const struct drm_display_mode *mode,
429 				int num_joined_pipes);
430 enum drm_mode_status
431 intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,
432 				const struct drm_display_mode *mode);
433 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
434 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
435 bool is_trans_port_sync_master(const struct intel_crtc_state *state);
436 u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);
437 bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);
438 bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);
439 bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state);
440 bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state);
441 bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state);
442 bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state);
443 bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state);
444 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);
445 u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state);
446 u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state);
447 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state);
448 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
449 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
450 			       const struct intel_crtc_state *pipe_config,
451 			       bool fastset);
452 
453 void intel_plane_destroy(struct drm_plane *plane);
454 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
455 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
456 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
457 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
458 void i830_enable_pipe(struct intel_display *display, enum pipe pipe);
459 void i830_disable_pipe(struct intel_display *display, enum pipe pipe);
460 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
461 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
462 		      const char *name, u32 reg, int ref_freq);
463 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
464 			   const char *name, u32 reg);
465 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
466 unsigned int intel_fb_xy_to_linear(int x, int y,
467 				   const struct intel_plane_state *state,
468 				   int plane);
469 void intel_add_fb_offsets(int *x, int *y,
470 			  const struct intel_plane_state *state, int plane);
471 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
472 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
473 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
474 void intel_encoder_destroy(struct drm_encoder *encoder);
475 struct drm_display_mode *
476 intel_encoder_current_mode(struct intel_encoder *encoder);
477 void intel_encoder_get_config(struct intel_encoder *encoder,
478 			      struct intel_crtc_state *crtc_state);
479 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
480 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
481 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
482 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
483 			      enum port port);
484 
485 enum phy intel_encoder_to_phy(struct intel_encoder *encoder);
486 bool intel_encoder_is_combo(struct intel_encoder *encoder);
487 bool intel_encoder_is_snps(struct intel_encoder *encoder);
488 bool intel_encoder_is_tc(struct intel_encoder *encoder);
489 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);
490 
491 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
492 void vlv_wait_port_ready(struct intel_display *display,
493 			 struct intel_digital_port *dig_port,
494 			 unsigned int expected_mask);
495 
496 bool intel_fuzzy_clock_check(int clock1, int clock2);
497 
498 void intel_zero_m_n(struct intel_link_m_n *m_n);
499 void intel_set_m_n(struct drm_i915_private *i915,
500 		   const struct intel_link_m_n *m_n,
501 		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
502 		   i915_reg_t link_m_reg, i915_reg_t link_n_reg);
503 void intel_get_m_n(struct drm_i915_private *i915,
504 		   struct intel_link_m_n *m_n,
505 		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
506 		   i915_reg_t link_m_reg, i915_reg_t link_n_reg);
507 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
508 				    enum transcoder transcoder);
509 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
510 				    enum transcoder cpu_transcoder,
511 				    const struct intel_link_m_n *m_n);
512 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
513 				    enum transcoder cpu_transcoder,
514 				    const struct intel_link_m_n *m_n);
515 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
516 				    enum transcoder cpu_transcoder,
517 				    struct intel_link_m_n *m_n);
518 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
519 				    enum transcoder cpu_transcoder,
520 				    struct intel_link_m_n *m_n);
521 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
522 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
523 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
524 enum intel_display_power_domain
525 intel_aux_power_domain(struct intel_digital_port *dig_port);
526 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
527 				  struct intel_crtc_state *crtc_state);
528 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
529 
530 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc);
531 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
532 
533 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
534 
535 struct intel_encoder *
536 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
537 			   const struct intel_crtc_state *crtc_state);
538 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
539 				  struct intel_plane *plane);
540 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
541 			     struct intel_plane_state *plane_state,
542 			     bool visible);
543 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
544 
545 void intel_update_watermarks(struct drm_i915_private *i915);
546 
547 bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
548 			      struct intel_crtc *crtc);
549 
550 /* modesetting */
551 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
552 				      const char *reason, u8 pipe_mask);
553 int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
554 				 const char *reason);
555 int intel_modeset_commit_pipes(struct drm_i915_private *i915,
556 			       u8 pipe_mask,
557 			       struct drm_modeset_acquire_ctx *ctx);
558 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
559 					  struct intel_power_domain_mask *old_domains);
560 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
561 					  struct intel_power_domain_mask *domains);
562 
563 /* interface for intel_display_driver.c */
564 void intel_setup_outputs(struct drm_i915_private *i915);
565 int intel_initial_commit(struct drm_device *dev);
566 void intel_panel_sanitize_ssc(struct drm_i915_private *i915);
567 void intel_update_czclk(struct drm_i915_private *i915);
568 void intel_atomic_helper_free_state_worker(struct work_struct *work);
569 enum drm_mode_status intel_mode_valid(struct drm_device *dev,
570 				      const struct drm_display_mode *mode);
571 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
572 			bool nonblock);
573 
574 void intel_hpd_poll_fini(struct drm_i915_private *i915);
575 
576 /* modesetting asserts */
577 void assert_transcoder(struct drm_i915_private *dev_priv,
578 		       enum transcoder cpu_transcoder, bool state);
579 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
580 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
581 
582 bool assert_port_valid(struct drm_i915_private *i915, enum port port);
583 
584 /*
585  * Use INTEL_DISPLAY_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw
586  * state sanity checks to check for unexpected conditions which may not
587  * necessarily be a user visible problem. This will either drm_WARN() or
588  * drm_err() depending on the verbose_state_checks module param, to enable
589  * distros and users to tailor their preferred amount of i915 abrt spam.
590  */
591 #define INTEL_DISPLAY_STATE_WARN(__display, condition, format...) ({	\
592 	int __ret_warn_on = !!(condition);				\
593 	if (unlikely(__ret_warn_on))					\
594 		if (!drm_WARN((__display)->drm, (__display)->params.verbose_state_checks, format)) \
595 			drm_err((__display)->drm, format);		\
596 	unlikely(__ret_warn_on);					\
597 })
598 
599 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915);
600 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
601 
602 #endif
603