1 /*
2 * Copyright 2008-2012 Freescale Semiconductor Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution.
11 * * Neither the name of Freescale Semiconductor nor the
12 * names of its contributors may be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 *
16 * ALTERNATIVELY, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL") as published by the Free Software
18 * Foundation, either version 2 of that License or (at your option) any
19 * later version.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33
34 /******************************************************************************
35 @File fm_pcd.h
36
37 @Description FM PCD ...
38 *//***************************************************************************/
39 #ifndef __FM_PCD_H
40 #define __FM_PCD_H
41
42 #include "std_ext.h"
43 #include "error_ext.h"
44 #include "list_ext.h"
45 #include "fm_pcd_ext.h"
46 #include "fm_common.h"
47 #include "fsl_fman_prs.h"
48 #include "fsl_fman_kg.h"
49
50 #define __ERR_MODULE__ MODULE_FM_PCD
51
52
53 /****************************/
54 /* Defaults */
55 /****************************/
56 #define DEFAULT_plcrAutoRefresh FALSE
57 #define DEFAULT_fmPcdKgErrorExceptions (FM_EX_KG_DOUBLE_ECC | FM_EX_KG_KEYSIZE_OVERFLOW)
58 #define DEFAULT_fmPcdPlcrErrorExceptions (FM_PCD_EX_PLCR_DOUBLE_ECC | FM_PCD_EX_PLCR_INIT_ENTRY_ERROR)
59 #define DEFAULT_fmPcdPlcrExceptions 0
60 #define DEFAULT_fmPcdPrsErrorExceptions (FM_PCD_EX_PRS_DOUBLE_ECC)
61
62 #define DEFAULT_fmPcdPrsExceptions FM_PCD_EX_PRS_SINGLE_ECC
63 #define DEFAULT_numOfUsedProfilesPerWindow 16
64 #define DEFAULT_numOfSharedPlcrProfiles 4
65
66 /****************************/
67 /* Network defines */
68 /****************************/
69 #define UDP_HEADER_SIZE 8
70
71 #define ESP_SPI_OFFSET 0
72 #define ESP_SPI_SIZE 4
73 #define ESP_SEQ_NUM_OFFSET ESP_SPI_SIZE
74 #define ESP_SEQ_NUM_SIZE 4
75
76 /****************************/
77 /* General defines */
78 /****************************/
79 #define ILLEGAL_CLS_PLAN 0xff
80 #define ILLEGAL_NETENV 0xff
81
82 #define FM_PCD_MAX_NUM_OF_ALIAS_HDRS 3
83
84 /****************************/
85 /* Error defines */
86 /****************************/
87
88 #define FM_PCD_EX_PLCR_DOUBLE_ECC 0x20000000
89 #define FM_PCD_EX_PLCR_INIT_ENTRY_ERROR 0x10000000
90 #define FM_PCD_EX_PLCR_PRAM_SELF_INIT_COMPLETE 0x08000000
91 #define FM_PCD_EX_PLCR_ATOMIC_ACTION_COMPLETE 0x04000000
92
93 #define GET_FM_PCD_EXCEPTION_FLAG(bitMask, exception) \
94 switch (exception){ \
95 case e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC: \
96 bitMask = FM_EX_KG_DOUBLE_ECC; break; \
97 case e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC: \
98 bitMask = FM_PCD_EX_PLCR_DOUBLE_ECC; break; \
99 case e_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW: \
100 bitMask = FM_EX_KG_KEYSIZE_OVERFLOW; break; \
101 case e_FM_PCD_PLCR_EXCEPTION_INIT_ENTRY_ERROR: \
102 bitMask = FM_PCD_EX_PLCR_INIT_ENTRY_ERROR; break; \
103 case e_FM_PCD_PLCR_EXCEPTION_PRAM_SELF_INIT_COMPLETE: \
104 bitMask = FM_PCD_EX_PLCR_PRAM_SELF_INIT_COMPLETE; break; \
105 case e_FM_PCD_PLCR_EXCEPTION_ATOMIC_ACTION_COMPLETE: \
106 bitMask = FM_PCD_EX_PLCR_ATOMIC_ACTION_COMPLETE; break; \
107 case e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC: \
108 bitMask = FM_PCD_EX_PRS_DOUBLE_ECC; break; \
109 case e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC: \
110 bitMask = FM_PCD_EX_PRS_SINGLE_ECC; break; \
111 default: bitMask = 0;break;}
112
113 /***********************************************************************/
114 /* Policer defines */
115 /***********************************************************************/
116 #define FM_PCD_PLCR_GCR_STEN 0x40000000
117 #define FM_PCD_PLCR_DOUBLE_ECC 0x80000000
118 #define FM_PCD_PLCR_INIT_ENTRY_ERROR 0x40000000
119 #define FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE 0x80000000
120 #define FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE 0x40000000
121
122 /***********************************************************************/
123 /* Memory map */
124 /***********************************************************************/
125 #if defined(__MWERKS__) && !defined(__GNUC__)
126 #pragma pack(push,1)
127 #endif /* defined(__MWERKS__) && ... */
128
129
130 typedef struct {
131 /* General Configuration and Status Registers */
132 volatile uint32_t fmpl_gcr; /* 0x000 FMPL_GCR - FM Policer General Configuration */
133 volatile uint32_t fmpl_gsr; /* 0x004 FMPL_GSR - FM Policer Global Status Register */
134 volatile uint32_t fmpl_evr; /* 0x008 FMPL_EVR - FM Policer Event Register */
135 volatile uint32_t fmpl_ier; /* 0x00C FMPL_IER - FM Policer Interrupt Enable Register */
136 volatile uint32_t fmpl_ifr; /* 0x010 FMPL_IFR - FM Policer Interrupt Force Register */
137 volatile uint32_t fmpl_eevr; /* 0x014 FMPL_EEVR - FM Policer Error Event Register */
138 volatile uint32_t fmpl_eier; /* 0x018 FMPL_EIER - FM Policer Error Interrupt Enable Register */
139 volatile uint32_t fmpl_eifr; /* 0x01C FMPL_EIFR - FM Policer Error Interrupt Force Register */
140 /* Global Statistic Counters */
141 volatile uint32_t fmpl_rpcnt; /* 0x020 FMPL_RPC - FM Policer RED Packets Counter */
142 volatile uint32_t fmpl_ypcnt; /* 0x024 FMPL_YPC - FM Policer YELLOW Packets Counter */
143 volatile uint32_t fmpl_rrpcnt; /* 0x028 FMPL_RRPC - FM Policer Recolored RED Packet Counter */
144 volatile uint32_t fmpl_rypcnt; /* 0x02C FMPL_RYPC - FM Policer Recolored YELLOW Packet Counter */
145 volatile uint32_t fmpl_tpcnt; /* 0x030 FMPL_TPC - FM Policer Total Packet Counter */
146 volatile uint32_t fmpl_flmcnt; /* 0x034 FMPL_FLMC - FM Policer Frame Length Mismatch Counter */
147 volatile uint32_t fmpl_res0[21]; /* 0x038 - 0x08B Reserved */
148 /* Profile RAM Access Registers */
149 volatile uint32_t fmpl_par; /* 0x08C FMPL_PAR - FM Policer Profile Action Register*/
150 t_FmPcdPlcrProfileRegs profileRegs;
151 /* Error Capture Registers */
152 volatile uint32_t fmpl_serc; /* 0x100 FMPL_SERC - FM Policer Soft Error Capture */
153 volatile uint32_t fmpl_upcr; /* 0x104 FMPL_UPCR - FM Policer Uninitialized Profile Capture Register */
154 volatile uint32_t fmpl_res2; /* 0x108 Reserved */
155 /* Debug Registers */
156 volatile uint32_t fmpl_res3[61]; /* 0x10C-0x200 Reserved Debug*/
157 /* Profile Selection Mapping Registers Per Port-ID (n=1-11, 16) */
158 volatile uint32_t fmpl_dpmr; /* 0x200 FMPL_DPMR - FM Policer Default Mapping Register */
159 volatile uint32_t fmpl_pmr[63]; /*+default 0x204-0x2FF FMPL_PMR1 - FMPL_PMR63, - FM Policer Profile Mapping Registers.
160 (for port-ID 1-11, only for supported Port-ID registers) */
161 } t_FmPcdPlcrRegs;
162
163 #if defined(__MWERKS__) && !defined(__GNUC__)
164 #pragma pack(pop)
165 #endif /* defined(__MWERKS__) && ... */
166
167
168 /***********************************************************************/
169 /* Driver's internal structures */
170 /***********************************************************************/
171
172 typedef struct {
173 bool known;
174 uint8_t id;
175 } t_FmPcdKgSchemesExtractsEntry;
176
177 typedef struct {
178 t_FmPcdKgSchemesExtractsEntry extractsArray[FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY];
179 } t_FmPcdKgSchemesExtracts;
180
181 typedef struct {
182 t_Handle h_Manip;
183 bool keepRes;
184 e_FmPcdEngine nextEngine;
185 uint8_t parseCode;
186 } t_FmPcdInfoForManip;
187
188 /**************************************************************************//**
189 @Description A structure of parameters to communicate
190 between the port and PCD regarding the KG scheme.
191 *//***************************************************************************/
192 typedef struct {
193 uint8_t netEnvId; /* in */
194 uint8_t numOfDistinctionUnits; /* in */
195 uint8_t unitIds[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; /* in */
196 uint32_t vector; /* out */
197 } t_NetEnvParams;
198
199 typedef struct {
200 bool allocated;
201 uint8_t ownerId; /* guestId for KG in multi-partition only.
202 portId for PLCR in any environment */
203 } t_FmPcdAllocMng;
204
205 typedef struct {
206 volatile bool lock;
207 bool used;
208 uint8_t owners;
209 uint8_t netEnvId;
210 uint8_t guestId;
211 uint8_t baseEntry;
212 uint16_t sizeOfGrp;
213 protocolOpt_t optArray[FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)];
214 } t_FmPcdKgClsPlanGrp;
215
216 typedef struct {
217 t_Handle h_FmPcd;
218 uint8_t schemeId;
219 t_FmPcdLock *p_Lock;
220 bool valid;
221 uint8_t netEnvId;
222 uint8_t owners;
223 uint32_t matchVector;
224 uint32_t ccUnits;
225 bool nextRelativePlcrProfile;
226 uint16_t relativeProfileId;
227 uint16_t numOfProfiles;
228 t_FmPcdKgKeyOrder orderedArray;
229 e_FmPcdEngine nextEngine;
230 e_FmPcdDoneAction doneAction;
231 bool requiredActionFlag;
232 uint32_t requiredAction;
233 bool extractedOrs;
234 uint8_t bitOffsetInPlcrProfile;
235 bool directPlcr;
236 #if (DPAA_VERSION >= 11)
237 bool vspe;
238 #endif
239 } t_FmPcdKgScheme;
240
241 typedef union {
242 struct fman_kg_scheme_regs schemeRegs;
243 struct fman_kg_pe_regs portRegs;
244 struct fman_kg_cp_regs clsPlanRegs;
245 } u_FmPcdKgIndirectAccessRegs;
246
247 typedef struct {
248 struct fman_kg_regs *p_FmPcdKgRegs;
249 uint32_t schemeExceptionsBitMask;
250 uint8_t numOfSchemes;
251 t_Handle h_HwSpinlock;
252 uint8_t schemesIds[FM_PCD_KG_NUM_OF_SCHEMES];
253 t_FmPcdKgScheme schemes[FM_PCD_KG_NUM_OF_SCHEMES];
254 t_FmPcdKgClsPlanGrp clsPlanGrps[FM_MAX_NUM_OF_PORTS];
255 uint8_t emptyClsPlanGrpId;
256 t_FmPcdAllocMng schemesMng[FM_PCD_KG_NUM_OF_SCHEMES]; /* only for MASTER ! */
257 t_FmPcdAllocMng clsPlanBlocksMng[FM_PCD_MAX_NUM_OF_CLS_PLANS/CLS_PLAN_NUM_PER_GRP];
258 u_FmPcdKgIndirectAccessRegs *p_IndirectAccessRegs;
259 } t_FmPcdKg;
260
261 typedef struct {
262 uint16_t profilesBase;
263 uint16_t numOfProfiles;
264 t_Handle h_FmPort;
265 } t_FmPcdPlcrMapParam;
266
267 typedef struct {
268 uint16_t absoluteProfileId;
269 t_Handle h_FmPcd;
270 bool valid;
271 t_FmPcdLock *p_Lock;
272 t_FmPcdAllocMng profilesMng;
273 bool requiredActionFlag;
274 uint32_t requiredAction;
275 e_FmPcdEngine nextEngineOnGreen; /**< Green next engine type */
276 u_FmPcdPlcrNextEngineParams paramsOnGreen; /**< Green next engine params */
277
278 e_FmPcdEngine nextEngineOnYellow; /**< Yellow next engine type */
279 u_FmPcdPlcrNextEngineParams paramsOnYellow; /**< Yellow next engine params */
280
281 e_FmPcdEngine nextEngineOnRed; /**< Red next engine type */
282 u_FmPcdPlcrNextEngineParams paramsOnRed; /**< Red next engine params */
283 } t_FmPcdPlcrProfile;
284
285 typedef struct {
286 t_FmPcdPlcrRegs *p_FmPcdPlcrRegs;
287 uint16_t partPlcrProfilesBase;
288 uint16_t partNumOfPlcrProfiles;
289 t_FmPcdPlcrProfile profiles[FM_PCD_PLCR_NUM_ENTRIES];
290 uint16_t numOfSharedProfiles;
291 uint16_t sharedProfilesIds[FM_PCD_PLCR_NUM_ENTRIES];
292 t_FmPcdPlcrMapParam portsMapping[FM_MAX_NUM_OF_PORTS];
293 t_Handle h_HwSpinlock;
294 t_Handle h_SwSpinlock;
295 } t_FmPcdPlcr;
296
297 typedef struct {
298 uint32_t *p_SwPrsCode;
299 uint32_t *p_CurrSwPrs;
300 uint8_t currLabel;
301 struct fman_prs_regs *p_FmPcdPrsRegs;
302 t_FmPcdPrsLabelParams labelsTable[FM_PCD_PRS_NUM_OF_LABELS];
303 uint32_t fmPcdPrsPortIdStatistics;
304 } t_FmPcdPrs;
305
306 typedef struct {
307 struct {
308 e_NetHeaderType hdr;
309 protocolOpt_t opt; /* only one option !! */
310 } hdrs[FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS];
311 } t_FmPcdIntDistinctionUnit;
312
313 typedef struct {
314 e_NetHeaderType hdr;
315 protocolOpt_t opt; /* only one option !! */
316 e_NetHeaderType aliasHdr;
317 } t_FmPcdNetEnvAliases;
318
319 typedef struct {
320 uint8_t netEnvId;
321 t_Handle h_FmPcd;
322 t_Handle h_Spinlock;
323 bool used;
324 uint8_t owners;
325 uint8_t clsPlanGrpId;
326 t_FmPcdIntDistinctionUnit units[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS];
327 uint32_t unitsVectors[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS];
328 uint32_t lcvs[FM_PCD_PRS_NUM_OF_HDRS];
329 uint32_t macsecVector;
330 t_FmPcdNetEnvAliases aliasHdrs[FM_PCD_MAX_NUM_OF_ALIAS_HDRS];
331 } t_FmPcdNetEnv;
332
333 typedef struct {
334 struct fman_prs_cfg dfltCfg;
335 bool plcrAutoRefresh;
336 uint16_t prsMaxParseCycleLimit;
337 } t_FmPcdDriverParam;
338
339 typedef struct {
340 t_Handle h_Fm;
341 t_Handle h_FmMuram;
342 t_FmRevisionInfo fmRevInfo;
343
344 uint64_t physicalMuramBase;
345
346 t_Handle h_Spinlock;
347 t_List freeLocksLst;
348 t_List acquiredLocksLst;
349
350 t_Handle h_IpcSession; /* relevant for guest only */
351 bool enabled;
352 uint8_t guestId; /**< Guest Partition Id */
353 uint8_t numOfEnabledGuestPartitionsPcds;
354 char fmPcdModuleName[MODULE_NAME_SIZE];
355 char fmPcdIpcHandlerModuleName[MODULE_NAME_SIZE]; /* relevant for guest only - this is the master's name */
356 t_FmPcdNetEnv netEnvs[FM_MAX_NUM_OF_PORTS];
357 t_FmPcdKg *p_FmPcdKg;
358 t_FmPcdPlcr *p_FmPcdPlcr;
359 t_FmPcdPrs *p_FmPcdPrs;
360
361 void *p_CcShadow; /**< CC MURAM shadow */
362 uint32_t ccShadowSize;
363 uint32_t ccShadowAlign;
364 volatile bool shadowLock;
365 t_Handle h_ShadowSpinlock;
366
367 t_Handle h_Hc;
368
369 uint32_t exceptions;
370 t_FmPcdExceptionCallback *f_Exception;
371 t_FmPcdIdExceptionCallback *f_FmPcdIndexedException;
372 t_Handle h_App;
373 uintptr_t ipv6FrameIdAddr;
374 uintptr_t capwapFrameIdAddr;
375 bool advancedOffloadSupport;
376
377 t_FmPcdDriverParam *p_FmPcdDriverParam;
378 } t_FmPcd;
379
380 #if (DPAA_VERSION >= 11)
381 typedef uint8_t t_FmPcdFrmReplicUpdateType;
382 #define FRM_REPLIC_UPDATE_COUNTER 0x01
383 #define FRM_REPLIC_UPDATE_INFO 0x02
384 #endif /* (DPAA_VERSION >= 11) */
385 /***********************************************************************/
386 /* PCD internal routines */
387 /***********************************************************************/
388
389 t_Error PcdGetVectorForOpt(t_FmPcd *p_FmPcd, uint8_t netEnvId, protocolOpt_t opt, uint32_t *p_Vector);
390 t_Error PcdGetUnitsVector(t_FmPcd *p_FmPcd, t_NetEnvParams *p_Params);
391 bool PcdNetEnvIsUnitWithoutOpts(t_FmPcd *p_FmPcd, uint8_t netEnvId, uint32_t unitVector);
392 t_Error PcdGetClsPlanGrpParams(t_FmPcd *p_FmPcd, t_FmPcdKgInterModuleClsPlanGrpParams *p_GrpParams);
393 void FmPcdSetClsPlanGrpId(t_FmPcd *p_FmPcd, uint8_t netEnvId, uint8_t clsPlanGrpId);
394 e_NetHeaderType FmPcdGetAliasHdr(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr);
395 uint8_t FmPcdNetEnvGetUnitIdForSingleHdr(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr);
396 uint8_t FmPcdNetEnvGetUnitId(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr, bool interchangeable, protocolOpt_t opt);
397
398 t_Error FmPcdManipBuildIpReassmScheme(t_FmPcd *p_FmPcd, t_Handle h_NetEnv, t_Handle h_CcTree, t_Handle h_Manip, bool isIpv4, uint8_t groupId);
399 t_Error FmPcdManipDeleteIpReassmSchemes(t_Handle h_Manip);
400 t_Error FmPcdManipBuildCapwapReassmScheme(t_FmPcd *p_FmPcd, t_Handle h_NetEnv, t_Handle h_CcTree, t_Handle h_Manip, uint8_t groupId);
401 t_Error FmPcdManipDeleteCapwapReassmSchemes(t_Handle h_Manip);
402 bool FmPcdManipIpReassmIsIpv6Hdr(t_Handle h_Manip);
403
404 t_Handle KgConfig( t_FmPcd *p_FmPcd, t_FmPcdParams *p_FmPcdParams);
405 t_Error KgInit(t_FmPcd *p_FmPcd);
406 t_Error KgFree(t_FmPcd *p_FmPcd);
407 void KgSetClsPlan(t_Handle h_FmPcd, t_FmPcdKgInterModuleClsPlanSet *p_Set);
408 bool KgIsSchemeAlwaysDirect(t_Handle h_FmPcd, uint8_t schemeId);
409 void KgEnable(t_FmPcd *p_FmPcd);
410 void KgDisable(t_FmPcd *p_FmPcd);
411 t_Error KgAllocClsPlanEntries(t_Handle h_FmPcd, uint16_t numOfClsPlanEntries, uint8_t guestId, uint8_t *p_First);
412 void KgFreeClsPlanEntries(t_Handle h_FmPcd, uint16_t numOfClsPlanEntries, uint8_t guestId, uint8_t base);
413
414 /* only for MULTI partittion */
415 t_Error FmPcdKgAllocSchemes(t_Handle h_FmPcd, uint8_t numOfSchemes, uint8_t guestId, uint8_t *p_SchemesIds);
416 t_Error FmPcdKgFreeSchemes(t_Handle h_FmPcd, uint8_t numOfSchemes, uint8_t guestId, uint8_t *p_SchemesIds);
417 /* only for SINGLE partittion */
418 t_Error KgBindPortToSchemes(t_Handle h_FmPcd , uint8_t hardwarePortId, uint32_t spReg);
419
420 t_FmPcdLock *FmPcdAcquireLock(t_Handle h_FmPcd);
421 void FmPcdReleaseLock(t_Handle h_FmPcd, t_FmPcdLock *p_Lock);
422
423 t_Handle PlcrConfig(t_FmPcd *p_FmPcd, t_FmPcdParams *p_FmPcdParams);
424 t_Error PlcrInit(t_FmPcd *p_FmPcd);
425 t_Error PlcrFree(t_FmPcd *p_FmPcd);
426 void PlcrEnable(t_FmPcd *p_FmPcd);
427 void PlcrDisable(t_FmPcd *p_FmPcd);
428 uint16_t PlcrAllocProfilesForPartition(t_FmPcd *p_FmPcd, uint16_t base, uint16_t numOfProfiles, uint8_t guestId);
429 void PlcrFreeProfilesForPartition(t_FmPcd *p_FmPcd, uint16_t base, uint16_t numOfProfiles, uint8_t guestId);
430 t_Error PlcrSetPortProfiles(t_FmPcd *p_FmPcd,
431 uint8_t hardwarePortId,
432 uint16_t numOfProfiles,
433 uint16_t base);
434 t_Error PlcrClearPortProfiles(t_FmPcd *p_FmPcd, uint8_t hardwarePortId);
435
436 t_Handle PrsConfig(t_FmPcd *p_FmPcd,t_FmPcdParams *p_FmPcdParams);
437 t_Error PrsInit(t_FmPcd *p_FmPcd);
438 void PrsEnable(t_FmPcd *p_FmPcd);
439 void PrsDisable(t_FmPcd *p_FmPcd);
440 void PrsFree(t_FmPcd *p_FmPcd );
441 t_Error PrsIncludePortInStatistics(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, bool include);
442
443 t_Error FmPcdCcGetGrpParams(t_Handle treeId, uint8_t grpId, uint32_t *p_GrpBits, uint8_t *p_GrpBase);
444 uint8_t FmPcdCcGetOffset(t_Handle h_CcNode);
445 uint8_t FmPcdCcGetParseCode(t_Handle h_CcNode);
446 uint16_t FmPcdCcGetNumOfKeys(t_Handle h_CcNode);
447 t_Error ValidateNextEngineParams(t_Handle h_FmPcd, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams, e_FmPcdCcStatsMode supportedStatsMode);
448
449 void FmPcdManipUpdateOwner(t_Handle h_Manip, bool add);
450 t_Error FmPcdManipCheckParamsForCcNextEngine(t_FmPcdCcNextEngineParams *p_InfoForManip, uint32_t *requiredAction);
451 void FmPcdManipUpdateAdResultForCc(t_Handle h_Manip,
452 t_FmPcdCcNextEngineParams *p_CcNextEngineParams,
453 t_Handle p_Ad,
454 t_Handle *p_AdNewPtr);
455 void FmPcdManipUpdateAdContLookupForCc(t_Handle h_Manip, t_Handle p_Ad, t_Handle *p_AdNew, uint32_t adTableOffset);
456 void FmPcdManipUpdateOwner(t_Handle h_Manip, bool add);
457 t_Error FmPcdManipCheckParamsWithCcNodeParams(t_Handle h_Manip, t_Handle h_FmPcdCcNode);
458 #ifdef FM_CAPWAP_SUPPORT
459 t_Handle FmPcdManipApplSpecificBuild(void);
460 bool FmPcdManipIsCapwapApplSpecific(t_Handle h_Manip);
461 #endif /* FM_CAPWAP_SUPPORT */
462 #if (DPAA_VERSION >= 11)
463 void * FrmReplicGroupGetSourceTableDescriptor(t_Handle h_ReplicGroup);
464 void FrmReplicGroupUpdateOwner(t_Handle h_ReplicGroup, bool add);
465 void FrmReplicGroupUpdateAd(t_Handle h_ReplicGroup, void *p_Ad, t_Handle *h_AdNew);
466
467 void FmPcdCcGetAdTablesThatPointOnReplicGroup(t_Handle h_Node,
468 t_Handle h_ReplicGroup,
469 t_List *p_AdTables,
470 uint32_t *p_NumOfAdTables);
471 #endif /* (DPAA_VERSION >= 11) */
472
473 void EnqueueNodeInfoToRelevantLst(t_List *p_List, t_CcNodeInformation *p_CcInfo, t_Handle h_Spinlock);
474 void DequeueNodeInfoFromRelevantLst(t_List *p_List, t_Handle h_Info, t_Handle h_Spinlock);
475 t_CcNodeInformation* FindNodeInfoInReleventLst(t_List *p_List, t_Handle h_Info, t_Handle h_Spinlock);
476 t_List *FmPcdManipGetSpinlock(t_Handle h_Manip);
477 t_List *FmPcdManipGetNodeLstPointedOnThisManip(t_Handle h_Manip);
478
479 typedef struct
480 {
481 t_Handle h_StatsAd;
482 t_Handle h_StatsCounters;
483 #if (DPAA_VERSION >= 11)
484 t_Handle h_StatsFLRs;
485 #endif /* (DPAA_VERSION >= 11) */
486 } t_FmPcdCcStatsParams;
487
488 void NextStepAd(t_Handle h_Ad,
489 t_FmPcdCcStatsParams *p_FmPcdCcStatsParams,
490 t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams,
491 t_FmPcd *p_FmPcd);
492 void ReleaseLst(t_List *p_List);
493
FmPcdGetMuramHandle(t_Handle h_FmPcd)494 static __inline__ t_Handle FmPcdGetMuramHandle(t_Handle h_FmPcd)
495 {
496 t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
497 ASSERT_COND(p_FmPcd);
498 return p_FmPcd->h_FmMuram;
499 }
500
FmPcdGetMuramPhysBase(t_Handle h_FmPcd)501 static __inline__ uint64_t FmPcdGetMuramPhysBase(t_Handle h_FmPcd)
502 {
503 t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
504 ASSERT_COND(p_FmPcd);
505 return p_FmPcd->physicalMuramBase;
506 }
507
FmPcdLockSpinlock(t_FmPcdLock * p_Lock)508 static __inline__ uint32_t FmPcdLockSpinlock(t_FmPcdLock *p_Lock)
509 {
510 ASSERT_COND(p_Lock);
511 return XX_LockIntrSpinlock(p_Lock->h_Spinlock);
512 }
513
FmPcdUnlockSpinlock(t_FmPcdLock * p_Lock,uint32_t flags)514 static __inline__ void FmPcdUnlockSpinlock(t_FmPcdLock *p_Lock, uint32_t flags)
515 {
516 ASSERT_COND(p_Lock);
517 XX_UnlockIntrSpinlock(p_Lock->h_Spinlock, flags);
518 }
519
FmPcdLockTryLock(t_FmPcdLock * p_Lock)520 static __inline__ bool FmPcdLockTryLock(t_FmPcdLock *p_Lock)
521 {
522 uint32_t intFlags;
523
524 ASSERT_COND(p_Lock);
525 intFlags = XX_LockIntrSpinlock(p_Lock->h_Spinlock);
526 if (p_Lock->flag)
527 {
528 XX_UnlockIntrSpinlock(p_Lock->h_Spinlock, intFlags);
529 return FALSE;
530 }
531 p_Lock->flag = TRUE;
532 XX_UnlockIntrSpinlock(p_Lock->h_Spinlock, intFlags);
533 return TRUE;
534 }
535
FmPcdLockUnlock(t_FmPcdLock * p_Lock)536 static __inline__ void FmPcdLockUnlock(t_FmPcdLock *p_Lock)
537 {
538 ASSERT_COND(p_Lock);
539 p_Lock->flag = FALSE;
540 }
541
542
543 #endif /* __FM_PCD_H */
544