1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 #ifndef __AMDGPU_GMC_H__
27 #define __AMDGPU_GMC_H__
28
29 #include <linux/types.h>
30
31 #include "amdgpu_irq.h"
32 #include "amdgpu_ras.h"
33
34 /* VA hole for 48bit addresses on Vega10 */
35 #define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL
36 #define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL
37
38 /*
39 * Hardware is programmed as if the hole doesn't exists with start and end
40 * address values.
41 *
42 * This mask is used to remove the upper 16bits of the VA and so come up with
43 * the linear addr value.
44 */
45 #define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL
46
47 /*
48 * Ring size as power of two for the log of recent faults.
49 */
50 #define AMDGPU_GMC_FAULT_RING_ORDER 8
51 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER)
52
53 /*
54 * Hash size as power of two for the log of recent faults
55 */
56 #define AMDGPU_GMC_FAULT_HASH_ORDER 8
57 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER)
58
59 /*
60 * Number of IH timestamp ticks until a fault is considered handled
61 */
62 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL
63
64 struct firmware;
65
66 enum amdgpu_memory_partition {
67 UNKNOWN_MEMORY_PARTITION_MODE = 0,
68 AMDGPU_NPS1_PARTITION_MODE = 1,
69 AMDGPU_NPS2_PARTITION_MODE = 2,
70 AMDGPU_NPS3_PARTITION_MODE = 3,
71 AMDGPU_NPS4_PARTITION_MODE = 4,
72 AMDGPU_NPS6_PARTITION_MODE = 6,
73 AMDGPU_NPS8_PARTITION_MODE = 8,
74 };
75
76 /*
77 * GMC page fault information
78 */
79 struct amdgpu_gmc_fault {
80 uint64_t timestamp:48;
81 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER;
82 atomic64_t key;
83 uint64_t timestamp_expiry:48;
84 };
85
86 /*
87 * VMHUB structures, functions & helpers
88 */
89 struct amdgpu_vmhub_funcs {
90 void (*print_l2_protection_fault_status)(struct amdgpu_device *adev,
91 uint32_t status);
92 uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type);
93 };
94
95 struct amdgpu_vmhub {
96 uint32_t ctx0_ptb_addr_lo32;
97 uint32_t ctx0_ptb_addr_hi32;
98 uint32_t vm_inv_eng0_sem;
99 uint32_t vm_inv_eng0_req;
100 uint32_t vm_inv_eng0_ack;
101 uint32_t vm_context0_cntl;
102 uint32_t vm_l2_pro_fault_status;
103 uint32_t vm_l2_pro_fault_cntl;
104
105 /*
106 * store the register distances between two continuous context domain
107 * and invalidation engine.
108 */
109 uint32_t ctx_distance;
110 uint32_t ctx_addr_distance; /* include LO32/HI32 */
111 uint32_t eng_distance;
112 uint32_t eng_addr_distance; /* include LO32/HI32 */
113
114 uint32_t vm_cntx_cntl;
115 uint32_t vm_cntx_cntl_vm_fault;
116 uint32_t vm_l2_bank_select_reserved_cid2;
117
118 uint32_t vm_contexts_disable;
119
120 bool sdma_invalidation_workaround;
121
122 const struct amdgpu_vmhub_funcs *vmhub_funcs;
123 };
124
125 /*
126 * GPU MC structures, functions & helpers
127 */
128 struct amdgpu_gmc_funcs {
129 /* flush the vm tlb via mmio */
130 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
131 uint32_t vmhub, uint32_t flush_type);
132 /* flush the vm tlb via pasid */
133 void (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
134 uint32_t flush_type, bool all_hub,
135 uint32_t inst);
136 /* flush the vm tlb via ring */
137 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
138 uint64_t pd_addr);
139 /* Change the VMID -> PASID mapping */
140 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
141 unsigned pasid);
142 /* enable/disable PRT support */
143 void (*set_prt)(struct amdgpu_device *adev, bool enable);
144 /* map mtype to hardware flags */
145 uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags);
146 /* get the pde for a given mc addr */
147 void (*get_vm_pde)(struct amdgpu_device *adev, int level,
148 u64 *dst, u64 *flags);
149 /* get the pte flags to use for a BO VA mapping */
150 void (*get_vm_pte)(struct amdgpu_device *adev,
151 struct amdgpu_bo_va_mapping *mapping,
152 uint64_t *flags);
153 /* override per-page pte flags */
154 void (*override_vm_pte_flags)(struct amdgpu_device *dev,
155 struct amdgpu_vm *vm,
156 uint64_t addr, uint64_t *flags);
157 /* get the amount of memory used by the vbios for pre-OS console */
158 unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev);
159 /* get the DCC buffer alignment */
160 unsigned int (*get_dcc_alignment)(struct amdgpu_device *adev);
161
162 enum amdgpu_memory_partition (*query_mem_partition_mode)(
163 struct amdgpu_device *adev);
164 };
165
166 struct amdgpu_xgmi_ras {
167 struct amdgpu_ras_block_object ras_block;
168 };
169
170 struct amdgpu_xgmi {
171 /* from psp */
172 u64 node_id;
173 u64 hive_id;
174 /* fixed per family */
175 u64 node_segment_size;
176 /* physical node (0-3) */
177 unsigned physical_node_id;
178 /* number of nodes (0-4) */
179 unsigned num_physical_nodes;
180 /* gpu list in the same hive */
181 struct list_head head;
182 bool supported;
183 struct ras_common_if *ras_if;
184 bool connected_to_cpu;
185 bool pending_reset;
186 struct amdgpu_xgmi_ras *ras;
187 };
188
189 struct amdgpu_mem_partition_info {
190 union {
191 struct {
192 uint32_t fpfn;
193 uint32_t lpfn;
194 } range;
195 struct {
196 int node;
197 } numa;
198 };
199 uint64_t size;
200 };
201
202 #define INVALID_PFN -1
203
204 struct amdgpu_gmc_memrange {
205 uint64_t base_address;
206 uint64_t limit_address;
207 uint32_t flags;
208 int nid_mask;
209 };
210
211 enum amdgpu_gart_placement {
212 AMDGPU_GART_PLACEMENT_BEST_FIT = 0,
213 AMDGPU_GART_PLACEMENT_HIGH,
214 AMDGPU_GART_PLACEMENT_LOW,
215 };
216
217 struct amdgpu_gmc {
218 /* FB's physical address in MMIO space (for CPU to
219 * map FB). This is different compared to the agp/
220 * gart/vram_start/end field as the later is from
221 * GPU's view and aper_base is from CPU's view.
222 */
223 resource_size_t aper_size;
224 resource_size_t aper_base;
225 /* for some chips with <= 32MB we need to lie
226 * about vram size near mc fb location */
227 u64 mc_vram_size;
228 u64 visible_vram_size;
229 /* AGP aperture start and end in MC address space
230 * Driver find a hole in the MC address space
231 * to place AGP by setting MC_VM_AGP_BOT/TOP registers
232 * Under VMID0, logical address == MC address. AGP
233 * aperture maps to physical bus or IOVA addressed.
234 * AGP aperture is used to simulate FB in ZFB case.
235 * AGP aperture is also used for page table in system
236 * memory (mainly for APU).
237 *
238 */
239 u64 agp_size;
240 u64 agp_start;
241 u64 agp_end;
242 /* GART aperture start and end in MC address space
243 * Driver find a hole in the MC address space
244 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR
245 * registers
246 * Under VMID0, logical address inside GART aperture will
247 * be translated through gpuvm gart page table to access
248 * paged system memory
249 */
250 u64 gart_size;
251 u64 gart_start;
252 u64 gart_end;
253 /* Frame buffer aperture of this GPU device. Different from
254 * fb_start (see below), this only covers the local GPU device.
255 * If driver uses FB aperture to access FB, driver get fb_start from
256 * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start
257 * of this local device by adding an offset inside the XGMI hive.
258 * If driver uses GART table for VMID0 FB access, driver finds a hole in
259 * VMID0's virtual address space to place the SYSVM aperture inside
260 * which the first part is vram and the second part is gart (covering
261 * system ram).
262 */
263 u64 vram_start;
264 u64 vram_end;
265 /* FB region , it's same as local vram region in single GPU, in XGMI
266 * configuration, this region covers all GPUs in the same hive ,
267 * each GPU in the hive has the same view of this FB region .
268 * GPU0's vram starts at offset (0 * segment size) ,
269 * GPU1 starts at offset (1 * segment size), etc.
270 */
271 u64 fb_start;
272 u64 fb_end;
273 unsigned vram_width;
274 u64 real_vram_size;
275 int vram_mtrr;
276 u64 mc_mask;
277 const struct firmware *fw; /* MC firmware */
278 uint32_t fw_version;
279 struct amdgpu_irq_src vm_fault;
280 uint32_t vram_type;
281 uint8_t vram_vendor;
282 uint32_t srbm_soft_reset;
283 bool prt_warning;
284 uint32_t sdpif_register;
285 /* apertures */
286 u64 shared_aperture_start;
287 u64 shared_aperture_end;
288 u64 private_aperture_start;
289 u64 private_aperture_end;
290 /* protects concurrent invalidation */
291 spinlock_t invalidate_lock;
292 bool translate_further;
293 struct kfd_vm_fault_info *vm_fault_info;
294 atomic_t vm_fault_info_updated;
295
296 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE];
297 struct {
298 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER;
299 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE];
300 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER;
301
302 bool tmz_enabled;
303 bool is_app_apu;
304
305 struct amdgpu_mem_partition_info *mem_partitions;
306 uint8_t num_mem_partitions;
307 const struct amdgpu_gmc_funcs *gmc_funcs;
308
309 struct amdgpu_xgmi xgmi;
310 struct amdgpu_irq_src ecc_irq;
311 int noretry;
312
313 uint32_t vmid0_page_table_block_size;
314 uint32_t vmid0_page_table_depth;
315 struct amdgpu_bo *pdb0_bo;
316 /* CPU kmapped address of pdb0*/
317 void *ptr_pdb0;
318
319 /* MALL size */
320 u64 mall_size;
321 uint32_t m_half_use;
322
323 /* number of UMC instances */
324 int num_umc;
325 /* mode2 save restore */
326 u64 VM_L2_CNTL;
327 u64 VM_L2_CNTL2;
328 u64 VM_DUMMY_PAGE_FAULT_CNTL;
329 u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32;
330 u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32;
331 u64 VM_L2_PROTECTION_FAULT_CNTL;
332 u64 VM_L2_PROTECTION_FAULT_CNTL2;
333 u64 VM_L2_PROTECTION_FAULT_MM_CNTL3;
334 u64 VM_L2_PROTECTION_FAULT_MM_CNTL4;
335 u64 VM_L2_PROTECTION_FAULT_ADDR_LO32;
336 u64 VM_L2_PROTECTION_FAULT_ADDR_HI32;
337 u64 VM_DEBUG;
338 u64 VM_L2_MM_GROUP_RT_CLASSES;
339 u64 VM_L2_BANK_SELECT_RESERVED_CID;
340 u64 VM_L2_BANK_SELECT_RESERVED_CID2;
341 u64 VM_L2_CACHE_PARITY_CNTL;
342 u64 VM_L2_IH_LOG_CNTL;
343 u64 VM_CONTEXT_CNTL[16];
344 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16];
345 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16];
346 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16];
347 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16];
348 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16];
349 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16];
350 u64 MC_VM_MX_L1_TLB_CNTL;
351
352 u64 noretry_flags;
353
354 bool flush_tlb_needs_extra_type_0;
355 bool flush_tlb_needs_extra_type_2;
356 bool flush_pasid_uses_kiq;
357 };
358
359 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
360 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
361 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
362 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
363 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags))
364 #define amdgpu_gmc_override_vm_pte_flags(adev, vm, addr, pte_flags) \
365 (adev)->gmc.gmc_funcs->override_vm_pte_flags \
366 ((adev), (vm), (addr), (pte_flags))
367 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev))
368 #define amdgpu_gmc_get_dcc_alignment(adev) ({ \
369 typeof(adev) _adev = (adev); \
370 _adev->gmc.gmc_funcs->get_dcc_alignment(_adev); \
371 })
372
373 /**
374 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
375 *
376 * @adev: amdgpu_device pointer
377 *
378 * Returns:
379 * True if full VRAM is visible through the BAR
380 */
amdgpu_gmc_vram_full_visible(struct amdgpu_gmc * gmc)381 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
382 {
383 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size);
384
385 return (gmc->real_vram_size == gmc->visible_vram_size);
386 }
387
388 /**
389 * amdgpu_gmc_sign_extend - sign extend the given gmc address
390 *
391 * @addr: address to extend
392 */
amdgpu_gmc_sign_extend(uint64_t addr)393 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
394 {
395 if (addr >= AMDGPU_GMC_HOLE_START)
396 addr |= AMDGPU_GMC_HOLE_END;
397
398 return addr;
399 }
400
401 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev);
402 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
403 uint64_t *addr, uint64_t *flags);
404 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
405 uint32_t gpu_page_idx, uint64_t addr,
406 uint64_t flags);
407 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
408 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
409 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc);
410 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
411 u64 base);
412 void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
413 struct amdgpu_gmc *mc,
414 enum amdgpu_gart_placement gart_placement);
415 void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
416 struct amdgpu_gmc *mc);
417 void amdgpu_gmc_set_agp_default(struct amdgpu_device *adev,
418 struct amdgpu_gmc *mc);
419 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
420 struct amdgpu_ih_ring *ih, uint64_t addr,
421 uint16_t pasid, uint64_t timestamp);
422 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
423 uint16_t pasid);
424 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev);
425 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev);
426 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev);
427 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev);
428 void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
429 uint32_t vmhub, uint32_t flush_type);
430 int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid,
431 uint32_t flush_type, bool all_hub,
432 uint32_t inst);
433 void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev,
434 uint32_t reg0, uint32_t reg1,
435 uint32_t ref, uint32_t mask,
436 uint32_t xcc_inst);
437
438 extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev);
439 extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev);
440
441 extern void
442 amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
443 bool enable);
444
445 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev);
446
447 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev);
448 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);
449 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
450 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
451 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev);
452 int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev);
453 void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev);
454
455 int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev,
456 struct amdgpu_mem_partition_info *mem_ranges,
457 int exp_ranges);
458
459 #endif
460