1 /*-
2 * Copyright (c) 2021 Alstom Group.
3 * Copyright (c) 2021 Semihalf.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26 #include <sys/cdefs.h>
27 #include "opt_platform.h"
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bio.h>
32 #include <sys/endian.h>
33 #include <sys/kernel.h>
34 #include <sys/kthread.h>
35 #include <sys/lock.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/rman.h>
40
41 #include <geom/geom_disk.h>
42
43 #include <machine/bus.h>
44
45 #include <dev/clk/clk.h>
46 #include <dev/fdt/fdt_common.h>
47 #include <dev/ofw/ofw_bus_subr.h>
48
49 #include <vm/pmap.h>
50
51 #include "flex_spi.h"
52
53 static MALLOC_DEFINE(SECTOR_BUFFER, "flex_spi", "FSL QSPI sector buffer memory");
54
55 #define AHB_LUT_ID 31
56 #define MHZ(x) ((x)*1000*1000)
57 #define SPI_DEFAULT_CLK_RATE (MHZ(10))
58
59 static int driver_flags = 0;
60 SYSCTL_NODE(_hw, OID_AUTO, flex_spi, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
61 "FlexSPI driver parameters");
62 SYSCTL_INT(_hw_flex_spi, OID_AUTO, driver_flags, CTLFLAG_RDTUN, &driver_flags, 0,
63 "Configuration flags and quirks");
64
65 static struct ofw_compat_data flex_spi_compat_data[] = {
66 {"nxp,lx2160a-fspi", true},
67 {NULL, false}
68 };
69
70 struct flex_spi_flash_info {
71 char* name;
72 uint32_t jedecid;
73 uint32_t sectorsize;
74 uint32_t sectorcount;
75 uint32_t erasesize;
76 uint32_t maxclk;
77 };
78
79 /* Add information about supported Flashes. TODO: use SFDP instead */
80 static struct flex_spi_flash_info flex_spi_flash_info[] = {
81 {"W25Q128JW", 0x001860ef, 64*1024, 256, 4096, MHZ(100)},
82 {NULL, 0, 0, 0, 0, 0}
83 };
84
85 struct flex_spi_softc
86 {
87 device_t dev;
88 unsigned int flags;
89
90 struct bio_queue_head bio_queue;
91 struct mtx disk_mtx;
92 struct disk *disk;
93 struct proc *p;
94 unsigned int taskstate;
95 uint8_t *buf;
96
97 struct resource *ahb_mem_res;
98 struct resource *mem_res;
99
100 clk_t fspi_clk_en;
101 clk_t fspi_clk;
102 uint64_t fspi_clk_en_hz;
103 uint64_t fspi_clk_hz;
104
105 /* TODO: support more than one Flash per bus */
106 uint64_t fspi_max_clk;
107 uint32_t quirks;
108
109 /* Flash parameters */
110 uint32_t sectorsize;
111 uint32_t sectorcount;
112 uint32_t erasesize;
113 };
114
115 static int flex_spi_read(struct flex_spi_softc *sc, off_t offset, caddr_t data,
116 size_t count);
117 static int flex_spi_write(struct flex_spi_softc *sc, off_t offset,
118 uint8_t *data, size_t size);
119
120 static int flex_spi_attach(device_t dev);
121 static int flex_spi_probe(device_t dev);
122 static int flex_spi_detach(device_t dev);
123
124 /* disk routines */
125 static int flex_spi_open(struct disk *dp);
126 static int flex_spi_close(struct disk *dp);
127 static int flex_spi_ioctl(struct disk *, u_long, void *, int, struct thread *);
128 static void flex_spi_strategy(struct bio *bp);
129 static int flex_spi_getattr(struct bio *bp);
130 static void flex_spi_task(void *arg);
131
132 static uint32_t
read_reg(struct flex_spi_softc * sc,uint32_t offset)133 read_reg(struct flex_spi_softc *sc, uint32_t offset)
134 {
135
136 return ((bus_read_4(sc->mem_res, offset)));
137 }
138
139 static void
write_reg(struct flex_spi_softc * sc,uint32_t offset,uint32_t value)140 write_reg(struct flex_spi_softc *sc, uint32_t offset, uint32_t value)
141 {
142
143 bus_write_4(sc->mem_res, offset, (value));
144 }
145
146 static int
reg_read_poll_tout(struct flex_spi_softc * sc,uint32_t offset,uint32_t mask,uint32_t delay_us,uint32_t iterations,bool positive)147 reg_read_poll_tout(struct flex_spi_softc *sc, uint32_t offset, uint32_t mask,
148 uint32_t delay_us, uint32_t iterations, bool positive)
149 {
150 uint32_t reg;
151 uint32_t condition = 0;
152
153 do {
154 reg = read_reg(sc, offset);
155 if (positive)
156 condition = ((reg & mask) == 0);
157 else
158 condition = ((reg & mask) != 0);
159
160 if (condition == 0)
161 break;
162
163 DELAY(delay_us);
164 } while (condition && (--iterations > 0));
165
166 return (condition != 0);
167 }
168
169 static int
flex_spi_clk_setup(struct flex_spi_softc * sc,uint32_t rate)170 flex_spi_clk_setup(struct flex_spi_softc *sc, uint32_t rate)
171 {
172 int ret = 0;
173
174 /* disable to avoid glitching */
175 ret |= clk_disable(sc->fspi_clk_en);
176 ret |= clk_disable(sc->fspi_clk);
177
178 ret |= clk_set_freq(sc->fspi_clk, rate, 0);
179 sc->fspi_clk_hz = rate;
180
181 /* enable clocks back */
182 ret |= clk_enable(sc->fspi_clk_en);
183 ret |= clk_enable(sc->fspi_clk);
184
185 if (ret)
186 return (EINVAL);
187
188 return (0);
189 }
190
191 static void
flex_spi_prepare_lut(struct flex_spi_softc * sc,uint8_t op)192 flex_spi_prepare_lut(struct flex_spi_softc *sc, uint8_t op)
193 {
194 uint32_t lut_id;
195 uint32_t lut;
196
197 /* unlock LUT */
198 write_reg(sc, FSPI_LUTKEY, FSPI_LUTKEY_VALUE);
199 write_reg(sc, FSPI_LCKCR, FSPI_LCKER_UNLOCK);
200
201 /* Read JEDEC ID */
202 lut_id = 0;
203
204 switch (op) {
205 case LUT_FLASH_CMD_JEDECID:
206 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_READ_IDENT);
207 lut |= LUT_DEF(1, LUT_NXP_READ, LUT_PAD(1), 0);
208 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
209 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, 0);
210 break;
211 case LUT_FLASH_CMD_READ:
212 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_FAST_READ);
213 lut |= LUT_DEF(1, LUT_ADDR, LUT_PAD(1), 3*8);
214 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
215 lut = LUT_DEF(0, LUT_DUMMY, LUT_PAD(1), 1*8);
216 lut |= LUT_DEF(1, LUT_NXP_READ, LUT_PAD(1), 0);
217 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, lut);
218 write_reg(sc, FSPI_LUT_REG(lut_id) + 8, 0);
219 break;
220 case LUT_FLASH_CMD_STATUS_READ:
221 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_READ_STATUS);
222 lut |= LUT_DEF(1, LUT_NXP_READ, LUT_PAD(1), 0);
223 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
224 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, 0);
225 break;
226 case LUT_FLASH_CMD_PAGE_PROGRAM:
227 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_PAGE_PROGRAM);
228 lut |= LUT_DEF(1, LUT_ADDR, LUT_PAD(1), 3*8);
229 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
230 lut = LUT_DEF(0, LUT_NXP_WRITE, LUT_PAD(1), 0);
231 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, lut);
232 write_reg(sc, FSPI_LUT_REG(lut_id) + 8, 0);
233 break;
234 case LUT_FLASH_CMD_WRITE_ENABLE:
235 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_WRITE_ENABLE);
236 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
237 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, 0);
238 break;
239 case LUT_FLASH_CMD_WRITE_DISABLE:
240 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_WRITE_DISABLE);
241 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
242 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, 0);
243 break;
244 case LUT_FLASH_CMD_SECTOR_ERASE:
245 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_SECTOR_ERASE);
246 lut |= LUT_DEF(1, LUT_ADDR, LUT_PAD(1), 3*8);
247 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
248 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, 0);
249 break;
250 default:
251 write_reg(sc, FSPI_LUT_REG(lut_id), 0);
252 }
253
254 /* lock LUT */
255 write_reg(sc, FSPI_LUTKEY, FSPI_LUTKEY_VALUE);
256 write_reg(sc, FSPI_LCKCR, FSPI_LCKER_LOCK);
257 }
258
259 static void
flex_spi_prepare_ahb_lut(struct flex_spi_softc * sc)260 flex_spi_prepare_ahb_lut(struct flex_spi_softc *sc)
261 {
262 uint32_t lut_id;
263 uint32_t lut;
264
265 /* unlock LUT */
266 write_reg(sc, FSPI_LUTKEY, FSPI_LUTKEY_VALUE);
267 write_reg(sc, FSPI_LCKCR, FSPI_LCKER_UNLOCK);
268
269 lut_id = AHB_LUT_ID;
270 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_FAST_READ);
271 lut |= LUT_DEF(1, LUT_ADDR, LUT_PAD(1), 3*8);
272 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
273 lut = LUT_DEF(0, LUT_DUMMY, LUT_PAD(1), 1*8);
274 lut |= LUT_DEF(1, LUT_NXP_READ, LUT_PAD(1), 0);
275 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, lut);
276 write_reg(sc, FSPI_LUT_REG(lut_id) + 8, 0);
277
278 /* lock LUT */
279 write_reg(sc, FSPI_LUTKEY, FSPI_LUTKEY_VALUE);
280 write_reg(sc, FSPI_LCKCR, FSPI_LCKER_LOCK);
281 }
282
283 #define DIR_READ 0
284 #define DIR_WRITE 1
285
286 static void
flex_spi_read_rxfifo(struct flex_spi_softc * sc,uint8_t * buf,uint8_t size)287 flex_spi_read_rxfifo(struct flex_spi_softc *sc, uint8_t *buf, uint8_t size)
288 {
289 int i, ret, reg;
290
291 /*
292 * Default value of water mark level is 8 bytes, hence in single
293 * read request controller can read max 8 bytes of data.
294 */
295 for (i = 0; i < size; i += 4) {
296 /* Wait for RXFIFO available */
297 if (i % 8 == 0) {
298 ret = reg_read_poll_tout(sc, FSPI_INTR, FSPI_INTR_IPRXWA,
299 1, 50000, 1);
300 if (ret)
301 device_printf(sc->dev,
302 "timed out waiting for FSPI_INTR_IPRXWA\n");
303 }
304
305 if (i % 8 == 0)
306 reg = read_reg(sc, FSPI_RFDR);
307 else
308 reg = read_reg(sc, FSPI_RFDR + 4);
309
310 if (size >= (i + 4))
311 *(uint32_t *)(buf + i) = reg;
312 else
313 memcpy(buf + i, ®, size - i);
314
315 /* move the FIFO pointer */
316 if (i % 8 != 0)
317 write_reg(sc, FSPI_INTR, FSPI_INTR_IPRXWA);
318 }
319
320 /* invalid the RXFIFO */
321 write_reg(sc, FSPI_IPRXFCR, FSPI_IPRXFCR_CLR);
322 /* move the FIFO pointer */
323 write_reg(sc, FSPI_INTR, FSPI_INTR_IPRXWA);
324 }
325
326 static void
flex_spi_write_txfifo(struct flex_spi_softc * sc,uint8_t * buf,uint8_t size)327 flex_spi_write_txfifo(struct flex_spi_softc *sc, uint8_t *buf, uint8_t size)
328 {
329 int i, ret, reg;
330
331 /* invalid the TXFIFO */
332 write_reg(sc, FSPI_IPRXFCR, FSPI_IPTXFCR_CLR);
333
334 /*
335 * Default value of water mark level is 8 bytes, hence in single
336 * read request controller can read max 8 bytes of data.
337 */
338 for (i = 0; i < size; i += 4) {
339 /* Wait for RXFIFO available */
340 if (i % 8 == 0) {
341 ret = reg_read_poll_tout(sc, FSPI_INTR, FSPI_INTR_IPTXWE,
342 1, 50000, 1);
343 if (ret)
344 device_printf(sc->dev,
345 "timed out waiting for FSPI_INTR_IPRXWA\n");
346 }
347
348 if (size >= (i + 4))
349 reg = *(uint32_t *)(buf + i);
350 else {
351 reg = 0;
352 memcpy(®, buf + i, size - i);
353 }
354
355 if (i % 8 == 0)
356 write_reg(sc, FSPI_TFDR, reg);
357 else
358 write_reg(sc, FSPI_TFDR + 4, reg);
359
360 /* move the FIFO pointer */
361 if (i % 8 != 0)
362 write_reg(sc, FSPI_INTR, FSPI_INTR_IPTXWE);
363 }
364
365 /* move the FIFO pointer */
366 write_reg(sc, FSPI_INTR, FSPI_INTR_IPTXWE);
367 }
368
369 static int
flex_spi_do_op(struct flex_spi_softc * sc,uint32_t op,uint32_t addr,uint8_t * buf,uint8_t size,uint8_t dir)370 flex_spi_do_op(struct flex_spi_softc *sc, uint32_t op, uint32_t addr,
371 uint8_t *buf, uint8_t size, uint8_t dir)
372 {
373
374 uint32_t cnt = 1000, reg;
375
376 reg = read_reg(sc, FSPI_IPRXFCR);
377 /* invalidate RXFIFO first */
378 reg &= ~FSPI_IPRXFCR_DMA_EN;
379 reg |= FSPI_IPRXFCR_CLR;
380 write_reg(sc, FSPI_IPRXFCR, reg);
381
382 /* Prepare LUT */
383 flex_spi_prepare_lut(sc, op);
384
385 write_reg(sc, FSPI_IPCR0, addr);
386 /*
387 * Always start the sequence at the same index since we update
388 * the LUT at each BIO operation. And also specify the DATA
389 * length, since it's has not been specified in the LUT.
390 */
391 write_reg(sc, FSPI_IPCR1, size |
392 (0 << FSPI_IPCR1_SEQID_SHIFT) | (0 << FSPI_IPCR1_SEQNUM_SHIFT));
393
394 if ((size != 0) && (dir == DIR_WRITE))
395 flex_spi_write_txfifo(sc, buf, size);
396
397 /* Trigger the LUT now. */
398 write_reg(sc, FSPI_IPCMD, FSPI_IPCMD_TRG);
399
400
401 /* Wait for completion. */
402 do {
403 reg = read_reg(sc, FSPI_INTR);
404 if (reg & FSPI_INTR_IPCMDDONE) {
405 write_reg(sc, FSPI_INTR, FSPI_INTR_IPCMDDONE);
406 break;
407 }
408 DELAY(1);
409 } while (--cnt);
410 if (cnt == 0) {
411 device_printf(sc->dev, "timed out waiting for command completion\n");
412 return (ETIMEDOUT);
413 }
414
415 /* Invoke IP data read, if request is of data read. */
416 if ((size != 0) && (dir == DIR_READ))
417 flex_spi_read_rxfifo(sc, buf, size);
418
419 return (0);
420 }
421
422 static int
flex_spi_wait_for_controller(struct flex_spi_softc * sc)423 flex_spi_wait_for_controller(struct flex_spi_softc *sc)
424 {
425 int err;
426
427 /* Wait for controller being ready. */
428 err = reg_read_poll_tout(sc, FSPI_STS0,
429 FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, 1);
430
431 return (err);
432 }
433
434 static int
flex_spi_wait_for_flash(struct flex_spi_softc * sc)435 flex_spi_wait_for_flash(struct flex_spi_softc *sc)
436 {
437 int ret;
438 uint32_t status = 0;
439
440 ret = flex_spi_wait_for_controller(sc);
441 if (ret != 0) {
442 device_printf(sc->dev, "%s: timed out waiting for controller", __func__);
443 return (ret);
444 }
445
446 do {
447 ret = flex_spi_do_op(sc, LUT_FLASH_CMD_STATUS_READ, 0, (void*)&status,
448 1, DIR_READ);
449 if (ret != 0) {
450 device_printf(sc->dev, "ERROR: failed to get flash status\n");
451 return (ret);
452 }
453
454 } while (status & STATUS_WIP);
455
456 return (0);
457 }
458
459 static int
flex_spi_identify(struct flex_spi_softc * sc)460 flex_spi_identify(struct flex_spi_softc *sc)
461 {
462 int ret;
463 uint32_t id = 0;
464 struct flex_spi_flash_info *finfo = flex_spi_flash_info;
465
466 ret = flex_spi_do_op(sc, LUT_FLASH_CMD_JEDECID, 0, (void*)&id, sizeof(id), DIR_READ);
467 if (ret != 0) {
468 device_printf(sc->dev, "ERROR: failed to identify device\n");
469 return (ret);
470 }
471
472 /* XXX TODO: SFDP to be implemented */
473 while (finfo->jedecid != 0) {
474 if (id == finfo->jedecid) {
475 device_printf(sc->dev, "found %s Flash\n", finfo->name);
476 sc->sectorsize = finfo->sectorsize;
477 sc->sectorcount = finfo->sectorcount;
478 sc->erasesize = finfo->erasesize;
479 sc->fspi_max_clk = finfo->maxclk;
480 return (0);
481 }
482 finfo++;
483 }
484
485 return (EINVAL);
486 }
487
488 static inline int
flex_spi_force_ip_mode(struct flex_spi_softc * sc)489 flex_spi_force_ip_mode(struct flex_spi_softc *sc)
490 {
491
492 if (sc->quirks & FSPI_QUIRK_USE_IP_ONLY)
493 return (1);
494 if (driver_flags & FSPI_QUIRK_USE_IP_ONLY)
495 return (1);
496
497 return (0);
498 }
499
500 static int
flex_spi_read(struct flex_spi_softc * sc,off_t offset,caddr_t data,size_t count)501 flex_spi_read(struct flex_spi_softc *sc, off_t offset, caddr_t data,
502 size_t count)
503 {
504 int err;
505 size_t len;
506
507 /* Wait for controller being ready. */
508 err = flex_spi_wait_for_controller(sc);
509 if (err)
510 device_printf(sc->dev,
511 "warning: spi_read, timed out waiting for controller");
512
513 /* Use AHB access whenever we can */
514 if (flex_spi_force_ip_mode(sc) != 0) {
515 do {
516 if (((offset % 4) != 0) || (count < 4)) {
517 *(uint8_t*)data = bus_read_1(sc->ahb_mem_res, offset);
518 data++;
519 count--;
520 offset++;
521 } else {
522 *(uint32_t*)data = bus_read_4(sc->ahb_mem_res, offset);
523 data += 4;
524 count -= 4;
525 offset += 4;
526 }
527 } while (count);
528
529 return (0);
530 }
531
532 do {
533 len = min(64, count);
534 err = flex_spi_do_op(sc, LUT_FLASH_CMD_READ, offset, (void*)data,
535 len, DIR_READ);
536 if (err)
537 return (err);
538 offset += len;
539 data += len;
540 count -= len;
541 } while (count);
542
543 return (0);
544 }
545
546 static int
flex_spi_write(struct flex_spi_softc * sc,off_t offset,uint8_t * data,size_t size)547 flex_spi_write(struct flex_spi_softc *sc, off_t offset, uint8_t *data,
548 size_t size)
549 {
550 int ret = 0;
551 size_t ptr;
552
553 flex_spi_wait_for_flash(sc);
554 ret = flex_spi_do_op(sc, LUT_FLASH_CMD_WRITE_ENABLE, offset, NULL,
555 0, DIR_READ);
556 if (ret != 0) {
557 device_printf(sc->dev, "ERROR: failed to enable writes\n");
558 return (ret);
559 }
560 flex_spi_wait_for_flash(sc);
561
562 /* per-sector write */
563 while (size > 0) {
564 uint32_t sector_base = rounddown2(offset, sc->erasesize);
565 size_t size_in_sector = size;
566
567 if (size_in_sector + offset > sector_base + sc->erasesize)
568 size_in_sector = sector_base + sc->erasesize - offset;
569
570 /* Read sector */
571 ret = flex_spi_read(sc, sector_base, sc->buf, sc->erasesize);
572 if (ret != 0) {
573 device_printf(sc->dev, "ERROR: failed to read sector %d\n",
574 sector_base);
575 goto exit;
576 }
577
578 /* Erase sector */
579 flex_spi_wait_for_flash(sc);
580 ret = flex_spi_do_op(sc, LUT_FLASH_CMD_SECTOR_ERASE, offset, NULL,
581 0, DIR_READ);
582 if (ret != 0) {
583 device_printf(sc->dev, "ERROR: failed to erase sector %d\n",
584 sector_base);
585 goto exit;
586 }
587
588 /* Update buffer with input data */
589 memcpy(sc->buf + (offset - sector_base), data, size_in_sector);
590
591 /* Write buffer back to the flash
592 * Up to 32 bytes per single request, request cannot spread
593 * across 256-byte page boundary
594 */
595 for (ptr = 0; ptr < sc->erasesize; ptr += 32) {
596 flex_spi_wait_for_flash(sc);
597 ret = flex_spi_do_op(sc, LUT_FLASH_CMD_PAGE_PROGRAM,
598 sector_base + ptr, (void*)(sc->buf + ptr), 32, DIR_WRITE);
599 if (ret != 0) {
600 device_printf(sc->dev, "ERROR: failed to write address %ld\n",
601 sector_base + ptr);
602 goto exit;
603 }
604 }
605
606 /* update pointers */
607 size = size - size_in_sector;
608 offset = offset + size;
609 }
610
611 flex_spi_wait_for_flash(sc);
612 ret = flex_spi_do_op(sc, LUT_FLASH_CMD_WRITE_DISABLE, offset, (void*)sc->buf,
613 0, DIR_READ);
614 if (ret != 0) {
615 device_printf(sc->dev, "ERROR: failed to disable writes\n");
616 goto exit;
617 }
618 flex_spi_wait_for_flash(sc);
619
620 exit:
621
622 return (ret);
623 }
624
625 static int
flex_spi_default_setup(struct flex_spi_softc * sc)626 flex_spi_default_setup(struct flex_spi_softc *sc)
627 {
628 int ret, i;
629 uint32_t reg;
630
631 /* Default clock speed */
632 ret = flex_spi_clk_setup(sc, SPI_DEFAULT_CLK_RATE);
633 if (ret)
634 return (ret);
635
636 /* Reset the module */
637 /* w1c register, wait unit clear */
638 reg = read_reg(sc, FSPI_MCR0);
639 reg |= FSPI_MCR0_SWRST;
640 write_reg(sc, FSPI_MCR0, reg);
641 ret = reg_read_poll_tout(sc, FSPI_MCR0, FSPI_MCR0_SWRST, 1000, POLL_TOUT, 0);
642 if (ret != 0) {
643 device_printf(sc->dev, "time out waiting for reset");
644 return (ret);
645 }
646
647 /* Disable the module */
648 write_reg(sc, FSPI_MCR0, FSPI_MCR0_MDIS);
649
650 /* Reset the DLL register to default value */
651 write_reg(sc, FSPI_DLLACR, FSPI_DLLACR_OVRDEN);
652 write_reg(sc, FSPI_DLLBCR, FSPI_DLLBCR_OVRDEN);
653
654 /* enable module */
655 write_reg(sc, FSPI_MCR0, FSPI_MCR0_AHB_TIMEOUT(0xFF) |
656 FSPI_MCR0_IP_TIMEOUT(0xFF) | (uint32_t) FSPI_MCR0_OCTCOMB_EN);
657
658 /*
659 * Disable same device enable bit and configure all slave devices
660 * independently.
661 */
662 reg = read_reg(sc, FSPI_MCR2);
663 reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
664 write_reg(sc, FSPI_MCR2, reg);
665
666 /* AHB configuration for access buffer 0~7. */
667 for (i = 0; i < 7; i++)
668 write_reg(sc, FSPI_AHBRX_BUF0CR0 + 4 * i, 0);
669
670 /*
671 * Set ADATSZ with the maximum AHB buffer size to improve the read
672 * performance.
673 */
674 write_reg(sc, FSPI_AHBRX_BUF7CR0, (2048 / 8 |
675 FSPI_AHBRXBUF0CR7_PREF));
676
677 /* prefetch and no start address alignment limitation */
678 write_reg(sc, FSPI_AHBCR, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT);
679
680 /* AHB Read - Set lut sequence ID for all CS. */
681 flex_spi_prepare_ahb_lut(sc);
682 write_reg(sc, FSPI_FLSHA1CR2, AHB_LUT_ID);
683 write_reg(sc, FSPI_FLSHA2CR2, AHB_LUT_ID);
684 write_reg(sc, FSPI_FLSHB1CR2, AHB_LUT_ID);
685 write_reg(sc, FSPI_FLSHB2CR2, AHB_LUT_ID);
686
687 /* disable interrupts */
688 write_reg(sc, FSPI_INTEN, 0);
689
690 return (0);
691 }
692
693 static int
flex_spi_probe(device_t dev)694 flex_spi_probe(device_t dev)
695 {
696
697 if (!ofw_bus_status_okay(dev))
698 return (ENXIO);
699
700 if (!ofw_bus_search_compatible(dev, flex_spi_compat_data)->ocd_data)
701 return (ENXIO);
702
703 device_set_desc(dev, "NXP FlexSPI Flash");
704 return (BUS_PROBE_SPECIFIC);
705 }
706
707 static int
flex_spi_attach(device_t dev)708 flex_spi_attach(device_t dev)
709 {
710 struct flex_spi_softc *sc;
711 phandle_t node;
712 int rid;
713 uint32_t reg;
714
715 node = ofw_bus_get_node(dev);
716 sc = device_get_softc(dev);
717 sc->dev = dev;
718
719 mtx_init(&sc->disk_mtx, "flex_spi_DISK", "QSPI disk mtx", MTX_DEF);
720
721 /* Get memory resources. */
722 rid = 0;
723 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
724 RF_ACTIVE);
725
726 rid = 1;
727 sc->ahb_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
728 RF_ACTIVE | RF_SHAREABLE);
729
730 if (sc->mem_res == NULL || sc->ahb_mem_res == NULL) {
731 device_printf(dev, "could not allocate resources\n");
732 flex_spi_detach(dev);
733 return (ENOMEM);
734 }
735
736 /* Get clocks */
737 if ((clk_get_by_ofw_name(dev, node, "fspi_en", &sc->fspi_clk_en) != 0)
738 || (clk_get_freq(sc->fspi_clk_en, &sc->fspi_clk_en_hz) != 0)) {
739 device_printf(dev, "could not get fspi_en clock\n");
740 flex_spi_detach(dev);
741 return (EINVAL);
742 }
743 if ((clk_get_by_ofw_name(dev, node, "fspi", &sc->fspi_clk) != 0)
744 || (clk_get_freq(sc->fspi_clk, &sc->fspi_clk_hz) != 0)) {
745 device_printf(dev, "could not get fspi clock\n");
746 flex_spi_detach(dev);
747 return (EINVAL);
748 }
749
750 /* Enable clocks */
751 if (clk_enable(sc->fspi_clk_en) != 0 ||
752 clk_enable(sc->fspi_clk) != 0) {
753 device_printf(dev, "could not enable clocks\n");
754 flex_spi_detach(dev);
755 return (EINVAL);
756 }
757
758 /* Clear potential interrupts */
759 reg = read_reg(sc, FSPI_INTR);
760 if (reg)
761 write_reg(sc, FSPI_INTR, reg);
762
763 /* Default setup */
764 if (flex_spi_default_setup(sc) != 0) {
765 device_printf(sc->dev, "Unable to initialize defaults\n");
766 flex_spi_detach(dev);
767 return (ENXIO);
768 }
769
770 /* Identify attached Flash */
771 if(flex_spi_identify(sc) != 0) {
772 device_printf(sc->dev, "Unable to identify Flash\n");
773 flex_spi_detach(dev);
774 return (ENXIO);
775 }
776
777 if (flex_spi_clk_setup(sc, sc->fspi_max_clk) != 0) {
778 device_printf(sc->dev, "Unable to set up SPI max clock\n");
779 flex_spi_detach(dev);
780 return (ENXIO);
781 }
782
783 sc->buf = malloc(sc->erasesize, SECTOR_BUFFER, M_WAITOK);
784 /* Move it to per-flash */
785 sc->disk = disk_alloc();
786 sc->disk->d_open = flex_spi_open;
787 sc->disk->d_close = flex_spi_close;
788 sc->disk->d_strategy = flex_spi_strategy;
789 sc->disk->d_getattr = flex_spi_getattr;
790 sc->disk->d_ioctl = flex_spi_ioctl;
791 sc->disk->d_name = "flash/qspi";
792 sc->disk->d_drv1 = sc;
793 /* the most that can fit in a single spi transaction */
794 sc->disk->d_maxsize = DFLTPHYS;
795 sc->disk->d_sectorsize = FLASH_SECTORSIZE;
796 sc->disk->d_unit = device_get_unit(sc->dev);
797 sc->disk->d_dump = NULL;
798
799 sc->disk->d_mediasize = sc->sectorsize * sc->sectorcount;
800 sc->disk->d_stripesize = sc->erasesize;
801
802 bioq_init(&sc->bio_queue);
803 sc->taskstate = TSTATE_RUNNING;
804 kproc_create(&flex_spi_task, sc, &sc->p, 0, 0, "task: qspi flash");
805 disk_create(sc->disk, DISK_VERSION);
806
807 return (0);
808 }
809
810 static int
flex_spi_detach(device_t dev)811 flex_spi_detach(device_t dev)
812 {
813 struct flex_spi_softc *sc;
814 int err;
815
816 sc = device_get_softc(dev);
817 err = 0;
818
819 if (!device_is_attached(dev))
820 goto free_resources;
821
822 mtx_lock(&sc->disk_mtx);
823 if (sc->taskstate == TSTATE_RUNNING) {
824 sc->taskstate = TSTATE_STOPPING;
825 wakeup(sc->disk);
826 while (err == 0 && sc->taskstate != TSTATE_STOPPED) {
827 err = mtx_sleep(sc->disk, &sc->disk_mtx, 0, "flex_spi",
828 hz * 3);
829 if (err != 0) {
830 sc->taskstate = TSTATE_RUNNING;
831 device_printf(sc->dev,
832 "Failed to stop queue task\n");
833 }
834 }
835 }
836
837 mtx_unlock(&sc->disk_mtx);
838 mtx_destroy(&sc->disk_mtx);
839
840 if (err == 0 && sc->taskstate == TSTATE_STOPPED) {
841 disk_destroy(sc->disk);
842 bioq_flush(&sc->bio_queue, NULL, ENXIO);
843 }
844
845 /* Disable hardware. */
846 free_resources:
847 /* Release memory resource. */
848 if (sc->mem_res != NULL)
849 bus_release_resource(dev, SYS_RES_MEMORY,
850 rman_get_rid(sc->mem_res), sc->mem_res);
851
852 if (sc->ahb_mem_res != NULL)
853 bus_release_resource(dev, SYS_RES_MEMORY,
854 rman_get_rid(sc->ahb_mem_res), sc->ahb_mem_res);
855
856 /* Disable clocks */
857 if (sc->fspi_clk_en_hz)
858 clk_disable(sc->fspi_clk_en);
859 if (sc->fspi_clk_hz)
860 clk_disable(sc->fspi_clk);
861
862 free(sc->buf, SECTOR_BUFFER);
863
864 return (err);
865 }
866
867 static int
flex_spi_open(struct disk * dp)868 flex_spi_open(struct disk *dp)
869 {
870
871 return (0);
872 }
873
874 static int
flex_spi_close(struct disk * dp)875 flex_spi_close(struct disk *dp)
876 {
877
878 return (0);
879 }
880
881 static int
flex_spi_ioctl(struct disk * dp,u_long cmd,void * data,int fflag,struct thread * td)882 flex_spi_ioctl(struct disk *dp, u_long cmd, void *data, int fflag,
883 struct thread *td)
884 {
885
886 return (ENOTSUP);
887 }
888
889 static void
flex_spi_strategy(struct bio * bp)890 flex_spi_strategy(struct bio *bp)
891 {
892 struct flex_spi_softc *sc;
893
894 sc = (struct flex_spi_softc *)bp->bio_disk->d_drv1;
895 mtx_lock(&sc->disk_mtx);
896 bioq_disksort(&sc->bio_queue, bp);
897 mtx_unlock(&sc->disk_mtx);
898 wakeup(sc->disk);
899 }
900
901 static int
flex_spi_getattr(struct bio * bp)902 flex_spi_getattr(struct bio *bp)
903 {
904 struct flex_spi_softc *sc;
905 device_t dev;
906
907 if (bp->bio_disk == NULL || bp->bio_disk->d_drv1 == NULL) {
908 return (ENXIO);
909 }
910
911 sc = bp->bio_disk->d_drv1;
912 dev = sc->dev;
913
914 if (strcmp(bp->bio_attribute, "SPI::device") != 0) {
915 return (-1);
916 }
917
918 if (bp->bio_length != sizeof(dev)) {
919 return (EFAULT);
920 }
921
922 bcopy(&dev, bp->bio_data, sizeof(dev));
923
924 return (0);
925 }
926
927 static void
flex_spi_task(void * arg)928 flex_spi_task(void *arg)
929 {
930 struct flex_spi_softc *sc;
931 struct bio *bp;
932
933 sc = (struct flex_spi_softc *)arg;
934 for (;;) {
935 mtx_lock(&sc->disk_mtx);
936 do {
937 if (sc->taskstate == TSTATE_STOPPING) {
938 sc->taskstate = TSTATE_STOPPED;
939 mtx_unlock(&sc->disk_mtx);
940 wakeup(sc->disk);
941 kproc_exit(0);
942 }
943 bp = bioq_first(&sc->bio_queue);
944 if (bp == NULL)
945 mtx_sleep(sc->disk, &sc->disk_mtx, PRIBIO,
946 "flex_spi", 0);
947 } while (bp == NULL);
948 bioq_remove(&sc->bio_queue, bp);
949 mtx_unlock(&sc->disk_mtx);
950
951 switch (bp->bio_cmd) {
952 case BIO_READ:
953 bp->bio_error = flex_spi_read(sc, bp->bio_offset,
954 bp->bio_data, bp->bio_bcount);
955 break;
956 case BIO_WRITE:
957 bp->bio_error = flex_spi_write(sc, bp->bio_offset,
958 bp->bio_data, bp->bio_bcount);
959 break;
960 default:
961 bp->bio_error = EINVAL;
962 }
963 biodone(bp);
964 }
965 }
966
967 static device_method_t flex_spi_methods[] = {
968 /* Device interface */
969 DEVMETHOD(device_probe, flex_spi_probe),
970 DEVMETHOD(device_attach, flex_spi_attach),
971 DEVMETHOD(device_detach, flex_spi_detach),
972
973 { 0, 0 }
974 };
975
976 static driver_t flex_spi_driver = {
977 "flex_spi",
978 flex_spi_methods,
979 sizeof(struct flex_spi_softc),
980 };
981
982 DRIVER_MODULE(flex_spi, simplebus, flex_spi_driver, 0, 0);
983 SIMPLEBUS_PNP_INFO(flex_spi_compat_data);
984