1 /*
2 * Implement fast Fletcher4 with SSE2,SSSE3 instructions. (x86)
3 *
4 * Use the 128-bit SSE2/SSSE3 SIMD instructions and registers to compute
5 * Fletcher4 in two incremental 64-bit parallel accumulator streams,
6 * and then combine the streams to form the final four checksum words.
7 * This implementation is a derivative of the AVX SIMD implementation by
8 * James Guilford and Jinshan Xiong from Intel (see zfs_fletcher_intel.c).
9 *
10 * Copyright (C) 2016 Tyler J. Stachecki.
11 *
12 * Authors:
13 * Tyler J. Stachecki <stachecki.tyler@gmail.com>
14 *
15 * This software is available to you under a choice of one of two
16 * licenses. You may choose to be licensed under the terms of the GNU
17 * General Public License (GPL) Version 2, available from the file
18 * COPYING in the main directory of this source tree, or the
19 * OpenIB.org BSD license below:
20 *
21 * Redistribution and use in source and binary forms, with or
22 * without modification, are permitted provided that the following
23 * conditions are met:
24 *
25 * - Redistributions of source code must retain the above
26 * copyright notice, this list of conditions and the following
27 * disclaimer.
28 *
29 * - Redistributions in binary form must reproduce the above
30 * copyright notice, this list of conditions and the following
31 * disclaimer in the documentation and/or other materials
32 * provided with the distribution.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
36 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
38 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
39 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
40 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
41 * SOFTWARE.
42 */
43
44 #ifdef __amd64
45
46 #include <sys/types.h>
47 #include <sys/sunddi.h>
48 #include <sys/byteorder.h>
49 #include <sys/simd.h>
50 #include <sys/spa_checksum.h>
51 #include <zfs_fletcher.h>
52 #ifndef _KERNEL
53 #include <strings.h>
54 #endif
55
56 struct zfs_fletcher_sse_array {
57 uint64_t v[2] __attribute__((aligned(16)));
58 };
59
60 static void
fletcher_4_sse2_init(fletcher_4_ctx_t * ctx)61 fletcher_4_sse2_init(fletcher_4_ctx_t *ctx)
62 {
63 bzero(ctx->sse, 4 * sizeof (zfs_fletcher_sse_t));
64 }
65
66 static void
fletcher_4_sse2_fini(fletcher_4_ctx_t * ctx,zio_cksum_t * zcp)67 fletcher_4_sse2_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp)
68 {
69 uint64_t A, B, C, D;
70
71 /*
72 * The mixing matrix for checksum calculation is:
73 * a = a0 + a1
74 * b = 2b0 + 2b1 - a1
75 * c = 4c0 - b0 + 4c1 -3b1
76 * d = 8d0 - 4c0 + 8d1 - 8c1 + b1;
77 *
78 * c and d are multiplied by 4 and 8, respectively,
79 * before spilling the vectors out to memory.
80 */
81 A = ctx->sse[0].v[0] + ctx->sse[0].v[1];
82 B = 2 * ctx->sse[1].v[0] + 2 * ctx->sse[1].v[1] - ctx->sse[0].v[1];
83 C = 4 * ctx->sse[2].v[0] - ctx->sse[1].v[0] + 4 * ctx->sse[2].v[1] -
84 3 * ctx->sse[1].v[1];
85 D = 8 * ctx->sse[3].v[0] - 4 * ctx->sse[2].v[0] + 8 * ctx->sse[3].v[1] -
86 8 * ctx->sse[2].v[1] + ctx->sse[1].v[1];
87
88 ZIO_SET_CHECKSUM(zcp, A, B, C, D);
89 }
90
91 #define FLETCHER_4_SSE_RESTORE_CTX(ctx) \
92 { \
93 __asm("movdqu %0, %%xmm0" :: "m" ((ctx)->sse[0])); \
94 __asm("movdqu %0, %%xmm1" :: "m" ((ctx)->sse[1])); \
95 __asm("movdqu %0, %%xmm2" :: "m" ((ctx)->sse[2])); \
96 __asm("movdqu %0, %%xmm3" :: "m" ((ctx)->sse[3])); \
97 }
98
99 #define FLETCHER_4_SSE_SAVE_CTX(ctx) \
100 { \
101 __asm("movdqu %%xmm0, %0" : "=m" ((ctx)->sse[0])); \
102 __asm("movdqu %%xmm1, %0" : "=m" ((ctx)->sse[1])); \
103 __asm("movdqu %%xmm2, %0" : "=m" ((ctx)->sse[2])); \
104 __asm("movdqu %%xmm3, %0" : "=m" ((ctx)->sse[3])); \
105 }
106
107 static void
fletcher_4_sse2_native(fletcher_4_ctx_t * ctx,const void * buf,size_t size)108 fletcher_4_sse2_native(fletcher_4_ctx_t *ctx, const void *buf, size_t size)
109 {
110 const uint64_t *ip = buf;
111 const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
112
113 FLETCHER_4_SSE_RESTORE_CTX(ctx);
114
115 __asm("pxor %xmm4, %xmm4");
116
117 do {
118 __asm("movdqu %0, %%xmm5" :: "m"(*ip));
119 __asm("movdqa %xmm5, %xmm6");
120 __asm("punpckldq %xmm4, %xmm5");
121 __asm("punpckhdq %xmm4, %xmm6");
122 __asm("paddq %xmm5, %xmm0");
123 __asm("paddq %xmm0, %xmm1");
124 __asm("paddq %xmm1, %xmm2");
125 __asm("paddq %xmm2, %xmm3");
126 __asm("paddq %xmm6, %xmm0");
127 __asm("paddq %xmm0, %xmm1");
128 __asm("paddq %xmm1, %xmm2");
129 __asm("paddq %xmm2, %xmm3");
130 } while ((ip += 2) < ipend);
131
132 FLETCHER_4_SSE_SAVE_CTX(ctx);
133 }
134
135 static void
fletcher_4_sse2_byteswap(fletcher_4_ctx_t * ctx,const void * buf,size_t size)136 fletcher_4_sse2_byteswap(fletcher_4_ctx_t *ctx, const void *buf, size_t size)
137 {
138 const uint32_t *ip = buf;
139 const uint32_t *ipend = (uint32_t *)((uint8_t *)ip + size);
140
141 FLETCHER_4_SSE_RESTORE_CTX(ctx);
142
143 do {
144 uint32_t scratch1 = BSWAP_32(ip[0]);
145 uint32_t scratch2 = BSWAP_32(ip[1]);
146
147 __asm("movd %0, %%xmm5" :: "r"(scratch1));
148 __asm("movd %0, %%xmm6" :: "r"(scratch2));
149 __asm("punpcklqdq %xmm6, %xmm5");
150 __asm("paddq %xmm5, %xmm0");
151 __asm("paddq %xmm0, %xmm1");
152 __asm("paddq %xmm1, %xmm2");
153 __asm("paddq %xmm2, %xmm3");
154 } while ((ip += 2) < ipend);
155
156 FLETCHER_4_SSE_SAVE_CTX(ctx);
157 }
158
159 static boolean_t
fletcher_4_sse2_valid(void)160 fletcher_4_sse2_valid(void)
161 {
162 return (kfpu_allowed() && zfs_sse2_available());
163 }
164
165 const fletcher_4_ops_t fletcher_4_sse2_ops = {
166 .init_native = fletcher_4_sse2_init,
167 .fini_native = fletcher_4_sse2_fini,
168 .compute_native = fletcher_4_sse2_native,
169 .init_byteswap = fletcher_4_sse2_init,
170 .fini_byteswap = fletcher_4_sse2_fini,
171 .compute_byteswap = fletcher_4_sse2_byteswap,
172 .valid = fletcher_4_sse2_valid,
173 .uses_fpu_native = B_TRUE,
174 .uses_fpu_byteswap = B_TRUE,
175 .name = "sse2"
176 };
177
178 static void
fletcher_4_ssse3_byteswap(fletcher_4_ctx_t * ctx,const void * buf,size_t size)179 fletcher_4_ssse3_byteswap(fletcher_4_ctx_t *ctx, const void *buf, size_t size)
180 {
181 static const zfs_fletcher_sse_t mask = {
182 .v = { 0x0405060700010203, 0x0C0D0E0F08090A0B }
183 };
184
185 const uint64_t *ip = buf;
186 const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
187
188 FLETCHER_4_SSE_RESTORE_CTX(ctx);
189
190 __asm("movdqa %0, %%xmm7"::"m" (mask));
191 __asm("pxor %xmm4, %xmm4");
192
193 do {
194 __asm("movdqu %0, %%xmm5"::"m" (*ip));
195 __asm("pshufb %xmm7, %xmm5");
196 __asm("movdqa %xmm5, %xmm6");
197 __asm("punpckldq %xmm4, %xmm5");
198 __asm("punpckhdq %xmm4, %xmm6");
199 __asm("paddq %xmm5, %xmm0");
200 __asm("paddq %xmm0, %xmm1");
201 __asm("paddq %xmm1, %xmm2");
202 __asm("paddq %xmm2, %xmm3");
203 __asm("paddq %xmm6, %xmm0");
204 __asm("paddq %xmm0, %xmm1");
205 __asm("paddq %xmm1, %xmm2");
206 __asm("paddq %xmm2, %xmm3");
207 } while ((ip += 2) < ipend);
208
209 FLETCHER_4_SSE_SAVE_CTX(ctx);
210 }
211
fletcher_4_ssse3_valid(void)212 static boolean_t fletcher_4_ssse3_valid(void)
213 {
214 return (zfs_sse2_available() && zfs_ssse3_available());
215 }
216
217 const fletcher_4_ops_t fletcher_4_ssse3_ops = {
218 .init_native = fletcher_4_sse2_init,
219 .fini_native = fletcher_4_sse2_fini,
220 .compute_native = fletcher_4_sse2_native,
221 .init_byteswap = fletcher_4_sse2_init,
222 .fini_byteswap = fletcher_4_sse2_fini,
223 .compute_byteswap = fletcher_4_ssse3_byteswap,
224 .valid = fletcher_4_ssse3_valid,
225 .uses_fpu_native = B_TRUE,
226 .uses_fpu_byteswap = B_TRUE,
227 .name = "ssse3"
228 };
229
230 #endif /* __amd64 */
231