1 // SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0-only
2 /*
3 * Implement fast Fletcher4 with SSE2,SSSE3 instructions. (x86)
4 *
5 * Use the 128-bit SSE2/SSSE3 SIMD instructions and registers to compute
6 * Fletcher4 in two incremental 64-bit parallel accumulator streams,
7 * and then combine the streams to form the final four checksum words.
8 * This implementation is a derivative of the AVX SIMD implementation by
9 * James Guilford and Jinshan Xiong from Intel (see zfs_fletcher_intel.c).
10 *
11 * Copyright (C) 2016 Tyler J. Stachecki.
12 *
13 * Authors:
14 * Tyler J. Stachecki <stachecki.tyler@gmail.com>
15 *
16 * This software is available to you under a choice of one of two
17 * licenses. You may choose to be licensed under the terms of the GNU
18 * General Public License (GPL) Version 2, available from the file
19 * COPYING in the main directory of this source tree, or the
20 * OpenIB.org BSD license below:
21 *
22 * Redistribution and use in source and binary forms, with or
23 * without modification, are permitted provided that the following
24 * conditions are met:
25 *
26 * - Redistributions of source code must retain the above
27 * copyright notice, this list of conditions and the following
28 * disclaimer.
29 *
30 * - Redistributions in binary form must reproduce the above
31 * copyright notice, this list of conditions and the following
32 * disclaimer in the documentation and/or other materials
33 * provided with the distribution.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
39 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
40 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
41 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
42 * SOFTWARE.
43 */
44
45 #if defined(HAVE_SSE2)
46
47 #include <sys/simd.h>
48 #include <sys/spa_checksum.h>
49 #include <sys/string.h>
50 #include <sys/byteorder.h>
51 #include <zfs_fletcher.h>
52
53 static void
fletcher_4_sse2_init(fletcher_4_ctx_t * ctx)54 fletcher_4_sse2_init(fletcher_4_ctx_t *ctx)
55 {
56 memset(ctx->sse, 0, 4 * sizeof (zfs_fletcher_sse_t));
57 }
58
59 static void
fletcher_4_sse2_fini(fletcher_4_ctx_t * ctx,zio_cksum_t * zcp)60 fletcher_4_sse2_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp)
61 {
62 uint64_t A, B, C, D;
63
64 /*
65 * The mixing matrix for checksum calculation is:
66 * a = a0 + a1
67 * b = 2b0 + 2b1 - a1
68 * c = 4c0 - b0 + 4c1 -3b1
69 * d = 8d0 - 4c0 + 8d1 - 8c1 + b1;
70 *
71 * c and d are multiplied by 4 and 8, respectively,
72 * before spilling the vectors out to memory.
73 */
74 A = ctx->sse[0].v[0] + ctx->sse[0].v[1];
75 B = 2 * ctx->sse[1].v[0] + 2 * ctx->sse[1].v[1] - ctx->sse[0].v[1];
76 C = 4 * ctx->sse[2].v[0] - ctx->sse[1].v[0] + 4 * ctx->sse[2].v[1] -
77 3 * ctx->sse[1].v[1];
78 D = 8 * ctx->sse[3].v[0] - 4 * ctx->sse[2].v[0] + 8 * ctx->sse[3].v[1] -
79 8 * ctx->sse[2].v[1] + ctx->sse[1].v[1];
80
81 ZIO_SET_CHECKSUM(zcp, A, B, C, D);
82 }
83
84 #define FLETCHER_4_SSE_RESTORE_CTX(ctx) \
85 { \
86 asm volatile("movdqu %0, %%xmm0" :: "m" ((ctx)->sse[0])); \
87 asm volatile("movdqu %0, %%xmm1" :: "m" ((ctx)->sse[1])); \
88 asm volatile("movdqu %0, %%xmm2" :: "m" ((ctx)->sse[2])); \
89 asm volatile("movdqu %0, %%xmm3" :: "m" ((ctx)->sse[3])); \
90 }
91
92 #define FLETCHER_4_SSE_SAVE_CTX(ctx) \
93 { \
94 asm volatile("movdqu %%xmm0, %0" : "=m" ((ctx)->sse[0])); \
95 asm volatile("movdqu %%xmm1, %0" : "=m" ((ctx)->sse[1])); \
96 asm volatile("movdqu %%xmm2, %0" : "=m" ((ctx)->sse[2])); \
97 asm volatile("movdqu %%xmm3, %0" : "=m" ((ctx)->sse[3])); \
98 }
99
100 static void
fletcher_4_sse2_native(fletcher_4_ctx_t * ctx,const void * buf,uint64_t size)101 fletcher_4_sse2_native(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size)
102 {
103 const uint64_t *ip = buf;
104 const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
105
106 FLETCHER_4_SSE_RESTORE_CTX(ctx);
107
108 asm volatile("pxor %xmm4, %xmm4");
109
110 do {
111 asm volatile("movdqu %0, %%xmm5" :: "m"(*ip));
112 asm volatile("movdqa %xmm5, %xmm6");
113 asm volatile("punpckldq %xmm4, %xmm5");
114 asm volatile("punpckhdq %xmm4, %xmm6");
115 asm volatile("paddq %xmm5, %xmm0");
116 asm volatile("paddq %xmm0, %xmm1");
117 asm volatile("paddq %xmm1, %xmm2");
118 asm volatile("paddq %xmm2, %xmm3");
119 asm volatile("paddq %xmm6, %xmm0");
120 asm volatile("paddq %xmm0, %xmm1");
121 asm volatile("paddq %xmm1, %xmm2");
122 asm volatile("paddq %xmm2, %xmm3");
123 } while ((ip += 2) < ipend);
124
125 FLETCHER_4_SSE_SAVE_CTX(ctx);
126 }
127
128 static void
fletcher_4_sse2_byteswap(fletcher_4_ctx_t * ctx,const void * buf,uint64_t size)129 fletcher_4_sse2_byteswap(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size)
130 {
131 const uint32_t *ip = buf;
132 const uint32_t *ipend = (uint32_t *)((uint8_t *)ip + size);
133
134 FLETCHER_4_SSE_RESTORE_CTX(ctx);
135
136 do {
137 uint32_t scratch1 = BSWAP_32(ip[0]);
138 uint32_t scratch2 = BSWAP_32(ip[1]);
139 asm volatile("movd %0, %%xmm5" :: "r"(scratch1));
140 asm volatile("movd %0, %%xmm6" :: "r"(scratch2));
141 asm volatile("punpcklqdq %xmm6, %xmm5");
142 asm volatile("paddq %xmm5, %xmm0");
143 asm volatile("paddq %xmm0, %xmm1");
144 asm volatile("paddq %xmm1, %xmm2");
145 asm volatile("paddq %xmm2, %xmm3");
146 } while ((ip += 2) < ipend);
147
148 FLETCHER_4_SSE_SAVE_CTX(ctx);
149 }
150
fletcher_4_sse2_valid(void)151 static boolean_t fletcher_4_sse2_valid(void)
152 {
153 return (kfpu_allowed() && zfs_sse2_available());
154 }
155
156 const fletcher_4_ops_t fletcher_4_sse2_ops = {
157 .init_native = fletcher_4_sse2_init,
158 .fini_native = fletcher_4_sse2_fini,
159 .compute_native = fletcher_4_sse2_native,
160 .init_byteswap = fletcher_4_sse2_init,
161 .fini_byteswap = fletcher_4_sse2_fini,
162 .compute_byteswap = fletcher_4_sse2_byteswap,
163 .valid = fletcher_4_sse2_valid,
164 .uses_fpu = B_TRUE,
165 .name = "sse2"
166 };
167
168 #endif /* defined(HAVE_SSE2) */
169
170 #if defined(HAVE_SSE2) && defined(HAVE_SSSE3)
171 static void
fletcher_4_ssse3_byteswap(fletcher_4_ctx_t * ctx,const void * buf,uint64_t size)172 fletcher_4_ssse3_byteswap(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size)
173 {
174 static const zfs_fletcher_sse_t mask = {
175 .v = { 0x0405060700010203, 0x0C0D0E0F08090A0B }
176 };
177
178 const uint64_t *ip = buf;
179 const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
180
181 FLETCHER_4_SSE_RESTORE_CTX(ctx);
182
183 asm volatile("movdqu %0, %%xmm7"::"m" (mask));
184 asm volatile("pxor %xmm4, %xmm4");
185
186 do {
187 asm volatile("movdqu %0, %%xmm5"::"m" (*ip));
188 asm volatile("pshufb %xmm7, %xmm5");
189 asm volatile("movdqa %xmm5, %xmm6");
190 asm volatile("punpckldq %xmm4, %xmm5");
191 asm volatile("punpckhdq %xmm4, %xmm6");
192 asm volatile("paddq %xmm5, %xmm0");
193 asm volatile("paddq %xmm0, %xmm1");
194 asm volatile("paddq %xmm1, %xmm2");
195 asm volatile("paddq %xmm2, %xmm3");
196 asm volatile("paddq %xmm6, %xmm0");
197 asm volatile("paddq %xmm0, %xmm1");
198 asm volatile("paddq %xmm1, %xmm2");
199 asm volatile("paddq %xmm2, %xmm3");
200 } while ((ip += 2) < ipend);
201
202 FLETCHER_4_SSE_SAVE_CTX(ctx);
203 }
204
fletcher_4_ssse3_valid(void)205 static boolean_t fletcher_4_ssse3_valid(void)
206 {
207 return (kfpu_allowed() && zfs_sse2_available() &&
208 zfs_ssse3_available());
209 }
210
211 const fletcher_4_ops_t fletcher_4_ssse3_ops = {
212 .init_native = fletcher_4_sse2_init,
213 .fini_native = fletcher_4_sse2_fini,
214 .compute_native = fletcher_4_sse2_native,
215 .init_byteswap = fletcher_4_sse2_init,
216 .fini_byteswap = fletcher_4_sse2_fini,
217 .compute_byteswap = fletcher_4_ssse3_byteswap,
218 .valid = fletcher_4_ssse3_valid,
219 .uses_fpu = B_TRUE,
220 .name = "ssse3"
221 };
222
223 #endif /* defined(HAVE_SSE2) && defined(HAVE_SSSE3) */
224