1 /*
2 * Implement fast Fletcher4 with AVX2 instructions. (x86_64)
3 *
4 * Use the 256-bit AVX2 SIMD instructions and registers to compute
5 * Fletcher4 in four incremental 64-bit parallel accumulator streams,
6 * and then combine the streams to form the final four checksum words.
7 *
8 * Copyright (C) 2015 Intel Corporation.
9 *
10 * Authors:
11 * James Guilford <james.guilford@intel.com>
12 * Jinshan Xiong <jinshan.xiong@intel.com>
13 *
14 * This software is available to you under a choice of one of two
15 * licenses. You may choose to be licensed under the terms of the GNU
16 * General Public License (GPL) Version 2, available from the file
17 * COPYING in the main directory of this source tree, or the
18 * OpenIB.org BSD license below:
19 *
20 * Redistribution and use in source and binary forms, with or
21 * without modification, are permitted provided that the following
22 * conditions are met:
23 *
24 * - Redistributions of source code must retain the above
25 * copyright notice, this list of conditions and the following
26 * disclaimer.
27 *
28 * - Redistributions in binary form must reproduce the above
29 * copyright notice, this list of conditions and the following
30 * disclaimer in the documentation and/or other materials
31 * provided with the distribution.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
35 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
37 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
38 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
39 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 * SOFTWARE.
41 */
42
43 #ifdef __amd64
44
45 #include <sys/types.h>
46 #include <sys/sunddi.h>
47 #include <sys/simd.h>
48 #include <sys/spa_checksum.h>
49 #include <zfs_fletcher.h>
50 #ifndef _KERNEL
51 #include <strings.h>
52 #endif
53
54 static void
fletcher_4_avx2_init(fletcher_4_ctx_t * ctx)55 fletcher_4_avx2_init(fletcher_4_ctx_t *ctx)
56 {
57 bzero(ctx->avx, 4 * sizeof (zfs_fletcher_avx_t));
58 }
59
60 static void
fletcher_4_avx2_fini(fletcher_4_ctx_t * ctx,zio_cksum_t * zcp)61 fletcher_4_avx2_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp)
62 {
63 uint64_t A, B, C, D;
64
65 A = ctx->avx[0].v[0] + ctx->avx[0].v[1] +
66 ctx->avx[0].v[2] + ctx->avx[0].v[3];
67 B = 0 - ctx->avx[0].v[1] - 2 * ctx->avx[0].v[2] - 3 * ctx->avx[0].v[3] +
68 4 * ctx->avx[1].v[0] + 4 * ctx->avx[1].v[1] + 4 * ctx->avx[1].v[2] +
69 4 * ctx->avx[1].v[3];
70
71 C = ctx->avx[0].v[2] + 3 * ctx->avx[0].v[3] - 6 * ctx->avx[1].v[0] -
72 10 * ctx->avx[1].v[1] - 14 * ctx->avx[1].v[2] -
73 18 * ctx->avx[1].v[3] + 16 * ctx->avx[2].v[0] +
74 16 * ctx->avx[2].v[1] + 16 * ctx->avx[2].v[2] +
75 16 * ctx->avx[2].v[3];
76
77 D = 0 - ctx->avx[0].v[3] + 4 * ctx->avx[1].v[0] +
78 10 * ctx->avx[1].v[1] + 20 * ctx->avx[1].v[2] +
79 34 * ctx->avx[1].v[3] - 48 * ctx->avx[2].v[0] -
80 64 * ctx->avx[2].v[1] - 80 * ctx->avx[2].v[2] -
81 96 * ctx->avx[2].v[3] + 64 * ctx->avx[3].v[0] +
82 64 * ctx->avx[3].v[1] + 64 * ctx->avx[3].v[2] +
83 64 * ctx->avx[3].v[3];
84
85 ZIO_SET_CHECKSUM(zcp, A, B, C, D);
86 }
87
88 #define FLETCHER_4_AVX2_RESTORE_CTX(ctx) \
89 { \
90 __asm("vmovdqu %0, %%ymm0" :: "m" ((ctx)->avx[0])); \
91 __asm("vmovdqu %0, %%ymm1" :: "m" ((ctx)->avx[1])); \
92 __asm("vmovdqu %0, %%ymm2" :: "m" ((ctx)->avx[2])); \
93 __asm("vmovdqu %0, %%ymm3" :: "m" ((ctx)->avx[3])); \
94 }
95
96 #define FLETCHER_4_AVX2_SAVE_CTX(ctx) \
97 { \
98 __asm("vmovdqu %%ymm0, %0" : "=m" ((ctx)->avx[0])); \
99 __asm("vmovdqu %%ymm1, %0" : "=m" ((ctx)->avx[1])); \
100 __asm("vmovdqu %%ymm2, %0" : "=m" ((ctx)->avx[2])); \
101 __asm("vmovdqu %%ymm3, %0" : "=m" ((ctx)->avx[3])); \
102 }
103
104 static void
fletcher_4_avx2_native(fletcher_4_ctx_t * ctx,const void * buf,size_t size)105 fletcher_4_avx2_native(fletcher_4_ctx_t *ctx, const void *buf, size_t size)
106 {
107 const uint64_t *ip = buf;
108 const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
109
110 FLETCHER_4_AVX2_RESTORE_CTX(ctx);
111
112 do {
113 __asm("vpmovzxdq %0, %%ymm4"::"m" (*ip));
114 __asm("vpaddq %ymm4, %ymm0, %ymm0");
115 __asm("vpaddq %ymm0, %ymm1, %ymm1");
116 __asm("vpaddq %ymm1, %ymm2, %ymm2");
117 __asm("vpaddq %ymm2, %ymm3, %ymm3");
118 } while ((ip += 2) < ipend);
119
120 FLETCHER_4_AVX2_SAVE_CTX(ctx);
121 __asm("vzeroupper");
122 }
123
124 static void
fletcher_4_avx2_byteswap(fletcher_4_ctx_t * ctx,const void * buf,size_t size)125 fletcher_4_avx2_byteswap(fletcher_4_ctx_t *ctx, const void *buf, size_t size)
126 {
127 static const zfs_fletcher_avx_t mask = {
128 .v = {
129 0xFFFFFFFF00010203, 0xFFFFFFFF08090A0B,
130 0xFFFFFFFF00010203, 0xFFFFFFFF08090A0B
131 }
132 };
133 const uint64_t *ip = buf;
134 const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
135
136 FLETCHER_4_AVX2_RESTORE_CTX(ctx);
137
138 __asm("vmovdqu %0, %%ymm5" :: "m" (mask));
139
140 do {
141 __asm("vpmovzxdq %0, %%ymm4"::"m" (*ip));
142 __asm("vpshufb %ymm5, %ymm4, %ymm4");
143
144 __asm("vpaddq %ymm4, %ymm0, %ymm0");
145 __asm("vpaddq %ymm0, %ymm1, %ymm1");
146 __asm("vpaddq %ymm1, %ymm2, %ymm2");
147 __asm("vpaddq %ymm2, %ymm3, %ymm3");
148 } while ((ip += 2) < ipend);
149
150 FLETCHER_4_AVX2_SAVE_CTX(ctx);
151 __asm("vzeroupper");
152 }
153
154 static boolean_t
fletcher_4_avx2_valid(void)155 fletcher_4_avx2_valid(void)
156 {
157 return (kfpu_allowed() && zfs_avx_available() && zfs_avx2_available());
158 }
159
160 const fletcher_4_ops_t fletcher_4_avx2_ops = {
161 .init_native = fletcher_4_avx2_init,
162 .fini_native = fletcher_4_avx2_fini,
163 .compute_native = fletcher_4_avx2_native,
164 .init_byteswap = fletcher_4_avx2_init,
165 .fini_byteswap = fletcher_4_avx2_fini,
166 .compute_byteswap = fletcher_4_avx2_byteswap,
167 .valid = fletcher_4_avx2_valid,
168 .uses_fpu_native = B_TRUE,
169 .uses_fpu_byteswap = B_TRUE,
170 .name = "avx2"
171 };
172
173 #endif /* __amd64 */
174