1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include "opt_inet.h" 30 #include "opt_inet6.h" 31 #include "opt_acpi.h" 32 33 #include <sys/param.h> 34 #include <sys/types.h> 35 #include <sys/bus.h> 36 #include <sys/counter.h> 37 #include <sys/eventhandler.h> 38 #include <sys/fail.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/module.h> 43 #include <sys/kobj.h> 44 #include <sys/pcpu.h> 45 #include <sys/proc.h> 46 #include <sys/rman.h> 47 #include <sys/sbuf.h> 48 #include <sys/sched.h> 49 #include <sys/smp.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <sys/syslog.h> 54 #include <sys/taskqueue.h> 55 #include <sys/limits.h> 56 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_private.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/debugnet.h> 66 #include <net/pfil.h> 67 #include <net/vnet.h> 68 69 #include <netinet/in.h> 70 #include <netinet/in_pcb.h> 71 #include <netinet/tcp_lro.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/if_ether.h> 74 #include <netinet/ip.h> 75 #include <netinet/ip6.h> 76 #include <netinet/tcp.h> 77 #include <netinet/udp.h> 78 #include <netinet/ip_var.h> 79 #include <netinet6/ip6_var.h> 80 81 #include <machine/bus.h> 82 #include <machine/in_cksum.h> 83 84 #include <vm/vm.h> 85 #include <vm/pmap.h> 86 87 #include <dev/led/led.h> 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pci_private.h> 91 92 #include <net/iflib.h> 93 #include <net/if_vf_status.h> 94 95 #include "ifdi_if.h" 96 97 #ifdef PCI_IOV 98 #include <dev/pci/pci_iov.h> 99 #endif 100 101 #include <sys/bitstring.h> 102 /* 103 * enable accounting of every mbuf as it comes in to and goes out of 104 * iflib's software descriptor references 105 */ 106 #define MEMORY_LOGGING 0 107 /* 108 * Enable mbuf vectors for compressing long mbuf chains 109 */ 110 111 /* 112 * NB: 113 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 114 * we prefetch needs to be determined by the time spent in m_free vis a vis 115 * the cost of a prefetch. This will of course vary based on the workload: 116 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 117 * is quite expensive, thus suggesting very little prefetch. 118 * - small packet forwarding which is just returning a single mbuf to 119 * UMA will typically be very fast vis a vis the cost of a memory 120 * access. 121 */ 122 123 /* 124 * File organization: 125 * - private structures 126 * - iflib private utility functions 127 * - ifnet functions 128 * - vlan registry and other exported functions 129 * - iflib public core functions 130 * 131 * 132 */ 133 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 134 135 #define IFLIB_RXEOF_MORE (1U << 0) 136 #define IFLIB_RXEOF_EMPTY (2U << 0) 137 #define IFLIB_TXQ_QUIESCING (1U << 31) 138 #define IFLIB_TXQ_PRODUCER_LLC_SHIFT 20 139 #define IFLIB_TXQ_PRODUCER_MAX \ 140 ((1U << IFLIB_TXQ_PRODUCER_LLC_SHIFT) - 1) 141 #define IFLIB_TXQ_PRODUCER(_state) \ 142 ((_state) & IFLIB_TXQ_PRODUCER_MAX) 143 #define IFLIB_TXQ_PRODUCER_LLC_MASK \ 144 (~(IFLIB_TXQ_QUIESCING | IFLIB_TXQ_PRODUCER_MAX)) 145 #define IFLIB_TXQ_PRODUCER_LLC(_state) \ 146 (((_state) & IFLIB_TXQ_PRODUCER_LLC_MASK) >> \ 147 IFLIB_TXQ_PRODUCER_LLC_SHIFT) 148 149 CTASSERT(MAXCPU - 1 <= (IFLIB_TXQ_PRODUCER_LLC_MASK >> 150 IFLIB_TXQ_PRODUCER_LLC_SHIFT)); 151 struct iflib_txq; 152 typedef struct iflib_txq *iflib_txq_t; 153 struct iflib_rxq; 154 typedef struct iflib_rxq *iflib_rxq_t; 155 struct iflib_fl; 156 typedef struct iflib_fl *iflib_fl_t; 157 158 struct iflib_ctx; 159 160 /* 161 * This state describes access to queue mappings owned by iflib. It does not 162 * describe driver-owned administrative DMA or the PCI function's power state. 163 * Normal transitions are serialized by ifc_ctx_sx. 164 * 165 * Only STOPPED establishes that the device can no longer access the mappings; 166 * a failed initialization can leave queues active. IFF_UP separately records 167 * administrative intent. ifc_running separately gates software traffic, 168 * but clearing it does not establish quiescence: the watchdog closes that 169 * gate before the admin task stops the hardware. Use this state for lifecycle 170 * decisions under ifc_ctx_sx, not as an unlocked datapath admission check. 171 */ 172 enum iflib_datapath_state { 173 IFLIB_DP_UNKNOWN = 0, 174 IFLIB_DP_STOPPED, 175 IFLIB_DP_FAILED, 176 IFLIB_DP_STARTING, 177 IFLIB_DP_RUNNING, 178 IFLIB_DP_STOPPING, 179 }; 180 181 /* 182 * Power-transition state is separate from datapath ownership. It gates 183 * configuration callbacks while the device is entering or remains in low 184 * power without making any claim about driver-owned firmware or admin DMA. 185 */ 186 enum iflib_pm_state { 187 IFLIB_PM_ACTIVE = 0, 188 IFLIB_PM_SUSPENDING, 189 IFLIB_PM_SUSPENDED, 190 }; 191 192 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 193 static void iflib_timer(void *arg); 194 static void iflib_tqg_detach(if_ctx_t ctx); 195 static int iflib_simple_transmit(if_t ifp, struct mbuf *m); 196 static int iflib_simple_transmit_txq_select(if_t ifp, struct mbuf *m); 197 static int iflib_simple_transmit_txq_select_v2(if_t ifp, struct mbuf *m); 198 static void iflib_simple_if_start(if_t ifp); 199 static void iflib_simple_txq_drain(iflib_txq_t txq); 200 201 typedef struct iflib_filter_info { 202 driver_filter_t *ifi_filter; 203 void *ifi_filter_arg; 204 struct grouptask *ifi_task; 205 void *ifi_ctx; 206 } *iflib_filter_info_t; 207 208 struct iflib_ctx { 209 KOBJ_FIELDS; 210 /* 211 * Pointer to hardware driver's softc 212 */ 213 void *ifc_softc; 214 device_t ifc_dev; 215 if_t ifc_ifp; 216 217 cpuset_t ifc_cpus; 218 if_shared_ctx_t ifc_sctx; 219 struct if_softc_ctx ifc_softc_ctx; 220 221 struct sx ifc_ctx_sx; 222 struct mtx ifc_state_mtx; 223 224 iflib_txq_t ifc_txqs; 225 iflib_rxq_t ifc_rxqs; 226 uint32_t ifc_if_flags; 227 uint32_t ifc_flags; 228 enum iflib_datapath_state ifc_datapath_state; 229 enum iflib_pm_state ifc_pm_state; 230 /* Atomic software admission snapshot, not proof of DMA quiescence. */ 231 u_int ifc_running; 232 uint32_t ifc_max_fl_buf_size; 233 uint32_t ifc_rx_mbuf_sz; 234 235 int ifc_link_state; 236 uint32_t ifc_tx_watchdog_events; 237 struct cdev *ifc_led_dev; 238 int ifc_led_state; 239 struct resource *ifc_msix_mem; 240 241 struct if_irq ifc_legacy_irq; 242 struct task ifc_admin_task; 243 struct task ifc_led_task; 244 struct task ifc_vflr_task; 245 struct taskqueue *ifc_tq; 246 struct iflib_filter_info ifc_filter_info; 247 struct ifmedia ifc_media; 248 struct ifmedia *ifc_mediap; 249 250 struct sysctl_ctx_list ifc_sysctl_ctx; 251 struct sysctl_oid *ifc_sysctl_node; 252 uint16_t ifc_sysctl_ntxqs; 253 uint16_t ifc_sysctl_nrxqs; 254 uint16_t ifc_sysctl_qs_eq_override; 255 uint16_t ifc_sysctl_rx_budget; 256 uint16_t ifc_sysctl_tx_abdicate; 257 uint16_t ifc_sysctl_core_offset; 258 #define CORE_OFFSET_UNSPECIFIED 0xffff 259 uint8_t ifc_sysctl_separate_txrx; 260 uint8_t ifc_sysctl_use_logical_cores; 261 uint16_t ifc_sysctl_extra_msix_vectors; 262 bool ifc_cpus_are_physical_cores; 263 bool ifc_core_offset_ref; 264 bool ifc_sysctl_simple_tx; 265 bool ifc_sysctl_tx_defer_mfree; 266 uint16_t ifc_sysctl_tx_reclaim_thresh; 267 uint16_t ifc_sysctl_tx_reclaim_ticks; 268 269 qidx_t ifc_sysctl_ntxds[8]; 270 qidx_t ifc_sysctl_nrxds[8]; 271 struct if_txrx ifc_txrx; 272 #define isc_txd_encap ifc_txrx.ift_txd_encap 273 #define isc_txd_flush ifc_txrx.ift_txd_flush 274 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 275 #define isc_rxd_available ifc_txrx.ift_rxd_available 276 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 277 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 278 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 279 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 280 #define isc_txq_select ifc_txrx.ift_txq_select 281 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2 282 283 eventhandler_tag ifc_vlan_attach_event; 284 eventhandler_tag ifc_vlan_detach_event; 285 struct ether_addr ifc_mac; 286 }; 287 288 void * 289 iflib_get_softc(if_ctx_t ctx) 290 { 291 292 return (ctx->ifc_softc); 293 } 294 295 device_t 296 iflib_get_dev(if_ctx_t ctx) 297 { 298 299 return (ctx->ifc_dev); 300 } 301 302 if_t 303 iflib_get_ifp(if_ctx_t ctx) 304 { 305 306 return (ctx->ifc_ifp); 307 } 308 309 bool 310 iflib_is_running(if_ctx_t ctx) 311 { 312 313 return (atomic_load_acq_int(&ctx->ifc_running) != 0); 314 } 315 316 struct ifmedia * 317 iflib_get_media(if_ctx_t ctx) 318 { 319 320 return (ctx->ifc_mediap); 321 } 322 323 void 324 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 325 { 326 327 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 328 } 329 330 if_softc_ctx_t 331 iflib_get_softc_ctx(if_ctx_t ctx) 332 { 333 334 return (&ctx->ifc_softc_ctx); 335 } 336 337 if_shared_ctx_t 338 iflib_get_sctx(if_ctx_t ctx) 339 { 340 341 return (ctx->ifc_sctx); 342 } 343 344 uint16_t 345 iflib_get_extra_msix_vectors_sysctl(if_ctx_t ctx) 346 { 347 348 return (ctx->ifc_sysctl_extra_msix_vectors); 349 } 350 351 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 352 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE / sizeof(void *)) 353 #define CACHE_PTR_NEXT(ptr) ((void *)(roundup2(ptr, CACHE_LINE_SIZE))) 354 355 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 356 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 357 358 typedef struct iflib_sw_rx_desc_array { 359 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 360 struct mbuf **ifsd_m; /* pkthdr mbufs */ 361 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 362 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 363 } iflib_rxsd_array_t; 364 365 typedef struct iflib_sw_tx_desc_array { 366 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 367 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 368 struct mbuf **ifsd_m; /* pkthdr mbufs */ 369 struct mbuf **ifsd_m_defer; /* deferred mbuf ptr */ 370 struct mbuf **ifsd_m_deferb;/* deferred mbuf backing ptr */ 371 } if_txsd_vec_t; 372 373 /* magic number that should be high enough for any hardware */ 374 #define IFLIB_MAX_TX_SEGS 128 375 #define IFLIB_RX_COPY_THRESH 128 376 #define IFLIB_MAX_RX_REFRESH 32 377 /* The minimum descriptors per second before we start coalescing */ 378 #define IFLIB_MIN_DESC_SEC 16384 379 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 380 /* maximum number of txqs that can share an rx interrupt */ 381 #define IFLIB_MAX_TX_SHARED_INTR 4 382 383 /* this should really scale with ring size - this is a fairly arbitrary value */ 384 #define TX_BATCH_SIZE 32 385 386 #define IFLIB_RESTART_BUDGET 8 387 388 389 /* 390 * Encode TSO or !TSO in the low bits of the tx ifsd_m pointer so as 391 * to avoid defref'ing the mbuf to determine the correct busdma resources 392 * to release 393 */ 394 #define IFLIB_TSO (1ULL << 0) 395 #define IFLIB_NO_TSO (2ULL << 0) 396 #define IFLIB_FLAGS_MASK (0x3ULL) 397 #define IFLIB_SAVE_MBUF(mbuf, flags) ((void *)(((uintptr_t)mbuf) | flags)) 398 #define IFLIB_GET_FLAGS(a) ((uintptr_t)a & IFLIB_FLAGS_MASK) 399 #define IFLIB_GET_MBUF(a) ((struct mbuf *)((uintptr_t)a & ~IFLIB_FLAGS_MASK)) 400 401 402 #define IFC_LEGACY 0x001 403 #define IFC_QFLUSH 0x002 404 #define IFC_MULTISEG 0x004 405 #define IFC_INIT_FAILED 0x008 406 #define IFC_SC_ALLOCATED 0x010 407 #define IFC_INIT_DONE 0x020 408 #define IFC_PREFETCH 0x040 409 #define IFC_DO_RESET 0x080 410 #define IFC_DO_WATCHDOG 0x100 411 #define IFC_DO_RESET_IF_UP 0x200 412 #define IFC_SPARE2 0x400 413 #define IFC_IN_DETACH 0x800 414 415 #define IFC_NETMAP_TX_IRQ 0x80000000 416 417 #define CSUM_OFFLOAD (CSUM_IP_TSO | CSUM_IP6_TSO | CSUM_IP | \ 418 CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_SCTP | \ 419 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_SCTP) 420 421 struct iflib_txq { 422 qidx_t ift_in_use; 423 qidx_t ift_cidx; 424 qidx_t ift_cidx_processed; 425 qidx_t ift_pidx; 426 uint8_t ift_gen; 427 uint8_t ift_br_offset:1, 428 ift_defer_mfree:1, 429 ift_spare_bits0:6; 430 uint16_t ift_npending; 431 uint16_t ift_db_pending; 432 uint16_t ift_rs_pending; 433 uint32_t ift_last_reclaim; 434 uint16_t ift_reclaim_thresh; 435 uint16_t ift_reclaim_ticks; 436 uint8_t ift_txd_size[8]; 437 uint64_t ift_processed; 438 uint64_t ift_cleaned; 439 uint64_t ift_processed_prev; 440 #if MEMORY_LOGGING 441 uint64_t ift_enqueued; 442 uint64_t ift_dequeued; 443 #endif 444 uint64_t ift_no_tx_dma_setup; 445 uint64_t ift_no_desc_avail; 446 uint64_t ift_mbuf_defrag_failed; 447 uint64_t ift_mbuf_defrag; 448 uint64_t ift_map_failed; 449 uint64_t ift_txd_encap_efbig; 450 uint64_t ift_pullups; 451 uint64_t ift_last_timer_tick; 452 uint64_t ift_drbr_direct; 453 uint64_t ift_drbr_stall; 454 counter_u64_t ift_drbr_deferred; 455 counter_u64_t ift_drbr_drops; 456 counter_u64_t ift_drbr_blocked; 457 counter_u64_t ift_drbr_remote; 458 459 /* Lockless producer count and current llc. */ 460 volatile u_int ift_producers __aligned(CACHE_LINE_SIZE); 461 462 struct mtx ift_mtx; 463 struct mtx ift_db_mtx; 464 465 /* constant values */ 466 if_ctx_t ift_ctx; 467 struct ifmp_ring *ift_br; 468 struct buf_ring *ift_drbr; 469 struct grouptask ift_task; 470 qidx_t ift_size; 471 qidx_t ift_pad; 472 uint16_t ift_id; 473 struct callout ift_timer; 474 #ifdef DEV_NETMAP 475 struct callout ift_netmap_timer; 476 #endif /* DEV_NETMAP */ 477 478 if_txsd_vec_t ift_sds; 479 /* 480 * TX watchdog state, updated once per iflib_timer period. The 481 * period count saturates instead of wrapping, and is 16 bits 482 * wide so that it still reaches any value 483 * net.iflib.tx_watchdog_periods is plausibly set to; an 8-bit 484 * counter would silently disable the check for a threshold 485 * above 255. 486 */ 487 qidx_t ift_outstanding_prev; 488 uint16_t ift_wdog_armed; 489 uint8_t ift_closed; 490 uint8_t ift_update_freq; 491 uint8_t ift_spare0[2]; /* pad to the next pointer boundary */ 492 struct iflib_filter_info ift_filter_info; 493 bus_dma_tag_t ift_buf_tag; 494 bus_dma_tag_t ift_tso_buf_tag; 495 iflib_dma_info_t ift_ifdi; 496 #define MTX_NAME_LEN 32 497 char ift_mtx_name[MTX_NAME_LEN]; 498 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 499 #ifdef IFLIB_DIAGNOSTICS 500 uint64_t ift_cpu_exec_count[256]; 501 #endif 502 } __aligned(CACHE_LINE_SIZE); 503 504 struct iflib_fl { 505 qidx_t ifl_cidx; 506 qidx_t ifl_pidx; 507 qidx_t ifl_credits; 508 uint8_t ifl_gen; 509 uint8_t ifl_rxd_size; 510 #if MEMORY_LOGGING 511 uint64_t ifl_m_enqueued; 512 uint64_t ifl_m_dequeued; 513 uint64_t ifl_cl_enqueued; 514 uint64_t ifl_cl_dequeued; 515 #endif 516 /* implicit pad */ 517 bitstr_t *ifl_rx_bitmap; 518 qidx_t ifl_fragidx; 519 /* constant */ 520 qidx_t ifl_size; 521 uint16_t ifl_buf_size; 522 uint16_t ifl_cltype; 523 uma_zone_t ifl_zone; 524 iflib_rxsd_array_t ifl_sds; 525 iflib_rxq_t ifl_rxq; 526 uint8_t ifl_id; 527 bus_dma_tag_t ifl_buf_tag; 528 iflib_dma_info_t ifl_ifdi; 529 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 530 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 531 } __aligned(CACHE_LINE_SIZE); 532 533 static inline qidx_t 534 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 535 { 536 qidx_t used; 537 538 if (pidx > cidx) 539 used = pidx - cidx; 540 else if (pidx < cidx) 541 used = size - cidx + pidx; 542 else if (gen == 0 && pidx == cidx) 543 used = 0; 544 else if (gen == 1 && pidx == cidx) 545 used = size; 546 else 547 panic("bad state"); 548 549 return (used); 550 } 551 552 #define TXQ_AVAIL(txq) ((txq->ift_size - txq->ift_pad) -\ 553 get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 554 555 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 556 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 557 558 #define IDXDIFF(head, tail, wrap) \ 559 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 560 561 struct iflib_rxq { 562 if_ctx_t ifr_ctx; 563 iflib_fl_t ifr_fl; 564 struct pfil_head *pfil; 565 /* 566 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 567 * the completion queue consumer index. Otherwise it's unused. 568 */ 569 qidx_t ifr_cq_cidx; 570 uint16_t ifr_id; 571 uint8_t ifr_nfl; 572 uint8_t ifr_ntxqirq; 573 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 574 uint8_t ifr_fl_offset; 575 struct lro_ctrl ifr_lc; 576 struct grouptask ifr_task; 577 struct callout ifr_watchdog; 578 struct iflib_filter_info ifr_filter_info; 579 iflib_dma_info_t ifr_ifdi; 580 581 /* dynamically allocate if any drivers need a value substantially larger than this */ 582 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 583 #ifdef IFLIB_DIAGNOSTICS 584 uint64_t ifr_cpu_exec_count[256]; 585 #endif 586 } __aligned(CACHE_LINE_SIZE); 587 588 typedef struct if_rxsd { 589 caddr_t *ifsd_cl; 590 iflib_fl_t ifsd_fl; 591 } *if_rxsd_t; 592 593 /* 594 * Only allow a single packet to take up most 1/nth of the tx ring 595 */ 596 #define MAX_SINGLE_PACKET_FRACTION 12 597 #define IF_BAD_DMA ((bus_addr_t)-1) 598 599 #define CTX_ACTIVE(ctx) iflib_is_running(ctx) 600 601 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 602 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 603 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 604 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 605 606 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 607 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 608 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 609 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 610 611 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 612 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 613 614 static bool 615 iflib_admin_enabled(if_ctx_t ctx) 616 { 617 618 sx_assert(&ctx->ifc_ctx_sx, SA_XLOCKED); 619 /* 620 * Before the first stop/init, only drivers with an always-running 621 * admin path need deferred updates. Stopped and failed datapaths 622 * still need link, mailbox and recovery work after that point. 623 */ 624 return (ctx->ifc_datapath_state != IFLIB_DP_UNKNOWN || 625 (ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN) != 0); 626 } 627 628 /* Our boot-time initialization hook */ 629 static int iflib_module_event_handler(module_t, int, void *); 630 631 static moduledata_t iflib_moduledata = { 632 "iflib", 633 iflib_module_event_handler, 634 NULL 635 }; 636 637 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 638 MODULE_VERSION(iflib, 1); 639 640 MODULE_DEPEND(iflib, pci, 1, 1, 1); 641 MODULE_DEPEND(iflib, ether, 1, 1, 1); 642 643 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 644 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 645 646 #ifndef IFLIB_DEBUG_COUNTERS 647 #ifdef INVARIANTS 648 #define IFLIB_DEBUG_COUNTERS 1 649 #else 650 #define IFLIB_DEBUG_COUNTERS 0 651 #endif /* !INVARIANTS */ 652 #endif 653 654 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 655 "iflib driver parameters"); 656 657 static SYSCTL_NODE(_debug_fail_point, OID_AUTO, iflib, 658 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, "iflib fail points"); 659 660 static char iflib_register_fail_device[32]; 661 SYSCTL_STRING(_debug_fail_point_iflib, OID_AUTO, register_device, 662 CTLFLAG_RW | CTLFLAG_MPSAFE, 663 iflib_register_fail_device, sizeof(iflib_register_fail_device), 664 "device name eligible for registration fail points"); 665 666 static char iflib_admin_task_fail_device[32]; 667 SYSCTL_STRING(_debug_fail_point_iflib, OID_AUTO, admin_task_device, 668 CTLFLAG_RW | CTLFLAG_MPSAFE, 669 iflib_admin_task_fail_device, sizeof(iflib_admin_task_fail_device), 670 "device name eligible for admin task fail points"); 671 672 /* 673 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 674 */ 675 static int iflib_min_tx_latency = 0; 676 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 677 &iflib_min_tx_latency, 0, 678 "minimize transmit latency at the possible expense of throughput"); 679 static int iflib_no_tx_batch = 0; 680 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 681 &iflib_no_tx_batch, 0, 682 "minimize transmit latency at the possible expense of throughput"); 683 static int iflib_timer_default = 1000; 684 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 685 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 686 /* 687 * Consecutive timer periods a TX queue must stay frozen while demand 688 * persists - see iflib_timer(), which defines those states - before the 689 * hardware is asked whether it has completions pending. Four periods is 690 * roughly two seconds with the default timer interval: a healthy queue on 691 * hardware that coalesces completion reports (e.g. 8254x, TXDCTL.WTHRESH) 692 * stays frozen for at most two (measured on 82541PI), a wedged one until it 693 * is reset. 694 */ 695 static int iflib_tx_watchdog_periods = 4; 696 SYSCTL_INT(_net_iflib, OID_AUTO, tx_watchdog_periods, CTLFLAG_RWTUN, 697 &iflib_tx_watchdog_periods, 0, 698 "consecutive frozen timer periods under demand before a TX queue is " 699 "checked for a hang (0 disables the check)"); 700 701 #define IFLIB_SIMPLE_TXBR_MIN 64 702 #define IFLIB_SIMPLE_TXBR_SIZE 1024 703 static int iflib_simple_txbr_size = IFLIB_SIMPLE_TXBR_SIZE; 704 SYSCTL_INT(_net_iflib, OID_AUTO, simple_txbr_size, CTLFLAG_RDTUN, 705 &iflib_simple_txbr_size, 0, 706 "number of entries in the simple tx deferral ring"); 707 static bool iflib_prefer_mpring = true; 708 SYSCTL_BOOL(_net_iflib, OID_AUTO, prefer_mpring, CTLFLAG_RDTUN, 709 &iflib_prefer_mpring, 0, 710 "prefer the mp_ring transmit path by default"); 711 static u_int iflib_simple_drain_quota = 8; 712 SYSCTL_UINT(_net_iflib, OID_AUTO, simple_drain_quota, CTLFLAG_RWTUN, 713 &iflib_simple_drain_quota, 0, 714 "maximum packets sent per simple tx deferral ring drain from the tx task"); 715 static u_int iflib_simple_drain_quota_thread = 65536; 716 SYSCTL_UINT(_net_iflib, OID_AUTO, simple_drain_quota_thread, CTLFLAG_RWTUN, 717 &iflib_simple_drain_quota_thread, 0, 718 "maximum packets sent per simple tx deferral ring drain from another thread"); 719 static u_int iflib_max_producers = 8; 720 static bool iflib_single_llc __read_mostly; 721 static bool iflib_producer_gate __read_mostly; 722 723 static int 724 iflib_sysctl_max_producers(SYSCTL_HANDLER_ARGS) 725 { 726 u_int max_producers; 727 int error; 728 729 max_producers = iflib_max_producers; 730 error = sysctl_handle_int(oidp, &max_producers, 0, req); 731 if (error != 0 || req->newptr == NULL) 732 return (error); 733 734 max_producers = MIN(max_producers, IFLIB_TXQ_PRODUCER_MAX); 735 iflib_max_producers = max_producers; 736 if (iflib_single_llc) 737 iflib_producer_gate = mp_ncpus > max_producers; 738 return (0); 739 } 740 SYSCTL_PROC(_net_iflib, OID_AUTO, max_producers, 741 CTLTYPE_UINT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, &iflib_max_producers, 0, 742 iflib_sysctl_max_producers, "IU", 743 "maximum concurrent lockless producers per transmit queue"); 744 745 /* Encoded llc for each CPU. */ 746 static uint16_t iflib_cpu_llc[MAXCPU] __read_mostly; 747 748 #if IFLIB_DEBUG_COUNTERS 749 750 static int iflib_tx_seen; 751 static int iflib_tx_sent; 752 static int iflib_tx_encap; 753 static int iflib_rx_allocs; 754 static int iflib_fl_refills; 755 static int iflib_fl_refills_large; 756 static int iflib_tx_frees; 757 758 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, &iflib_tx_seen, 0, 759 "# TX mbufs seen"); 760 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, &iflib_tx_sent, 0, 761 "# TX mbufs sent"); 762 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, &iflib_tx_encap, 0, 763 "# TX mbufs encapped"); 764 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, &iflib_tx_frees, 0, 765 "# TX frees"); 766 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, &iflib_rx_allocs, 0, 767 "# RX allocations"); 768 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, &iflib_fl_refills, 0, 769 "# refills"); 770 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 771 &iflib_fl_refills_large, 0, "# large refills"); 772 773 static int iflib_txq_drain_flushing; 774 static int iflib_txq_drain_stopped; 775 static int iflib_txq_drain_notready; 776 777 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 778 &iflib_txq_drain_flushing, 0, "# drain flushes"); 779 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_stopped, CTLFLAG_RD, 780 &iflib_txq_drain_stopped, 0, "# drains interrupted by stop"); 781 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 782 &iflib_txq_drain_notready, 0, "# drain notready"); 783 784 static int iflib_encap_load_mbuf_fail; 785 static int iflib_encap_pad_mbuf_fail; 786 static int iflib_encap_txq_avail_fail; 787 static int iflib_encap_txd_encap_fail; 788 789 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 790 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 791 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 792 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 793 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 794 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 795 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 796 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 797 798 static int iflib_task_fn_rxs; 799 static int iflib_rx_intr_enables; 800 static int iflib_fast_intrs; 801 static int iflib_rx_unavail; 802 static int iflib_rx_ctx_inactive; 803 static int iflib_rx_if_input; 804 static int iflib_rxd_flush; 805 806 static int iflib_verbose_debug; 807 808 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, &iflib_task_fn_rxs, 0, 809 "# task_fn_rx calls"); 810 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 811 &iflib_rx_intr_enables, 0, "# RX intr enables"); 812 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, &iflib_fast_intrs, 0, 813 "# fast_intr calls"); 814 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, &iflib_rx_unavail, 0, 815 "# times rxeof called with no available data"); 816 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 817 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 818 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, &iflib_rx_if_input, 819 0, "# times rxeof called if_input"); 820 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, &iflib_rxd_flush, 0, 821 "# times rxd_flush called"); 822 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 823 &iflib_verbose_debug, 0, "enable verbose debugging"); 824 825 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 826 static void 827 iflib_debug_reset(void) 828 { 829 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 830 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 831 iflib_txq_drain_flushing = iflib_txq_drain_stopped = 832 iflib_txq_drain_notready = 833 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 834 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 835 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 836 iflib_rx_unavail = 837 iflib_rx_ctx_inactive = iflib_rx_if_input = 838 iflib_rxd_flush = 0; 839 } 840 841 #else 842 #define DBG_COUNTER_INC(name) 843 static void iflib_debug_reset(void) {} 844 #endif 845 846 #define IFLIB_DEBUG 0 847 848 static void iflib_tx_structures_free(if_ctx_t ctx); 849 static void iflib_rx_structures_free(if_ctx_t ctx); 850 static int iflib_queues_alloc(if_ctx_t ctx); 851 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 852 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 853 static int iflib_qset_structures_setup(if_ctx_t ctx); 854 static int iflib_msix_init(if_ctx_t ctx); 855 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 856 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 857 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 858 #ifdef ALTQ 859 static void iflib_altq_if_start(if_t ifp); 860 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 861 #endif 862 static void iflib_register(if_ctx_t); 863 static void iflib_deregister(if_ctx_t); 864 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 865 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 866 static void iflib_init_locked(if_ctx_t ctx); 867 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 868 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 869 static void iflib_ifmp_purge(iflib_txq_t txq); 870 static void _iflib_pre_assert(if_softc_ctx_t scctx); 871 static void iflib_stop(if_ctx_t ctx); 872 static void iflib_if_init_locked(if_ctx_t ctx); 873 static void iflib_free_intr_mem(if_ctx_t ctx); 874 #ifndef __NO_STRICT_ALIGNMENT 875 static struct mbuf *iflib_fixup_rx(struct mbuf *m); 876 #endif 877 static __inline int iflib_completed_tx_reclaim(iflib_txq_t txq, 878 struct mbuf **m_defer); 879 static __inline void iflib_completed_tx_reclaim_force(iflib_txq_t txq); 880 881 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 882 SLIST_HEAD_INITIALIZER(cpu_offsets); 883 struct cpu_offset { 884 SLIST_ENTRY(cpu_offset) entries; 885 cpuset_t set; 886 unsigned int refcount; 887 uint16_t next_cpuid; 888 }; 889 static struct mtx cpu_offset_mtx; 890 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 891 MTX_DEF); 892 893 DEBUGNET_DEFINE(iflib); 894 895 static int 896 iflib_num_rx_descs(if_ctx_t ctx) 897 { 898 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 899 if_shared_ctx_t sctx = ctx->ifc_sctx; 900 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 901 902 return (scctx->isc_nrxd[first_rxq]); 903 } 904 905 static int 906 iflib_num_tx_descs(if_ctx_t ctx) 907 { 908 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 909 if_shared_ctx_t sctx = ctx->ifc_sctx; 910 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 911 912 return (scctx->isc_ntxd[first_txq]); 913 } 914 915 #ifdef DEV_NETMAP 916 #include <sys/selinfo.h> 917 #include <net/netmap.h> 918 #include <dev/netmap/netmap_kern.h> 919 920 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 921 922 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 923 static void iflib_netmap_timer(void *arg); 924 925 /* 926 * device-specific sysctl variables: 927 * 928 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 929 * During regular operations the CRC is stripped, but on some 930 * hardware reception of frames not multiple of 64 is slower, 931 * so using crcstrip=0 helps in benchmarks. 932 * 933 * iflib_rx_miss, iflib_rx_miss_bufs: 934 * count packets that might be missed due to lost interrupts. 935 */ 936 SYSCTL_DECL(_dev_netmap); 937 /* 938 * The xl driver by default strips CRCs and we do not override it. 939 */ 940 941 int iflib_crcstrip = 1; 942 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 943 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 944 945 int iflib_rx_miss, iflib_rx_miss_bufs; 946 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 947 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 948 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 949 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 950 951 /* 952 * Register/unregister. We are already under netmap lock. 953 * Only called on the first register or the last unregister. 954 */ 955 static int 956 iflib_netmap_register(struct netmap_adapter *na, int onoff) 957 { 958 if_t ifp = na->ifp; 959 if_ctx_t ctx = if_getsoftc(ifp); 960 int status; 961 962 CTX_LOCK(ctx); 963 if (!CTX_IS_VF(ctx)) 964 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 965 966 iflib_stop(ctx); 967 968 /* 969 * Enable (or disable) netmap flags, and intercept (or restore) 970 * ifp->if_transmit. This is done once the device has been stopped 971 * to prevent race conditions. Also, this must be done after 972 * calling netmap_disable_all_rings() and before calling 973 * netmap_enable_all_rings(), so that these two functions see the 974 * updated state of the NAF_NETMAP_ON bit. 975 */ 976 if (onoff) { 977 nm_set_native_flags(na); 978 } else { 979 nm_clear_native_flags(na); 980 } 981 982 iflib_init_locked(ctx); 983 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 984 status = ctx->ifc_datapath_state == IFLIB_DP_RUNNING ? 0 : 1; 985 if (status) 986 nm_clear_native_flags(na); 987 CTX_UNLOCK(ctx); 988 return (status); 989 } 990 991 static int 992 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 993 { 994 if_t ifp = na->ifp; 995 if_ctx_t ctx = if_getsoftc(ifp); 996 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 997 iflib_fl_t fl = &rxq->ifr_fl[0]; 998 999 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1000 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1001 info->num_tx_descs = iflib_num_tx_descs(ctx); 1002 info->num_rx_descs = iflib_num_rx_descs(ctx); 1003 info->rx_buf_maxsize = fl->ifl_buf_size; 1004 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 1005 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 1006 info->num_rx_descs, info->rx_buf_maxsize); 1007 1008 return (0); 1009 } 1010 1011 static int 1012 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 1013 { 1014 struct netmap_adapter *na = kring->na; 1015 u_int const lim = kring->nkr_num_slots - 1; 1016 struct netmap_ring *ring = kring->ring; 1017 bus_dmamap_t *map; 1018 struct if_rxd_update iru; 1019 if_ctx_t ctx = rxq->ifr_ctx; 1020 iflib_fl_t fl = &rxq->ifr_fl[0]; 1021 u_int nic_i_first, nic_i; 1022 u_int nm_i; 1023 int i, n; 1024 #if IFLIB_DEBUG_COUNTERS 1025 int rf_count = 0; 1026 #endif 1027 1028 /* 1029 * This function is used both at initialization and in rxsync. 1030 * At initialization we need to prepare (with isc_rxd_refill()) 1031 * all the netmap buffers currently owned by the kernel, in 1032 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 1033 * (except for kring->nkr_hwofs). These may be less than 1034 * kring->nkr_num_slots if netmap_reset() was called while 1035 * an application using the kring that still owned some 1036 * buffers. 1037 * At rxsync time, both indexes point to the next buffer to be 1038 * refilled. 1039 * In any case we publish (with isc_rxd_flush()) up to 1040 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 1041 * pointer to overrun the head/cons pointer, although this is 1042 * not necessary for some NICs (e.g. vmx). 1043 */ 1044 if (__predict_false(init)) { 1045 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 1046 } else { 1047 n = kring->rhead - kring->nr_hwcur; 1048 if (n == 0) 1049 return (0); /* Nothing to do. */ 1050 if (n < 0) 1051 n += kring->nkr_num_slots; 1052 } 1053 1054 iru_init(&iru, rxq, 0 /* flid */); 1055 map = fl->ifl_sds.ifsd_map; 1056 nic_i = fl->ifl_pidx; 1057 nm_i = netmap_idx_n2k(kring, nic_i); 1058 if (__predict_false(init)) { 1059 /* 1060 * On init/reset, nic_i must be 0, and we must 1061 * start to refill from hwtail (see netmap_reset()). 1062 */ 1063 MPASS(nic_i == 0); 1064 MPASS(nm_i == kring->nr_hwtail); 1065 } else 1066 MPASS(nm_i == kring->nr_hwcur); 1067 DBG_COUNTER_INC(fl_refills); 1068 while (n > 0) { 1069 #if IFLIB_DEBUG_COUNTERS 1070 if (++rf_count == 9) 1071 DBG_COUNTER_INC(fl_refills_large); 1072 #endif 1073 nic_i_first = nic_i; 1074 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 1075 struct netmap_slot *slot = &ring->slot[nm_i]; 1076 uint64_t paddr; 1077 void *addr = PNMB(na, slot, &paddr); 1078 1079 MPASS(i < IFLIB_MAX_RX_REFRESH); 1080 1081 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 1082 return (netmap_ring_reinit(kring)); 1083 1084 fl->ifl_bus_addrs[i] = paddr + 1085 nm_get_offset(kring, slot); 1086 fl->ifl_rxd_idxs[i] = nic_i; 1087 1088 if (__predict_false(init)) { 1089 netmap_load_map(na, fl->ifl_buf_tag, 1090 map[nic_i], addr); 1091 } else if (slot->flags & NS_BUF_CHANGED) { 1092 /* buffer has changed, reload map */ 1093 netmap_reload_map(na, fl->ifl_buf_tag, 1094 map[nic_i], addr); 1095 } 1096 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 1097 BUS_DMASYNC_PREREAD); 1098 slot->flags &= ~NS_BUF_CHANGED; 1099 1100 nm_i = nm_next(nm_i, lim); 1101 nic_i = nm_next(nic_i, lim); 1102 } 1103 1104 iru.iru_pidx = nic_i_first; 1105 iru.iru_count = i; 1106 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1107 } 1108 fl->ifl_pidx = nic_i; 1109 /* 1110 * At the end of the loop we must have refilled everything 1111 * we could possibly refill. 1112 */ 1113 MPASS(nm_i == kring->rhead); 1114 kring->nr_hwcur = nm_i; 1115 1116 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1117 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1118 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 1119 nm_prev(nic_i, lim)); 1120 DBG_COUNTER_INC(rxd_flush); 1121 1122 return (0); 1123 } 1124 1125 #define NETMAP_TX_TIMER_US 90 1126 1127 /* 1128 * Reconcile kernel and user view of the transmit ring. 1129 * 1130 * All information is in the kring. 1131 * Userspace wants to send packets up to the one before kring->rhead, 1132 * kernel knows kring->nr_hwcur is the first unsent packet. 1133 * 1134 * Here we push packets out (as many as possible), and possibly 1135 * reclaim buffers from previously completed transmission. 1136 * 1137 * The caller (netmap) guarantees that there is only one instance 1138 * running at any time. Any interference with other driver 1139 * methods should be handled by the individual drivers. 1140 */ 1141 static int 1142 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 1143 { 1144 struct netmap_adapter *na = kring->na; 1145 if_t ifp = na->ifp; 1146 struct netmap_ring *ring = kring->ring; 1147 u_int nm_i; /* index into the netmap kring */ 1148 u_int nic_i; /* index into the NIC ring */ 1149 u_int const lim = kring->nkr_num_slots - 1; 1150 u_int const head = kring->rhead; 1151 struct if_pkt_info pi; 1152 int tx_pkts = 0, tx_bytes = 0; 1153 1154 /* 1155 * interrupts on every tx packet are expensive so request 1156 * them every half ring, or where NS_REPORT is set 1157 */ 1158 u_int report_frequency = kring->nkr_num_slots >> 1; 1159 /* device-specific */ 1160 if_ctx_t ctx = if_getsoftc(ifp); 1161 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1162 1163 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1164 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1165 1166 /* 1167 * First part: process new packets to send. 1168 * nm_i is the current index in the netmap kring, 1169 * nic_i is the corresponding index in the NIC ring. 1170 * 1171 * If we have packets to send (nm_i != head) 1172 * iterate over the netmap ring, fetch length and update 1173 * the corresponding slot in the NIC ring. Some drivers also 1174 * need to update the buffer's physical address in the NIC slot 1175 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1176 * 1177 * The netmap_reload_map() calls is especially expensive, 1178 * even when (as in this case) the tag is 0, so do only 1179 * when the buffer has actually changed. 1180 * 1181 * If possible do not set the report/intr bit on all slots, 1182 * but only a few times per ring or when NS_REPORT is set. 1183 * 1184 * Finally, on 10G and faster drivers, it might be useful 1185 * to prefetch the next slot and txr entry. 1186 */ 1187 1188 nm_i = kring->nr_hwcur; 1189 if (nm_i != head) { /* we have new packets to send */ 1190 uint32_t pkt_len = 0, seg_idx = 0; 1191 int nic_i_start = -1, flags = 0; 1192 memset(&pi, 0, sizeof(pi)); 1193 pi.ipi_segs = txq->ift_segs; 1194 pi.ipi_qsidx = kring->ring_id; 1195 nic_i = netmap_idx_k2n(kring, nm_i); 1196 1197 __builtin_prefetch(&ring->slot[nm_i]); 1198 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1199 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1200 1201 while (nm_i != head) { 1202 struct netmap_slot *slot = &ring->slot[nm_i]; 1203 uint64_t offset = nm_get_offset(kring, slot); 1204 u_int len = slot->len; 1205 uint64_t paddr; 1206 void *addr = PNMB(na, slot, &paddr); 1207 1208 flags |= (slot->flags & NS_REPORT || 1209 nic_i == 0 || nic_i == report_frequency) ? 1210 IPI_TX_INTR : 0; 1211 1212 /* 1213 * If this is the first packet fragment, save the 1214 * index of the first NIC slot for later. 1215 */ 1216 if (nic_i_start < 0) 1217 nic_i_start = nic_i; 1218 1219 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1220 pi.ipi_segs[seg_idx].ds_len = len; 1221 if (len) { 1222 pkt_len += len; 1223 seg_idx++; 1224 } 1225 1226 if (!(slot->flags & NS_MOREFRAG)) { 1227 pi.ipi_len = pkt_len; 1228 pi.ipi_nsegs = seg_idx; 1229 pi.ipi_pidx = nic_i_start; 1230 pi.ipi_ndescs = 0; 1231 pi.ipi_flags = flags; 1232 1233 /* Prepare the NIC TX ring. */ 1234 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1235 DBG_COUNTER_INC(tx_encap); 1236 1237 /* Update transmit counters */ 1238 tx_bytes += pi.ipi_len; 1239 tx_pkts++; 1240 1241 /* Reinit per-packet info for the next one. */ 1242 flags = seg_idx = pkt_len = 0; 1243 nic_i_start = -1; 1244 } 1245 1246 /* prefetch for next round */ 1247 __builtin_prefetch(&ring->slot[nm_i + 1]); 1248 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1249 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1250 1251 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1252 1253 if (slot->flags & NS_BUF_CHANGED) { 1254 /* buffer has changed, reload map */ 1255 netmap_reload_map(na, txq->ift_buf_tag, 1256 txq->ift_sds.ifsd_map[nic_i], addr); 1257 } 1258 /* make sure changes to the buffer are synced */ 1259 bus_dmamap_sync(txq->ift_buf_tag, 1260 txq->ift_sds.ifsd_map[nic_i], 1261 BUS_DMASYNC_PREWRITE); 1262 1263 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1264 nm_i = nm_next(nm_i, lim); 1265 nic_i = nm_next(nic_i, lim); 1266 } 1267 kring->nr_hwcur = nm_i; 1268 1269 /* synchronize the NIC ring */ 1270 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1271 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1272 1273 /* (re)start the tx unit up to slot nic_i (excluded) */ 1274 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1275 } 1276 1277 /* 1278 * Second part: reclaim buffers for completed transmissions. 1279 * 1280 * If there are unclaimed buffers, attempt to reclaim them. 1281 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1282 * trigger a per-tx-queue timer to try again later. 1283 */ 1284 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1285 if (iflib_tx_credits_update(ctx, txq)) { 1286 /* some tx completed, increment avail */ 1287 nic_i = txq->ift_cidx_processed; 1288 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1289 } 1290 } 1291 1292 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1293 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1294 callout_reset_sbt_on(&txq->ift_netmap_timer, 1295 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1296 iflib_netmap_timer, txq, 1297 txq->ift_netmap_timer.c_cpu, 0); 1298 } 1299 1300 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1301 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1302 1303 return (0); 1304 } 1305 1306 /* 1307 * Reconcile kernel and user view of the receive ring. 1308 * Same as for the txsync, this routine must be efficient. 1309 * The caller guarantees a single invocations, but races against 1310 * the rest of the driver should be handled here. 1311 * 1312 * On call, kring->rhead is the first packet that userspace wants 1313 * to keep, and kring->rcur is the wakeup point. 1314 * The kernel has previously reported packets up to kring->rtail. 1315 * 1316 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1317 * of whether or not we received an interrupt. 1318 */ 1319 static int 1320 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1321 { 1322 struct netmap_adapter *na = kring->na; 1323 struct netmap_ring *ring = kring->ring; 1324 if_t ifp = na->ifp; 1325 uint32_t nm_i; /* index into the netmap ring */ 1326 uint32_t nic_i; /* index into the NIC ring */ 1327 u_int n; 1328 u_int const lim = kring->nkr_num_slots - 1; 1329 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1330 int i = 0, rx_bytes = 0, rx_pkts = 0; 1331 1332 if_ctx_t ctx = if_getsoftc(ifp); 1333 if_shared_ctx_t sctx = ctx->ifc_sctx; 1334 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1335 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1336 iflib_fl_t fl = &rxq->ifr_fl[0]; 1337 struct if_rxd_info ri; 1338 qidx_t *cidxp; 1339 1340 /* 1341 * netmap only uses free list 0, to avoid out of order consumption 1342 * of receive buffers 1343 */ 1344 1345 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1346 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1347 1348 /* 1349 * First part: import newly received packets. 1350 * 1351 * nm_i is the index of the next free slot in the netmap ring, 1352 * nic_i is the index of the next received packet in the NIC ring 1353 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1354 * differ in case if_init() has been called while 1355 * in netmap mode. For the receive ring we have 1356 * 1357 * nic_i = fl->ifl_cidx; 1358 * nm_i = kring->nr_hwtail (previous) 1359 * and 1360 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1361 * 1362 * fl->ifl_cidx is set to 0 on a ring reinit 1363 */ 1364 if (netmap_no_pendintr || force_update) { 1365 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1366 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1367 int crclen = iflib_crcstrip ? 0 : 4; 1368 int error, avail; 1369 1370 /* 1371 * For the free list consumer index, we use the same 1372 * logic as in iflib_rxeof(). 1373 */ 1374 if (have_rxcq) 1375 cidxp = &rxq->ifr_cq_cidx; 1376 else 1377 cidxp = &fl->ifl_cidx; 1378 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1379 rxq->ifr_id, *cidxp, USHRT_MAX); 1380 1381 nic_i = fl->ifl_cidx; 1382 nm_i = netmap_idx_n2k(kring, nic_i); 1383 MPASS(nm_i == kring->nr_hwtail); 1384 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1385 memset(&ri, 0, sizeof(ri)); 1386 ri.iri_frags = rxq->ifr_frags; 1387 ri.iri_qsidx = kring->ring_id; 1388 ri.iri_ifp = ctx->ifc_ifp; 1389 ri.iri_cidx = *cidxp; 1390 1391 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1392 for (i = 0; i < ri.iri_nfrags; i++) { 1393 if (error) { 1394 ring->slot[nm_i].len = 0; 1395 ring->slot[nm_i].flags = 0; 1396 } else { 1397 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1398 if (i == (ri.iri_nfrags - 1)) { 1399 ring->slot[nm_i].len -= crclen; 1400 ring->slot[nm_i].flags = 0; 1401 1402 /* Update receive counters */ 1403 rx_bytes += ri.iri_len; 1404 rx_pkts++; 1405 } else 1406 ring->slot[nm_i].flags = NS_MOREFRAG; 1407 } 1408 1409 bus_dmamap_sync(fl->ifl_buf_tag, 1410 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1411 nm_i = nm_next(nm_i, lim); 1412 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1413 } 1414 1415 if (have_rxcq) { 1416 *cidxp = ri.iri_cidx; 1417 while (*cidxp >= scctx->isc_nrxd[0]) 1418 *cidxp -= scctx->isc_nrxd[0]; 1419 } 1420 1421 } 1422 if (n) { /* update the state variables */ 1423 if (netmap_no_pendintr && !force_update) { 1424 /* diagnostics */ 1425 iflib_rx_miss++; 1426 iflib_rx_miss_bufs += n; 1427 } 1428 kring->nr_hwtail = nm_i; 1429 } 1430 kring->nr_kflags &= ~NKR_PENDINTR; 1431 } 1432 /* 1433 * Second part: skip past packets that userspace has released. 1434 * (kring->nr_hwcur to head excluded), 1435 * and make the buffers available for reception. 1436 * As usual nm_i is the index in the netmap ring, 1437 * nic_i is the index in the NIC ring, and 1438 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1439 */ 1440 netmap_fl_refill(rxq, kring, false); 1441 1442 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1443 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1444 1445 return (0); 1446 } 1447 1448 static void 1449 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1450 { 1451 if_ctx_t ctx = if_getsoftc(na->ifp); 1452 1453 CTX_LOCK(ctx); 1454 if (onoff) { 1455 IFDI_INTR_ENABLE(ctx); 1456 } else { 1457 IFDI_INTR_DISABLE(ctx); 1458 } 1459 CTX_UNLOCK(ctx); 1460 } 1461 1462 static int 1463 iflib_netmap_attach(if_ctx_t ctx) 1464 { 1465 struct netmap_adapter na; 1466 1467 bzero(&na, sizeof(na)); 1468 1469 na.ifp = ctx->ifc_ifp; 1470 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1471 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1472 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1473 1474 na.num_tx_desc = iflib_num_tx_descs(ctx); 1475 na.num_rx_desc = iflib_num_rx_descs(ctx); 1476 na.nm_txsync = iflib_netmap_txsync; 1477 na.nm_rxsync = iflib_netmap_rxsync; 1478 na.nm_register = iflib_netmap_register; 1479 na.nm_intr = iflib_netmap_intr; 1480 na.nm_config = iflib_netmap_config; 1481 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1482 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1483 return (netmap_attach(&na)); 1484 } 1485 1486 static int 1487 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1488 { 1489 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1490 struct netmap_slot *slot; 1491 1492 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1493 if (slot == NULL) 1494 return (0); 1495 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1496 /* 1497 * In netmap mode, set the map for the packet buffer. 1498 * NOTE: Some drivers (not this one) also need to set 1499 * the physical buffer address in the NIC ring. 1500 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1501 * netmap slot index, si 1502 */ 1503 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1504 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1505 NMB(na, slot + si)); 1506 } 1507 return (1); 1508 } 1509 1510 static int 1511 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1512 { 1513 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1514 struct netmap_kring *kring; 1515 struct netmap_slot *slot; 1516 1517 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1518 if (slot == NULL) 1519 return (0); 1520 kring = na->rx_rings[rxq->ifr_id]; 1521 netmap_fl_refill(rxq, kring, true); 1522 return (1); 1523 } 1524 1525 static void 1526 iflib_netmap_timer(void *arg) 1527 { 1528 iflib_txq_t txq = arg; 1529 if_ctx_t ctx = txq->ift_ctx; 1530 1531 /* 1532 * Wake up the netmap application, to give it a chance to 1533 * call txsync and reclaim more completed TX buffers. 1534 */ 1535 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1536 } 1537 1538 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1539 1540 #else 1541 #define iflib_netmap_txq_init(ctx, txq) (0) 1542 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1543 #define iflib_netmap_detach(ifp) 1544 #define netmap_enable_all_rings(ifp) 1545 #define netmap_disable_all_rings(ifp) 1546 1547 #define iflib_netmap_attach(ctx) (0) 1548 #define netmap_rx_irq(ifp, qid, budget) (0) 1549 #endif 1550 1551 #if defined(__i386__) || defined(__amd64__) 1552 static __inline void 1553 prefetch(void *x) 1554 { 1555 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1556 } 1557 1558 static __inline void 1559 prefetch2cachelines(void *x) 1560 { 1561 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1562 #if (CACHE_LINE_SIZE < 128) 1563 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x) + CACHE_LINE_SIZE / (sizeof(unsigned long))))); 1564 #endif 1565 } 1566 #else 1567 static __inline void 1568 prefetch(void *x) 1569 { 1570 } 1571 1572 static __inline void 1573 prefetch2cachelines(void *x) 1574 { 1575 } 1576 #endif 1577 1578 static void 1579 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1580 { 1581 iflib_fl_t fl; 1582 1583 fl = &rxq->ifr_fl[flid]; 1584 iru->iru_paddrs = fl->ifl_bus_addrs; 1585 iru->iru_idxs = fl->ifl_rxd_idxs; 1586 iru->iru_qsidx = rxq->ifr_id; 1587 iru->iru_buf_size = fl->ifl_buf_size; 1588 iru->iru_flidx = fl->ifl_id; 1589 } 1590 1591 static void 1592 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1593 { 1594 if (err) 1595 return; 1596 *(bus_addr_t *) arg = segs[0].ds_addr; 1597 } 1598 1599 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1600 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1601 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1602 1603 int 1604 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1605 { 1606 int err; 1607 device_t dev = ctx->ifc_dev; 1608 bus_addr_t lowaddr; 1609 1610 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1611 1612 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1613 align, 0, /* alignment, bounds */ 1614 lowaddr, /* lowaddr */ 1615 BUS_SPACE_MAXADDR, /* highaddr */ 1616 NULL, NULL, /* filter, filterarg */ 1617 size, /* maxsize */ 1618 1, /* nsegments */ 1619 size, /* maxsegsize */ 1620 BUS_DMA_ALLOCNOW, /* flags */ 1621 NULL, /* lockfunc */ 1622 NULL, /* lockarg */ 1623 &dma->idi_tag); 1624 if (err) { 1625 device_printf(dev, 1626 "%s: bus_dma_tag_create failed: %d (size=%d, align=%d)\n", 1627 __func__, err, size, align); 1628 goto fail_0; 1629 } 1630 1631 err = bus_dmamem_alloc(dma->idi_tag, (void **)&dma->idi_vaddr, 1632 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1633 if (err) { 1634 device_printf(dev, 1635 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1636 __func__, (uintmax_t)size, err); 1637 goto fail_1; 1638 } 1639 1640 dma->idi_paddr = IF_BAD_DMA; 1641 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1642 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1643 if (err || dma->idi_paddr == IF_BAD_DMA) { 1644 device_printf(dev, 1645 "%s: bus_dmamap_load failed: %d\n", 1646 __func__, err); 1647 goto fail_2; 1648 } 1649 1650 dma->idi_size = size; 1651 return (0); 1652 1653 fail_2: 1654 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1655 fail_1: 1656 bus_dma_tag_destroy(dma->idi_tag); 1657 fail_0: 1658 dma->idi_tag = NULL; 1659 1660 return (err); 1661 } 1662 1663 int 1664 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1665 { 1666 if_shared_ctx_t sctx = ctx->ifc_sctx; 1667 1668 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1669 1670 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1671 } 1672 1673 int 1674 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1675 { 1676 int i, err; 1677 iflib_dma_info_t *dmaiter; 1678 1679 dmaiter = dmalist; 1680 for (i = 0; i < count; i++, dmaiter++) { 1681 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1682 break; 1683 } 1684 if (err) 1685 iflib_dma_free_multi(dmalist, i); 1686 return (err); 1687 } 1688 1689 void 1690 iflib_dma_free(iflib_dma_info_t dma) 1691 { 1692 if (dma->idi_tag == NULL) 1693 return; 1694 if (dma->idi_paddr != IF_BAD_DMA) { 1695 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1696 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1697 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1698 dma->idi_paddr = IF_BAD_DMA; 1699 } 1700 if (dma->idi_vaddr != NULL) { 1701 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1702 dma->idi_vaddr = NULL; 1703 } 1704 bus_dma_tag_destroy(dma->idi_tag); 1705 dma->idi_tag = NULL; 1706 } 1707 1708 void 1709 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1710 { 1711 int i; 1712 iflib_dma_info_t *dmaiter = dmalist; 1713 1714 for (i = 0; i < count; i++, dmaiter++) 1715 iflib_dma_free(*dmaiter); 1716 } 1717 1718 static int 1719 iflib_fast_intr(void *arg) 1720 { 1721 iflib_filter_info_t info = arg; 1722 struct grouptask *gtask = info->ifi_task; 1723 int result; 1724 1725 DBG_COUNTER_INC(fast_intrs); 1726 if (info->ifi_filter != NULL) { 1727 result = info->ifi_filter(info->ifi_filter_arg); 1728 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1729 return (result); 1730 } 1731 1732 GROUPTASK_ENQUEUE(gtask); 1733 return (FILTER_HANDLED); 1734 } 1735 1736 static int 1737 iflib_fast_intr_rxtx(void *arg) 1738 { 1739 iflib_filter_info_t info = arg; 1740 struct grouptask *gtask = info->ifi_task; 1741 if_ctx_t ctx; 1742 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1743 iflib_txq_t txq; 1744 void *sc; 1745 int i, cidx, result; 1746 qidx_t txqid; 1747 bool intr_enable, intr_legacy; 1748 1749 DBG_COUNTER_INC(fast_intrs); 1750 if (info->ifi_filter != NULL) { 1751 result = info->ifi_filter(info->ifi_filter_arg); 1752 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1753 return (result); 1754 } 1755 1756 ctx = rxq->ifr_ctx; 1757 sc = ctx->ifc_softc; 1758 intr_enable = false; 1759 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1760 MPASS(rxq->ifr_ntxqirq); 1761 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1762 txqid = rxq->ifr_txqid[i]; 1763 txq = &ctx->ifc_txqs[txqid]; 1764 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1765 BUS_DMASYNC_POSTREAD); 1766 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1767 if (intr_legacy) 1768 intr_enable = true; 1769 else 1770 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1771 continue; 1772 } 1773 GROUPTASK_ENQUEUE(&txq->ift_task); 1774 } 1775 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1776 cidx = rxq->ifr_cq_cidx; 1777 else 1778 cidx = rxq->ifr_fl[0].ifl_cidx; 1779 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1780 GROUPTASK_ENQUEUE(gtask); 1781 else { 1782 if (intr_legacy) 1783 intr_enable = true; 1784 else 1785 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1786 DBG_COUNTER_INC(rx_intr_enables); 1787 } 1788 if (intr_enable) 1789 IFDI_INTR_ENABLE(ctx); 1790 return (FILTER_HANDLED); 1791 } 1792 1793 static int 1794 iflib_fast_intr_ctx(void *arg) 1795 { 1796 iflib_filter_info_t info = arg; 1797 if_ctx_t ctx = info->ifi_ctx; 1798 int result; 1799 1800 DBG_COUNTER_INC(fast_intrs); 1801 if (info->ifi_filter != NULL) { 1802 result = info->ifi_filter(info->ifi_filter_arg); 1803 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1804 return (result); 1805 } 1806 1807 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task); 1808 return (FILTER_HANDLED); 1809 } 1810 1811 static int 1812 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1813 driver_filter_t filter, driver_intr_t handler, void *arg, 1814 const char *name) 1815 { 1816 struct resource *res; 1817 void *tag = NULL; 1818 device_t dev = ctx->ifc_dev; 1819 int flags, i, rc; 1820 1821 flags = RF_ACTIVE; 1822 if (ctx->ifc_flags & IFC_LEGACY) 1823 flags |= RF_SHAREABLE; 1824 MPASS(rid < 512); 1825 i = rid; 1826 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1827 if (res == NULL) { 1828 device_printf(dev, 1829 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1830 return (ENOMEM); 1831 } 1832 irq->ii_res = res; 1833 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1834 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1835 filter, handler, arg, &tag); 1836 if (rc != 0) { 1837 device_printf(dev, 1838 "failed to setup interrupt for rid %d, name %s: %d\n", 1839 rid, name ? name : "unknown", rc); 1840 return (rc); 1841 } else if (name) 1842 bus_describe_intr(dev, res, tag, "%s", name); 1843 1844 irq->ii_tag = tag; 1845 return (0); 1846 } 1847 1848 /********************************************************************* 1849 * 1850 * Allocate DMA resources for TX buffers as well as memory for the TX 1851 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1852 * iflib_sw_tx_desc_array structure, storing all the information that 1853 * is needed to transmit a packet on the wire. This is called only 1854 * once at attach, setup is done every reset. 1855 * 1856 **********************************************************************/ 1857 static int 1858 iflib_txsd_alloc(iflib_txq_t txq) 1859 { 1860 if_ctx_t ctx = txq->ift_ctx; 1861 if_shared_ctx_t sctx = ctx->ifc_sctx; 1862 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1863 device_t dev = ctx->ifc_dev; 1864 bus_size_t tsomaxsize; 1865 bus_addr_t lowaddr; 1866 int err, nsegments, ntsosegments; 1867 bool tso; 1868 1869 nsegments = scctx->isc_tx_nsegments; 1870 ntsosegments = scctx->isc_tx_tso_segments_max; 1871 tsomaxsize = scctx->isc_tx_tso_size_max; 1872 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1873 tsomaxsize += sizeof(struct ether_vlan_header); 1874 MPASS(scctx->isc_ntxd[0] > 0); 1875 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1876 MPASS(nsegments > 0); 1877 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1878 MPASS(ntsosegments > 0); 1879 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1880 } 1881 1882 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1883 1884 /* 1885 * Set up DMA tags for TX buffers. 1886 */ 1887 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1888 1, 0, /* alignment, bounds */ 1889 lowaddr, /* lowaddr */ 1890 BUS_SPACE_MAXADDR, /* highaddr */ 1891 NULL, NULL, /* filter, filterarg */ 1892 sctx->isc_tx_maxsize, /* maxsize */ 1893 nsegments, /* nsegments */ 1894 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1895 0, /* flags */ 1896 NULL, /* lockfunc */ 1897 NULL, /* lockfuncarg */ 1898 &txq->ift_buf_tag))) { 1899 device_printf(dev, "Unable to allocate TX DMA tag: %d\n", err); 1900 device_printf(dev, "maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1901 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1902 goto fail; 1903 } 1904 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1905 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1906 1, 0, /* alignment, bounds */ 1907 lowaddr, /* lowaddr */ 1908 BUS_SPACE_MAXADDR, /* highaddr */ 1909 NULL, NULL, /* filter, filterarg */ 1910 tsomaxsize, /* maxsize */ 1911 ntsosegments, /* nsegments */ 1912 sctx->isc_tso_maxsegsize, /* maxsegsize */ 1913 0, /* flags */ 1914 NULL, /* lockfunc */ 1915 NULL, /* lockfuncarg */ 1916 &txq->ift_tso_buf_tag))) { 1917 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1918 err); 1919 goto fail; 1920 } 1921 1922 /* Allocate memory for the TX mbuf map. */ 1923 if (!(txq->ift_sds.ifsd_m = 1924 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1925 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1926 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1927 err = ENOMEM; 1928 goto fail; 1929 } 1930 if (ctx->ifc_sysctl_simple_tx) { 1931 if (!(txq->ift_sds.ifsd_m_defer = 1932 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1933 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1934 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1935 err = ENOMEM; 1936 goto fail; 1937 } 1938 } 1939 txq->ift_sds.ifsd_m_deferb = txq->ift_sds.ifsd_m_defer; 1940 /* 1941 * Create the DMA maps for TX buffers. 1942 */ 1943 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1944 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1945 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1946 device_printf(dev, 1947 "Unable to allocate TX buffer DMA map memory\n"); 1948 err = ENOMEM; 1949 goto fail; 1950 } 1951 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1952 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1953 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1954 device_printf(dev, 1955 "Unable to allocate TSO TX buffer map memory\n"); 1956 err = ENOMEM; 1957 goto fail; 1958 } 1959 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1960 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1961 &txq->ift_sds.ifsd_map[i]); 1962 if (err != 0) { 1963 device_printf(dev, "Unable to create TX DMA map\n"); 1964 goto fail; 1965 } 1966 if (!tso) 1967 continue; 1968 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1969 &txq->ift_sds.ifsd_tso_map[i]); 1970 if (err != 0) { 1971 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1972 goto fail; 1973 } 1974 } 1975 return (0); 1976 fail: 1977 /* We free all, it handles case where we are in the middle */ 1978 iflib_tx_structures_free(ctx); 1979 return (err); 1980 } 1981 1982 static void 1983 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1984 { 1985 bus_dmamap_t map; 1986 1987 if (txq->ift_sds.ifsd_map != NULL) { 1988 map = txq->ift_sds.ifsd_map[i]; 1989 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1990 bus_dmamap_unload(txq->ift_buf_tag, map); 1991 bus_dmamap_destroy(txq->ift_buf_tag, map); 1992 txq->ift_sds.ifsd_map[i] = NULL; 1993 } 1994 1995 if (txq->ift_sds.ifsd_tso_map != NULL) { 1996 map = txq->ift_sds.ifsd_tso_map[i]; 1997 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1998 BUS_DMASYNC_POSTWRITE); 1999 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 2000 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 2001 txq->ift_sds.ifsd_tso_map[i] = NULL; 2002 } 2003 } 2004 2005 static void 2006 iflib_txq_destroy(iflib_txq_t txq) 2007 { 2008 if_ctx_t ctx = txq->ift_ctx; 2009 2010 for (int i = 0; i < txq->ift_size; i++) 2011 iflib_txsd_destroy(ctx, txq, i); 2012 2013 if (txq->ift_br != NULL) { 2014 ifmp_ring_free(txq->ift_br); 2015 txq->ift_br = NULL; 2016 } 2017 2018 /* Free any mbufs stranded in the deferral ring */ 2019 if (txq->ift_drbr != NULL) { 2020 mtx_lock(&txq->ift_mtx); 2021 drbr_flush(NULL, txq->ift_drbr); 2022 mtx_unlock(&txq->ift_mtx); 2023 buf_ring_free(txq->ift_drbr, M_IFLIB); 2024 txq->ift_drbr = NULL; 2025 } 2026 if (txq->ift_drbr_deferred != NULL) { 2027 counter_u64_free(txq->ift_drbr_deferred); 2028 txq->ift_drbr_deferred = NULL; 2029 } 2030 if (txq->ift_drbr_blocked != NULL) { 2031 counter_u64_free(txq->ift_drbr_blocked); 2032 txq->ift_drbr_blocked = NULL; 2033 } 2034 if (txq->ift_drbr_remote != NULL) { 2035 counter_u64_free(txq->ift_drbr_remote); 2036 txq->ift_drbr_remote = NULL; 2037 } 2038 if (txq->ift_drbr_drops != NULL) { 2039 counter_u64_free(txq->ift_drbr_drops); 2040 txq->ift_drbr_drops = NULL; 2041 } 2042 2043 mtx_destroy(&txq->ift_mtx); 2044 2045 if (txq->ift_sds.ifsd_map != NULL) { 2046 free(txq->ift_sds.ifsd_map, M_IFLIB); 2047 txq->ift_sds.ifsd_map = NULL; 2048 } 2049 if (txq->ift_sds.ifsd_tso_map != NULL) { 2050 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 2051 txq->ift_sds.ifsd_tso_map = NULL; 2052 } 2053 if (txq->ift_sds.ifsd_m != NULL) { 2054 free(txq->ift_sds.ifsd_m, M_IFLIB); 2055 txq->ift_sds.ifsd_m = NULL; 2056 } 2057 if (txq->ift_sds.ifsd_m_defer != NULL) { 2058 free(txq->ift_sds.ifsd_m_defer, M_IFLIB); 2059 txq->ift_sds.ifsd_m_defer = NULL; 2060 } 2061 if (txq->ift_buf_tag != NULL) { 2062 bus_dma_tag_destroy(txq->ift_buf_tag); 2063 txq->ift_buf_tag = NULL; 2064 } 2065 if (txq->ift_tso_buf_tag != NULL) { 2066 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 2067 txq->ift_tso_buf_tag = NULL; 2068 } 2069 if (txq->ift_ifdi != NULL) { 2070 free(txq->ift_ifdi, M_IFLIB); 2071 } 2072 } 2073 2074 static void 2075 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 2076 { 2077 struct mbuf *m; 2078 2079 m = IFLIB_GET_MBUF(txq->ift_sds.ifsd_m[i]); 2080 if (m == NULL) 2081 return; 2082 2083 if (txq->ift_sds.ifsd_map != NULL) { 2084 bus_dmamap_sync(txq->ift_buf_tag, 2085 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 2086 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 2087 } 2088 if (txq->ift_sds.ifsd_tso_map != NULL) { 2089 bus_dmamap_sync(txq->ift_tso_buf_tag, 2090 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 2091 bus_dmamap_unload(txq->ift_tso_buf_tag, 2092 txq->ift_sds.ifsd_tso_map[i]); 2093 } 2094 txq->ift_sds.ifsd_m[i] = NULL; 2095 m_freem(m); 2096 DBG_COUNTER_INC(tx_frees); 2097 } 2098 2099 static int 2100 iflib_txq_setup(iflib_txq_t txq) 2101 { 2102 if_ctx_t ctx = txq->ift_ctx; 2103 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2104 if_shared_ctx_t sctx = ctx->ifc_sctx; 2105 iflib_dma_info_t di; 2106 int i; 2107 2108 /* XXX make configurable */ 2109 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 2110 2111 /* Reset indices */ 2112 txq->ift_cidx_processed = 0; 2113 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 2114 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 2115 txq->ift_pad = scctx->isc_tx_pad; 2116 2117 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 2118 bzero((void *)di->idi_vaddr, di->idi_size); 2119 2120 IFDI_TXQ_SETUP(ctx, txq->ift_id); 2121 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 2122 bus_dmamap_sync(di->idi_tag, di->idi_map, 2123 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2124 return (0); 2125 } 2126 2127 /********************************************************************* 2128 * 2129 * Allocate DMA resources for RX buffers as well as memory for the RX 2130 * mbuf map, direct RX cluster pointer map and RX cluster bus address 2131 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 2132 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 2133 * Since we use use one entry in iflib_sw_rx_desc_array per received 2134 * packet, the maximum number of entries we'll need is equal to the 2135 * number of hardware receive descriptors that we've allocated. 2136 * 2137 **********************************************************************/ 2138 static int 2139 iflib_rxsd_alloc(iflib_rxq_t rxq) 2140 { 2141 if_ctx_t ctx = rxq->ifr_ctx; 2142 if_shared_ctx_t sctx = ctx->ifc_sctx; 2143 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2144 device_t dev = ctx->ifc_dev; 2145 iflib_fl_t fl; 2146 bus_addr_t lowaddr; 2147 int err; 2148 2149 MPASS(scctx->isc_nrxd[0] > 0); 2150 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 2151 2152 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 2153 2154 fl = rxq->ifr_fl; 2155 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 2156 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 2157 /* Set up DMA tag for RX buffers. */ 2158 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 2159 1, 0, /* alignment, bounds */ 2160 lowaddr, /* lowaddr */ 2161 BUS_SPACE_MAXADDR, /* highaddr */ 2162 NULL, NULL, /* filter, filterarg */ 2163 sctx->isc_rx_maxsize, /* maxsize */ 2164 sctx->isc_rx_nsegments, /* nsegments */ 2165 sctx->isc_rx_maxsegsize, /* maxsegsize */ 2166 0, /* flags */ 2167 NULL, /* lockfunc */ 2168 NULL, /* lockarg */ 2169 &fl->ifl_buf_tag); 2170 if (err) { 2171 device_printf(dev, 2172 "Unable to allocate RX DMA tag: %d\n", err); 2173 goto fail; 2174 } 2175 2176 /* Allocate memory for the RX mbuf map. */ 2177 if (!(fl->ifl_sds.ifsd_m = 2178 (struct mbuf **) malloc(sizeof(struct mbuf *) * 2179 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2180 device_printf(dev, 2181 "Unable to allocate RX mbuf map memory\n"); 2182 err = ENOMEM; 2183 goto fail; 2184 } 2185 2186 /* Allocate memory for the direct RX cluster pointer map. */ 2187 if (!(fl->ifl_sds.ifsd_cl = 2188 (caddr_t *) malloc(sizeof(caddr_t) * 2189 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2190 device_printf(dev, 2191 "Unable to allocate RX cluster map memory\n"); 2192 err = ENOMEM; 2193 goto fail; 2194 } 2195 2196 /* Allocate memory for the RX cluster bus address map. */ 2197 if (!(fl->ifl_sds.ifsd_ba = 2198 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 2199 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2200 device_printf(dev, 2201 "Unable to allocate RX bus address map memory\n"); 2202 err = ENOMEM; 2203 goto fail; 2204 } 2205 2206 /* 2207 * Create the DMA maps for RX buffers. 2208 */ 2209 if (!(fl->ifl_sds.ifsd_map = 2210 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2211 device_printf(dev, 2212 "Unable to allocate RX buffer DMA map memory\n"); 2213 err = ENOMEM; 2214 goto fail; 2215 } 2216 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2217 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2218 &fl->ifl_sds.ifsd_map[i]); 2219 if (err != 0) { 2220 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2221 goto fail; 2222 } 2223 } 2224 } 2225 return (0); 2226 2227 fail: 2228 iflib_rx_structures_free(ctx); 2229 return (err); 2230 } 2231 2232 /* 2233 * Internal service routines 2234 */ 2235 2236 struct rxq_refill_cb_arg { 2237 int error; 2238 bus_dma_segment_t seg; 2239 int nseg; 2240 }; 2241 2242 static void 2243 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2244 { 2245 struct rxq_refill_cb_arg *cb_arg = arg; 2246 2247 cb_arg->error = error; 2248 cb_arg->seg = segs[0]; 2249 cb_arg->nseg = nseg; 2250 } 2251 2252 /** 2253 * iflib_fl_refill - refill an rxq free-buffer list 2254 * @ctx: the iflib context 2255 * @fl: the free list to refill 2256 * @count: the number of new buffers to allocate 2257 * 2258 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2259 * The caller must assure that @count does not exceed the queue's capacity 2260 * minus one (since we always leave a descriptor unavailable). 2261 */ 2262 static uint8_t 2263 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2264 { 2265 struct if_rxd_update iru; 2266 struct rxq_refill_cb_arg cb_arg; 2267 struct mbuf *m; 2268 caddr_t cl, *sd_cl; 2269 struct mbuf **sd_m; 2270 bus_dmamap_t *sd_map; 2271 bus_addr_t bus_addr, *sd_ba; 2272 int err, frag_idx, i, idx, n, pidx; 2273 qidx_t credits; 2274 2275 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2276 2277 sd_m = fl->ifl_sds.ifsd_m; 2278 sd_map = fl->ifl_sds.ifsd_map; 2279 sd_cl = fl->ifl_sds.ifsd_cl; 2280 sd_ba = fl->ifl_sds.ifsd_ba; 2281 pidx = fl->ifl_pidx; 2282 idx = pidx; 2283 frag_idx = fl->ifl_fragidx; 2284 credits = fl->ifl_credits; 2285 2286 i = 0; 2287 n = count; 2288 MPASS(n > 0); 2289 MPASS(credits + n <= fl->ifl_size); 2290 2291 if (pidx < fl->ifl_cidx) 2292 MPASS(pidx + n <= fl->ifl_cidx); 2293 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2294 MPASS(fl->ifl_gen == 0); 2295 if (pidx > fl->ifl_cidx) 2296 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2297 2298 DBG_COUNTER_INC(fl_refills); 2299 if (n > 8) 2300 DBG_COUNTER_INC(fl_refills_large); 2301 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2302 while (n-- > 0) { 2303 /* 2304 * We allocate an uninitialized mbuf + cluster, mbuf is 2305 * initialized after rx. 2306 * 2307 * If the cluster is still set then we know a minimum sized 2308 * packet was received 2309 */ 2310 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2311 &frag_idx); 2312 if (frag_idx < 0) 2313 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2314 MPASS(frag_idx >= 0); 2315 if ((cl = sd_cl[frag_idx]) == NULL) { 2316 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2317 if (__predict_false(cl == NULL)) 2318 break; 2319 2320 cb_arg.error = 0; 2321 MPASS(sd_map != NULL); 2322 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2323 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2324 BUS_DMA_NOWAIT); 2325 if (__predict_false(err != 0 || cb_arg.error)) { 2326 uma_zfree(fl->ifl_zone, cl); 2327 break; 2328 } 2329 2330 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2331 sd_cl[frag_idx] = cl; 2332 #if MEMORY_LOGGING 2333 fl->ifl_cl_enqueued++; 2334 #endif 2335 } else { 2336 bus_addr = sd_ba[frag_idx]; 2337 } 2338 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2339 BUS_DMASYNC_PREREAD); 2340 2341 if (sd_m[frag_idx] == NULL) { 2342 m = m_gethdr_raw(M_NOWAIT, 0); 2343 if (__predict_false(m == NULL)) 2344 break; 2345 sd_m[frag_idx] = m; 2346 } 2347 bit_set(fl->ifl_rx_bitmap, frag_idx); 2348 #if MEMORY_LOGGING 2349 fl->ifl_m_enqueued++; 2350 #endif 2351 2352 DBG_COUNTER_INC(rx_allocs); 2353 fl->ifl_rxd_idxs[i] = frag_idx; 2354 fl->ifl_bus_addrs[i] = bus_addr; 2355 credits++; 2356 i++; 2357 MPASS(credits <= fl->ifl_size); 2358 if (++idx == fl->ifl_size) { 2359 #ifdef INVARIANTS 2360 fl->ifl_gen = 1; 2361 #endif 2362 idx = 0; 2363 } 2364 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2365 iru.iru_pidx = pidx; 2366 iru.iru_count = i; 2367 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2368 fl->ifl_pidx = idx; 2369 fl->ifl_credits = credits; 2370 pidx = idx; 2371 i = 0; 2372 } 2373 } 2374 2375 if (n < count - 1) { 2376 if (i != 0) { 2377 iru.iru_pidx = pidx; 2378 iru.iru_count = i; 2379 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2380 fl->ifl_pidx = idx; 2381 fl->ifl_credits = credits; 2382 } 2383 DBG_COUNTER_INC(rxd_flush); 2384 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2385 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2386 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2387 fl->ifl_id, fl->ifl_pidx); 2388 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2389 fl->ifl_fragidx = frag_idx + 1; 2390 if (fl->ifl_fragidx == fl->ifl_size) 2391 fl->ifl_fragidx = 0; 2392 } else { 2393 fl->ifl_fragidx = frag_idx; 2394 } 2395 } 2396 2397 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2398 } 2399 2400 static inline uint8_t 2401 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2402 { 2403 /* 2404 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2405 * This is important as it confuses most NICs. For instance, 2406 * Intel NICs have (per receive ring) RDH and RDT registers, where 2407 * RDH points to the next receive descriptor to be used by the NIC, 2408 * and RDT for the next receive descriptor to be published by the 2409 * driver to the NIC (RDT - 1 is thus the last valid one). 2410 * The condition RDH == RDT means no descriptors are available to 2411 * the NIC, and thus it would be ambiguous if it also meant that 2412 * all the descriptors are available to the NIC. 2413 */ 2414 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2415 #ifdef INVARIANTS 2416 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2417 #endif 2418 2419 MPASS(fl->ifl_credits <= fl->ifl_size); 2420 MPASS(reclaimable == delta); 2421 2422 if (reclaimable > 0) 2423 return (iflib_fl_refill(ctx, fl, reclaimable)); 2424 return (0); 2425 } 2426 2427 uint8_t 2428 iflib_in_detach(if_ctx_t ctx) 2429 { 2430 bool in_detach; 2431 2432 STATE_LOCK(ctx); 2433 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2434 STATE_UNLOCK(ctx); 2435 return (in_detach); 2436 } 2437 2438 static void 2439 iflib_fl_bufs_free(iflib_fl_t fl) 2440 { 2441 iflib_dma_info_t idi = fl->ifl_ifdi; 2442 bus_dmamap_t sd_map; 2443 uint32_t i; 2444 2445 for (i = 0; i < fl->ifl_size; i++) { 2446 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2447 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2448 2449 if (*sd_cl != NULL) { 2450 sd_map = fl->ifl_sds.ifsd_map[i]; 2451 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2452 BUS_DMASYNC_POSTREAD); 2453 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2454 uma_zfree(fl->ifl_zone, *sd_cl); 2455 *sd_cl = NULL; 2456 if (*sd_m != NULL) { 2457 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2458 m_free_raw(*sd_m); 2459 *sd_m = NULL; 2460 } 2461 } else { 2462 MPASS(*sd_m == NULL); 2463 } 2464 #if MEMORY_LOGGING 2465 fl->ifl_m_dequeued++; 2466 fl->ifl_cl_dequeued++; 2467 #endif 2468 } 2469 #ifdef INVARIANTS 2470 for (i = 0; i < fl->ifl_size; i++) { 2471 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2472 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2473 } 2474 #endif 2475 /* 2476 * Reset free list values 2477 */ 2478 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2479 bzero(idi->idi_vaddr, idi->idi_size); 2480 } 2481 2482 /********************************************************************* 2483 * 2484 * Initialize a free list and its buffers. 2485 * 2486 **********************************************************************/ 2487 static int 2488 iflib_fl_setup(iflib_fl_t fl) 2489 { 2490 iflib_rxq_t rxq = fl->ifl_rxq; 2491 if_ctx_t ctx = rxq->ifr_ctx; 2492 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2493 int qidx; 2494 2495 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2496 /* 2497 * Free current RX buffer structs and their mbufs 2498 */ 2499 iflib_fl_bufs_free(fl); 2500 /* Now replenish the mbufs */ 2501 MPASS(fl->ifl_credits == 0); 2502 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2503 if (scctx->isc_rxd_buf_size[qidx] != 0) 2504 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2505 else 2506 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2507 /* 2508 * ifl_buf_size may be a driver-supplied value, so pull it up 2509 * to the selected mbuf size. 2510 */ 2511 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2512 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2513 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2514 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2515 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2516 2517 /* 2518 * Avoid pre-allocating zillions of clusters to an idle card 2519 * potentially speeding up attach. In any case make sure 2520 * to leave a descriptor unavailable. See the comment in 2521 * iflib_fl_refill_all(). 2522 */ 2523 MPASS(fl->ifl_size > 0); 2524 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2525 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2526 return (ENOBUFS); 2527 /* 2528 * handle failure 2529 */ 2530 MPASS(rxq != NULL); 2531 MPASS(fl->ifl_ifdi != NULL); 2532 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2533 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2534 return (0); 2535 } 2536 2537 /********************************************************************* 2538 * 2539 * Free receive ring data structures 2540 * 2541 **********************************************************************/ 2542 static void 2543 iflib_rx_sds_free(iflib_rxq_t rxq) 2544 { 2545 iflib_fl_t fl; 2546 int i, j; 2547 2548 if (rxq->ifr_fl != NULL) { 2549 for (i = 0; i < rxq->ifr_nfl; i++) { 2550 fl = &rxq->ifr_fl[i]; 2551 if (fl->ifl_buf_tag != NULL) { 2552 if (fl->ifl_sds.ifsd_map != NULL) { 2553 for (j = 0; j < fl->ifl_size; j++) { 2554 bus_dmamap_sync( 2555 fl->ifl_buf_tag, 2556 fl->ifl_sds.ifsd_map[j], 2557 BUS_DMASYNC_POSTREAD); 2558 bus_dmamap_unload( 2559 fl->ifl_buf_tag, 2560 fl->ifl_sds.ifsd_map[j]); 2561 bus_dmamap_destroy( 2562 fl->ifl_buf_tag, 2563 fl->ifl_sds.ifsd_map[j]); 2564 } 2565 } 2566 bus_dma_tag_destroy(fl->ifl_buf_tag); 2567 fl->ifl_buf_tag = NULL; 2568 } 2569 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2570 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2571 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2572 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2573 free(fl->ifl_rx_bitmap, M_IFLIB); 2574 fl->ifl_sds.ifsd_m = NULL; 2575 fl->ifl_sds.ifsd_cl = NULL; 2576 fl->ifl_sds.ifsd_ba = NULL; 2577 fl->ifl_sds.ifsd_map = NULL; 2578 fl->ifl_rx_bitmap = NULL; 2579 } 2580 free(rxq->ifr_fl, M_IFLIB); 2581 rxq->ifr_fl = NULL; 2582 free(rxq->ifr_ifdi, M_IFLIB); 2583 rxq->ifr_ifdi = NULL; 2584 rxq->ifr_cq_cidx = 0; 2585 } 2586 } 2587 2588 /* 2589 * Serialize admission changes and publication of the legacy driver flags. 2590 * Opening admission publishes queue setup to lockless readers before device 2591 * interrupts are enabled. Closing it does not wait for existing users: 2592 * queue locks, task drains and the driver stop contract still apply. 2593 */ 2594 static void 2595 iflib_set_running(if_ctx_t ctx, bool running) 2596 { 2597 2598 mtx_assert(&ctx->ifc_state_mtx, MA_OWNED); 2599 if (running) { 2600 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, 2601 IFF_DRV_OACTIVE); 2602 atomic_store_rel_int(&ctx->ifc_running, 1); 2603 } else { 2604 atomic_store_rel_int(&ctx->ifc_running, 0); 2605 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, 2606 IFF_DRV_RUNNING); 2607 } 2608 } 2609 2610 /* 2611 * Timer routine 2612 */ 2613 static void 2614 iflib_timer(void *arg) 2615 { 2616 iflib_txq_t txq = arg; 2617 if_ctx_t ctx = txq->ift_ctx; 2618 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2619 uint64_t this_tick = ticks; 2620 2621 if (!iflib_is_running(ctx)) 2622 return; 2623 2624 /* 2625 * Check on the state of the TX queue(s); this can be done 2626 * without the lock: the counters the check reads are only 2627 * advanced by the queue's tx task and a stale read just 2628 * delays the verdict by one timer period. 2629 */ 2630 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2631 qidx_t in_use, outstanding; 2632 bool demand, frozen; 2633 2634 txq->ift_last_timer_tick = this_tick; 2635 IFDI_TIMER(ctx, txq->ift_id); 2636 2637 /* 2638 * Descriptors the hardware has not reported as 2639 * completed: neither harvested as credits 2640 * (ift_processed) nor reclaimed (ift_cleaned accounts 2641 * the difference to ift_in_use). The tail whose 2642 * report-status request is still deferred is never 2643 * reported and must not count. 2644 */ 2645 in_use = txq->ift_in_use; 2646 outstanding = in_use - 2647 (qidx_t)(txq->ift_processed - txq->ift_cleaned); 2648 2649 /* 2650 * The queue is frozen while it has descriptors the 2651 * hardware has not reported as completed and none 2652 * were reclaimed over the period; the link must be 2653 * up, with no pause frames and no pending doorbell 2654 * (the laggard check below rings it). 2655 * 2656 * Being frozen is not a fault - the hardware may defer 2657 * marking descriptors as completed indefinitely, and 2658 * 8254x hardware does so for a quiet queue. Continue 2659 * arming only while demand persists: the outstanding 2660 * count grows, the software ring is stalled, or the 2661 * hardware ring has reached iflib's backpressure 2662 * threshold. The last condition covers simple-TX, which 2663 * does not use the software ring. This also prevents one 2664 * mixed lockless counter sample from arming a quiet queue 2665 * until the verdict. Act only once it has stayed frozen 2666 * under demand for 2667 * net.iflib.tx_watchdog_periods consecutive periods. 2668 */ 2669 frozen = outstanding > txq->ift_rs_pending && 2670 txq->ift_processed == txq->ift_processed_prev && 2671 txq->ift_db_pending == 0 && 2672 sctx->isc_pause_frames == 0 && 2673 ctx->ifc_link_state == LINK_STATE_UP; 2674 demand = outstanding > txq->ift_outstanding_prev || 2675 ifmp_ring_is_stalled(txq->ift_br) || 2676 in_use + MAX_TX_DESC(ctx) >= txq->ift_size - txq->ift_pad; 2677 if (!frozen || !demand) 2678 txq->ift_wdog_armed = 0; 2679 else { 2680 if (txq->ift_wdog_armed < UINT16_MAX) 2681 txq->ift_wdog_armed++; 2682 } 2683 2684 /* 2685 * Frozen long enough: ask the hardware. Completions 2686 * ready but unharvested for this long mean the 2687 * completion interrupt went missing - kick the 2688 * queue's task. Nothing ready while demand persisted 2689 * means it is hung. 2690 */ 2691 if (iflib_tx_watchdog_periods > 0 && 2692 txq->ift_wdog_armed >= iflib_tx_watchdog_periods) { 2693 bus_dmamap_sync(txq->ift_ifdi->idi_tag, 2694 txq->ift_ifdi->idi_map, BUS_DMASYNC_POSTREAD); 2695 if (ctx->isc_txd_credits_update(ctx->ifc_softc, 2696 txq->ift_id, false) == 0) { 2697 device_printf(ctx->ifc_dev, 2698 "Watchdog timeout (TX: %d desc " 2699 "avail: %d pidx: %d) -- resetting\n", 2700 txq->ift_id, TXQ_AVAIL(txq), 2701 txq->ift_pidx); 2702 STATE_LOCK(ctx); 2703 iflib_set_running(ctx, false); 2704 ctx->ifc_flags |= 2705 (IFC_DO_WATCHDOG | IFC_DO_RESET); 2706 iflib_admin_intr_deferred(ctx); 2707 STATE_UNLOCK(ctx); 2708 return; 2709 } 2710 GROUPTASK_ENQUEUE(&txq->ift_task); 2711 } 2712 txq->ift_outstanding_prev = outstanding; 2713 txq->ift_processed_prev = txq->ift_processed; 2714 } 2715 /* Handle any laggards */ 2716 if (txq->ift_db_pending || 2717 (txq->ift_drbr != NULL && 2718 (!if_altq_is_enabled(ctx->ifc_ifp) || txq->ift_id == 0) && 2719 !drbr_empty(ctx->ifc_ifp, txq->ift_drbr))) 2720 GROUPTASK_ENQUEUE(&txq->ift_task); 2721 2722 sctx->isc_pause_frames = 0; 2723 if (iflib_is_running(ctx)) 2724 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2725 txq, txq->ift_timer.c_cpu); 2726 } 2727 2728 static uint16_t 2729 iflib_get_mbuf_size_for(unsigned int size) 2730 { 2731 2732 if (size <= MCLBYTES) 2733 return (MCLBYTES); 2734 else 2735 return (MJUMPAGESIZE); 2736 } 2737 2738 static void 2739 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2740 { 2741 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2742 2743 /* 2744 * XXX don't set the max_frame_size to larger 2745 * than the hardware can handle 2746 */ 2747 ctx->ifc_rx_mbuf_sz = 2748 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2749 } 2750 2751 uint32_t 2752 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2753 { 2754 2755 return (ctx->ifc_rx_mbuf_sz); 2756 } 2757 2758 static void 2759 iflib_init_locked(if_ctx_t ctx) 2760 { 2761 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2762 if_t ifp = ctx->ifc_ifp; 2763 iflib_fl_t fl; 2764 iflib_txq_t txq; 2765 iflib_rxq_t rxq; 2766 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2767 bool init_failed; 2768 2769 sx_assert(&ctx->ifc_ctx_sx, SA_XLOCKED); 2770 /* Configuration changes made during suspend take effect on resume. */ 2771 if (ctx->ifc_pm_state != IFLIB_PM_ACTIVE) 2772 return; 2773 KASSERT(ctx->ifc_datapath_state == IFLIB_DP_STOPPED, 2774 ("iflib init from datapath state %d", ctx->ifc_datapath_state)); 2775 ctx->ifc_datapath_state = IFLIB_DP_STARTING; 2776 2777 STATE_LOCK(ctx); 2778 iflib_set_running(ctx, false); 2779 STATE_UNLOCK(ctx); 2780 IFDI_INTR_DISABLE(ctx); 2781 2782 /* 2783 * See iflib_stop(). Useful in case iflib_init_locked() is 2784 * called without first calling iflib_stop(). 2785 */ 2786 netmap_disable_all_rings(ifp); 2787 2788 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2789 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2790 /* Set hardware offload abilities */ 2791 if_clearhwassist(ifp); 2792 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2793 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2794 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2795 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2796 if (if_getcapenable(ifp) & IFCAP_TSO4) 2797 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2798 if (if_getcapenable(ifp) & IFCAP_TSO6) 2799 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2800 2801 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 2802 CALLOUT_LOCK(txq); 2803 callout_stop(&txq->ift_timer); 2804 #ifdef DEV_NETMAP 2805 callout_stop(&txq->ift_netmap_timer); 2806 #endif /* DEV_NETMAP */ 2807 CALLOUT_UNLOCK(txq); 2808 (void)iflib_netmap_txq_init(ctx, txq); 2809 } 2810 /* 2811 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2812 * that drivers can use the value when setting up the hardware receive 2813 * buffers. 2814 */ 2815 iflib_calc_rx_mbuf_sz(ctx); 2816 2817 #ifdef INVARIANTS 2818 i = if_getdrvflags(ifp); 2819 #endif 2820 STATE_LOCK(ctx); 2821 ctx->ifc_flags &= ~IFC_INIT_FAILED; 2822 STATE_UNLOCK(ctx); 2823 IFDI_INIT(ctx); 2824 MPASS(if_getdrvflags(ifp) == i); 2825 STATE_LOCK(ctx); 2826 init_failed = (ctx->ifc_flags & IFC_INIT_FAILED) != 0; 2827 STATE_UNLOCK(ctx); 2828 if (init_failed) { 2829 /* 2830 * IFDI_INIT failed, but that alone does not prove that the 2831 * driver stopped every queue or fenced DMA. Force the next 2832 * lifecycle transition through the driver's stop method. 2833 */ 2834 ctx->ifc_datapath_state = IFLIB_DP_FAILED; 2835 return; 2836 } 2837 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 2838 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2839 /* This rxq is in netmap mode. Skip normal init. */ 2840 continue; 2841 } 2842 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2843 if (iflib_fl_setup(fl)) { 2844 device_printf(ctx->ifc_dev, 2845 "setting up free list %d failed - " 2846 "check cluster settings\n", j); 2847 /* 2848 * IFDI_INIT has started the hardware. Stop it before 2849 * releasing partially populated receive mappings. 2850 */ 2851 iflib_init_failed(ctx); 2852 iflib_stop(ctx); 2853 return; 2854 } 2855 } 2856 } 2857 /* Open every TX queue before publishing admission to transmitters. */ 2858 if (ctx->ifc_sysctl_simple_tx) { 2859 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; 2860 i++, txq++) 2861 atomic_clear_rel_int(&txq->ift_producers, 2862 IFLIB_TXQ_QUIESCING); 2863 } 2864 STATE_LOCK(ctx); 2865 iflib_set_running(ctx, true); 2866 STATE_UNLOCK(ctx); 2867 IFDI_INTR_ENABLE(ctx); 2868 txq = ctx->ifc_txqs; 2869 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) 2870 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2871 txq->ift_timer.c_cpu); 2872 2873 /* Re-enable txsync/rxsync. */ 2874 netmap_enable_all_rings(ifp); 2875 ctx->ifc_datapath_state = IFLIB_DP_RUNNING; 2876 } 2877 2878 static int 2879 iflib_media_change(if_t ifp) 2880 { 2881 if_ctx_t ctx = if_getsoftc(ifp); 2882 bool restart; 2883 int err; 2884 2885 CTX_LOCK(ctx); 2886 if (ctx->ifc_pm_state != IFLIB_PM_ACTIVE) { 2887 CTX_UNLOCK(ctx); 2888 return (EBUSY); 2889 } 2890 restart = (if_getflags(ifp) & IFF_UP) != 0 || 2891 ctx->ifc_datapath_state == IFLIB_DP_RUNNING; 2892 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0 && restart) 2893 iflib_if_init_locked(ctx); 2894 CTX_UNLOCK(ctx); 2895 return (err); 2896 } 2897 2898 static void 2899 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2900 { 2901 if_ctx_t ctx = if_getsoftc(ifp); 2902 2903 CTX_LOCK(ctx); 2904 if (ctx->ifc_pm_state != IFLIB_PM_ACTIVE) { 2905 ifmr->ifm_status = IFM_AVALID; 2906 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 2907 CTX_UNLOCK(ctx); 2908 return; 2909 } 2910 /* 2911 * There is no need to update the admin status when it is done regularly by 2912 * _task_fn_admin(), so only do it if that's not running. That can be quite 2913 * expensive on some drivers. 2914 */ 2915 if (!iflib_admin_enabled(ctx)) { 2916 IFDI_UPDATE_ADMIN_STATUS(ctx); 2917 } 2918 IFDI_MEDIA_STATUS(ctx, ifmr); 2919 CTX_UNLOCK(ctx); 2920 } 2921 2922 static void 2923 iflib_stop(if_ctx_t ctx) 2924 { 2925 iflib_txq_t txq = ctx->ifc_txqs; 2926 iflib_rxq_t rxq = ctx->ifc_rxqs; 2927 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2928 if_shared_ctx_t sctx = ctx->ifc_sctx; 2929 iflib_dma_info_t di; 2930 iflib_fl_t fl; 2931 bool stop_hardware; 2932 int i, j; 2933 2934 sx_assert(&ctx->ifc_ctx_sx, SA_XLOCKED); 2935 KASSERT(ctx->ifc_datapath_state != IFLIB_DP_STOPPING, 2936 ("recursive iflib stop")); 2937 stop_hardware = ctx->ifc_datapath_state != IFLIB_DP_STOPPED; 2938 2939 if (ctx->ifc_sysctl_simple_tx && stop_hardware) { 2940 /* close deferral rings to new traffic */ 2941 for (i = 0; i < scctx->isc_ntxqsets; i++) { 2942 atomic_set_int(&txq[i].ift_producers, 2943 IFLIB_TXQ_QUIESCING); 2944 } 2945 } 2946 2947 /* Tell the stack that the interface is no longer active */ 2948 STATE_LOCK(ctx); 2949 iflib_set_running(ctx, false); 2950 STATE_UNLOCK(ctx); 2951 2952 if (stop_hardware) { 2953 ctx->ifc_datapath_state = IFLIB_DP_STOPPING; 2954 IFDI_INTR_DISABLE(ctx); 2955 DELAY(1000); 2956 IFDI_STOP(ctx); 2957 DELAY(1000); 2958 ctx->ifc_datapath_state = IFLIB_DP_STOPPED; 2959 } 2960 2961 /* 2962 * Stop any pending txsync/rxsync and prevent new ones 2963 * form starting. Processes blocked in poll() will get 2964 * POLLERR. 2965 */ 2966 netmap_disable_all_rings(ctx->ifc_ifp); 2967 2968 iflib_debug_reset(); 2969 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2970 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2971 /* make sure all transmitters have completed before proceeding XXX */ 2972 2973 CALLOUT_LOCK(txq); 2974 callout_stop(&txq->ift_timer); 2975 #ifdef DEV_NETMAP 2976 callout_stop(&txq->ift_netmap_timer); 2977 #endif /* DEV_NETMAP */ 2978 CALLOUT_UNLOCK(txq); 2979 2980 /* clean any enqueued buffers */ 2981 if (!ctx->ifc_sysctl_simple_tx) { 2982 iflib_ifmp_purge(txq); 2983 } else { 2984 mtx_lock(&txq->ift_mtx); 2985 drbr_flush(ctx->ifc_ifp, txq->ift_drbr); 2986 mtx_unlock(&txq->ift_mtx); 2987 } 2988 /* Free any existing tx buffers. */ 2989 for (j = 0; j < txq->ift_size; j++) { 2990 iflib_txsd_free(ctx, txq, j); 2991 } 2992 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2993 txq->ift_processed_prev = 0; 2994 txq->ift_outstanding_prev = 0; 2995 txq->ift_wdog_armed = 0; 2996 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2997 txq->ift_npending = txq->ift_db_pending = 0; 2998 txq->ift_rs_pending = 0; 2999 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 3000 txq->ift_cidx = txq->ift_pidx; 3001 else 3002 txq->ift_cidx = txq->ift_pidx = 0; 3003 3004 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 3005 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 3006 txq->ift_pullups = 0; 3007 txq->ift_drbr_direct = txq->ift_drbr_stall = 0; 3008 if (ctx->ifc_sysctl_simple_tx) { 3009 counter_u64_zero(txq->ift_drbr_deferred); 3010 counter_u64_zero(txq->ift_drbr_drops); 3011 counter_u64_zero(txq->ift_drbr_blocked); 3012 counter_u64_zero(txq->ift_drbr_remote); 3013 } 3014 ifmp_ring_reset_stats(txq->ift_br); 3015 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 3016 bzero((void *)di->idi_vaddr, di->idi_size); 3017 } 3018 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 3019 if (rxq->ifr_task.gt_taskqueue != NULL) 3020 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 3021 &rxq->ifr_task.gt_task); 3022 3023 rxq->ifr_cq_cidx = 0; 3024 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 3025 bzero((void *)di->idi_vaddr, di->idi_size); 3026 /* also resets the free lists pidx/cidx */ 3027 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 3028 iflib_fl_bufs_free(fl); 3029 } 3030 } 3031 3032 static inline caddr_t 3033 calc_next_rxd(iflib_fl_t fl, int cidx) 3034 { 3035 qidx_t size; 3036 int nrxd; 3037 caddr_t start, end, cur, next; 3038 3039 nrxd = fl->ifl_size; 3040 size = fl->ifl_rxd_size; 3041 start = fl->ifl_ifdi->idi_vaddr; 3042 3043 if (__predict_false(size == 0)) 3044 return (start); 3045 cur = start + size * cidx; 3046 end = start + size * nrxd; 3047 next = CACHE_PTR_NEXT(cur); 3048 return (next < end ? next : start); 3049 } 3050 3051 static inline void 3052 prefetch_pkts(iflib_fl_t fl, int cidx) 3053 { 3054 int nextptr; 3055 int nrxd = fl->ifl_size; 3056 caddr_t next_rxd; 3057 3058 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd - 1); 3059 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 3060 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 3061 next_rxd = calc_next_rxd(fl, cidx); 3062 prefetch(next_rxd); 3063 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd - 1)]); 3064 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd - 1)]); 3065 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd - 1)]); 3066 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd - 1)]); 3067 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd - 1)]); 3068 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd - 1)]); 3069 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd - 1)]); 3070 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd - 1)]); 3071 } 3072 3073 static struct mbuf * 3074 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 3075 int *pf_rv, if_rxd_info_t ri) 3076 { 3077 bus_dmamap_t map; 3078 iflib_fl_t fl; 3079 caddr_t payload; 3080 struct mbuf *m; 3081 int flid, cidx, len, next; 3082 3083 map = NULL; 3084 flid = irf->irf_flid; 3085 cidx = irf->irf_idx; 3086 fl = &rxq->ifr_fl[flid]; 3087 sd->ifsd_fl = fl; 3088 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 3089 fl->ifl_credits--; 3090 #if MEMORY_LOGGING 3091 fl->ifl_m_dequeued++; 3092 #endif 3093 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 3094 prefetch_pkts(fl, cidx); 3095 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size - 1); 3096 prefetch(&fl->ifl_sds.ifsd_map[next]); 3097 map = fl->ifl_sds.ifsd_map[cidx]; 3098 3099 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 3100 3101 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 3102 irf->irf_len != 0) { 3103 payload = *sd->ifsd_cl; 3104 payload += ri->iri_pad; 3105 len = ri->iri_len - ri->iri_pad; 3106 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m); 3107 switch (*pf_rv) { 3108 case PFIL_DROPPED: 3109 case PFIL_CONSUMED: 3110 /* 3111 * The filter ate it. Everything is recycled. 3112 */ 3113 m = NULL; 3114 unload = 0; 3115 break; 3116 case PFIL_REALLOCED: 3117 /* 3118 * The filter copied it. Everything is recycled. 3119 * 'm' points at new mbuf. 3120 */ 3121 unload = 0; 3122 break; 3123 case PFIL_PASS: 3124 /* 3125 * Filter said it was OK, so receive like 3126 * normal 3127 */ 3128 m = fl->ifl_sds.ifsd_m[cidx]; 3129 fl->ifl_sds.ifsd_m[cidx] = NULL; 3130 break; 3131 default: 3132 MPASS(0); 3133 } 3134 } else { 3135 m = fl->ifl_sds.ifsd_m[cidx]; 3136 fl->ifl_sds.ifsd_m[cidx] = NULL; 3137 if (pf_rv != NULL) 3138 *pf_rv = PFIL_PASS; 3139 } 3140 3141 if (unload && irf->irf_len != 0) 3142 bus_dmamap_unload(fl->ifl_buf_tag, map); 3143 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size - 1); 3144 if (__predict_false(fl->ifl_cidx == 0)) 3145 fl->ifl_gen = 0; 3146 bit_clear(fl->ifl_rx_bitmap, cidx); 3147 return (m); 3148 } 3149 3150 static struct mbuf * 3151 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 3152 { 3153 struct mbuf *m, *mh, *mt; 3154 caddr_t cl; 3155 int *pf_rv_ptr, flags, i, padlen; 3156 bool consumed; 3157 3158 i = 0; 3159 mh = NULL; 3160 consumed = false; 3161 *pf_rv = PFIL_PASS; 3162 pf_rv_ptr = pf_rv; 3163 do { 3164 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 3165 pf_rv_ptr, ri); 3166 3167 MPASS(*sd->ifsd_cl != NULL); 3168 3169 /* 3170 * Exclude zero-length frags & frags from 3171 * packets the filter has consumed or dropped 3172 */ 3173 if (ri->iri_frags[i].irf_len == 0 || consumed || 3174 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 3175 if (mh == NULL) { 3176 consumed = true; 3177 pf_rv_ptr = NULL; 3178 } 3179 /* XXX we can save the cluster here, but not the mbuf */ 3180 if (m != NULL) { 3181 m_init(m, M_NOWAIT, MT_DATA, 0); 3182 m_free(m); 3183 } 3184 continue; 3185 } 3186 if (mh == NULL) { 3187 flags = M_PKTHDR | M_EXT; 3188 mh = mt = m; 3189 padlen = ri->iri_pad; 3190 } else { 3191 flags = M_EXT; 3192 mt->m_next = m; 3193 mt = m; 3194 /* assuming padding is only on the first fragment */ 3195 padlen = 0; 3196 } 3197 cl = *sd->ifsd_cl; 3198 *sd->ifsd_cl = NULL; 3199 3200 /* Can these two be made one ? */ 3201 m_init(m, M_NOWAIT, MT_DATA, flags); 3202 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 3203 /* 3204 * These must follow m_init and m_cljset 3205 */ 3206 m->m_data += padlen; 3207 ri->iri_len -= padlen; 3208 m->m_len = ri->iri_frags[i].irf_len; 3209 } while (++i < ri->iri_nfrags); 3210 3211 return (mh); 3212 } 3213 3214 /* 3215 * Process one software descriptor 3216 */ 3217 static struct mbuf * 3218 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 3219 { 3220 struct if_rxsd sd; 3221 struct mbuf *m; 3222 int pf_rv; 3223 3224 /* should I merge this back in now that the two paths are basically duplicated? */ 3225 if (ri->iri_nfrags == 1 && 3226 ri->iri_frags[0].irf_len != 0 && 3227 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 3228 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 3229 &pf_rv, ri); 3230 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 3231 return (m); 3232 if (pf_rv == PFIL_PASS) { 3233 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 3234 #ifndef __NO_STRICT_ALIGNMENT 3235 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 3236 m->m_data += 2; 3237 #endif 3238 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 3239 m->m_len = ri->iri_frags[0].irf_len; 3240 m->m_data += ri->iri_pad; 3241 ri->iri_len -= ri->iri_pad; 3242 } 3243 } else { 3244 m = assemble_segments(rxq, ri, &sd, &pf_rv); 3245 if (m == NULL) 3246 return (NULL); 3247 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 3248 return (m); 3249 } 3250 m->m_pkthdr.len = ri->iri_len; 3251 m->m_pkthdr.rcvif = ri->iri_ifp; 3252 m->m_flags |= ri->iri_flags & IFLIB_IRI_VALID_FLAGS; 3253 m->m_pkthdr.ether_vtag = ri->iri_vtag; 3254 m->m_pkthdr.flowid = ri->iri_flowid; 3255 #ifdef NUMA 3256 m->m_pkthdr.numa_domain = if_getnumadomain(ri->iri_ifp); 3257 #endif 3258 M_HASHTYPE_SET(m, ri->iri_rsstype); 3259 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 3260 m->m_pkthdr.csum_data = ri->iri_csum_data; 3261 m->m_pkthdr.rcv_tstmp = ri->iri_rcv_tstmp; 3262 return (m); 3263 } 3264 3265 static void 3266 _task_fn_rx_watchdog(void *context) 3267 { 3268 iflib_rxq_t rxq = context; 3269 3270 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3271 } 3272 3273 static uint8_t 3274 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 3275 { 3276 if_t ifp; 3277 if_ctx_t ctx = rxq->ifr_ctx; 3278 if_shared_ctx_t sctx = ctx->ifc_sctx; 3279 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 3280 int avail, i; 3281 qidx_t *cidxp; 3282 struct if_rxd_info ri; 3283 int err, budget_left, rx_bytes, rx_pkts; 3284 iflib_fl_t fl; 3285 #if defined(INET6) || defined(INET) 3286 int lro_enabled; 3287 #endif 3288 uint8_t retval = 0; 3289 3290 /* 3291 * XXX early demux data packets so that if_input processing only handles 3292 * acks in interrupt context 3293 */ 3294 struct mbuf *m, *mh, *mt; 3295 3296 NET_EPOCH_ASSERT(); 3297 3298 ifp = ctx->ifc_ifp; 3299 mh = mt = NULL; 3300 MPASS(budget > 0); 3301 rx_pkts = rx_bytes = 0; 3302 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 3303 cidxp = &rxq->ifr_cq_cidx; 3304 else 3305 cidxp = &rxq->ifr_fl[0].ifl_cidx; 3306 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 3307 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3308 retval |= iflib_fl_refill_all(ctx, fl); 3309 DBG_COUNTER_INC(rx_unavail); 3310 return (retval); 3311 } 3312 3313 #if defined(INET6) || defined(INET) 3314 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3315 #endif 3316 3317 /* pfil needs the vnet to be set */ 3318 CURVNET_SET_QUIET(if_getvnet(ifp)); 3319 for (budget_left = budget; budget_left > 0 && avail > 0;) { 3320 if (__predict_false(!CTX_ACTIVE(ctx))) { 3321 DBG_COUNTER_INC(rx_ctx_inactive); 3322 break; 3323 } 3324 /* 3325 * Reset client set fields to their default values 3326 */ 3327 memset(&ri, 0, sizeof(ri)); 3328 ri.iri_qsidx = rxq->ifr_id; 3329 ri.iri_cidx = *cidxp; 3330 ri.iri_ifp = ifp; 3331 ri.iri_frags = rxq->ifr_frags; 3332 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 3333 3334 if (err) { 3335 CURVNET_RESTORE(); 3336 goto err; 3337 } 3338 rx_pkts += 1; 3339 rx_bytes += ri.iri_len; 3340 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 3341 *cidxp = ri.iri_cidx; 3342 /* Update our consumer index */ 3343 /* XXX NB: shurd - check if this is still safe */ 3344 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 3345 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 3346 /* was this only a completion queue message? */ 3347 if (__predict_false(ri.iri_nfrags == 0)) 3348 continue; 3349 } 3350 MPASS(ri.iri_nfrags != 0); 3351 MPASS(ri.iri_len != 0); 3352 3353 /* will advance the cidx on the corresponding free lists */ 3354 m = iflib_rxd_pkt_get(rxq, &ri); 3355 avail--; 3356 budget_left--; 3357 if (avail == 0 && budget_left) 3358 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 3359 3360 if (__predict_false(m == NULL)) 3361 continue; 3362 3363 #ifndef __NO_STRICT_ALIGNMENT 3364 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3365 continue; 3366 #endif 3367 #if defined(INET6) || defined(INET) 3368 if (lro_enabled) { 3369 tcp_lro_queue_mbuf(&rxq->ifr_lc, m); 3370 continue; 3371 } 3372 #endif 3373 3374 if (mh == NULL) 3375 mh = mt = m; 3376 else { 3377 mt->m_nextpkt = m; 3378 mt = m; 3379 } 3380 } 3381 CURVNET_RESTORE(); 3382 /* make sure that we can refill faster than drain */ 3383 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3384 retval |= iflib_fl_refill_all(ctx, fl); 3385 3386 if (mh != NULL) { 3387 if_input(ifp, mh); 3388 DBG_COUNTER_INC(rx_if_input); 3389 } 3390 3391 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3392 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3393 3394 /* 3395 * Flush any outstanding LRO work 3396 */ 3397 #if defined(INET6) || defined(INET) 3398 tcp_lro_flush_all(&rxq->ifr_lc); 3399 #endif 3400 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3401 retval |= IFLIB_RXEOF_MORE; 3402 return (retval); 3403 err: 3404 STATE_LOCK(ctx); 3405 ctx->ifc_flags |= IFC_DO_RESET; 3406 iflib_admin_intr_deferred(ctx); 3407 STATE_UNLOCK(ctx); 3408 return (0); 3409 } 3410 3411 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq) - 1) 3412 static inline qidx_t 3413 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3414 { 3415 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3416 qidx_t minthresh = txq->ift_size / 8; 3417 if (in_use > 4 * minthresh) 3418 return (notify_count); 3419 if (in_use > 2 * minthresh) 3420 return (notify_count >> 1); 3421 if (in_use > minthresh) 3422 return (notify_count >> 3); 3423 return (0); 3424 } 3425 3426 static inline qidx_t 3427 txq_max_rs_deferred(iflib_txq_t txq) 3428 { 3429 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3430 qidx_t minthresh = txq->ift_size / 8; 3431 if (txq->ift_in_use > 4 * minthresh) 3432 return (notify_count); 3433 if (txq->ift_in_use > 2 * minthresh) 3434 return (notify_count >> 1); 3435 if (txq->ift_in_use > minthresh) 3436 return (notify_count >> 2); 3437 return (2); 3438 } 3439 3440 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3441 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3442 3443 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3444 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3445 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3446 3447 /* forward compatibility for cxgb */ 3448 #define FIRST_QSET(ctx) 0 3449 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3450 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3451 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3452 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3453 3454 static inline bool 3455 iflib_txd_db_check(iflib_txq_t txq, int ring) 3456 { 3457 if_ctx_t ctx = txq->ift_ctx; 3458 qidx_t dbval, max; 3459 3460 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3461 3462 /* force || threshold exceeded || at the edge of the ring */ 3463 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx))) { 3464 3465 /* 3466 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3467 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3468 * producer index explicitly (INTC). 3469 */ 3470 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3471 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3472 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3473 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3474 3475 /* 3476 * Absent bugs there are zero packets pending so reset pending counts to zero. 3477 */ 3478 txq->ift_db_pending = txq->ift_npending = 0; 3479 return (true); 3480 } 3481 return (false); 3482 } 3483 3484 #ifdef PKT_DEBUG 3485 static void 3486 print_pkt(if_pkt_info_t pi) 3487 { 3488 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3489 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3490 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3491 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3492 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3493 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3494 } 3495 #endif 3496 3497 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3498 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3499 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3500 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3501 3502 /** 3503 * Parses out ethernet header information in the given mbuf. 3504 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length) 3505 * 3506 * This will account for the VLAN header if present. 3507 * 3508 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those 3509 * types of packets. 3510 */ 3511 static int 3512 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3513 { 3514 struct ether_vlan_header *eh; 3515 struct mbuf *m; 3516 3517 m = *mp; 3518 if (__predict_false(m->m_len < sizeof(*eh))) { 3519 (*pullups)++; 3520 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3521 return (ENOMEM); 3522 } 3523 eh = mtod(m, struct ether_vlan_header *); 3524 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3525 pi->ipi_etype = ntohs(eh->evl_proto); 3526 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3527 } else { 3528 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3529 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3530 } 3531 *mp = m; 3532 3533 return (0); 3534 } 3535 3536 /** 3537 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi. 3538 * Currently this information includes: IP ToS value, IP header version/presence 3539 * 3540 * This is missing some checks and doesn't edit the packet content as it goes, 3541 * unlike iflib_parse_header(), in order to keep the amount of code here minimal. 3542 */ 3543 static int 3544 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3545 { 3546 struct mbuf *m; 3547 int err; 3548 3549 *pullups = 0; 3550 m = *mp; 3551 if (!M_WRITABLE(m)) { 3552 m = m_dup(m, M_NOWAIT); 3553 m_freem(*mp); 3554 DBG_COUNTER_INC(tx_frees); 3555 *mp = m; 3556 if (m == NULL) 3557 return (ENOMEM); 3558 } 3559 3560 /* Fills out pi->ipi_etype */ 3561 err = iflib_parse_ether_header(pi, mp, pullups); 3562 if (err) 3563 return (err); 3564 m = *mp; 3565 3566 switch (pi->ipi_etype) { 3567 #ifdef INET 3568 case ETHERTYPE_IP: 3569 { 3570 struct mbuf *n; 3571 struct ip *ip = NULL; 3572 int miniplen; 3573 3574 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip)); 3575 if (__predict_false(m->m_len < miniplen)) { 3576 /* 3577 * Check for common case where the first mbuf only contains 3578 * the Ethernet header 3579 */ 3580 if (m->m_len == pi->ipi_ehdrlen) { 3581 n = m->m_next; 3582 MPASS(n); 3583 /* If next mbuf contains at least the minimal IP header, then stop */ 3584 if (n->m_len >= sizeof(*ip)) { 3585 ip = (struct ip *)n->m_data; 3586 } else { 3587 (*pullups)++; 3588 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3589 return (ENOMEM); 3590 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3591 } 3592 } else { 3593 (*pullups)++; 3594 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3595 return (ENOMEM); 3596 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3597 } 3598 } else { 3599 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3600 } 3601 3602 /* Have the IPv4 header w/ no options here */ 3603 pi->ipi_ip_hlen = ip->ip_hl << 2; 3604 pi->ipi_ipproto = ip->ip_p; 3605 pi->ipi_ip_tos = ip->ip_tos; 3606 pi->ipi_flags |= IPI_TX_IPV4; 3607 3608 break; 3609 } 3610 #endif 3611 #ifdef INET6 3612 case ETHERTYPE_IPV6: 3613 { 3614 struct ip6_hdr *ip6; 3615 3616 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3617 (*pullups)++; 3618 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3619 return (ENOMEM); 3620 } 3621 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3622 3623 /* Have the IPv6 fixed header here */ 3624 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3625 pi->ipi_ipproto = ip6->ip6_nxt; 3626 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3627 pi->ipi_flags |= IPI_TX_IPV6; 3628 3629 break; 3630 } 3631 #endif 3632 default: 3633 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3634 pi->ipi_ip_hlen = 0; 3635 break; 3636 } 3637 *mp = m; 3638 3639 return (0); 3640 3641 } 3642 3643 static int 3644 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3645 { 3646 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3647 struct mbuf *m; 3648 int err; 3649 3650 m = *mp; 3651 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3652 M_WRITABLE(m) == 0) { 3653 m = m_dup(m, M_NOWAIT); 3654 m_freem(*mp); 3655 DBG_COUNTER_INC(tx_frees); 3656 *mp = m; 3657 if (m == NULL) 3658 return (ENOMEM); 3659 } 3660 3661 /* Fills out pi->ipi_etype */ 3662 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups); 3663 if (__predict_false(err)) 3664 return (err); 3665 m = *mp; 3666 3667 switch (pi->ipi_etype) { 3668 #ifdef INET 3669 case ETHERTYPE_IP: 3670 { 3671 struct ip *ip; 3672 struct tcphdr *th; 3673 uint8_t hlen; 3674 3675 hlen = pi->ipi_ehdrlen + sizeof(*ip); 3676 if (__predict_false(m->m_len < hlen)) { 3677 txq->ift_pullups++; 3678 if (__predict_false((m = m_pullup(m, hlen)) == NULL)) 3679 return (ENOMEM); 3680 } 3681 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3682 hlen = pi->ipi_ehdrlen + (ip->ip_hl << 2); 3683 if (ip->ip_p == IPPROTO_TCP) { 3684 hlen += sizeof(*th); 3685 th = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2)); 3686 } else if (ip->ip_p == IPPROTO_UDP) { 3687 hlen += sizeof(struct udphdr); 3688 } 3689 if (__predict_false(m->m_len < hlen)) { 3690 txq->ift_pullups++; 3691 if ((m = m_pullup(m, hlen)) == NULL) 3692 return (ENOMEM); 3693 /* reset pointers after pullup */ 3694 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3695 th = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2)); 3696 } 3697 pi->ipi_ip_hlen = ip->ip_hl << 2; 3698 pi->ipi_ipproto = ip->ip_p; 3699 pi->ipi_ip_tos = ip->ip_tos; 3700 pi->ipi_flags |= IPI_TX_IPV4; 3701 3702 /* TCP checksum offload may require TCP header length */ 3703 if (IS_TX_OFFLOAD4(pi)) { 3704 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3705 pi->ipi_tcp_hflags = tcp_get_flags(th); 3706 pi->ipi_tcp_hlen = th->th_off << 2; 3707 pi->ipi_tcp_seq = th->th_seq; 3708 } 3709 if (IS_TSO4(pi)) { 3710 MPASS(ip->ip_p == IPPROTO_TCP); 3711 /* 3712 * TSO always requires hardware checksum offload. 3713 */ 3714 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3715 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3716 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3717 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3718 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3719 ip->ip_sum = 0; 3720 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3721 } 3722 } 3723 } 3724 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3725 ip->ip_sum = 0; 3726 3727 break; 3728 } 3729 #endif 3730 #ifdef INET6 3731 case ETHERTYPE_IPV6: 3732 { 3733 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3734 struct tcphdr *th; 3735 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3736 3737 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3738 txq->ift_pullups++; 3739 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3740 return (ENOMEM); 3741 /* reset pointers after pullup */ 3742 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3743 } 3744 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3745 3746 /* XXX-BZ this will go badly in case of ext hdrs. */ 3747 pi->ipi_ipproto = ip6->ip6_nxt; 3748 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3749 pi->ipi_flags |= IPI_TX_IPV6; 3750 3751 /* TCP checksum offload may require TCP header length */ 3752 if (IS_TX_OFFLOAD6(pi)) { 3753 if (pi->ipi_ipproto == IPPROTO_TCP) { 3754 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3755 txq->ift_pullups++; 3756 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3757 return (ENOMEM); 3758 /* reset pointers after pullup */ 3759 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3760 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3761 } 3762 pi->ipi_tcp_hflags = tcp_get_flags(th); 3763 pi->ipi_tcp_hlen = th->th_off << 2; 3764 pi->ipi_tcp_seq = th->th_seq; 3765 } 3766 if (IS_TSO6(pi)) { 3767 MPASS(ip6->ip6_nxt == IPPROTO_TCP); 3768 /* 3769 * TSO always requires hardware checksum offload. 3770 */ 3771 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3772 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3773 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3774 } 3775 } 3776 break; 3777 } 3778 #endif 3779 default: 3780 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3781 pi->ipi_ip_hlen = 0; 3782 break; 3783 } 3784 *mp = m; 3785 3786 return (0); 3787 } 3788 3789 /* 3790 * If dodgy hardware rejects the scatter gather chain we've handed it 3791 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3792 * m_defrag'd mbufs 3793 */ 3794 static __noinline struct mbuf * 3795 iflib_remove_mbuf(iflib_txq_t txq) 3796 { 3797 int ntxd, pidx; 3798 struct mbuf *m, **ifsd_m; 3799 3800 ifsd_m = txq->ift_sds.ifsd_m; 3801 ntxd = txq->ift_size; 3802 pidx = txq->ift_pidx & (ntxd - 1); 3803 ifsd_m = txq->ift_sds.ifsd_m; 3804 m = IFLIB_GET_MBUF(ifsd_m[pidx]); 3805 ifsd_m[pidx] = NULL; 3806 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3807 if (txq->ift_sds.ifsd_tso_map != NULL) 3808 bus_dmamap_unload(txq->ift_tso_buf_tag, 3809 txq->ift_sds.ifsd_tso_map[pidx]); 3810 #if MEMORY_LOGGING 3811 txq->ift_dequeued++; 3812 #endif 3813 return (m); 3814 } 3815 3816 /* 3817 * Pad an mbuf to ensure a minimum ethernet frame size. 3818 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3819 */ 3820 static __noinline int 3821 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3822 { 3823 /* 3824 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3825 * and ARP message is the smallest common payload I can think of 3826 */ 3827 static char pad[18]; /* just zeros */ 3828 int n; 3829 struct mbuf *new_head; 3830 3831 if (!M_WRITABLE(*m_head)) { 3832 new_head = m_dup(*m_head, M_NOWAIT); 3833 m_freem(*m_head); 3834 *m_head = new_head; 3835 if (new_head == NULL) { 3836 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3837 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3838 DBG_COUNTER_INC(tx_frees); 3839 return (ENOMEM); 3840 } 3841 } 3842 3843 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3844 n > 0; n -= sizeof(pad)) 3845 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3846 break; 3847 3848 if (n > 0) { 3849 m_freem(*m_head); 3850 *m_head = NULL; 3851 device_printf(dev, "cannot pad short frame\n"); 3852 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3853 DBG_COUNTER_INC(tx_frees); 3854 return (ENOMEM); 3855 } 3856 3857 return (0); 3858 } 3859 3860 static int 3861 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp, int *obytes, int *opkts) 3862 { 3863 if_ctx_t ctx; 3864 if_shared_ctx_t sctx; 3865 if_softc_ctx_t scctx; 3866 bus_dma_tag_t buf_tag; 3867 bus_dma_segment_t *segs; 3868 struct mbuf *m_head, **ifsd_m; 3869 bus_dmamap_t map; 3870 struct if_pkt_info pi; 3871 uintptr_t flags; 3872 int remap = 0; 3873 int err, nsegs, ndesc, max_segs, pidx; 3874 3875 ctx = txq->ift_ctx; 3876 sctx = ctx->ifc_sctx; 3877 scctx = &ctx->ifc_softc_ctx; 3878 segs = txq->ift_segs; 3879 m_head = *m_headp; 3880 map = NULL; 3881 3882 /* 3883 * If we're doing TSO the next descriptor to clean may be quite far ahead 3884 */ 3885 pidx = txq->ift_pidx; 3886 map = txq->ift_sds.ifsd_map[pidx]; 3887 ifsd_m = txq->ift_sds.ifsd_m; 3888 3889 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3890 buf_tag = txq->ift_tso_buf_tag; 3891 max_segs = scctx->isc_tx_tso_segments_max; 3892 map = txq->ift_sds.ifsd_tso_map[pidx]; 3893 MPASS(buf_tag != NULL); 3894 MPASS(max_segs > 0); 3895 flags = IFLIB_TSO; 3896 } else { 3897 buf_tag = txq->ift_buf_tag; 3898 max_segs = scctx->isc_tx_nsegments; 3899 map = txq->ift_sds.ifsd_map[pidx]; 3900 flags = IFLIB_NO_TSO; 3901 } 3902 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3903 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3904 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3905 if (err) { 3906 DBG_COUNTER_INC(encap_txd_encap_fail); 3907 return (err); 3908 } 3909 } 3910 m_head = *m_headp; 3911 3912 memset(&pi, 0, sizeof(pi)); 3913 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG | M_BCAST | M_MCAST)); 3914 pi.ipi_pidx = pidx; 3915 pi.ipi_qsidx = txq->ift_id; 3916 pi.ipi_len = m_head->m_pkthdr.len; 3917 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3918 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3919 3920 /* deliberate bitwise OR to make one condition */ 3921 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3922 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3923 DBG_COUNTER_INC(encap_txd_encap_fail); 3924 return (err); 3925 } 3926 m_head = *m_headp; 3927 } 3928 3929 retry: 3930 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3931 BUS_DMA_NOWAIT); 3932 defrag: 3933 if (__predict_false(err)) { 3934 switch (err) { 3935 case EFBIG: 3936 /* try collapse once and defrag once */ 3937 if (remap == 0) { 3938 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3939 /* try defrag if collapsing fails */ 3940 if (m_head == NULL) 3941 remap++; 3942 } 3943 if (remap == 1) { 3944 txq->ift_mbuf_defrag++; 3945 m_head = m_defrag(*m_headp, M_NOWAIT); 3946 } 3947 /* 3948 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3949 * failed to map an mbuf that was run through m_defrag 3950 */ 3951 MPASS(remap <= 1); 3952 if (__predict_false(m_head == NULL || remap > 1)) 3953 goto defrag_failed; 3954 remap++; 3955 *m_headp = m_head; 3956 goto retry; 3957 break; 3958 case ENOMEM: 3959 /* FALLTHROUGH */ 3960 default: 3961 txq->ift_no_tx_dma_setup++; 3962 m_freem(*m_headp); 3963 DBG_COUNTER_INC(tx_frees); 3964 *m_headp = NULL; 3965 break; 3966 } 3967 txq->ift_map_failed++; 3968 DBG_COUNTER_INC(encap_load_mbuf_fail); 3969 DBG_COUNTER_INC(encap_txd_encap_fail); 3970 return (err); 3971 } 3972 ifsd_m[pidx] = IFLIB_SAVE_MBUF(m_head, flags); 3973 if (m_head->m_pkthdr.csum_flags & CSUM_SND_TAG) 3974 pi.ipi_mbuf = m_head; 3975 else 3976 pi.ipi_mbuf = NULL; 3977 /* 3978 * XXX assumes a 1 to 1 relationship between segments and 3979 * descriptors - this does not hold true on all drivers, e.g. 3980 * cxgb 3981 */ 3982 if (__predict_false(nsegs > TXQ_AVAIL(txq))) { 3983 iflib_completed_tx_reclaim_force(txq); 3984 if (__predict_false(nsegs > TXQ_AVAIL(txq))) { 3985 txq->ift_no_desc_avail++; 3986 bus_dmamap_unload(buf_tag, map); 3987 DBG_COUNTER_INC(encap_txq_avail_fail); 3988 DBG_COUNTER_INC(encap_txd_encap_fail); 3989 if (ctx->ifc_sysctl_simple_tx) { 3990 *m_headp = m_head = iflib_remove_mbuf(txq); 3991 m_freem(*m_headp); 3992 DBG_COUNTER_INC(tx_frees); 3993 *m_headp = NULL; 3994 } 3995 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3996 GROUPTASK_ENQUEUE(&txq->ift_task); 3997 return (ENOBUFS); 3998 } 3999 } 4000 /* 4001 * On Intel cards we can greatly reduce the number of TX interrupts 4002 * we see by only setting report status on every Nth descriptor. 4003 * However, this also means that the driver will need to keep track 4004 * of the descriptors that RS was set on to check them for the DD bit. 4005 */ 4006 if (txq->ift_rs_pending + nsegs + 1 > TXQ_MAX_RS_DEFERRED(txq) || 4007 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx)) { 4008 pi.ipi_flags |= IPI_TX_INTR; 4009 } 4010 4011 pi.ipi_segs = segs; 4012 pi.ipi_nsegs = nsegs; 4013 4014 MPASS(pidx >= 0 && pidx < txq->ift_size); 4015 #ifdef PKT_DEBUG 4016 print_pkt(&pi); 4017 #endif 4018 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 4019 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 4020 DBG_COUNTER_INC(tx_encap); 4021 MPASS(pi.ipi_new_pidx < txq->ift_size); 4022 4023 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 4024 if (pi.ipi_new_pidx < pi.ipi_pidx) { 4025 ndesc += txq->ift_size; 4026 txq->ift_gen = 1; 4027 } 4028 4029 if (pi.ipi_flags & IPI_TX_INTR) 4030 txq->ift_rs_pending = 0; 4031 else 4032 txq->ift_rs_pending += ndesc; 4033 /* 4034 * drivers can need up to ift_pad sentinels 4035 */ 4036 MPASS(ndesc <= pi.ipi_nsegs + txq->ift_pad); 4037 MPASS(pi.ipi_new_pidx != pidx); 4038 MPASS(ndesc > 0); 4039 txq->ift_in_use += ndesc; 4040 txq->ift_db_pending += ndesc; 4041 4042 /* 4043 * We update the last software descriptor again here because there may 4044 * be a sentinel and/or there may be more mbufs than segments 4045 */ 4046 txq->ift_pidx = pi.ipi_new_pidx; 4047 txq->ift_npending += pi.ipi_ndescs; 4048 4049 /* 4050 * Update packets / bytes sent 4051 */ 4052 if (flags & IFLIB_TSO) { 4053 int hlen = pi.ipi_ehdrlen + pi.ipi_ip_hlen + pi.ipi_tcp_hlen; 4054 int tsolen = pi.ipi_len - hlen; 4055 int nsegs = (tsolen + pi.ipi_tso_segsz - 1) / pi.ipi_tso_segsz; 4056 *obytes += tsolen + nsegs * hlen; 4057 *opkts += nsegs; 4058 } else { 4059 *obytes += pi.ipi_len; 4060 *opkts += 1; 4061 } 4062 } else { 4063 *m_headp = m_head = iflib_remove_mbuf(txq); 4064 if (err == EFBIG) { 4065 txq->ift_txd_encap_efbig++; 4066 if (remap < 2) { 4067 remap = 1; 4068 goto defrag; 4069 } 4070 goto defrag_failed; 4071 } 4072 /* mp_ring assumes ENOBUFS means we didn't consume the mbuf */ 4073 if (err == ENOBUFS && !ctx->ifc_sysctl_simple_tx) 4074 err = ENOMEM; 4075 goto out_with_error; 4076 } 4077 /* 4078 * err can't possibly be non-zero here, so we don't neet to test it 4079 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 4080 */ 4081 return (err); 4082 4083 defrag_failed: 4084 err = ENOMEM; 4085 txq->ift_mbuf_defrag_failed++; 4086 out_with_error: 4087 txq->ift_map_failed++; 4088 m_freem(*m_headp); 4089 DBG_COUNTER_INC(tx_frees); 4090 *m_headp = NULL; 4091 DBG_COUNTER_INC(encap_txd_encap_fail); 4092 return (err); 4093 } 4094 4095 static void 4096 iflib_tx_desc_free(iflib_txq_t txq, int n, struct mbuf **m_defer) 4097 { 4098 uint32_t qsize, cidx, gen; 4099 struct mbuf *m, **ifsd_m; 4100 uintptr_t flags; 4101 4102 cidx = txq->ift_cidx; 4103 gen = txq->ift_gen; 4104 qsize = txq->ift_size; 4105 ifsd_m =txq->ift_sds.ifsd_m; 4106 4107 while (n-- > 0) { 4108 if ((m = IFLIB_GET_MBUF(ifsd_m[cidx])) != NULL) { 4109 flags = IFLIB_GET_FLAGS(ifsd_m[cidx]); 4110 MPASS(flags != 0); 4111 if (flags & IFLIB_TSO) { 4112 bus_dmamap_sync(txq->ift_tso_buf_tag, 4113 txq->ift_sds.ifsd_tso_map[cidx], 4114 BUS_DMASYNC_POSTWRITE); 4115 bus_dmamap_unload(txq->ift_tso_buf_tag, 4116 txq->ift_sds.ifsd_tso_map[cidx]); 4117 } else { 4118 bus_dmamap_sync(txq->ift_buf_tag, 4119 txq->ift_sds.ifsd_map[cidx], 4120 BUS_DMASYNC_POSTWRITE); 4121 bus_dmamap_unload(txq->ift_buf_tag, 4122 txq->ift_sds.ifsd_map[cidx]); 4123 } 4124 /* XXX we don't support any drivers that batch packets yet */ 4125 MPASS(m->m_nextpkt == NULL); 4126 if (m_defer == NULL) { 4127 m_freem(m); 4128 } else if (m != NULL) { 4129 *m_defer = m; 4130 m_defer++; 4131 } 4132 ifsd_m[cidx] = NULL; 4133 #if MEMORY_LOGGING 4134 txq->ift_dequeued++; 4135 #endif 4136 DBG_COUNTER_INC(tx_frees); 4137 } 4138 if (__predict_false(++cidx == qsize)) { 4139 cidx = 0; 4140 gen = 0; 4141 } 4142 } 4143 txq->ift_cidx = cidx; 4144 txq->ift_gen = gen; 4145 } 4146 4147 static __inline int 4148 iflib_txq_can_reclaim(iflib_txq_t txq) 4149 { 4150 int reclaim, thresh; 4151 4152 thresh = txq->ift_reclaim_thresh; 4153 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 4154 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 4155 4156 if (ticks <= (txq->ift_last_reclaim + txq->ift_reclaim_ticks) && 4157 txq->ift_in_use < thresh) 4158 return (false); 4159 iflib_tx_credits_update(txq->ift_ctx, txq); 4160 reclaim = DESC_RECLAIMABLE(txq); 4161 if (reclaim <= thresh) { 4162 #ifdef INVARIANTS 4163 if (iflib_verbose_debug) { 4164 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __func__, 4165 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 4166 reclaim, thresh); 4167 } 4168 #endif 4169 return (0); 4170 } 4171 return (reclaim); 4172 } 4173 4174 static __inline void 4175 _iflib_completed_tx_reclaim(iflib_txq_t txq, struct mbuf **m_defer, int reclaim) 4176 { 4177 txq->ift_last_reclaim = ticks; 4178 iflib_tx_desc_free(txq, reclaim, m_defer); 4179 txq->ift_cleaned += reclaim; 4180 txq->ift_in_use -= reclaim; 4181 } 4182 4183 static __inline int 4184 iflib_completed_tx_reclaim(iflib_txq_t txq, struct mbuf **m_defer) 4185 { 4186 int reclaim; 4187 4188 reclaim = iflib_txq_can_reclaim(txq); 4189 if (reclaim <= 0) 4190 return (0); 4191 _iflib_completed_tx_reclaim(txq, m_defer, reclaim); 4192 return (reclaim); 4193 } 4194 4195 /* 4196 * Reclaim any transmit descriptors possible, ignoring coalescing 4197 */ 4198 static __inline void 4199 iflib_completed_tx_reclaim_force(iflib_txq_t txq) 4200 { 4201 int reclaim; 4202 4203 iflib_tx_credits_update(txq->ift_ctx, txq); 4204 reclaim = DESC_RECLAIMABLE(txq); 4205 if (reclaim != 0) 4206 _iflib_completed_tx_reclaim(txq, NULL, reclaim); 4207 } 4208 4209 static struct mbuf ** 4210 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 4211 { 4212 int next, size; 4213 struct mbuf **items; 4214 4215 size = r->size; 4216 next = (cidx + CACHE_PTR_INCREMENT) & (size - 1); 4217 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 4218 4219 prefetch(items[(cidx + offset) & (size - 1)]); 4220 if (remaining > 1) { 4221 prefetch2cachelines(&items[next]); 4222 prefetch2cachelines(items[(cidx + offset + 1) & (size - 1)]); 4223 prefetch2cachelines(items[(cidx + offset + 2) & (size - 1)]); 4224 prefetch2cachelines(items[(cidx + offset + 3) & (size - 1)]); 4225 } 4226 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size - 1)])); 4227 } 4228 4229 static void 4230 iflib_txq_check_drain(iflib_txq_t txq, int budget) 4231 { 4232 4233 ifmp_ring_check_drainage(txq->ift_br, budget); 4234 } 4235 4236 static uint32_t 4237 iflib_txq_can_drain(struct ifmp_ring *r) 4238 { 4239 iflib_txq_t txq = r->cookie; 4240 if_ctx_t ctx = txq->ift_ctx; 4241 4242 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx)) 4243 return (1); 4244 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 4245 BUS_DMASYNC_POSTREAD); 4246 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 4247 false)); 4248 } 4249 4250 static uint32_t 4251 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 4252 { 4253 iflib_txq_t txq = r->cookie; 4254 if_ctx_t ctx = txq->ift_ctx; 4255 if_t ifp = ctx->ifc_ifp; 4256 struct mbuf *m, **mp; 4257 int avail, bytes_sent, consumed, count, err, i; 4258 int mcast_sent, pkt_sent, reclaimed; 4259 bool do_prefetch, rang, ring; 4260 4261 if (__predict_false(!iflib_is_running(ctx) || !LINK_ACTIVE(ctx))) { 4262 DBG_COUNTER_INC(txq_drain_notready); 4263 return (0); 4264 } 4265 reclaimed = iflib_completed_tx_reclaim(txq, NULL); 4266 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 4267 avail = IDXDIFF(pidx, cidx, r->size); 4268 4269 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 4270 /* 4271 * The driver is unloading so we need to free all pending packets. 4272 */ 4273 DBG_COUNTER_INC(txq_drain_flushing); 4274 for (i = 0; i < avail; i++) { 4275 if (__predict_true(r->items[(cidx + i) & (r->size - 1)] != (void *)txq)) 4276 m_freem(r->items[(cidx + i) & (r->size - 1)]); 4277 r->items[(cidx + i) & (r->size - 1)] = NULL; 4278 } 4279 return (avail); 4280 } 4281 4282 if (__predict_false(!iflib_is_running(ctx))) { 4283 CALLOUT_LOCK(txq); 4284 callout_stop(&txq->ift_timer); 4285 CALLOUT_UNLOCK(txq); 4286 DBG_COUNTER_INC(txq_drain_stopped); 4287 return (0); 4288 } 4289 4290 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 4291 count = MIN(avail, TX_BATCH_SIZE); 4292 #ifdef INVARIANTS 4293 if (iflib_verbose_debug) 4294 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __func__, 4295 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 4296 #endif 4297 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 4298 err = 0; 4299 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx); i++) { 4300 int rem = do_prefetch ? count - i : 0; 4301 4302 mp = _ring_peek_one(r, cidx, i, rem); 4303 MPASS(mp != NULL && *mp != NULL); 4304 4305 /* 4306 * Completion interrupts will use the address of the txq 4307 * as a sentinel to enqueue _something_ in order to acquire 4308 * the lock on the mp_ring (there's no direct lock call). 4309 * We obviously whave to check for these sentinel cases 4310 * and skip them. 4311 */ 4312 if (__predict_false(*mp == (struct mbuf *)txq)) { 4313 consumed++; 4314 continue; 4315 } 4316 err = iflib_encap(txq, mp, &bytes_sent, &pkt_sent); 4317 if (__predict_false(err)) { 4318 /* no room - bail out */ 4319 if (err == ENOBUFS) 4320 break; 4321 consumed++; 4322 /* we can't send this packet - skip it */ 4323 continue; 4324 } 4325 consumed++; 4326 m = *mp; 4327 DBG_COUNTER_INC(tx_sent); 4328 mcast_sent += !!(m->m_flags & M_MCAST); 4329 4330 if (__predict_false(!iflib_is_running(ctx))) 4331 break; 4332 ETHER_BPF_MTAP(ifp, m); 4333 rang = iflib_txd_db_check(txq, false); 4334 } 4335 4336 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 4337 ring = rang ? false : (iflib_min_tx_latency | err | (!!txq->ift_reclaim_thresh)); 4338 iflib_txd_db_check(txq, ring); 4339 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 4340 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 4341 if (mcast_sent) 4342 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 4343 #ifdef INVARIANTS 4344 if (iflib_verbose_debug) 4345 printf("consumed=%d\n", consumed); 4346 #endif 4347 return (consumed); 4348 } 4349 4350 static uint32_t 4351 iflib_txq_drain_always(struct ifmp_ring *r) 4352 { 4353 return (1); 4354 } 4355 4356 static uint32_t 4357 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 4358 { 4359 int i, avail; 4360 struct mbuf **mp; 4361 iflib_txq_t txq; 4362 4363 txq = r->cookie; 4364 4365 CALLOUT_LOCK(txq); 4366 callout_stop(&txq->ift_timer); 4367 CALLOUT_UNLOCK(txq); 4368 4369 avail = IDXDIFF(pidx, cidx, r->size); 4370 for (i = 0; i < avail; i++) { 4371 mp = _ring_peek_one(r, cidx, i, avail - i); 4372 if (__predict_false(*mp == (struct mbuf *)txq)) 4373 continue; 4374 m_freem(*mp); 4375 DBG_COUNTER_INC(tx_frees); 4376 } 4377 MPASS(ifmp_ring_is_stalled(r) == 0); 4378 return (avail); 4379 } 4380 4381 static void 4382 iflib_ifmp_purge(iflib_txq_t txq) 4383 { 4384 struct ifmp_ring *r; 4385 4386 r = txq->ift_br; 4387 r->drain = iflib_txq_drain_free; 4388 r->can_drain = iflib_txq_drain_always; 4389 4390 ifmp_ring_check_drainage(r, r->size); 4391 4392 r->drain = iflib_txq_drain; 4393 r->can_drain = iflib_txq_can_drain; 4394 } 4395 4396 static void 4397 _task_fn_tx(void *context) 4398 { 4399 iflib_txq_t txq = context; 4400 if_ctx_t ctx = txq->ift_ctx; 4401 #if defined(DEV_NETMAP) || defined(ALTQ) 4402 if_t ifp = ctx->ifc_ifp; 4403 #endif 4404 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4405 4406 #ifdef IFLIB_DIAGNOSTICS 4407 txq->ift_cpu_exec_count[curcpu]++; 4408 #endif 4409 if (!iflib_is_running(ctx)) 4410 return; 4411 #ifdef DEV_NETMAP 4412 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 4413 netmap_tx_irq(ifp, txq->ift_id)) 4414 goto skip_ifmp; 4415 #endif 4416 if (ctx->ifc_sysctl_simple_tx) { 4417 iflib_simple_txq_drain(txq); 4418 goto skip_ifmp; 4419 } 4420 #ifdef ALTQ 4421 if (if_altq_is_enabled(ifp)) 4422 iflib_altq_if_start(ifp); 4423 #endif 4424 if (txq->ift_db_pending) 4425 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 4426 else if (!abdicate) 4427 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4428 /* 4429 * When abdicating, we always need to check drainage, not just when we don't enqueue 4430 */ 4431 if (abdicate) 4432 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4433 4434 skip_ifmp: 4435 if (ctx->ifc_flags & IFC_LEGACY) 4436 IFDI_INTR_ENABLE(ctx); 4437 else 4438 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 4439 } 4440 4441 static void 4442 _task_fn_rx(void *context) 4443 { 4444 iflib_rxq_t rxq = context; 4445 if_ctx_t ctx = rxq->ifr_ctx; 4446 uint8_t more; 4447 uint16_t budget; 4448 #ifdef DEV_NETMAP 4449 u_int work = 0; 4450 int nmirq; 4451 #endif 4452 4453 #ifdef IFLIB_DIAGNOSTICS 4454 rxq->ifr_cpu_exec_count[curcpu]++; 4455 #endif 4456 DBG_COUNTER_INC(task_fn_rxs); 4457 if (__predict_false(!iflib_is_running(ctx))) 4458 return; 4459 #ifdef DEV_NETMAP 4460 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4461 if (nmirq != NM_IRQ_PASS) { 4462 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4463 goto skip_rxeof; 4464 } 4465 #endif 4466 budget = ctx->ifc_sysctl_rx_budget; 4467 if (budget == 0) 4468 budget = 16; /* XXX */ 4469 more = iflib_rxeof(rxq, budget); 4470 #ifdef DEV_NETMAP 4471 skip_rxeof: 4472 #endif 4473 if ((more & IFLIB_RXEOF_MORE) == 0) { 4474 if (ctx->ifc_flags & IFC_LEGACY) 4475 IFDI_INTR_ENABLE(ctx); 4476 else 4477 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4478 DBG_COUNTER_INC(rx_intr_enables); 4479 } 4480 if (__predict_false(!iflib_is_running(ctx))) 4481 return; 4482 4483 if (more & IFLIB_RXEOF_MORE) 4484 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4485 else if (more & IFLIB_RXEOF_EMPTY) 4486 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4487 } 4488 4489 static void 4490 _task_fn_admin(void *context, int pending) 4491 { 4492 if_ctx_t ctx = context; 4493 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4494 iflib_txq_t txq; 4495 int i; 4496 bool do_reset, do_reset_if_up, do_watchdog; 4497 bool in_detach; 4498 4499 STATE_LOCK(ctx); 4500 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4501 do_reset_if_up = (ctx->ifc_flags & IFC_DO_RESET_IF_UP); 4502 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4503 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4504 ctx->ifc_flags &= ~(IFC_DO_RESET | IFC_DO_RESET_IF_UP | 4505 IFC_DO_WATCHDOG); 4506 STATE_UNLOCK(ctx); 4507 4508 if (in_detach) 4509 return; 4510 KFAIL_POINT_CODE_COND(_debug_fail_point_iflib, 4511 admin_task_after_detach_check, 4512 iflib_admin_task_fail_device[0] != '\0' && 4513 strcmp(device_get_nameunit(ctx->ifc_dev), 4514 iflib_admin_task_fail_device) == 0, FAIL_POINT_NONSLEEPABLE, {}); 4515 4516 CTX_LOCK(ctx); 4517 if (ctx->ifc_pm_state != IFLIB_PM_ACTIVE || 4518 !iflib_admin_enabled(ctx)) { 4519 CTX_UNLOCK(ctx); 4520 return; 4521 } 4522 if (!do_reset && do_reset_if_up && 4523 (if_getflags(ctx->ifc_ifp) & IFF_UP) != 0) 4524 do_reset = true; 4525 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4526 CALLOUT_LOCK(txq); 4527 callout_stop(&txq->ift_timer); 4528 CALLOUT_UNLOCK(txq); 4529 } 4530 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4531 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4532 if (do_watchdog) { 4533 ctx->ifc_tx_watchdog_events++; 4534 IFDI_WATCHDOG_RESET(ctx); 4535 } 4536 IFDI_UPDATE_ADMIN_STATUS(ctx); 4537 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4538 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4539 txq->ift_timer.c_cpu); 4540 } 4541 IFDI_LINK_INTR_ENABLE(ctx); 4542 if (do_reset) 4543 iflib_if_init_locked(ctx); 4544 CTX_UNLOCK(ctx); 4545 4546 if (LINK_ACTIVE(ctx) == 0) 4547 return; 4548 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4549 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4550 } 4551 4552 static void 4553 _task_fn_iov(void *context, int pending) 4554 { 4555 if_ctx_t ctx = context; 4556 4557 if (iflib_in_detach(ctx)) 4558 return; 4559 CTX_LOCK(ctx); 4560 if (ctx->ifc_pm_state != IFLIB_PM_ACTIVE || 4561 (!iflib_is_running(ctx) && 4562 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))) { 4563 CTX_UNLOCK(ctx); 4564 return; 4565 } 4566 IFDI_VFLR_HANDLE(ctx); 4567 CTX_UNLOCK(ctx); 4568 } 4569 4570 static int 4571 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4572 { 4573 int err; 4574 if_int_delay_info_t info; 4575 if_ctx_t ctx; 4576 4577 info = (if_int_delay_info_t)arg1; 4578 ctx = info->iidi_ctx; 4579 info->iidi_req = req; 4580 info->iidi_oidp = oidp; 4581 CTX_LOCK(ctx); 4582 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4583 CTX_UNLOCK(ctx); 4584 return (err); 4585 } 4586 4587 /********************************************************************* 4588 * 4589 * IFNET FUNCTIONS 4590 * 4591 **********************************************************************/ 4592 4593 static void 4594 iflib_if_init_locked(if_ctx_t ctx) 4595 { 4596 if (ctx->ifc_pm_state != IFLIB_PM_ACTIVE) 4597 return; 4598 if (ctx->ifc_datapath_state != IFLIB_DP_STOPPED) 4599 iflib_stop(ctx); 4600 iflib_init_locked(ctx); 4601 } 4602 4603 static void 4604 iflib_if_init(void *arg) 4605 { 4606 if_ctx_t ctx = arg; 4607 4608 CTX_LOCK(ctx); 4609 iflib_if_init_locked(ctx); 4610 CTX_UNLOCK(ctx); 4611 } 4612 4613 static int 4614 iflib_if_transmit(if_t ifp, struct mbuf *m) 4615 { 4616 if_ctx_t ctx = if_getsoftc(ifp); 4617 iflib_txq_t txq; 4618 int err, qidx; 4619 int abdicate; 4620 4621 if (__predict_false(!iflib_is_running(ctx) || !LINK_ACTIVE(ctx))) { 4622 DBG_COUNTER_INC(tx_frees); 4623 m_freem(m); 4624 return (ENETDOWN); 4625 } 4626 4627 MPASS(m->m_nextpkt == NULL); 4628 /* ALTQ-enabled interfaces always use queue 0. */ 4629 qidx = 0; 4630 /* Use driver-supplied queue selection method if it exists */ 4631 if (ctx->isc_txq_select_v2) { 4632 struct if_pkt_info pi; 4633 uint64_t early_pullups = 0; 4634 memset(&pi, 0, sizeof(pi)); 4635 4636 err = iflib_parse_header_partial(&pi, &m, &early_pullups); 4637 if (__predict_false(err != 0)) { 4638 /* Assign pullups for bad pkts to default queue */ 4639 ctx->ifc_txqs[0].ift_pullups += early_pullups; 4640 DBG_COUNTER_INC(encap_txd_encap_fail); 4641 return (err); 4642 } 4643 /* Let driver make queueing decision */ 4644 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi); 4645 ctx->ifc_txqs[qidx].ift_pullups += early_pullups; 4646 } 4647 /* Backwards compatibility w/ simpler queue select */ 4648 else if (ctx->isc_txq_select) 4649 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4650 /* If not, use iflib's standard method */ 4651 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp)) 4652 qidx = QIDX(ctx, m); 4653 4654 /* Set TX queue */ 4655 txq = &ctx->ifc_txqs[qidx]; 4656 4657 #ifdef DRIVER_BACKPRESSURE 4658 if (txq->ift_closed) { 4659 while (m != NULL) { 4660 next = m->m_nextpkt; 4661 m->m_nextpkt = NULL; 4662 m_freem(m); 4663 DBG_COUNTER_INC(tx_frees); 4664 m = next; 4665 } 4666 return (ENOBUFS); 4667 } 4668 #endif 4669 #ifdef notyet 4670 qidx = count = 0; 4671 mp = marr; 4672 next = m; 4673 do { 4674 count++; 4675 next = next->m_nextpkt; 4676 } while (next != NULL); 4677 4678 if (count > nitems(marr)) 4679 if ((mp = malloc(count * sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4680 /* XXX check nextpkt */ 4681 m_freem(m); 4682 /* XXX simplify for now */ 4683 DBG_COUNTER_INC(tx_frees); 4684 return (ENOBUFS); 4685 } 4686 for (next = m, i = 0; next != NULL; i++) { 4687 mp[i] = next; 4688 next = next->m_nextpkt; 4689 mp[i]->m_nextpkt = NULL; 4690 } 4691 #endif 4692 DBG_COUNTER_INC(tx_seen); 4693 abdicate = ctx->ifc_sysctl_tx_abdicate; 4694 4695 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4696 4697 if (abdicate) 4698 GROUPTASK_ENQUEUE(&txq->ift_task); 4699 if (err) { 4700 if (!abdicate) 4701 GROUPTASK_ENQUEUE(&txq->ift_task); 4702 /* support forthcoming later */ 4703 #ifdef DRIVER_BACKPRESSURE 4704 txq->ift_closed = TRUE; 4705 #endif 4706 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4707 m_freem(m); 4708 DBG_COUNTER_INC(tx_frees); 4709 if (err == ENOBUFS) 4710 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1); 4711 else 4712 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 4713 } 4714 4715 return (err); 4716 } 4717 4718 #ifdef ALTQ 4719 /* 4720 * The overall approach to integrating iflib with ALTQ is to continue to use 4721 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4722 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4723 * is redundant/unnecessary, but doing so minimizes the amount of 4724 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4725 * redundantly queueing to an intermediate mp_ring is swamped by the 4726 * performance limitations inherent in using ALTQ. 4727 * 4728 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4729 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4730 * given interface. If ALTQ is enabled for an interface, then all 4731 * transmitted packets for that interface will be submitted to the ALTQ 4732 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4733 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4734 * update stats that the iflib machinery handles, and which is sensitve to 4735 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4736 * will be installed as the start routine for use by ALTQ facilities that 4737 * need to trigger queue drains on a scheduled basis. 4738 * 4739 */ 4740 static void 4741 iflib_altq_if_start(if_t ifp) 4742 { 4743 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */ 4744 struct mbuf *m; 4745 4746 IFQ_LOCK(ifq); 4747 IFQ_DEQUEUE_NOLOCK(ifq, m); 4748 while (m != NULL) { 4749 iflib_if_transmit(ifp, m); 4750 IFQ_DEQUEUE_NOLOCK(ifq, m); 4751 } 4752 IFQ_UNLOCK(ifq); 4753 } 4754 4755 static int 4756 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4757 { 4758 int err; 4759 4760 if (if_altq_is_enabled(ifp)) { 4761 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */ 4762 if (err == 0) 4763 if_start(ifp); 4764 return (err); 4765 } 4766 return (iflib_if_transmit(ifp, m)); 4767 } 4768 #endif /* ALTQ */ 4769 4770 static void 4771 iflib_if_qflush(if_t ifp) 4772 { 4773 if_ctx_t ctx = if_getsoftc(ifp); 4774 iflib_txq_t txq = ctx->ifc_txqs; 4775 int i; 4776 4777 STATE_LOCK(ctx); 4778 ctx->ifc_flags |= IFC_QFLUSH; 4779 STATE_UNLOCK(ctx); 4780 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4781 if (txq->ift_drbr != NULL) { 4782 mtx_lock(&txq->ift_mtx); 4783 drbr_flush(ifp, txq->ift_drbr); 4784 mtx_unlock(&txq->ift_mtx); 4785 continue; 4786 } 4787 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4788 iflib_txq_check_drain(txq, 0); 4789 } 4790 STATE_LOCK(ctx); 4791 ctx->ifc_flags &= ~IFC_QFLUSH; 4792 STATE_UNLOCK(ctx); 4793 4794 /* 4795 * When ALTQ is enabled, this will also take care of purging the 4796 * ALTQ queue(s). 4797 */ 4798 if_qflush(ifp); 4799 } 4800 4801 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4802 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4803 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4804 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4805 4806 static int 4807 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4808 { 4809 if_ctx_t ctx = if_getsoftc(ifp); 4810 struct ifreq *ifr = (struct ifreq *)data; 4811 #if defined(INET) || defined(INET6) 4812 struct ifaddr *ifa = (struct ifaddr *)data; 4813 #endif 4814 bool avoid_reset = false, restart; 4815 int err = 0, reinit = 0; 4816 4817 switch (command) { 4818 case SIOCSIFADDR: 4819 #ifdef INET 4820 if (ifa->ifa_addr->sa_family == AF_INET) 4821 avoid_reset = true; 4822 #endif 4823 #ifdef INET6 4824 if (ifa->ifa_addr->sa_family == AF_INET6) 4825 avoid_reset = true; 4826 #endif 4827 /* 4828 * Calling init results in link renegotiation, 4829 * so we avoid doing it when possible. 4830 */ 4831 if (avoid_reset) { 4832 if_setflagbits(ifp, IFF_UP, 0); 4833 if (!iflib_is_running(ctx)) 4834 reinit = 1; 4835 #ifdef INET 4836 if (!(if_getflags(ifp) & IFF_NOARP)) 4837 arp_ifinit(ifp, ifa); 4838 #endif 4839 } else 4840 err = ether_ioctl(ifp, command, data); 4841 break; 4842 case SIOCSIFMTU: 4843 CTX_LOCK(ctx); 4844 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4845 CTX_UNLOCK(ctx); 4846 break; 4847 } 4848 restart = ctx->ifc_datapath_state == IFLIB_DP_RUNNING || 4849 (if_getflags(ifp) & IFF_UP) != 0; 4850 /* Quiesce a datapath whose stopped state is not established. */ 4851 if (ctx->ifc_datapath_state != IFLIB_DP_STOPPED) 4852 iflib_stop(ctx); 4853 4854 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4855 STATE_LOCK(ctx); 4856 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4857 ctx->ifc_flags |= IFC_MULTISEG; 4858 else 4859 ctx->ifc_flags &= ~IFC_MULTISEG; 4860 STATE_UNLOCK(ctx); 4861 err = if_setmtu(ifp, ifr->ifr_mtu); 4862 } 4863 if (restart) 4864 iflib_init_locked(ctx); 4865 CTX_UNLOCK(ctx); 4866 break; 4867 case SIOCSIFFLAGS: 4868 CTX_LOCK(ctx); 4869 if (if_getflags(ifp) & IFF_UP) { 4870 if (iflib_is_running(ctx)) { 4871 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4872 (IFF_PROMISC | IFF_ALLMULTI)) { 4873 CTX_UNLOCK(ctx); 4874 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4875 CTX_LOCK(ctx); 4876 } 4877 } else 4878 reinit = 1; 4879 } else if (ctx->ifc_datapath_state != IFLIB_DP_STOPPED) { 4880 /* Stop partially initialized hardware as well as running queues. */ 4881 iflib_stop(ctx); 4882 } 4883 ctx->ifc_if_flags = if_getflags(ifp); 4884 CTX_UNLOCK(ctx); 4885 break; 4886 case SIOCADDMULTI: 4887 case SIOCDELMULTI: 4888 CTX_LOCK(ctx); 4889 if (iflib_is_running(ctx)) { 4890 IFDI_INTR_DISABLE(ctx); 4891 IFDI_MULTI_SET(ctx); 4892 IFDI_INTR_ENABLE(ctx); 4893 } 4894 CTX_UNLOCK(ctx); 4895 break; 4896 case SIOCSIFMEDIA: 4897 CTX_LOCK(ctx); 4898 IFDI_MEDIA_SET(ctx); 4899 CTX_UNLOCK(ctx); 4900 /* FALLTHROUGH */ 4901 case SIOCGIFMEDIA: 4902 case SIOCGIFXMEDIA: 4903 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4904 break; 4905 case SIOCGI2C: 4906 /* FALLTHROUGH */ 4907 case SIOCGI2CPB: 4908 { 4909 struct ifi2creq i2c; 4910 if_shared_ctx_t sctx = ctx->ifc_sctx; 4911 4912 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4913 if (err != 0) 4914 break; 4915 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4916 err = EINVAL; 4917 break; 4918 } 4919 if (i2c.len > sizeof(i2c.data)) { 4920 err = EINVAL; 4921 break; 4922 } 4923 if (command == SIOCGI2C) { 4924 i2c.page = i2c.bank = 0; 4925 } else if ((sctx->isc_flags & IFLIB_I2C_PAGE_BANK) == 0) { 4926 err = EINVAL; 4927 break; 4928 } 4929 4930 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4931 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4932 sizeof(i2c)); 4933 break; 4934 } 4935 case SIOCSIFCAP: 4936 { 4937 int mask, setmask, oldmask; 4938 4939 oldmask = if_getcapenable(ifp); 4940 mask = ifr->ifr_reqcap ^ oldmask; 4941 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4942 setmask = 0; 4943 #ifdef TCP_OFFLOAD 4944 setmask |= mask & (IFCAP_TOE4 | IFCAP_TOE6); 4945 #endif 4946 setmask |= (mask & IFCAP_FLAGS); 4947 setmask |= (mask & IFCAP_WOL); 4948 4949 /* 4950 * If any RX csum has changed, change all the ones that 4951 * are supported by the driver. 4952 */ 4953 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4954 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4955 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4956 } 4957 4958 /* 4959 * want to ensure that traffic has stopped before we change any of the flags 4960 */ 4961 if (setmask) { 4962 CTX_LOCK(ctx); 4963 restart = (setmask & ~IFCAP_WOL) != 0 && 4964 (ctx->ifc_datapath_state == IFLIB_DP_RUNNING || 4965 (if_getflags(ifp) & IFF_UP) != 0); 4966 if (restart) 4967 iflib_stop(ctx); 4968 STATE_LOCK(ctx); 4969 if_togglecapenable(ifp, setmask); 4970 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4971 STATE_UNLOCK(ctx); 4972 if (restart) 4973 iflib_init_locked(ctx); 4974 CTX_UNLOCK(ctx); 4975 } 4976 if_vlancap(ifp); 4977 break; 4978 } 4979 case SIOCGPRIVATE_0: 4980 case SIOCSDRVSPEC: 4981 case SIOCGDRVSPEC: 4982 CTX_LOCK(ctx); 4983 err = IFDI_PRIV_IOCTL(ctx, command, data); 4984 CTX_UNLOCK(ctx); 4985 break; 4986 case SIOCGIFDOWNREASON: 4987 CTX_LOCK(ctx); 4988 err = IFDI_GET_DOWNREASON(ctx, (struct ifdownreason *)data); 4989 CTX_UNLOCK(ctx); 4990 break; 4991 default: 4992 err = ether_ioctl(ifp, command, data); 4993 break; 4994 } 4995 if (reinit) 4996 iflib_if_init(ctx); 4997 return (err); 4998 } 4999 5000 static int 5001 iflib_if_vf_status(if_t ifp, struct if_vf_status **statusp) 5002 { 5003 if_ctx_t ctx; 5004 int error; 5005 5006 ctx = if_getsoftc(ifp); 5007 CTX_LOCK(ctx); 5008 error = IFDI_VF_STATUS(ctx, statusp); 5009 CTX_UNLOCK(ctx); 5010 return (error); 5011 } 5012 5013 static uint64_t 5014 iflib_if_get_counter(if_t ifp, ift_counter cnt) 5015 { 5016 if_ctx_t ctx = if_getsoftc(ifp); 5017 5018 return (IFDI_GET_COUNTER(ctx, cnt)); 5019 } 5020 5021 /********************************************************************* 5022 * 5023 * OTHER FUNCTIONS EXPORTED TO THE STACK 5024 * 5025 **********************************************************************/ 5026 5027 static void 5028 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 5029 { 5030 if_ctx_t ctx = if_getsoftc(ifp); 5031 bool restart; 5032 5033 if ((void *)ctx != arg) 5034 return; 5035 5036 if ((vtag == 0) || (vtag > 4095)) 5037 return; 5038 5039 if (iflib_in_detach(ctx)) 5040 return; 5041 5042 CTX_LOCK(ctx); 5043 restart = IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG) && 5044 ((if_getflags(ifp) & IFF_UP) != 0 || 5045 ctx->ifc_datapath_state == IFLIB_DP_RUNNING); 5046 /* Driver may need all untagged packets to be flushed */ 5047 if (restart) 5048 iflib_stop(ctx); 5049 IFDI_VLAN_REGISTER(ctx, vtag); 5050 /* Re-init to load the changes, if required */ 5051 if (restart) 5052 iflib_init_locked(ctx); 5053 CTX_UNLOCK(ctx); 5054 } 5055 5056 static void 5057 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 5058 { 5059 if_ctx_t ctx = if_getsoftc(ifp); 5060 bool restart; 5061 5062 if ((void *)ctx != arg) 5063 return; 5064 5065 if ((vtag == 0) || (vtag > 4095)) 5066 return; 5067 5068 CTX_LOCK(ctx); 5069 restart = IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG) && 5070 ((if_getflags(ifp) & IFF_UP) != 0 || 5071 ctx->ifc_datapath_state == IFLIB_DP_RUNNING); 5072 /* Driver may need all tagged packets to be flushed */ 5073 if (restart) 5074 iflib_stop(ctx); 5075 IFDI_VLAN_UNREGISTER(ctx, vtag); 5076 /* Re-init to load the changes, if required */ 5077 if (restart) 5078 iflib_init_locked(ctx); 5079 CTX_UNLOCK(ctx); 5080 } 5081 5082 static void 5083 _task_fn_led(void *context, int pending __unused) 5084 { 5085 if_ctx_t ctx = context; 5086 bool in_detach; 5087 int onoff; 5088 5089 STATE_LOCK(ctx); 5090 in_detach = (ctx->ifc_flags & IFC_IN_DETACH) != 0; 5091 onoff = ctx->ifc_led_state; 5092 STATE_UNLOCK(ctx); 5093 if (in_detach) 5094 return; 5095 5096 CTX_LOCK(ctx); 5097 if (ctx->ifc_pm_state == IFLIB_PM_ACTIVE) 5098 IFDI_LED_FUNC(ctx, onoff); 5099 CTX_UNLOCK(ctx); 5100 } 5101 5102 static void 5103 iflib_led_func(void *arg, int onoff) 5104 { 5105 if_ctx_t ctx = arg; 5106 bool in_detach; 5107 5108 /* led(4) may invoke this callback from a non-sleepable callout. */ 5109 STATE_LOCK(ctx); 5110 ctx->ifc_led_state = onoff; 5111 in_detach = (ctx->ifc_flags & IFC_IN_DETACH) != 0; 5112 STATE_UNLOCK(ctx); 5113 if (!in_detach) 5114 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_led_task); 5115 } 5116 5117 /********************************************************************* 5118 * 5119 * BUS FUNCTION DEFINITIONS 5120 * 5121 **********************************************************************/ 5122 5123 int 5124 iflib_device_probe(device_t dev) 5125 { 5126 const pci_vendor_info_t *ent; 5127 if_shared_ctx_t sctx; 5128 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 5129 uint16_t pci_vendor_id; 5130 5131 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5132 return (ENOTSUP); 5133 5134 pci_vendor_id = pci_get_vendor(dev); 5135 pci_device_id = pci_get_device(dev); 5136 pci_subvendor_id = pci_get_subvendor(dev); 5137 pci_subdevice_id = pci_get_subdevice(dev); 5138 pci_rev_id = pci_get_revid(dev); 5139 if (sctx->isc_parse_devinfo != NULL) 5140 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 5141 5142 ent = sctx->isc_vendor_info; 5143 while (ent->pvi_vendor_id != 0) { 5144 if (pci_vendor_id != ent->pvi_vendor_id) { 5145 ent++; 5146 continue; 5147 } 5148 if ((pci_device_id == ent->pvi_device_id) && 5149 ((pci_subvendor_id == ent->pvi_subvendor_id) || 5150 (ent->pvi_subvendor_id == 0)) && 5151 ((pci_subdevice_id == ent->pvi_subdevice_id) || 5152 (ent->pvi_subdevice_id == 0)) && 5153 ((pci_rev_id == ent->pvi_rev_id) || 5154 (ent->pvi_rev_id == 0))) { 5155 device_set_desc_copy(dev, ent->pvi_name); 5156 /* this needs to be changed to zero if the bus probing code 5157 * ever stops re-probing on best match because the sctx 5158 * may have its values over written by register calls 5159 * in subsequent probes 5160 */ 5161 return (BUS_PROBE_DEFAULT); 5162 } 5163 ent++; 5164 } 5165 return (ENXIO); 5166 } 5167 5168 int 5169 iflib_device_probe_vendor(device_t dev) 5170 { 5171 int probe; 5172 5173 probe = iflib_device_probe(dev); 5174 if (probe == BUS_PROBE_DEFAULT) 5175 return (BUS_PROBE_VENDOR); 5176 else 5177 return (probe); 5178 } 5179 5180 static void 5181 iflib_reset_qvalues(if_ctx_t ctx) 5182 { 5183 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5184 if_shared_ctx_t sctx = ctx->ifc_sctx; 5185 device_t dev = ctx->ifc_dev; 5186 int i; 5187 5188 if (ctx->ifc_sysctl_ntxqs != 0) 5189 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 5190 if (ctx->ifc_sysctl_nrxqs != 0) 5191 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 5192 5193 for (i = 0; i < sctx->isc_ntxqs; i++) { 5194 if (ctx->ifc_sysctl_ntxds[i] != 0) 5195 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 5196 else 5197 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 5198 } 5199 5200 for (i = 0; i < sctx->isc_nrxqs; i++) { 5201 if (ctx->ifc_sysctl_nrxds[i] != 0) 5202 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 5203 else 5204 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 5205 } 5206 5207 for (i = 0; i < sctx->isc_nrxqs; i++) { 5208 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 5209 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 5210 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 5211 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 5212 } 5213 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 5214 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 5215 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 5216 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 5217 } 5218 if (!powerof2(scctx->isc_nrxd[i])) { 5219 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 5220 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 5221 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 5222 } 5223 } 5224 5225 for (i = 0; i < sctx->isc_ntxqs; i++) { 5226 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 5227 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 5228 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 5229 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 5230 } 5231 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 5232 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 5233 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 5234 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 5235 } 5236 if (!powerof2(scctx->isc_ntxd[i])) { 5237 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 5238 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 5239 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 5240 } 5241 } 5242 scctx->isc_tx_pad = 2; 5243 } 5244 5245 static void 5246 iflib_add_pfil(if_ctx_t ctx) 5247 { 5248 struct pfil_head *pfil; 5249 struct pfil_head_args pa; 5250 iflib_rxq_t rxq; 5251 int i; 5252 5253 pa.pa_version = PFIL_VERSION; 5254 pa.pa_flags = PFIL_IN; 5255 pa.pa_type = PFIL_TYPE_ETHERNET; 5256 pa.pa_headname = if_name(ctx->ifc_ifp); 5257 pfil = pfil_head_register(&pa); 5258 5259 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5260 rxq->pfil = pfil; 5261 } 5262 } 5263 5264 static void 5265 iflib_rem_pfil(if_ctx_t ctx) 5266 { 5267 struct pfil_head *pfil; 5268 iflib_rxq_t rxq; 5269 int i; 5270 5271 rxq = ctx->ifc_rxqs; 5272 pfil = rxq->pfil; 5273 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 5274 rxq->pfil = NULL; 5275 } 5276 pfil_head_unregister(pfil); 5277 } 5278 5279 5280 /* 5281 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 5282 * cpuid and wrapping as necessary. 5283 */ 5284 static unsigned int 5285 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 5286 { 5287 unsigned int first_valid; 5288 unsigned int last_valid; 5289 5290 /* cpuid should always be in the valid set */ 5291 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 5292 5293 /* valid set should never be empty */ 5294 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 5295 5296 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 5297 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 5298 n = n % CPU_COUNT(&ctx->ifc_cpus); 5299 while (n > 0) { 5300 do { 5301 cpuid++; 5302 if (cpuid > last_valid) 5303 cpuid = first_valid; 5304 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 5305 n--; 5306 } 5307 5308 return (cpuid); 5309 } 5310 5311 /* 5312 * CPU mapping behaviors 5313 * --------------------- 5314 * 'separate txrx' refers to the separate_txrx sysctl 5315 * 'use logical' refers to the use_logical_cores sysctl 5316 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 5317 * 5318 * separate use INTR 5319 * txrx logical CPUS result 5320 * ---------- --------- ------ ------------------------------------------------ 5321 * - - X RX and TX queues mapped to consecutive physical 5322 * cores with RX/TX pairs on same core and excess 5323 * of either following 5324 * - X X RX and TX queues mapped to consecutive cores 5325 * of any type with RX/TX pairs on same core and 5326 * excess of either following 5327 * X - X RX and TX queues mapped to consecutive physical 5328 * cores; all RX then all TX 5329 * X X X RX queues mapped to consecutive physical cores 5330 * first, then TX queues mapped to L2 neighbor of 5331 * the corresponding RX queue if one exists, 5332 * otherwise to consecutive physical cores 5333 * - n/a - RX and TX queues mapped to consecutive cores of 5334 * any type with RX/TX pairs on same core and excess 5335 * of either following 5336 * X n/a - RX and TX queues mapped to consecutive cores of 5337 * any type; all RX then all TX 5338 */ 5339 static unsigned int 5340 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 5341 bool is_tx) 5342 { 5343 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5344 unsigned int core_index; 5345 5346 if (ctx->ifc_sysctl_separate_txrx) { 5347 /* 5348 * When using separate CPUs for TX and RX, the assignment 5349 * will always be of a consecutive CPU out of the set of 5350 * context CPUs, except for the specific case where the 5351 * context CPUs are phsyical cores, the use of logical cores 5352 * has been enabled, the assignment is for TX, the TX qid 5353 * corresponds to an RX qid, and the CPU assigned to the 5354 * corresponding RX queue has an L2 neighbor. 5355 */ 5356 if (ctx->ifc_sysctl_use_logical_cores && 5357 ctx->ifc_cpus_are_physical_cores && 5358 is_tx && qid < scctx->isc_nrxqsets) { 5359 int l2_neighbor; 5360 unsigned int rx_cpuid; 5361 5362 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 5363 l2_neighbor = sched_find_l2_neighbor(rx_cpuid); 5364 if (l2_neighbor != -1) { 5365 return (l2_neighbor); 5366 } 5367 /* 5368 * ... else fall through to the normal 5369 * consecutive-after-RX assignment scheme. 5370 * 5371 * Note that we are assuming that all RX queue CPUs 5372 * have an L2 neighbor, or all do not. If a mixed 5373 * scenario is possible, we will have to keep track 5374 * separately of how many queues prior to this one 5375 * were not able to be assigned to an L2 neighbor. 5376 */ 5377 } 5378 if (is_tx) 5379 core_index = scctx->isc_nrxqsets + qid; 5380 else 5381 core_index = qid; 5382 } else { 5383 core_index = qid; 5384 } 5385 5386 return (cpuid_advance(ctx, base_cpuid, core_index)); 5387 } 5388 5389 static uint16_t 5390 get_ctx_core_offset(if_ctx_t ctx) 5391 { 5392 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5393 struct cpu_offset *op; 5394 cpuset_t assigned_cpus; 5395 unsigned int cores_consumed; 5396 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 5397 unsigned int first_valid; 5398 unsigned int last_valid; 5399 unsigned int i; 5400 5401 MPASS(!ctx->ifc_core_offset_ref); 5402 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 5403 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 5404 5405 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 5406 /* 5407 * Align the user-chosen base CPU ID to the next valid CPU 5408 * for this device. If the chosen base CPU ID is smaller 5409 * than the first valid CPU or larger than the last valid 5410 * CPU, we assume the user does not know what the valid 5411 * range is for this device and is thinking in terms of a 5412 * zero-based reference frame, and so we shift the given 5413 * value into the valid range (and wrap accordingly) so the 5414 * intent is translated to the proper frame of reference. 5415 * If the base CPU ID is within the valid first/last, but 5416 * does not correspond to a valid CPU, it is advanced to the 5417 * next valid CPU (wrapping if necessary). 5418 */ 5419 if (base_cpuid < first_valid || base_cpuid > last_valid) { 5420 /* shift from zero-based to first_valid-based */ 5421 base_cpuid += first_valid; 5422 /* wrap to range [first_valid, last_valid] */ 5423 base_cpuid = (base_cpuid - first_valid) % 5424 (last_valid - first_valid + 1); 5425 } 5426 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 5427 /* 5428 * base_cpuid is in [first_valid, last_valid], but 5429 * not a member of the valid set. In this case, 5430 * there will always be a member of the valid set 5431 * with a CPU ID that is greater than base_cpuid, 5432 * and we simply advance to it. 5433 */ 5434 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 5435 base_cpuid++; 5436 } 5437 return (base_cpuid); 5438 } 5439 5440 /* 5441 * Determine how many cores will be consumed by performing the CPU 5442 * assignments and counting how many of the assigned CPUs correspond 5443 * to CPUs in the set of context CPUs. This is done using the CPU 5444 * ID first_valid as the base CPU ID, as the base CPU must be within 5445 * the set of context CPUs. 5446 * 5447 * Note not all assigned CPUs will be in the set of context CPUs 5448 * when separate CPUs are being allocated to TX and RX queues, 5449 * assignment to logical cores has been enabled, the set of context 5450 * CPUs contains only physical CPUs, and TX queues are mapped to L2 5451 * neighbors of CPUs that RX queues have been mapped to - in this 5452 * case we do only want to count how many CPUs in the set of context 5453 * CPUs have been consumed, as that determines the next CPU in that 5454 * set to start allocating at for the next device for which 5455 * core_offset is not set. 5456 */ 5457 CPU_ZERO(&assigned_cpus); 5458 for (i = 0; i < scctx->isc_ntxqsets; i++) 5459 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 5460 &assigned_cpus); 5461 for (i = 0; i < scctx->isc_nrxqsets; i++) 5462 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 5463 &assigned_cpus); 5464 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 5465 cores_consumed = CPU_COUNT(&assigned_cpus); 5466 5467 mtx_lock(&cpu_offset_mtx); 5468 SLIST_FOREACH(op, &cpu_offsets, entries) { 5469 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5470 base_cpuid = op->next_cpuid; 5471 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 5472 cores_consumed); 5473 MPASS(op->refcount < UINT_MAX); 5474 op->refcount++; 5475 ctx->ifc_core_offset_ref = true; 5476 break; 5477 } 5478 } 5479 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 5480 base_cpuid = first_valid; 5481 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 5482 M_NOWAIT | M_ZERO); 5483 if (op == NULL) { 5484 device_printf(ctx->ifc_dev, 5485 "allocation for cpu offset failed.\n"); 5486 } else { 5487 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 5488 cores_consumed); 5489 op->refcount = 1; 5490 CPU_COPY(&ctx->ifc_cpus, &op->set); 5491 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 5492 ctx->ifc_core_offset_ref = true; 5493 } 5494 } 5495 mtx_unlock(&cpu_offset_mtx); 5496 5497 return (base_cpuid); 5498 } 5499 5500 static void 5501 unref_ctx_core_offset(if_ctx_t ctx) 5502 { 5503 struct cpu_offset *op, *top; 5504 5505 if (!ctx->ifc_core_offset_ref) 5506 return; 5507 5508 mtx_lock(&cpu_offset_mtx); 5509 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5510 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5511 MPASS(op->refcount > 0); 5512 op->refcount--; 5513 if (op->refcount == 0) { 5514 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5515 free(op, M_IFLIB); 5516 } 5517 ctx->ifc_core_offset_ref = false; 5518 break; 5519 } 5520 } 5521 mtx_unlock(&cpu_offset_mtx); 5522 MPASS(!ctx->ifc_core_offset_ref); 5523 } 5524 5525 static bool 5526 iflib_register_fail_device_matches(device_t dev) 5527 { 5528 const char *nameunit; 5529 5530 nameunit = device_get_nameunit(dev); 5531 return (iflib_register_fail_device[0] != '\0' && nameunit != NULL && 5532 strcmp(nameunit, iflib_register_fail_device) == 0); 5533 } 5534 5535 #define IFLIB_REGISTER_FAIL_POINT(_dev, _name, _error, _label) do { \ 5536 KFAIL_POINT_CODE_COND(_debug_fail_point_iflib, _name, \ 5537 iflib_register_fail_device_matches((_dev)), \ 5538 FAIL_POINT_NONSLEEPABLE, { \ 5539 (_error) = RETURN_VALUE; \ 5540 if ((_error) <= 0) \ 5541 (_error) = EIO; \ 5542 device_printf((_dev), \ 5543 "injecting iflib registration failure at %s: %d\n", \ 5544 #_name, (_error)); \ 5545 goto _label; \ 5546 }); \ 5547 } while (0) 5548 5549 int 5550 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5551 { 5552 if_ctx_t ctx; 5553 if_t ifp; 5554 if_softc_ctx_t scctx; 5555 kobjop_desc_t kobj_desc; 5556 kobj_method_t *kobj_method; 5557 bool attach_pre_succeeded, intr_allocated, queues_allocated; 5558 int err, msix, rid; 5559 #ifdef PCI_IOV 5560 int iov_error; 5561 #endif 5562 int num_txd, num_rxd; 5563 char namebuf[TASKQUEUE_NAMELEN]; 5564 5565 attach_pre_succeeded = false; 5566 intr_allocated = false; 5567 queues_allocated = false; 5568 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK | M_ZERO); 5569 ctx->ifc_datapath_state = IFLIB_DP_UNKNOWN; 5570 ctx->ifc_pm_state = IFLIB_PM_ACTIVE; 5571 5572 if (sc == NULL) { 5573 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK | M_ZERO); 5574 device_set_softc(dev, ctx); 5575 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5576 } 5577 5578 ctx->ifc_sctx = sctx; 5579 ctx->ifc_dev = dev; 5580 ctx->ifc_softc = sc; 5581 5582 iflib_register(ctx); 5583 iflib_add_device_sysctl_pre(ctx); 5584 5585 scctx = &ctx->ifc_softc_ctx; 5586 ifp = ctx->ifc_ifp; 5587 if (ctx->ifc_sysctl_simple_tx) { 5588 /* if_start drives the same drbr drain when ALTQ is active. */ 5589 if_settransmitfn(ifp, iflib_simple_transmit); 5590 if_setstartfn(ifp, iflib_simple_if_start); 5591 device_printf(dev, "using simple transmit\n"); 5592 } 5593 iflib_reset_qvalues(ctx); 5594 CTX_LOCK(ctx); 5595 IFLIB_REGISTER_FAIL_POINT(dev, register_before_attach_pre, err, 5596 fail_cleanup); 5597 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5598 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5599 goto fail_cleanup; 5600 } 5601 attach_pre_succeeded = true; 5602 IFLIB_REGISTER_FAIL_POINT(dev, register_after_attach_pre, err, 5603 fail_cleanup); 5604 _iflib_pre_assert(scctx); 5605 ctx->ifc_txrx = *scctx->isc_txrx; 5606 /* 5607 * Bind optional queue selection to a transmit entry point once, rather 5608 * than testing for optional methods for every packet. Prefer v2 when 5609 * the driver provides both methods. 5610 */ 5611 if (ctx->ifc_sysctl_simple_tx) { 5612 if (ctx->isc_txq_select_v2 != NULL) 5613 if_settransmitfn(ifp, 5614 iflib_simple_transmit_txq_select_v2); 5615 else if (ctx->isc_txq_select != NULL) 5616 if_settransmitfn(ifp, 5617 iflib_simple_transmit_txq_select); 5618 } 5619 5620 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5621 5622 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5623 ctx->ifc_mediap = scctx->isc_media; 5624 5625 #ifdef INVARIANTS 5626 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5627 MPASS(scctx->isc_tx_csum_flags); 5628 #endif 5629 5630 if_setcapabilities(ifp, 5631 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5632 if_setcapenable(ifp, 5633 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5634 5635 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5636 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5637 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5638 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5639 5640 num_txd = iflib_num_tx_descs(ctx); 5641 num_rxd = iflib_num_rx_descs(ctx); 5642 5643 /* XXX change for per-queue sizes */ 5644 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5645 num_txd, num_rxd); 5646 5647 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5648 scctx->isc_tx_nsegments = max(1, num_txd / 5649 MAX_SINGLE_PACKET_FRACTION); 5650 if (scctx->isc_tx_tso_segments_max > num_txd / 5651 MAX_SINGLE_PACKET_FRACTION) 5652 scctx->isc_tx_tso_segments_max = max(1, 5653 num_txd / MAX_SINGLE_PACKET_FRACTION); 5654 5655 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5656 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5657 /* 5658 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5659 * but some MACs do. 5660 */ 5661 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5662 IP_MAXPACKET)); 5663 /* 5664 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5665 * into account. In the worst case, each of these calls will 5666 * add another mbuf and, thus, the requirement for another DMA 5667 * segment. So for best performance, it doesn't make sense to 5668 * advertize a maximum of TSO segments that typically will 5669 * require defragmentation in iflib_encap(). 5670 */ 5671 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5672 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5673 } 5674 if (scctx->isc_rss_table_size == 0) 5675 scctx->isc_rss_table_size = 64; 5676 scctx->isc_rss_table_mask = scctx->isc_rss_table_size - 1; 5677 5678 /* Create and start admin taskqueue */ 5679 snprintf(namebuf, TASKQUEUE_NAMELEN, "if_%s_tq", device_get_nameunit(dev)); 5680 ctx->ifc_tq = taskqueue_create_fast(namebuf, M_NOWAIT, 5681 taskqueue_thread_enqueue, &ctx->ifc_tq); 5682 if (ctx->ifc_tq == NULL) { 5683 device_printf(dev, "Unable to create admin taskqueue\n"); 5684 err = ENOMEM; 5685 goto fail_cleanup; 5686 } 5687 5688 err = taskqueue_start_threads(&ctx->ifc_tq, 1, PI_NET, "%s", namebuf); 5689 if (err) { 5690 device_printf(dev, 5691 "Unable to start admin taskqueue threads error: %d\n", 5692 err); 5693 taskqueue_free(ctx->ifc_tq); 5694 ctx->ifc_tq = NULL; 5695 goto fail_cleanup; 5696 } 5697 5698 TASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5699 TASK_INIT(&ctx->ifc_led_task, 0, _task_fn_led, ctx); 5700 TASK_INIT(&ctx->ifc_vflr_task, 0, _task_fn_iov, ctx); 5701 IFLIB_REGISTER_FAIL_POINT(dev, register_after_taskqueue, err, 5702 fail_cleanup); 5703 5704 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5705 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5706 device_printf(dev, "Unable to fetch CPU list\n"); 5707 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5708 ctx->ifc_cpus_are_physical_cores = false; 5709 } else 5710 ctx->ifc_cpus_are_physical_cores = true; 5711 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5712 5713 /* 5714 * Now set up MSI or MSI-X, should return us the number of supported 5715 * vectors (will be 1 for a legacy interrupt and MSI). 5716 */ 5717 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5718 msix = scctx->isc_vectors; 5719 } else if (scctx->isc_msix_bar != 0) 5720 /* 5721 * The simple fact that isc_msix_bar is not 0 does not mean we 5722 * we have a good value there that is known to work. 5723 */ 5724 msix = iflib_msix_init(ctx); 5725 else { 5726 scctx->isc_vectors = 1; 5727 scctx->isc_ntxqsets = 1; 5728 scctx->isc_nrxqsets = 1; 5729 scctx->isc_intr = IFLIB_INTR_LEGACY; 5730 msix = 0; 5731 } 5732 intr_allocated = true; 5733 IFLIB_REGISTER_FAIL_POINT(dev, register_after_interrupts, err, 5734 fail_cleanup); 5735 /* Get memory for the station queues */ 5736 if ((err = iflib_queues_alloc(ctx))) { 5737 device_printf(dev, "Unable to allocate queue memory\n"); 5738 goto fail_cleanup; 5739 } 5740 queues_allocated = true; 5741 5742 if ((err = iflib_qset_structures_setup(ctx))) 5743 goto fail_cleanup; 5744 5745 /* 5746 * Now that we know how many queues there are, get the core offset. 5747 */ 5748 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5749 IFLIB_REGISTER_FAIL_POINT(dev, register_after_queues, err, 5750 fail_cleanup); 5751 5752 if (msix > 1) { 5753 /* 5754 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5755 * aren't the default NULL implementation. 5756 */ 5757 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5758 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5759 kobj_desc); 5760 if (kobj_method == &kobj_desc->deflt) { 5761 device_printf(dev, 5762 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5763 err = EOPNOTSUPP; 5764 goto fail_cleanup; 5765 } 5766 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5767 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5768 kobj_desc); 5769 if (kobj_method == &kobj_desc->deflt) { 5770 device_printf(dev, 5771 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5772 err = EOPNOTSUPP; 5773 goto fail_cleanup; 5774 } 5775 5776 /* 5777 * Assign the MSI-X vectors. 5778 * Note that the default NULL ifdi_msix_intr_assign method will 5779 * fail here, too. 5780 */ 5781 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5782 if (err != 0) { 5783 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5784 err); 5785 goto fail_cleanup; 5786 } 5787 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5788 rid = 0; 5789 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5790 MPASS(msix == 1); 5791 rid = 1; 5792 } 5793 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5794 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5795 goto fail_cleanup; 5796 } 5797 } else { 5798 device_printf(dev, 5799 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5800 err = ENODEV; 5801 goto fail_cleanup; 5802 } 5803 5804 /* 5805 * It prevents a double-locking panic with iflib_media_status when 5806 * the driver loads. 5807 */ 5808 CTX_UNLOCK(ctx); 5809 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5810 CTX_LOCK(ctx); 5811 5812 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5813 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5814 goto fail_detach; 5815 } 5816 IFLIB_REGISTER_FAIL_POINT(dev, register_after_attach_post, err, 5817 fail_detach); 5818 5819 /* 5820 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5821 * This must appear after the call to ether_ifattach() because 5822 * ether_ifattach() sets if_hdrlen to the default value. 5823 */ 5824 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5825 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5826 5827 if ((err = iflib_netmap_attach(ctx))) { 5828 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5829 goto fail_detach; 5830 } 5831 *ctxp = ctx; 5832 5833 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5834 5835 iflib_add_device_sysctl_post(ctx); 5836 iflib_add_pfil(ctx); 5837 ctx->ifc_flags |= IFC_INIT_DONE; 5838 CTX_UNLOCK(ctx); 5839 5840 /* Create led(4) devices if the driver defined the method */ 5841 kobj_desc = &ifdi_led_func_desc; 5842 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5843 kobj_desc); 5844 if (kobj_method != &kobj_desc->deflt && IFDI_LED_SUPPORTED(ctx)) 5845 iflib_led_create(ctx); 5846 5847 return (0); 5848 5849 fail_detach: 5850 STATE_LOCK(ctx); 5851 ctx->ifc_flags |= IFC_IN_DETACH; 5852 STATE_UNLOCK(ctx); 5853 /* Tasks may need the context lock; ether_ifdetach() may sleep. */ 5854 CTX_UNLOCK(ctx); 5855 taskqueue_drain_all(ctx->ifc_tq); 5856 #ifdef PCI_IOV 5857 /* 5858 * IFDI_ATTACH_POST may have registered an SR-IOV schema. Match the 5859 * normal deregistration order so a failed attach cannot leave a stale 5860 * /dev/iov node behind. device_attach() holds Giant throughout this 5861 * path, so an IOV configuration cannot race the detach. 5862 */ 5863 if (!CTX_IS_VF(ctx)) { 5864 iov_error = pci_iov_detach(dev); 5865 if (iov_error != 0) 5866 device_printf(dev, "Could not detach SR-IOV after " 5867 "attach failure: %d\n", iov_error); 5868 } 5869 #endif 5870 ether_ifdetach(ctx->ifc_ifp); 5871 CTX_LOCK(ctx); 5872 goto fail_cleanup_detaching; 5873 5874 fail_cleanup: 5875 STATE_LOCK(ctx); 5876 ctx->ifc_flags |= IFC_IN_DETACH; 5877 STATE_UNLOCK(ctx); 5878 5879 fail_cleanup_detaching: 5880 /* 5881 * The pre-attach sysctls contain pointers into ctx. Remove them on 5882 * every registration failure before iflib_deregister() frees ctx. 5883 */ 5884 if (ctx->ifc_sysctl_node != NULL) { 5885 sysctl_ctx_free(&ctx->ifc_sysctl_ctx); 5886 ctx->ifc_sysctl_node = NULL; 5887 } 5888 5889 if (ctx->ifc_tq != NULL) { 5890 /* 5891 * Drain without holding the context lock so configuration tasks can 5892 * run to completion. On fail_detach a second drain also catches 5893 * tasks queued during the first drain. 5894 */ 5895 CTX_UNLOCK(ctx); 5896 taskqueue_drain_all(ctx->ifc_tq); 5897 CTX_LOCK(ctx); 5898 } 5899 5900 if (queues_allocated) { 5901 iflib_tqg_detach(ctx); 5902 iflib_tx_structures_free(ctx); 5903 iflib_rx_structures_free(ctx); 5904 } 5905 5906 /* 5907 * A successful IFDI_ATTACH_PRE must be matched by IFDI_DETACH, even 5908 * when registration fails before queue allocation. Match 5909 * iflib_device_deregister by detaching before taskqueue_free. 5910 */ 5911 if (attach_pre_succeeded) { 5912 IFDI_DETACH(ctx); 5913 if (queues_allocated) 5914 IFDI_QUEUES_FREE(ctx); 5915 } 5916 if (ctx->ifc_tq != NULL) { 5917 taskqueue_free(ctx->ifc_tq); 5918 ctx->ifc_tq = NULL; 5919 } 5920 if (intr_allocated) 5921 iflib_free_intr_mem(ctx); 5922 5923 CTX_UNLOCK(ctx); 5924 iflib_deregister(ctx); 5925 device_set_softc(ctx->ifc_dev, NULL); 5926 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5927 free(ctx->ifc_softc, M_IFLIB); 5928 unref_ctx_core_offset(ctx); 5929 free(ctx, M_IFLIB); 5930 return (err); 5931 } 5932 5933 int 5934 iflib_device_attach(device_t dev) 5935 { 5936 if_ctx_t ctx; 5937 if_shared_ctx_t sctx; 5938 5939 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5940 return (ENOTSUP); 5941 5942 pci_enable_busmaster(dev); 5943 5944 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5945 } 5946 5947 int 5948 iflib_device_deregister(if_ctx_t ctx) 5949 { 5950 if_t ifp = ctx->ifc_ifp; 5951 device_t dev = ctx->ifc_dev; 5952 int error; 5953 5954 /* Make sure VLANS are not using driver */ 5955 if (if_vlantrunkinuse(ifp)) { 5956 device_printf(dev, "Vlan in use, detach first\n"); 5957 return (EBUSY); 5958 } 5959 #ifdef PCI_IOV 5960 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5961 device_printf(dev, "SR-IOV in use; detach first.\n"); 5962 return (EBUSY); 5963 } 5964 #endif 5965 5966 /* 5967 * Establish any ordering required by the terminal stop while the 5968 * interface is still intact. Once this succeeds, mark the context 5969 * inactive before releasing the lock so configuration tasks cannot 5970 * consume partially applied policy. 5971 */ 5972 CTX_LOCK(ctx); 5973 error = IFDI_POWER_PREPARE(ctx, IFLIB_POWER_DETACH); 5974 if (error != 0) { 5975 CTX_UNLOCK(ctx); 5976 return (error); 5977 } 5978 STATE_LOCK(ctx); 5979 ctx->ifc_flags |= IFC_IN_DETACH; 5980 STATE_UNLOCK(ctx); 5981 ctx->ifc_pm_state = IFLIB_PM_SUSPENDING; 5982 CTX_UNLOCK(ctx); 5983 5984 sysctl_ctx_free(&ctx->ifc_sysctl_ctx); 5985 ctx->ifc_sysctl_node = NULL; 5986 5987 /* Unregister VLAN handlers before calling iflib_stop() */ 5988 iflib_unregister_vlan_handlers(ctx); 5989 5990 iflib_netmap_detach(ifp); 5991 /* 5992 * A task that passed its IFC_IN_DETACH check before the flag was set 5993 * can still report a link change. Drain every private task before 5994 * ether_ifdetach() performs the final if_linktask drain. Drivers may 5995 * register their own link-related tasks on this taskqueue. 5996 */ 5997 taskqueue_drain_all(ctx->ifc_tq); 5998 ether_ifdetach(ifp); 5999 6000 CTX_LOCK(ctx); 6001 iflib_stop(ctx); 6002 CTX_UNLOCK(ctx); 6003 6004 iflib_rem_pfil(ctx); 6005 if (ctx->ifc_led_dev != NULL) { 6006 led_destroy(ctx->ifc_led_dev); 6007 taskqueue_drain(ctx->ifc_tq, &ctx->ifc_led_task); 6008 } 6009 6010 iflib_tqg_detach(ctx); 6011 iflib_tx_structures_free(ctx); 6012 iflib_rx_structures_free(ctx); 6013 6014 CTX_LOCK(ctx); 6015 IFDI_DETACH(ctx); 6016 IFDI_QUEUES_FREE(ctx); 6017 CTX_UNLOCK(ctx); 6018 6019 taskqueue_free(ctx->ifc_tq); 6020 ctx->ifc_tq = NULL; 6021 6022 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 6023 iflib_free_intr_mem(ctx); 6024 6025 bus_generic_detach(dev); 6026 6027 iflib_deregister(ctx); 6028 6029 device_set_softc(ctx->ifc_dev, NULL); 6030 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 6031 free(ctx->ifc_softc, M_IFLIB); 6032 unref_ctx_core_offset(ctx); 6033 free(ctx, M_IFLIB); 6034 return (0); 6035 } 6036 6037 static void 6038 iflib_tqg_detach(if_ctx_t ctx) 6039 { 6040 iflib_txq_t txq; 6041 iflib_rxq_t rxq; 6042 int i; 6043 struct taskqgroup *tqg; 6044 6045 /* XXX drain any dependent tasks */ 6046 tqg = qgroup_if_io_tqg; 6047 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 6048 callout_drain(&txq->ift_timer); 6049 #ifdef DEV_NETMAP 6050 callout_drain(&txq->ift_netmap_timer); 6051 #endif /* DEV_NETMAP */ 6052 if (txq->ift_task.gt_uniq != NULL) 6053 taskqgroup_detach(tqg, &txq->ift_task); 6054 } 6055 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 6056 if (rxq->ifr_task.gt_uniq != NULL) 6057 taskqgroup_detach(tqg, &rxq->ifr_task); 6058 } 6059 } 6060 6061 static void 6062 iflib_free_intr_mem(if_ctx_t ctx) 6063 { 6064 6065 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 6066 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 6067 } 6068 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 6069 pci_release_msi(ctx->ifc_dev); 6070 } 6071 if (ctx->ifc_msix_mem != NULL) { 6072 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 6073 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 6074 ctx->ifc_msix_mem = NULL; 6075 } 6076 } 6077 6078 int 6079 iflib_device_detach(device_t dev) 6080 { 6081 if_ctx_t ctx = device_get_softc(dev); 6082 6083 return (iflib_device_deregister(ctx)); 6084 } 6085 6086 static int 6087 iflib_device_resume_locked(if_ctx_t ctx) 6088 { 6089 if_t ifp; 6090 int error; 6091 6092 sx_assert(&ctx->ifc_ctx_sx, SA_XLOCKED); 6093 KASSERT(ctx->ifc_datapath_state == IFLIB_DP_STOPPED, 6094 ("iflib resume with active datapath state %d", 6095 ctx->ifc_datapath_state)); 6096 KASSERT(ctx->ifc_pm_state == IFLIB_PM_SUSPENDING || 6097 ctx->ifc_pm_state == IFLIB_PM_SUSPENDED, 6098 ("iflib resume from power state %d", ctx->ifc_pm_state)); 6099 6100 ifp = ctx->ifc_ifp; 6101 error = IFDI_RESUME(ctx); 6102 if (error != 0) 6103 return (error); 6104 ctx->ifc_pm_state = IFLIB_PM_ACTIVE; 6105 6106 if ((if_getflags(ifp) & IFF_UP) == 0) { 6107 STATE_LOCK(ctx); 6108 iflib_set_running(ctx, false); 6109 STATE_UNLOCK(ctx); 6110 return (0); 6111 } 6112 6113 iflib_init_locked(ctx); 6114 return (0); 6115 } 6116 6117 int 6118 iflib_device_suspend(device_t dev) 6119 { 6120 if_ctx_t ctx = device_get_softc(dev); 6121 int error, resume_error; 6122 6123 CTX_LOCK(ctx); 6124 error = IFDI_POWER_PREPARE(ctx, IFLIB_POWER_SUSPEND); 6125 if (error == 0) { 6126 iflib_stop(ctx); 6127 ctx->ifc_pm_state = IFLIB_PM_SUSPENDING; 6128 } 6129 CTX_UNLOCK(ctx); 6130 if (error != 0) 6131 return (error); 6132 6133 /* Driver configuration tasks must finish before entering low power. */ 6134 taskqueue_drain_all(ctx->ifc_tq); 6135 6136 CTX_LOCK(ctx); 6137 error = IFDI_SUSPEND(ctx); 6138 if (error == 0) 6139 ctx->ifc_pm_state = IFLIB_PM_SUSPENDED; 6140 else { 6141 resume_error = iflib_device_resume_locked(ctx); 6142 if (resume_error != 0) 6143 device_printf(dev, 6144 "failed to resume after suspend error: %d\n", 6145 resume_error); 6146 } 6147 CTX_UNLOCK(ctx); 6148 if (error != 0) 6149 return (error); 6150 6151 error = bus_generic_suspend(dev); 6152 if (error != 0) { 6153 CTX_LOCK(ctx); 6154 resume_error = iflib_device_resume_locked(ctx); 6155 CTX_UNLOCK(ctx); 6156 if (resume_error != 0) 6157 device_printf(dev, 6158 "failed to resume after child suspend error: %d\n", 6159 resume_error); 6160 } 6161 6162 return (error); 6163 } 6164 6165 int 6166 iflib_device_shutdown(device_t dev) 6167 { 6168 if_ctx_t ctx = device_get_softc(dev); 6169 int error; 6170 6171 CTX_LOCK(ctx); 6172 error = IFDI_POWER_PREPARE(ctx, IFLIB_POWER_SHUTDOWN); 6173 if (error == 0) { 6174 iflib_stop(ctx); 6175 ctx->ifc_pm_state = IFLIB_PM_SUSPENDING; 6176 } 6177 CTX_UNLOCK(ctx); 6178 if (error != 0) 6179 return (error); 6180 6181 taskqueue_drain_all(ctx->ifc_tq); 6182 6183 CTX_LOCK(ctx); 6184 error = IFDI_SHUTDOWN(ctx); 6185 if (error == 0) 6186 ctx->ifc_pm_state = IFLIB_PM_SUSPENDED; 6187 CTX_UNLOCK(ctx); 6188 if (error != 0) 6189 return (error); 6190 6191 return (bus_generic_suspend(dev)); 6192 } 6193 6194 int 6195 iflib_device_resume(device_t dev) 6196 { 6197 if_ctx_t ctx = device_get_softc(dev); 6198 iflib_txq_t txq = ctx->ifc_txqs; 6199 bool running; 6200 int error, child_error; 6201 6202 CTX_LOCK(ctx); 6203 error = iflib_device_resume_locked(ctx); 6204 running = ctx->ifc_datapath_state == IFLIB_DP_RUNNING; 6205 CTX_UNLOCK(ctx); 6206 if (running) { 6207 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 6208 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 6209 } 6210 6211 child_error = bus_generic_resume(dev); 6212 return (error != 0 ? error : child_error); 6213 } 6214 6215 int 6216 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 6217 { 6218 int error; 6219 if_ctx_t ctx = device_get_softc(dev); 6220 6221 CTX_LOCK(ctx); 6222 error = IFDI_IOV_INIT(ctx, num_vfs, params); 6223 CTX_UNLOCK(ctx); 6224 6225 return (error); 6226 } 6227 6228 int 6229 iflib_device_iov_init_restart(device_t dev, uint16_t num_vfs, 6230 const nvlist_t *params) 6231 { 6232 if_ctx_t ctx; 6233 if_t ifp; 6234 bool restart; 6235 int error; 6236 6237 ctx = device_get_softc(dev); 6238 ifp = ctx->ifc_ifp; 6239 6240 CTX_LOCK(ctx); 6241 /* 6242 * Drivers which change the PF queue layout need the complete iflib 6243 * stop/init sequence around their IOV callback. Administrative state 6244 * and software admission do not establish DMA quiescence: 6245 * failed initialization or a pending watchdog reset can leave DMA 6246 * active. Let iflib_stop() decide whether hardware needs quiescing, 6247 * and preserve administrative intent across the layout change. 6248 */ 6249 restart = (if_getflags(ifp) & IFF_UP) != 0; 6250 iflib_stop(ctx); 6251 error = IFDI_IOV_INIT(ctx, num_vfs, params); 6252 if (restart) 6253 iflib_init_locked(ctx); 6254 CTX_UNLOCK(ctx); 6255 return (error); 6256 } 6257 6258 void 6259 iflib_device_iov_uninit(device_t dev) 6260 { 6261 if_ctx_t ctx = device_get_softc(dev); 6262 6263 CTX_LOCK(ctx); 6264 IFDI_IOV_UNINIT(ctx); 6265 CTX_UNLOCK(ctx); 6266 } 6267 6268 void 6269 iflib_device_iov_uninit_restart(device_t dev) 6270 { 6271 if_ctx_t ctx; 6272 bool restart; 6273 6274 ctx = device_get_softc(dev); 6275 6276 CTX_LOCK(ctx); 6277 /* 6278 * Software admission can be closed while a watchdog reset is pending 6279 * but the hardware is still live. Always stop before the driver changes 6280 * its queue layout, and use IFF_UP only to preserve administrative intent. 6281 */ 6282 restart = (if_getflags(ctx->ifc_ifp) & IFF_UP) != 0; 6283 iflib_stop(ctx); 6284 IFDI_IOV_UNINIT(ctx); 6285 if (restart) 6286 iflib_init_locked(ctx); 6287 CTX_UNLOCK(ctx); 6288 } 6289 6290 int 6291 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 6292 { 6293 int error; 6294 if_ctx_t ctx = device_get_softc(dev); 6295 6296 CTX_LOCK(ctx); 6297 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 6298 CTX_UNLOCK(ctx); 6299 6300 return (error); 6301 } 6302 6303 /********************************************************************* 6304 * 6305 * MODULE FUNCTION DEFINITIONS 6306 * 6307 **********************************************************************/ 6308 6309 static void 6310 iflib_cpu_llc_init(void) 6311 { 6312 #ifdef SMP 6313 struct cpu_group *cg, *llc; 6314 uint16_t llc_id, first_llc_id; 6315 int cpu; 6316 #endif 6317 6318 iflib_single_llc = true; 6319 #ifdef SMP 6320 first_llc_id = USHRT_MAX; 6321 for (cpu = 0; cpu <= mp_maxid; cpu++) { 6322 if (CPU_ABSENT(cpu)) 6323 continue; 6324 6325 /* 6326 * Select the outermost shared-cache group containing this 6327 * CPU. On AMD systems this is the L3/CCX group. This also 6328 * gives sensible behavior when the llc is not L3. 6329 */ 6330 llc = NULL; 6331 for (cg = smp_topo_find(cpu_top, cpu); cg != NULL; 6332 cg = cg->cg_parent) { 6333 if (cg->cg_level != CG_SHARE_NONE) 6334 llc = cg; 6335 } 6336 6337 /* cg_first is a stable llc identifier. */ 6338 llc_id = llc != NULL ? llc->cg_first : cpu; 6339 iflib_cpu_llc[cpu] = llc_id; 6340 if (first_llc_id == USHRT_MAX) 6341 first_llc_id = llc_id; 6342 else if (llc_id != first_llc_id) 6343 iflib_single_llc = false; 6344 } 6345 #else 6346 iflib_cpu_llc[0] = 0; 6347 #endif 6348 iflib_producer_gate = !iflib_single_llc || 6349 mp_ncpus > iflib_max_producers; 6350 } 6351 6352 /* 6353 * - Start a fast taskqueue thread for each core 6354 * - Start a taskqueue for control operations 6355 */ 6356 static int 6357 iflib_module_init(void) 6358 { 6359 iflib_timer_default = hz / 2; 6360 iflib_cpu_llc_init(); 6361 6362 if (iflib_simple_txbr_size < IFLIB_SIMPLE_TXBR_MIN || 6363 !powerof2(iflib_simple_txbr_size)) { 6364 printf("iflib: simple_txbr_size %d is not a power of 2 >= %d " 6365 "- using default value of %d\n", iflib_simple_txbr_size, 6366 IFLIB_SIMPLE_TXBR_MIN, IFLIB_SIMPLE_TXBR_SIZE); 6367 iflib_simple_txbr_size = IFLIB_SIMPLE_TXBR_SIZE; 6368 } 6369 return (0); 6370 } 6371 6372 static int 6373 iflib_module_event_handler(module_t mod, int what, void *arg) 6374 { 6375 int err; 6376 6377 switch (what) { 6378 case MOD_LOAD: 6379 if ((err = iflib_module_init()) != 0) 6380 return (err); 6381 break; 6382 case MOD_UNLOAD: 6383 return (EBUSY); 6384 default: 6385 return (EOPNOTSUPP); 6386 } 6387 6388 return (0); 6389 } 6390 6391 /********************************************************************* 6392 * 6393 * PUBLIC FUNCTION DEFINITIONS 6394 * ordered as in iflib.h 6395 * 6396 **********************************************************************/ 6397 6398 static void 6399 _iflib_assert(if_shared_ctx_t sctx) 6400 { 6401 int i; 6402 6403 MPASS(sctx->isc_tx_maxsize); 6404 MPASS(sctx->isc_tx_maxsegsize); 6405 6406 MPASS(sctx->isc_rx_maxsize); 6407 MPASS(sctx->isc_rx_nsegments); 6408 MPASS(sctx->isc_rx_maxsegsize); 6409 6410 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 6411 for (i = 0; i < sctx->isc_nrxqs; i++) { 6412 MPASS(sctx->isc_nrxd_min[i]); 6413 MPASS(powerof2(sctx->isc_nrxd_min[i])); 6414 MPASS(sctx->isc_nrxd_max[i]); 6415 MPASS(powerof2(sctx->isc_nrxd_max[i])); 6416 MPASS(sctx->isc_nrxd_default[i]); 6417 MPASS(powerof2(sctx->isc_nrxd_default[i])); 6418 } 6419 6420 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 6421 for (i = 0; i < sctx->isc_ntxqs; i++) { 6422 MPASS(sctx->isc_ntxd_min[i]); 6423 MPASS(powerof2(sctx->isc_ntxd_min[i])); 6424 MPASS(sctx->isc_ntxd_max[i]); 6425 MPASS(powerof2(sctx->isc_ntxd_max[i])); 6426 MPASS(sctx->isc_ntxd_default[i]); 6427 MPASS(powerof2(sctx->isc_ntxd_default[i])); 6428 } 6429 } 6430 6431 static void 6432 _iflib_pre_assert(if_softc_ctx_t scctx) 6433 { 6434 6435 MPASS(scctx->isc_txrx->ift_txd_encap); 6436 MPASS(scctx->isc_txrx->ift_txd_flush); 6437 MPASS(scctx->isc_txrx->ift_txd_credits_update); 6438 MPASS(scctx->isc_txrx->ift_rxd_available); 6439 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 6440 MPASS(scctx->isc_txrx->ift_rxd_refill); 6441 MPASS(scctx->isc_txrx->ift_rxd_flush); 6442 } 6443 6444 static void 6445 iflib_register(if_ctx_t ctx) 6446 { 6447 if_shared_ctx_t sctx = ctx->ifc_sctx; 6448 driver_t *driver = sctx->isc_driver; 6449 device_t dev = ctx->ifc_dev; 6450 if_t ifp; 6451 6452 _iflib_assert(sctx); 6453 6454 CTX_LOCK_INIT(ctx); 6455 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 6456 ifp = ctx->ifc_ifp = if_alloc_dev(IFT_ETHER, dev); 6457 6458 /* 6459 * Initialize our context's device specific methods 6460 */ 6461 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 6462 kobj_class_compile((kobj_class_t) driver); 6463 6464 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 6465 if_setsoftc(ifp, ctx); 6466 if_setdev(ifp, dev); 6467 if_setinitfn(ifp, iflib_if_init); 6468 if_setioctlfn(ifp, iflib_if_ioctl); 6469 /* VF status describes children of an SR-IOV PF. */ 6470 if (!CTX_IS_VF(ctx)) 6471 if_setvfstatusfn(ifp, iflib_if_vf_status); 6472 #ifdef ALTQ 6473 if_setstartfn(ifp, iflib_altq_if_start); 6474 if_settransmitfn(ifp, iflib_altq_if_transmit); 6475 if_setsendqready(ifp); 6476 #else 6477 if_settransmitfn(ifp, iflib_if_transmit); 6478 #endif 6479 if_setqflushfn(ifp, iflib_if_qflush); 6480 if_setgetcounterfn(ifp, iflib_if_get_counter); 6481 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 6482 ctx->ifc_vlan_attach_event = 6483 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 6484 EVENTHANDLER_PRI_FIRST); 6485 ctx->ifc_vlan_detach_event = 6486 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 6487 EVENTHANDLER_PRI_FIRST); 6488 6489 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 6490 ctx->ifc_mediap = &ctx->ifc_media; 6491 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 6492 iflib_media_change, iflib_media_status); 6493 } 6494 } 6495 6496 static void 6497 iflib_unregister_vlan_handlers(if_ctx_t ctx) 6498 { 6499 /* Unregister VLAN events */ 6500 if (ctx->ifc_vlan_attach_event != NULL) { 6501 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 6502 ctx->ifc_vlan_attach_event = NULL; 6503 } 6504 if (ctx->ifc_vlan_detach_event != NULL) { 6505 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 6506 ctx->ifc_vlan_detach_event = NULL; 6507 } 6508 6509 } 6510 6511 static void 6512 iflib_deregister(if_ctx_t ctx) 6513 { 6514 if_t ifp = ctx->ifc_ifp; 6515 6516 /* Remove all media */ 6517 ifmedia_removeall(&ctx->ifc_media); 6518 6519 /* Ensure that VLAN event handlers are unregistered */ 6520 iflib_unregister_vlan_handlers(ctx); 6521 6522 /* Release kobject reference */ 6523 kobj_delete((kobj_t) ctx, NULL); 6524 6525 /* Free the ifnet structure */ 6526 if_free(ifp); 6527 6528 STATE_LOCK_DESTROY(ctx); 6529 6530 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 6531 CTX_LOCK_DESTROY(ctx); 6532 } 6533 6534 static int 6535 iflib_queues_alloc(if_ctx_t ctx) 6536 { 6537 if_shared_ctx_t sctx = ctx->ifc_sctx; 6538 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6539 device_t dev = ctx->ifc_dev; 6540 int nrxqsets = scctx->isc_nrxqsets; 6541 int ntxqsets = scctx->isc_ntxqsets; 6542 iflib_txq_t txq; 6543 iflib_rxq_t rxq; 6544 iflib_fl_t fl = NULL; 6545 int i, j, cpu, err; 6546 iflib_dma_info_t ifdip; 6547 uint32_t *rxqsizes = scctx->isc_rxqsizes; 6548 uint32_t *txqsizes = scctx->isc_txqsizes; 6549 uint8_t nrxqs = sctx->isc_nrxqs; 6550 uint8_t ntxqs = sctx->isc_ntxqs; 6551 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 6552 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 6553 caddr_t *vaddrs; 6554 uint64_t *paddrs; 6555 6556 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 6557 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 6558 KASSERT(nrxqs >= fl_offset + nfree_lists, 6559 ("there must be at least a rxq for each free list")); 6560 6561 /* Allocate the TX ring struct memory */ 6562 if (!(ctx->ifc_txqs = 6563 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 6564 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 6565 device_printf(dev, "Unable to allocate TX ring memory\n"); 6566 err = ENOMEM; 6567 goto fail; 6568 } 6569 6570 /* Now allocate the RX */ 6571 if (!(ctx->ifc_rxqs = 6572 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 6573 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 6574 device_printf(dev, "Unable to allocate RX ring memory\n"); 6575 err = ENOMEM; 6576 goto rx_fail; 6577 } 6578 6579 txq = ctx->ifc_txqs; 6580 rxq = ctx->ifc_rxqs; 6581 6582 /* 6583 * XXX handle allocation failure 6584 */ 6585 for (i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txq++, cpu = CPU_NEXT(cpu)) { 6586 /* Set up some basics */ 6587 6588 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 6589 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 6590 device_printf(dev, 6591 "Unable to allocate TX DMA info memory\n"); 6592 err = ENOMEM; 6593 goto err_tx_desc; 6594 } 6595 txq->ift_ifdi = ifdip; 6596 for (j = 0; j < ntxqs; j++, ifdip++) { 6597 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 6598 device_printf(dev, 6599 "Unable to allocate TX descriptors\n"); 6600 err = ENOMEM; 6601 goto err_tx_desc; 6602 } 6603 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 6604 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 6605 } 6606 txq->ift_ctx = ctx; 6607 txq->ift_id = i; 6608 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 6609 txq->ift_br_offset = 1; 6610 } else { 6611 txq->ift_br_offset = 0; 6612 } 6613 6614 if (iflib_txsd_alloc(txq)) { 6615 device_printf(dev, "Critical Failure setting up TX buffers\n"); 6616 err = ENOMEM; 6617 goto err_tx_desc; 6618 } 6619 6620 /* Initialize the TX lock */ 6621 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 6622 device_get_nameunit(dev), txq->ift_id); 6623 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 6624 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 6625 txq->ift_timer.c_cpu = cpu; 6626 #ifdef DEV_NETMAP 6627 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 6628 txq->ift_netmap_timer.c_cpu = cpu; 6629 #endif /* DEV_NETMAP */ 6630 6631 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 6632 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 6633 if (err) { 6634 /* XXX free any allocated rings */ 6635 device_printf(dev, "Unable to allocate buf_ring\n"); 6636 goto err_tx_desc; 6637 } 6638 if (ctx->ifc_sysctl_simple_tx) { 6639 txq->ift_drbr = buf_ring_alloc(iflib_simple_txbr_size, 6640 M_IFLIB, M_WAITOK, &txq->ift_mtx); 6641 txq->ift_drbr_deferred = counter_u64_alloc(M_WAITOK); 6642 txq->ift_drbr_drops = counter_u64_alloc(M_WAITOK); 6643 txq->ift_drbr_blocked = counter_u64_alloc(M_WAITOK); 6644 txq->ift_drbr_remote = counter_u64_alloc(M_WAITOK); 6645 } 6646 txq->ift_reclaim_thresh = ctx->ifc_sysctl_tx_reclaim_thresh; 6647 } 6648 6649 for (i = 0; i < nrxqsets; i++, rxq++) { 6650 /* Set up some basics */ 6651 callout_init(&rxq->ifr_watchdog, 1); 6652 6653 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 6654 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 6655 device_printf(dev, 6656 "Unable to allocate RX DMA info memory\n"); 6657 err = ENOMEM; 6658 goto err_tx_desc; 6659 } 6660 6661 rxq->ifr_ifdi = ifdip; 6662 /* XXX this needs to be changed if #rx queues != #tx queues */ 6663 rxq->ifr_ntxqirq = 1; 6664 rxq->ifr_txqid[0] = i; 6665 for (j = 0; j < nrxqs; j++, ifdip++) { 6666 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 6667 device_printf(dev, 6668 "Unable to allocate RX descriptors\n"); 6669 err = ENOMEM; 6670 goto err_tx_desc; 6671 } 6672 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 6673 } 6674 rxq->ifr_ctx = ctx; 6675 rxq->ifr_id = i; 6676 rxq->ifr_fl_offset = fl_offset; 6677 rxq->ifr_nfl = nfree_lists; 6678 if (!(fl = 6679 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 6680 device_printf(dev, "Unable to allocate free list memory\n"); 6681 err = ENOMEM; 6682 goto err_tx_desc; 6683 } 6684 rxq->ifr_fl = fl; 6685 for (j = 0; j < nfree_lists; j++) { 6686 fl[j].ifl_rxq = rxq; 6687 fl[j].ifl_id = j; 6688 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 6689 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 6690 } 6691 /* Allocate receive buffers for the ring */ 6692 if (iflib_rxsd_alloc(rxq)) { 6693 device_printf(dev, 6694 "Critical Failure setting up receive buffers\n"); 6695 err = ENOMEM; 6696 goto err_rx_desc; 6697 } 6698 6699 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 6700 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 6701 M_WAITOK); 6702 } 6703 6704 /* TXQs */ 6705 vaddrs = malloc(sizeof(caddr_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK); 6706 paddrs = malloc(sizeof(uint64_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK); 6707 for (i = 0; i < ntxqsets; i++) { 6708 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 6709 6710 for (j = 0; j < ntxqs; j++, di++) { 6711 vaddrs[i * ntxqs + j] = di->idi_vaddr; 6712 paddrs[i * ntxqs + j] = di->idi_paddr; 6713 } 6714 } 6715 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 6716 device_printf(ctx->ifc_dev, 6717 "Unable to allocate device TX queue\n"); 6718 iflib_tx_structures_free(ctx); 6719 free(vaddrs, M_IFLIB); 6720 free(paddrs, M_IFLIB); 6721 goto err_rx_desc; 6722 } 6723 free(vaddrs, M_IFLIB); 6724 free(paddrs, M_IFLIB); 6725 6726 /* RXQs */ 6727 vaddrs = malloc(sizeof(caddr_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK); 6728 paddrs = malloc(sizeof(uint64_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK); 6729 for (i = 0; i < nrxqsets; i++) { 6730 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6731 6732 for (j = 0; j < nrxqs; j++, di++) { 6733 vaddrs[i * nrxqs + j] = di->idi_vaddr; 6734 paddrs[i * nrxqs + j] = di->idi_paddr; 6735 } 6736 } 6737 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6738 device_printf(ctx->ifc_dev, 6739 "Unable to allocate device RX queue\n"); 6740 iflib_tx_structures_free(ctx); 6741 free(vaddrs, M_IFLIB); 6742 free(paddrs, M_IFLIB); 6743 goto err_rx_desc; 6744 } 6745 free(vaddrs, M_IFLIB); 6746 free(paddrs, M_IFLIB); 6747 6748 return (0); 6749 6750 /* XXX handle allocation failure changes */ 6751 err_rx_desc: 6752 err_tx_desc: 6753 rx_fail: 6754 if (ctx->ifc_rxqs != NULL) 6755 free(ctx->ifc_rxqs, M_IFLIB); 6756 ctx->ifc_rxqs = NULL; 6757 if (ctx->ifc_txqs != NULL) 6758 free(ctx->ifc_txqs, M_IFLIB); 6759 ctx->ifc_txqs = NULL; 6760 fail: 6761 return (err); 6762 } 6763 6764 static int 6765 iflib_tx_structures_setup(if_ctx_t ctx) 6766 { 6767 iflib_txq_t txq = ctx->ifc_txqs; 6768 int i; 6769 6770 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6771 iflib_txq_setup(txq); 6772 6773 return (0); 6774 } 6775 6776 static void 6777 iflib_tx_structures_free(if_ctx_t ctx) 6778 { 6779 iflib_txq_t txq = ctx->ifc_txqs; 6780 if_shared_ctx_t sctx = ctx->ifc_sctx; 6781 int i, j; 6782 6783 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6784 for (j = 0; j < sctx->isc_ntxqs; j++) 6785 iflib_dma_free(&txq->ift_ifdi[j]); 6786 iflib_txq_destroy(txq); 6787 } 6788 free(ctx->ifc_txqs, M_IFLIB); 6789 ctx->ifc_txqs = NULL; 6790 } 6791 6792 /********************************************************************* 6793 * 6794 * Initialize all receive rings. 6795 * 6796 **********************************************************************/ 6797 static int 6798 iflib_rx_structures_setup(if_ctx_t ctx) 6799 { 6800 iflib_rxq_t rxq = ctx->ifc_rxqs; 6801 int q; 6802 #if defined(INET6) || defined(INET) 6803 int err, i; 6804 #endif 6805 6806 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6807 #if defined(INET6) || defined(INET) 6808 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6809 TCP_LRO_ENTRIES, min(1024, 6810 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6811 if (err != 0) { 6812 device_printf(ctx->ifc_dev, 6813 "LRO Initialization failed!\n"); 6814 goto fail; 6815 } 6816 #endif 6817 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6818 } 6819 return (0); 6820 #if defined(INET6) || defined(INET) 6821 fail: 6822 /* 6823 * Free LRO resources allocated so far, we will only handle 6824 * the rings that completed, the failing case will have 6825 * cleaned up for itself. 'q' failed, so its the terminus. 6826 */ 6827 rxq = ctx->ifc_rxqs; 6828 for (i = 0; i < q; ++i, rxq++) { 6829 tcp_lro_free(&rxq->ifr_lc); 6830 } 6831 return (err); 6832 #endif 6833 } 6834 6835 /********************************************************************* 6836 * 6837 * Free all receive rings. 6838 * 6839 **********************************************************************/ 6840 static void 6841 iflib_rx_structures_free(if_ctx_t ctx) 6842 { 6843 iflib_rxq_t rxq = ctx->ifc_rxqs; 6844 if_shared_ctx_t sctx = ctx->ifc_sctx; 6845 int i, j; 6846 6847 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6848 for (j = 0; j < sctx->isc_nrxqs; j++) 6849 iflib_dma_free(&rxq->ifr_ifdi[j]); 6850 iflib_rx_sds_free(rxq); 6851 #if defined(INET6) || defined(INET) 6852 tcp_lro_free(&rxq->ifr_lc); 6853 #endif 6854 } 6855 free(ctx->ifc_rxqs, M_IFLIB); 6856 ctx->ifc_rxqs = NULL; 6857 } 6858 6859 static int 6860 iflib_qset_structures_setup(if_ctx_t ctx) 6861 { 6862 int err; 6863 6864 /* 6865 * It is expected that the caller takes care of freeing queues if this 6866 * fails. 6867 */ 6868 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6869 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6870 return (err); 6871 } 6872 6873 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6874 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6875 6876 return (err); 6877 } 6878 6879 int 6880 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6881 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6882 { 6883 6884 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6885 } 6886 6887 /* Just to avoid copy/paste */ 6888 static inline int 6889 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6890 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6891 const char *name) 6892 { 6893 device_t dev; 6894 unsigned int base_cpuid, cpuid; 6895 int err; 6896 6897 dev = ctx->ifc_dev; 6898 base_cpuid = ctx->ifc_sysctl_core_offset; 6899 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6900 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6901 irq ? irq->ii_res : NULL, name); 6902 if (err) { 6903 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6904 return (err); 6905 } 6906 #ifdef notyet 6907 if (cpuid > ctx->ifc_cpuid_highest) 6908 ctx->ifc_cpuid_highest = cpuid; 6909 #endif 6910 return (0); 6911 } 6912 6913 /* 6914 * Allocate a hardware interrupt for subctx using the parent (ctx)'s hardware 6915 * resources. 6916 * 6917 * Similar to iflib_irq_alloc_generic(), but for interrupt type IFLIB_INTR_RXTX 6918 * only. 6919 * 6920 * XXX: Could be removed if subctx's dev has its intr resource allocation 6921 * methods replaced with custom ones? 6922 */ 6923 int 6924 iflib_irq_alloc_generic_subctx(if_ctx_t ctx, if_ctx_t subctx, if_irq_t irq, 6925 int rid, iflib_intr_type_t type, 6926 driver_filter_t *filter, void *filter_arg, 6927 int qid, const char *name) 6928 { 6929 device_t dev, subdev; 6930 struct grouptask *gtask; 6931 struct taskqgroup *tqg; 6932 iflib_filter_info_t info; 6933 gtask_fn_t *fn; 6934 int tqrid, err; 6935 driver_filter_t *intr_fast; 6936 void *q; 6937 6938 MPASS(ctx != NULL); 6939 MPASS(subctx != NULL); 6940 6941 tqrid = rid; 6942 dev = ctx->ifc_dev; 6943 subdev = subctx->ifc_dev; 6944 6945 switch (type) { 6946 case IFLIB_INTR_RXTX: 6947 q = &subctx->ifc_rxqs[qid]; 6948 info = &subctx->ifc_rxqs[qid].ifr_filter_info; 6949 gtask = &subctx->ifc_rxqs[qid].ifr_task; 6950 tqg = qgroup_if_io_tqg; 6951 fn = _task_fn_rx; 6952 intr_fast = iflib_fast_intr_rxtx; 6953 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6954 break; 6955 default: 6956 device_printf(dev, "%s: unknown net intr type for subctx %s (%d)\n", 6957 __func__, device_get_nameunit(subdev), type); 6958 return (EINVAL); 6959 } 6960 6961 info->ifi_filter = filter; 6962 info->ifi_filter_arg = filter_arg; 6963 info->ifi_task = gtask; 6964 info->ifi_ctx = q; 6965 6966 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6967 6968 /* Allocate interrupts from hardware using parent context */ 6969 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6970 if (err != 0) { 6971 device_printf(dev, "_iflib_irq_alloc failed for subctx %s: %d\n", 6972 device_get_nameunit(subdev), err); 6973 return (err); 6974 } 6975 6976 if (tqrid != -1) { 6977 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6978 name); 6979 if (err) 6980 return (err); 6981 } else { 6982 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6983 } 6984 6985 return (0); 6986 } 6987 6988 int 6989 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6990 iflib_intr_type_t type, driver_filter_t *filter, 6991 void *filter_arg, int qid, const char *name) 6992 { 6993 device_t dev; 6994 struct grouptask *gtask; 6995 struct taskqgroup *tqg; 6996 iflib_filter_info_t info; 6997 gtask_fn_t *fn; 6998 int tqrid, err; 6999 driver_filter_t *intr_fast; 7000 void *q; 7001 7002 info = &ctx->ifc_filter_info; 7003 tqrid = rid; 7004 7005 switch (type) { 7006 /* XXX merge tx/rx for netmap? */ 7007 case IFLIB_INTR_TX: 7008 q = &ctx->ifc_txqs[qid]; 7009 info = &ctx->ifc_txqs[qid].ift_filter_info; 7010 gtask = &ctx->ifc_txqs[qid].ift_task; 7011 tqg = qgroup_if_io_tqg; 7012 fn = _task_fn_tx; 7013 intr_fast = iflib_fast_intr; 7014 GROUPTASK_INIT(gtask, 0, fn, q); 7015 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 7016 break; 7017 case IFLIB_INTR_RX: 7018 q = &ctx->ifc_rxqs[qid]; 7019 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 7020 gtask = &ctx->ifc_rxqs[qid].ifr_task; 7021 tqg = qgroup_if_io_tqg; 7022 fn = _task_fn_rx; 7023 intr_fast = iflib_fast_intr; 7024 NET_GROUPTASK_INIT(gtask, 0, fn, q); 7025 break; 7026 case IFLIB_INTR_RXTX: 7027 q = &ctx->ifc_rxqs[qid]; 7028 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 7029 gtask = &ctx->ifc_rxqs[qid].ifr_task; 7030 tqg = qgroup_if_io_tqg; 7031 fn = _task_fn_rx; 7032 intr_fast = iflib_fast_intr_rxtx; 7033 NET_GROUPTASK_INIT(gtask, 0, fn, q); 7034 break; 7035 case IFLIB_INTR_ADMIN: 7036 q = ctx; 7037 tqrid = -1; 7038 info = &ctx->ifc_filter_info; 7039 gtask = NULL; 7040 intr_fast = iflib_fast_intr_ctx; 7041 break; 7042 default: 7043 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 7044 __func__); 7045 return (EINVAL); 7046 } 7047 7048 info->ifi_filter = filter; 7049 info->ifi_filter_arg = filter_arg; 7050 info->ifi_task = gtask; 7051 info->ifi_ctx = q; 7052 7053 dev = ctx->ifc_dev; 7054 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 7055 if (err != 0) { 7056 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 7057 return (err); 7058 } 7059 if (type == IFLIB_INTR_ADMIN) 7060 return (0); 7061 7062 if (tqrid != -1) { 7063 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 7064 name); 7065 if (err) 7066 return (err); 7067 } else { 7068 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 7069 } 7070 7071 return (0); 7072 } 7073 7074 void 7075 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 7076 void *arg, int qid, const char *name) 7077 { 7078 device_t dev; 7079 struct grouptask *gtask; 7080 struct taskqgroup *tqg; 7081 gtask_fn_t *fn; 7082 void *q; 7083 int err; 7084 7085 switch (type) { 7086 case IFLIB_INTR_TX: 7087 q = &ctx->ifc_txqs[qid]; 7088 gtask = &ctx->ifc_txqs[qid].ift_task; 7089 tqg = qgroup_if_io_tqg; 7090 fn = _task_fn_tx; 7091 GROUPTASK_INIT(gtask, 0, fn, q); 7092 break; 7093 case IFLIB_INTR_RX: 7094 q = &ctx->ifc_rxqs[qid]; 7095 gtask = &ctx->ifc_rxqs[qid].ifr_task; 7096 tqg = qgroup_if_io_tqg; 7097 fn = _task_fn_rx; 7098 NET_GROUPTASK_INIT(gtask, 0, fn, q); 7099 break; 7100 case IFLIB_INTR_IOV: 7101 return; 7102 default: 7103 panic("unknown net intr type"); 7104 } 7105 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 7106 if (err) { 7107 dev = ctx->ifc_dev; 7108 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 7109 name); 7110 } 7111 } 7112 7113 void 7114 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 7115 { 7116 7117 if (irq->ii_tag) 7118 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 7119 7120 if (irq->ii_res) 7121 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 7122 rman_get_rid(irq->ii_res), irq->ii_res); 7123 } 7124 7125 static int 7126 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 7127 { 7128 iflib_txq_t txq = ctx->ifc_txqs; 7129 iflib_rxq_t rxq = ctx->ifc_rxqs; 7130 if_irq_t irq = &ctx->ifc_legacy_irq; 7131 iflib_filter_info_t info; 7132 device_t dev; 7133 struct grouptask *gtask; 7134 struct resource *res; 7135 int err, tqrid; 7136 bool rx_only; 7137 7138 info = &rxq->ifr_filter_info; 7139 gtask = &rxq->ifr_task; 7140 tqrid = *rid; 7141 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 7142 7143 ctx->ifc_flags |= IFC_LEGACY; 7144 info->ifi_filter = filter; 7145 info->ifi_filter_arg = filter_arg; 7146 info->ifi_task = gtask; 7147 info->ifi_ctx = rxq; 7148 7149 dev = ctx->ifc_dev; 7150 /* We allocate a single interrupt resource */ 7151 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr : 7152 iflib_fast_intr_rxtx, NULL, info, name); 7153 if (err != 0) 7154 return (err); 7155 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, rxq); 7156 res = irq->ii_res; 7157 taskqgroup_attach(qgroup_if_io_tqg, gtask, rxq, dev, res, name); 7158 7159 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 7160 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 7161 "tx"); 7162 return (0); 7163 } 7164 7165 void 7166 iflib_led_create(if_ctx_t ctx) 7167 { 7168 7169 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 7170 device_get_nameunit(ctx->ifc_dev)); 7171 } 7172 7173 void 7174 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 7175 { 7176 7177 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 7178 } 7179 7180 void 7181 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 7182 { 7183 7184 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 7185 } 7186 7187 void 7188 iflib_admin_intr_deferred(if_ctx_t ctx) 7189 { 7190 7191 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task); 7192 } 7193 7194 void 7195 iflib_iov_intr_deferred(if_ctx_t ctx) 7196 { 7197 7198 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_vflr_task); 7199 } 7200 7201 void 7202 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 7203 { 7204 7205 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 7206 name); 7207 } 7208 7209 void 7210 iflib_config_task_init(if_ctx_t ctx, struct task *config_task, task_fn_t *fn) 7211 { 7212 TASK_INIT(config_task, 0, fn, ctx); 7213 } 7214 7215 void 7216 iflib_config_task_enqueue(if_ctx_t ctx, struct task *config_task) 7217 { 7218 taskqueue_enqueue(ctx->ifc_tq, config_task); 7219 } 7220 7221 void 7222 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 7223 { 7224 if_t ifp = ctx->ifc_ifp; 7225 7226 if_setbaudrate(ifp, baudrate); 7227 if (baudrate >= IF_Gbps(10)) { 7228 STATE_LOCK(ctx); 7229 ctx->ifc_flags |= IFC_PREFETCH; 7230 STATE_UNLOCK(ctx); 7231 } 7232 ctx->ifc_link_state = link_state; 7233 if_link_state_change(ifp, link_state); 7234 } 7235 7236 static int 7237 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 7238 { 7239 int credits; 7240 #ifdef INVARIANTS 7241 int credits_pre = txq->ift_cidx_processed; 7242 #endif 7243 7244 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 7245 BUS_DMASYNC_POSTREAD); 7246 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 7247 return (0); 7248 7249 txq->ift_processed += credits; 7250 txq->ift_cidx_processed += credits; 7251 7252 MPASS(credits_pre + credits == txq->ift_cidx_processed); 7253 if (txq->ift_cidx_processed >= txq->ift_size) 7254 txq->ift_cidx_processed -= txq->ift_size; 7255 return (credits); 7256 } 7257 7258 static int 7259 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 7260 { 7261 iflib_fl_t fl; 7262 u_int i; 7263 7264 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 7265 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 7266 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 7267 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 7268 budget)); 7269 } 7270 7271 void 7272 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 7273 const char *description, if_int_delay_info_t info, 7274 int offset, int value) 7275 { 7276 info->iidi_ctx = ctx; 7277 info->iidi_offset = offset; 7278 info->iidi_value = value; 7279 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 7280 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 7281 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 7282 info, 0, iflib_sysctl_int_delay, "I", description); 7283 } 7284 7285 struct sx * 7286 iflib_ctx_lock_get(if_ctx_t ctx) 7287 { 7288 7289 return (&ctx->ifc_ctx_sx); 7290 } 7291 7292 static int 7293 iflib_msix_init(if_ctx_t ctx) 7294 { 7295 device_t dev = ctx->ifc_dev; 7296 if_shared_ctx_t sctx = ctx->ifc_sctx; 7297 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 7298 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 7299 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 7300 7301 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 7302 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 7303 7304 if (bootverbose) 7305 device_printf(dev, "msix_init qsets capped at %d\n", 7306 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 7307 7308 /* Override by tuneable */ 7309 if (scctx->isc_disable_msix) 7310 goto msi; 7311 7312 /* First try MSI-X */ 7313 if ((msgs = pci_msix_count(dev)) == 0) { 7314 if (bootverbose) 7315 device_printf(dev, "MSI-X not supported or disabled\n"); 7316 goto msi; 7317 } 7318 7319 bar = ctx->ifc_softc_ctx.isc_msix_bar; 7320 /* 7321 * bar == -1 => "trust me I know what I'm doing" 7322 * Some drivers are for hardware that is so shoddily 7323 * documented that no one knows which bars are which 7324 * so the developer has to map all bars. This hack 7325 * allows shoddy garbage to use MSI-X in this framework. 7326 */ 7327 if (bar != -1) { 7328 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 7329 SYS_RES_MEMORY, &bar, RF_ACTIVE); 7330 if (ctx->ifc_msix_mem == NULL) { 7331 device_printf(dev, "Unable to map MSI-X table\n"); 7332 goto msi; 7333 } 7334 } 7335 7336 admincnt = sctx->isc_admin_intrcnt; 7337 #if IFLIB_DEBUG 7338 /* use only 1 qset in debug mode */ 7339 queuemsgs = min(msgs - admincnt, 1); 7340 #else 7341 queuemsgs = msgs - admincnt; 7342 #endif 7343 #ifdef RSS 7344 queues = imin(queuemsgs, rss_getnumbuckets()); 7345 #else 7346 queues = queuemsgs; 7347 #endif 7348 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 7349 if (bootverbose) 7350 device_printf(dev, 7351 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 7352 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 7353 #ifdef RSS 7354 /* If we're doing RSS, clamp at the number of RSS buckets */ 7355 if (queues > rss_getnumbuckets()) 7356 queues = rss_getnumbuckets(); 7357 #endif 7358 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 7359 rx_queues = iflib_num_rx_queues; 7360 else 7361 rx_queues = queues; 7362 7363 if (rx_queues > scctx->isc_nrxqsets) 7364 rx_queues = scctx->isc_nrxqsets; 7365 7366 /* 7367 * We want this to be all logical CPUs by default 7368 */ 7369 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 7370 tx_queues = iflib_num_tx_queues; 7371 else 7372 tx_queues = mp_ncpus; 7373 7374 if (tx_queues > scctx->isc_ntxqsets) 7375 tx_queues = scctx->isc_ntxqsets; 7376 7377 if (ctx->ifc_sysctl_qs_eq_override == 0) { 7378 #ifdef INVARIANTS 7379 if (tx_queues != rx_queues) 7380 device_printf(dev, 7381 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 7382 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 7383 #endif 7384 tx_queues = min(rx_queues, tx_queues); 7385 rx_queues = min(rx_queues, tx_queues); 7386 } 7387 7388 vectors = rx_queues + admincnt; 7389 if (msgs < vectors) { 7390 device_printf(dev, 7391 "insufficient number of MSI-X vectors " 7392 "(supported %d, need %d)\n", msgs, vectors); 7393 goto msi; 7394 } 7395 7396 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 7397 tx_queues); 7398 msgs = vectors; 7399 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 7400 if (vectors != msgs) { 7401 device_printf(dev, 7402 "Unable to allocate sufficient MSI-X vectors " 7403 "(got %d, need %d)\n", vectors, msgs); 7404 pci_release_msi(dev); 7405 if (bar != -1) { 7406 bus_release_resource(dev, SYS_RES_MEMORY, bar, 7407 ctx->ifc_msix_mem); 7408 ctx->ifc_msix_mem = NULL; 7409 } 7410 goto msi; 7411 } 7412 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 7413 vectors); 7414 scctx->isc_vectors = vectors; 7415 scctx->isc_nrxqsets = rx_queues; 7416 scctx->isc_ntxqsets = tx_queues; 7417 scctx->isc_intr = IFLIB_INTR_MSIX; 7418 7419 return (vectors); 7420 } else { 7421 device_printf(dev, 7422 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 7423 err); 7424 if (bar != -1) { 7425 bus_release_resource(dev, SYS_RES_MEMORY, bar, 7426 ctx->ifc_msix_mem); 7427 ctx->ifc_msix_mem = NULL; 7428 } 7429 } 7430 7431 msi: 7432 vectors = pci_msi_count(dev); 7433 scctx->isc_nrxqsets = 1; 7434 scctx->isc_ntxqsets = 1; 7435 scctx->isc_vectors = vectors; 7436 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 7437 device_printf(dev, "Using an MSI interrupt\n"); 7438 scctx->isc_intr = IFLIB_INTR_MSI; 7439 } else { 7440 scctx->isc_vectors = 1; 7441 device_printf(dev, "Using a Legacy interrupt\n"); 7442 scctx->isc_intr = IFLIB_INTR_LEGACY; 7443 } 7444 7445 return (vectors); 7446 } 7447 7448 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 7449 7450 static int 7451 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 7452 { 7453 int rc; 7454 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 7455 struct sbuf *sb; 7456 const char *ring_state = "UNKNOWN"; 7457 7458 /* XXX needed ? */ 7459 rc = sysctl_wire_old_buffer(req, 0); 7460 MPASS(rc == 0); 7461 if (rc != 0) 7462 return (rc); 7463 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 7464 MPASS(sb != NULL); 7465 if (sb == NULL) 7466 return (ENOMEM); 7467 if (state[3] <= 3) 7468 ring_state = ring_states[state[3]]; 7469 7470 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 7471 state[0], state[1], state[2], ring_state); 7472 rc = sbuf_finish(sb); 7473 sbuf_delete(sb); 7474 return (rc); 7475 } 7476 7477 enum iflib_ndesc_handler { 7478 IFLIB_NTXD_HANDLER, 7479 IFLIB_NRXD_HANDLER, 7480 }; 7481 7482 static int 7483 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 7484 { 7485 if_ctx_t ctx = (void *)arg1; 7486 enum iflib_ndesc_handler type = arg2; 7487 char buf[256] = {0}; 7488 qidx_t *ndesc; 7489 char *p, *next; 7490 int nqs, rc, i; 7491 7492 nqs = 8; 7493 switch (type) { 7494 case IFLIB_NTXD_HANDLER: 7495 ndesc = ctx->ifc_sysctl_ntxds; 7496 if (ctx->ifc_sctx) 7497 nqs = ctx->ifc_sctx->isc_ntxqs; 7498 break; 7499 case IFLIB_NRXD_HANDLER: 7500 ndesc = ctx->ifc_sysctl_nrxds; 7501 if (ctx->ifc_sctx) 7502 nqs = ctx->ifc_sctx->isc_nrxqs; 7503 break; 7504 default: 7505 printf("%s: unhandled type\n", __func__); 7506 return (EINVAL); 7507 } 7508 if (nqs == 0) 7509 nqs = 8; 7510 7511 for (i = 0; i < 8; i++) { 7512 if (i >= nqs) 7513 break; 7514 if (i) 7515 strcat(buf, ","); 7516 sprintf(strchr(buf, 0), "%d", ndesc[i]); 7517 } 7518 7519 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 7520 if (rc || req->newptr == NULL) 7521 return (rc); 7522 7523 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 7524 i++, p = strsep(&next, " ,")) { 7525 ndesc[i] = strtoul(p, NULL, 10); 7526 } 7527 7528 return (rc); 7529 } 7530 7531 static int 7532 iflib_handle_tx_reclaim_thresh(SYSCTL_HANDLER_ARGS) 7533 { 7534 if_ctx_t ctx = (void *)arg1; 7535 iflib_txq_t txq; 7536 int i, err; 7537 int thresh; 7538 7539 thresh = ctx->ifc_sysctl_tx_reclaim_thresh; 7540 err = sysctl_handle_int(oidp, &thresh, arg2, req); 7541 if (err != 0) { 7542 return err; 7543 } 7544 7545 if (thresh == ctx->ifc_sysctl_tx_reclaim_thresh) 7546 return 0; 7547 7548 if (thresh > ctx->ifc_softc_ctx.isc_ntxd[0] / 2) { 7549 device_printf(ctx->ifc_dev, "TX Reclaim thresh must be <= %d\n", 7550 ctx->ifc_softc_ctx.isc_ntxd[0] / 2); 7551 return (EINVAL); 7552 } 7553 7554 ctx->ifc_sysctl_tx_reclaim_thresh = thresh; 7555 if (ctx->ifc_txqs == NULL) 7556 return (err); 7557 7558 txq = &ctx->ifc_txqs[0]; 7559 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 7560 txq->ift_reclaim_thresh = thresh; 7561 } 7562 return (err); 7563 } 7564 7565 static int 7566 iflib_handle_tx_reclaim_ticks(SYSCTL_HANDLER_ARGS) 7567 { 7568 if_ctx_t ctx = (void *)arg1; 7569 iflib_txq_t txq; 7570 int i, err; 7571 int ticks; 7572 7573 ticks = ctx->ifc_sysctl_tx_reclaim_ticks; 7574 err = sysctl_handle_int(oidp, &ticks, arg2, req); 7575 if (err != 0) { 7576 return err; 7577 } 7578 7579 if (ticks == ctx->ifc_sysctl_tx_reclaim_ticks) 7580 return 0; 7581 7582 if (ticks > hz) { 7583 device_printf(ctx->ifc_dev, 7584 "TX Reclaim ticks must be <= hz (%d)\n", hz); 7585 return (EINVAL); 7586 } 7587 7588 ctx->ifc_sysctl_tx_reclaim_ticks = ticks; 7589 if (ctx->ifc_txqs == NULL) 7590 return (err); 7591 7592 txq = &ctx->ifc_txqs[0]; 7593 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 7594 txq->ift_reclaim_ticks = ticks; 7595 } 7596 return (err); 7597 } 7598 7599 static int 7600 iflib_handle_tx_defer_mfree(SYSCTL_HANDLER_ARGS) 7601 { 7602 if_ctx_t ctx = (void *)arg1; 7603 iflib_txq_t txq; 7604 int i, err; 7605 int defer; 7606 7607 defer = ctx->ifc_sysctl_tx_defer_mfree; 7608 err = sysctl_handle_int(oidp, &defer, arg2, req); 7609 if (err != 0) { 7610 return err; 7611 } 7612 7613 if (defer == ctx->ifc_sysctl_tx_defer_mfree) 7614 return 0; 7615 7616 ctx->ifc_sysctl_tx_defer_mfree = defer; 7617 if (ctx->ifc_txqs == NULL) 7618 return (err); 7619 7620 txq = &ctx->ifc_txqs[0]; 7621 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 7622 txq->ift_defer_mfree = defer; 7623 } 7624 return (err); 7625 } 7626 7627 #define NAME_BUFLEN 32 7628 static void 7629 iflib_add_device_sysctl_pre(if_ctx_t ctx) 7630 { 7631 device_t dev = iflib_get_dev(ctx); 7632 struct sysctl_oid_list *child, *oid_list; 7633 struct sysctl_oid *node; 7634 7635 sysctl_ctx_init(&ctx->ifc_sysctl_ctx); 7636 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 7637 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(&ctx->ifc_sysctl_ctx, child, 7638 OID_AUTO, "iflib", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 7639 "IFLIB fields"); 7640 oid_list = SYSCTL_CHILDREN(node); 7641 7642 SYSCTL_ADD_CONST_STRING(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "driver_version", 7643 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, "driver version"); 7644 SYSCTL_ADD_U32(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, 7645 "tx_watchdog_events", CTLFLAG_RD, &ctx->ifc_tx_watchdog_events, 0, 7646 "TX watchdog resets initiated by iflib"); 7647 7648 ctx->ifc_sysctl_simple_tx = !iflib_prefer_mpring; 7649 SYSCTL_ADD_BOOL(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "simple_tx", 7650 CTLFLAG_RDTUN, &ctx->ifc_sysctl_simple_tx, 0, 7651 "use simple tx ring"); 7652 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_ntxqs", 7653 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 7654 "# of txqs to use, 0 => use default #"); 7655 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_nrxqs", 7656 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 7657 "# of rxqs to use, 0 => use default #"); 7658 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_qs_enable", 7659 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 7660 "permit #txq != #rxq"); 7661 SYSCTL_ADD_INT(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "disable_msix", 7662 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 7663 "disable MSI-X (default 0)"); 7664 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "rx_budget", 7665 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, "set the RX budget"); 7666 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "tx_abdicate", 7667 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 7668 "cause TX to abdicate instead of running to completion"); 7669 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 7670 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "core_offset", 7671 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 7672 "offset to start using cores at"); 7673 SYSCTL_ADD_U8(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "separate_txrx", 7674 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 7675 "use separate cores for TX and RX"); 7676 SYSCTL_ADD_U8(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "use_logical_cores", 7677 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 7678 "try to make use of logical cores for TX and RX"); 7679 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "use_extra_msix_vectors", 7680 CTLFLAG_RDTUN, &ctx->ifc_sysctl_extra_msix_vectors, 0, 7681 "attempt to reserve the given number of extra MSI-X vectors during driver load for the creation of additional interfaces later"); 7682 SYSCTL_ADD_INT(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "allocated_msix_vectors", 7683 CTLFLAG_RDTUN, &ctx->ifc_softc_ctx.isc_vectors, 0, 7684 "total # of MSI-X vectors allocated by driver"); 7685 7686 /* XXX change for per-queue sizes */ 7687 SYSCTL_ADD_PROC(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_ntxds", 7688 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 7689 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 7690 "list of # of TX descriptors to use, 0 = use default #"); 7691 SYSCTL_ADD_PROC(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_nrxds", 7692 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 7693 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 7694 "list of # of RX descriptors to use, 0 = use default #"); 7695 } 7696 7697 static void 7698 iflib_add_device_sysctl_post(if_ctx_t ctx) 7699 { 7700 if_shared_ctx_t sctx = ctx->ifc_sctx; 7701 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 7702 struct sysctl_oid_list *child; 7703 struct sysctl_ctx_list *ctx_list = &ctx->ifc_sysctl_ctx; 7704 iflib_fl_t fl; 7705 iflib_txq_t txq; 7706 iflib_rxq_t rxq; 7707 int i, j; 7708 char namebuf[NAME_BUFLEN]; 7709 char *qfmt; 7710 struct sysctl_oid *queue_node, *fl_node, *node; 7711 struct sysctl_oid_list *queue_list, *fl_list; 7712 7713 node = ctx->ifc_sysctl_node; 7714 child = SYSCTL_CHILDREN(node); 7715 7716 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_thresh", 7717 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 7718 0, iflib_handle_tx_reclaim_thresh, "I", 7719 "Number of TX descs outstanding before reclaim is called"); 7720 7721 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_ticks", 7722 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 7723 0, iflib_handle_tx_reclaim_ticks, "I", 7724 "Number of ticks before a TX reclaim is forced"); 7725 7726 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_defer_mfree", 7727 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 7728 0, iflib_handle_tx_defer_mfree, "I", 7729 "Free completed transmits outside of TX ring lock"); 7730 7731 if (scctx->isc_ntxqsets > 100) 7732 qfmt = "txq%03d"; 7733 else if (scctx->isc_ntxqsets > 10) 7734 qfmt = "txq%02d"; 7735 else 7736 qfmt = "txq%d"; 7737 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 7738 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7739 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7740 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7741 queue_list = SYSCTL_CHILDREN(queue_node); 7742 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7743 CTLFLAG_RD, &txq->ift_task.gt_cpu, 0, 7744 "cpu this queue is bound to"); 7745 #if MEMORY_LOGGING 7746 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 7747 CTLFLAG_RD, &txq->ift_dequeued, "total mbufs freed"); 7748 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 7749 CTLFLAG_RD, &txq->ift_enqueued, "total mbufs enqueued"); 7750 #endif 7751 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 7752 CTLFLAG_RD, &txq->ift_mbuf_defrag, 7753 "# of times m_defrag was called"); 7754 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 7755 CTLFLAG_RD, &txq->ift_pullups, 7756 "# of times m_pullup was called"); 7757 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7758 "mbuf_defrag_failed", CTLFLAG_RD, 7759 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 7760 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7761 "no_desc_avail", CTLFLAG_RD, &txq->ift_no_desc_avail, 7762 "# of times no descriptors were available"); 7763 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7764 "tx_map_failed", CTLFLAG_RD, &txq->ift_map_failed, 7765 "# of times DMA map failed"); 7766 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7767 "txd_encap_efbig", CTLFLAG_RD, &txq->ift_txd_encap_efbig, 7768 "# of times txd_encap returned EFBIG"); 7769 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7770 "no_tx_dma_setup", CTLFLAG_RD, &txq->ift_no_tx_dma_setup, 7771 "# of times map failed for other than EFBIG"); 7772 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 7773 CTLFLAG_RD, &txq->ift_pidx, 1, "Producer Index"); 7774 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 7775 CTLFLAG_RD, &txq->ift_cidx, 1, "Consumer Index"); 7776 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, 7777 "txq_cidx_processed", CTLFLAG_RD, &txq->ift_cidx_processed, 7778 1, "Consumer Index seen by credit update"); 7779 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 7780 CTLFLAG_RD, &txq->ift_in_use, 1, "descriptors in use"); 7781 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7782 "txq_processed", CTLFLAG_RD, &txq->ift_processed, 7783 "descriptors procesed for clean"); 7784 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 7785 CTLFLAG_RD, &txq->ift_cleaned, "total cleaned"); 7786 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 7787 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 7788 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 7789 mp_ring_state_handler, "A", "soft ring state"); 7790 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7791 "r_enqueues", CTLFLAG_RD, &txq->ift_br->enqueues, 7792 "# of enqueues to the mp_ring for this queue"); 7793 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7794 "r_drops", CTLFLAG_RD, &txq->ift_br->drops, 7795 "# of drops in the mp_ring for this queue"); 7796 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7797 "r_starts", CTLFLAG_RD, &txq->ift_br->starts, 7798 "# of normal consumer starts in mp_ring for this queue"); 7799 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7800 "r_stalls", CTLFLAG_RD, &txq->ift_br->stalls, 7801 "# of consumer stalls in the mp_ring for this queue"); 7802 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7803 "r_restarts", CTLFLAG_RD, &txq->ift_br->restarts, 7804 "# of consumer restarts in the mp_ring for this queue"); 7805 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7806 "r_abdications", CTLFLAG_RD, &txq->ift_br->abdications, 7807 "# of consumer abdications in the mp_ring for this queue"); 7808 if (txq->ift_drbr == NULL) 7809 continue; 7810 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7811 "drbr_direct", CTLFLAG_RD, &txq->ift_drbr_direct, 7812 "# of packets sent without touching the deferral ring"); 7813 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7814 "drbr_stall", CTLFLAG_RD, &txq->ift_drbr_stall, 7815 "# of times the drain stopped with no descriptors free"); 7816 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7817 "drbr_deferred", CTLFLAG_RD, &txq->ift_drbr_deferred, 7818 "# of packets deferred after losing the tx trylock"); 7819 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7820 "drbr_drops", CTLFLAG_RD, &txq->ift_drbr_drops, 7821 "# of packets dropped because the deferral ring was full"); 7822 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7823 "drbr_blocked", CTLFLAG_RD, &txq->ift_drbr_blocked, 7824 "# of times a full deferral ring forced a tx lock wait"); 7825 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7826 "drbr_remote", CTLFLAG_RD, &txq->ift_drbr_remote, 7827 "# of times a different llc or producer limit forced a tx " 7828 "lock wait"); 7829 } 7830 7831 if (scctx->isc_nrxqsets > 100) 7832 qfmt = "rxq%03d"; 7833 else if (scctx->isc_nrxqsets > 10) 7834 qfmt = "rxq%02d"; 7835 else 7836 qfmt = "rxq%d"; 7837 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 7838 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7839 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7840 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7841 queue_list = SYSCTL_CHILDREN(queue_node); 7842 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7843 CTLFLAG_RD, &rxq->ifr_task.gt_cpu, 0, 7844 "cpu this queue is bound to"); 7845 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 7846 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, 7847 "rxq_cq_cidx", CTLFLAG_RD, &rxq->ifr_cq_cidx, 1, 7848 "Consumer Index"); 7849 } 7850 7851 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7852 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7853 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, 7854 OID_AUTO, namebuf, CTLFLAG_RD | CTLFLAG_MPSAFE, 7855 NULL, "freelist Name"); 7856 fl_list = SYSCTL_CHILDREN(fl_node); 7857 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7858 CTLFLAG_RD, &fl->ifl_pidx, 1, "Producer Index"); 7859 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7860 CTLFLAG_RD, &fl->ifl_cidx, 1, "Consumer Index"); 7861 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7862 CTLFLAG_RD, &fl->ifl_credits, 1, 7863 "credits available"); 7864 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7865 CTLFLAG_RD, &fl->ifl_buf_size, 1, "buffer size"); 7866 #if MEMORY_LOGGING 7867 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7868 "fl_m_enqueued", CTLFLAG_RD, &fl->ifl_m_enqueued, 7869 "mbufs allocated"); 7870 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7871 "fl_m_dequeued", CTLFLAG_RD, &fl->ifl_m_dequeued, 7872 "mbufs freed"); 7873 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7874 "fl_cl_enqueued", CTLFLAG_RD, &fl->ifl_cl_enqueued, 7875 "clusters allocated"); 7876 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7877 "fl_cl_dequeued", CTLFLAG_RD, &fl->ifl_cl_dequeued, 7878 "clusters freed"); 7879 #endif 7880 } 7881 } 7882 7883 } 7884 7885 void 7886 iflib_request_reset(if_ctx_t ctx) 7887 { 7888 7889 STATE_LOCK(ctx); 7890 ctx->ifc_flags |= IFC_DO_RESET; 7891 STATE_UNLOCK(ctx); 7892 } 7893 7894 void 7895 iflib_request_reset_if_up(if_ctx_t ctx) 7896 { 7897 7898 STATE_LOCK(ctx); 7899 ctx->ifc_flags |= IFC_DO_RESET_IF_UP; 7900 STATE_UNLOCK(ctx); 7901 } 7902 7903 void 7904 iflib_init_failed(if_ctx_t ctx) 7905 { 7906 7907 sx_assert(&ctx->ifc_ctx_sx, SA_XLOCKED); 7908 KASSERT(ctx->ifc_datapath_state == IFLIB_DP_STARTING, 7909 ("iflib_init_failed outside IFDI_INIT, state %d", 7910 ctx->ifc_datapath_state)); 7911 STATE_LOCK(ctx); 7912 ctx->ifc_flags |= IFC_INIT_FAILED; 7913 STATE_UNLOCK(ctx); 7914 } 7915 7916 #ifndef __NO_STRICT_ALIGNMENT 7917 static struct mbuf * 7918 iflib_fixup_rx(struct mbuf *m) 7919 { 7920 struct mbuf *n; 7921 7922 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7923 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7924 m->m_data += ETHER_HDR_LEN; 7925 n = m; 7926 } else { 7927 MGETHDR(n, M_NOWAIT, MT_DATA); 7928 if (n == NULL) { 7929 m_freem(m); 7930 return (NULL); 7931 } 7932 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7933 m->m_data += ETHER_HDR_LEN; 7934 m->m_len -= ETHER_HDR_LEN; 7935 n->m_len = ETHER_HDR_LEN; 7936 M_MOVE_PKTHDR(n, m); 7937 n->m_next = m; 7938 } 7939 return (n); 7940 } 7941 #endif 7942 7943 #ifdef DEBUGNET 7944 static void 7945 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7946 { 7947 if_ctx_t ctx; 7948 7949 ctx = if_getsoftc(ifp); 7950 CTX_LOCK(ctx); 7951 *nrxr = NRXQSETS(ctx); 7952 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7953 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7954 CTX_UNLOCK(ctx); 7955 } 7956 7957 static void 7958 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7959 { 7960 if_ctx_t ctx; 7961 if_softc_ctx_t scctx; 7962 iflib_fl_t fl; 7963 iflib_rxq_t rxq; 7964 int i, j; 7965 7966 ctx = if_getsoftc(ifp); 7967 scctx = &ctx->ifc_softc_ctx; 7968 7969 switch (event) { 7970 case DEBUGNET_START: 7971 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7972 rxq = &ctx->ifc_rxqs[i]; 7973 for (j = 0; j < rxq->ifr_nfl; j++) { 7974 fl = rxq->ifr_fl; 7975 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7976 } 7977 } 7978 iflib_no_tx_batch = 1; 7979 break; 7980 default: 7981 break; 7982 } 7983 } 7984 7985 static int 7986 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7987 { 7988 if_ctx_t ctx; 7989 iflib_txq_t txq; 7990 int error; 7991 int bytes_sent = 0; 7992 int pkt_sent = 0; 7993 7994 ctx = if_getsoftc(ifp); 7995 if (!iflib_is_running(ctx)) 7996 return (EBUSY); 7997 7998 txq = &ctx->ifc_txqs[0]; 7999 error = iflib_encap(txq, &m, &bytes_sent, &pkt_sent); 8000 if (error == 0) 8001 (void)iflib_txd_db_check(txq, true); 8002 return (error); 8003 } 8004 8005 static int 8006 iflib_debugnet_poll(if_t ifp, int count) 8007 { 8008 struct epoch_tracker et; 8009 if_ctx_t ctx; 8010 if_softc_ctx_t scctx; 8011 iflib_txq_t txq; 8012 int i; 8013 8014 ctx = if_getsoftc(ifp); 8015 scctx = &ctx->ifc_softc_ctx; 8016 8017 if (!iflib_is_running(ctx)) 8018 return (EBUSY); 8019 8020 txq = &ctx->ifc_txqs[0]; 8021 (void)iflib_completed_tx_reclaim(txq, NULL); 8022 8023 NET_EPOCH_ENTER(et); 8024 for (i = 0; i < scctx->isc_nrxqsets; i++) 8025 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 8026 NET_EPOCH_EXIT(et); 8027 return (0); 8028 } 8029 #endif /* DEBUGNET */ 8030 8031 enum iflib_txq_producer_status { 8032 IFLIB_TXQ_PRODUCER_ENTERED, 8033 IFLIB_TXQ_PRODUCER_QUIESCING, 8034 IFLIB_TXQ_PRODUCER_REMOTE, 8035 }; 8036 8037 /* 8038 * Keep the most recent producer llc when the count reaches zero. Producers 8039 * in that llc can use fetchadd without contending on a compare-and-swap. 8040 * Another llc can take ownership only while the producer count is zero. 8041 */ 8042 static __inline enum iflib_txq_producer_status 8043 iflib_txq_producer_enter(iflib_txq_t txq, bool *pinned) 8044 { 8045 u_int count, llc_id, max_producers, newstate, old, state; 8046 8047 if (!iflib_producer_gate) { 8048 state = atomic_fetchadd_int(&txq->ift_producers, 1); 8049 if (__predict_false((state & IFLIB_TXQ_QUIESCING) != 0)) { 8050 atomic_subtract_int(&txq->ift_producers, 1); 8051 return (IFLIB_TXQ_PRODUCER_QUIESCING); 8052 } 8053 *pinned = false; 8054 return (IFLIB_TXQ_PRODUCER_ENTERED); 8055 } 8056 8057 max_producers = iflib_max_producers; 8058 if (iflib_single_llc) { 8059 state = atomic_fetchadd_int(&txq->ift_producers, 1); 8060 if (__predict_false((state & IFLIB_TXQ_QUIESCING) != 0)) { 8061 atomic_subtract_int(&txq->ift_producers, 1); 8062 return (IFLIB_TXQ_PRODUCER_QUIESCING); 8063 } 8064 count = IFLIB_TXQ_PRODUCER(state); 8065 if (count >= max_producers || 8066 count == IFLIB_TXQ_PRODUCER_MAX) { 8067 atomic_subtract_int(&txq->ift_producers, 1); 8068 return (IFLIB_TXQ_PRODUCER_REMOTE); 8069 } 8070 *pinned = false; 8071 return (IFLIB_TXQ_PRODUCER_ENTERED); 8072 } 8073 8074 sched_pin(); 8075 llc_id = iflib_cpu_llc[curcpu]; 8076 state = atomic_load_acq_int(&txq->ift_producers); 8077 for (;;) { 8078 if ((state & IFLIB_TXQ_QUIESCING) != 0) { 8079 sched_unpin(); 8080 return (IFLIB_TXQ_PRODUCER_QUIESCING); 8081 } 8082 8083 count = IFLIB_TXQ_PRODUCER(state); 8084 if (count >= max_producers || 8085 count == IFLIB_TXQ_PRODUCER_MAX) { 8086 sched_unpin(); 8087 return (IFLIB_TXQ_PRODUCER_REMOTE); 8088 } 8089 if (IFLIB_TXQ_PRODUCER_LLC(state) == llc_id) { 8090 /* 8091 * The llc can change between the load and fetchadd only 8092 * if the count was zero. Validate the returned 8093 * state and undo the increment if ownership changed. 8094 */ 8095 old = atomic_fetchadd_int(&txq->ift_producers, 1); 8096 if ((old & IFLIB_TXQ_QUIESCING) != 0) { 8097 atomic_subtract_int(&txq->ift_producers, 1); 8098 sched_unpin(); 8099 return (IFLIB_TXQ_PRODUCER_QUIESCING); 8100 } 8101 count = IFLIB_TXQ_PRODUCER(old); 8102 if (IFLIB_TXQ_PRODUCER_LLC(old) == llc_id && 8103 count < max_producers && 8104 count != IFLIB_TXQ_PRODUCER_MAX) { 8105 *pinned = true; 8106 return (IFLIB_TXQ_PRODUCER_ENTERED); 8107 } 8108 8109 atomic_subtract_int(&txq->ift_producers, 1); 8110 sched_unpin(); 8111 return (IFLIB_TXQ_PRODUCER_REMOTE); 8112 } 8113 8114 if (count != 0) { 8115 sched_unpin(); 8116 return (IFLIB_TXQ_PRODUCER_REMOTE); 8117 } 8118 8119 newstate = llc_id << IFLIB_TXQ_PRODUCER_LLC_SHIFT; 8120 newstate |= 1; 8121 if (atomic_fcmpset_acq_int(&txq->ift_producers, &state, 8122 newstate)) { 8123 *pinned = true; 8124 return (IFLIB_TXQ_PRODUCER_ENTERED); 8125 } 8126 } 8127 } 8128 8129 static __inline void 8130 iflib_txq_producer_exit(iflib_txq_t txq, bool pinned) 8131 { 8132 u_int state __diagused; 8133 8134 if (!pinned) { 8135 atomic_subtract_rel_int(&txq->ift_producers, 1); 8136 return; 8137 } 8138 8139 atomic_thread_fence_rel(); 8140 state = atomic_fetchadd_int(&txq->ift_producers, -1); 8141 KASSERT(IFLIB_TXQ_PRODUCER(state) != 0, 8142 ("%s: producer count underflow", __func__)); 8143 KASSERT(IFLIB_TXQ_PRODUCER_LLC(state) == iflib_cpu_llc[curcpu], 8144 ("%s: producer llc changed", __func__)); 8145 sched_unpin(); 8146 } 8147 8148 /* Consumes the mbuf in all cases */ 8149 static int 8150 iflib_simple_encap(iflib_txq_t txq, struct mbuf *m, int *bytes, int *pkts, 8151 int *mcasts) 8152 { 8153 if_t ifp; 8154 int error; 8155 8156 mtx_assert(&txq->ift_mtx, MA_OWNED); 8157 ifp = txq->ift_ctx->ifc_ifp; 8158 8159 error = iflib_encap(txq, &m, bytes, pkts); 8160 if (__predict_false(error != 0)) { 8161 /* iflib_encap() always frees the mbuf on failures */ 8162 if (error == ENOBUFS) 8163 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1); 8164 else 8165 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 8166 return (error); 8167 } 8168 *mcasts += !!(m->m_flags & M_MCAST); 8169 DBG_COUNTER_INC(tx_sent); 8170 ETHER_BPF_MTAP(ifp, m); 8171 (void)iflib_txd_db_check(txq, false); 8172 return (0); 8173 } 8174 8175 /* Drain the deferral ring into the hardware. */ 8176 static void 8177 iflib_simple_drbr_drain(iflib_txq_t txq, u_int quota, int *bytes, int *pkts, 8178 int *mcasts) 8179 { 8180 if_ctx_t ctx; 8181 struct mbuf *m; 8182 if_t ifp; 8183 u_int i; 8184 8185 mtx_assert(&txq->ift_mtx, MA_OWNED); 8186 ctx = txq->ift_ctx; 8187 ifp = ctx->ifc_ifp; 8188 if (__predict_false(!iflib_is_running(ctx) || !LINK_ACTIVE(ctx))) 8189 return; 8190 8191 #ifdef ALTQ 8192 /* We only drain from txq0 when altq is enabled. */ 8193 if (__predict_false(if_altq_is_enabled(ifp) && txq->ift_id != 0)) 8194 return; 8195 #endif 8196 for (i = 0; TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx); i++) { 8197 if (i == quota) 8198 return; 8199 m = drbr_dequeue(ifp, txq->ift_drbr); 8200 if (m == NULL) 8201 return; 8202 (void)iflib_simple_encap(txq, m, bytes, pkts, mcasts); 8203 } 8204 if (!drbr_empty(ifp, txq->ift_drbr)) { 8205 txq->ift_drbr_stall++; 8206 if (quota != iflib_simple_drain_quota && 8207 (txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 8208 GROUPTASK_ENQUEUE(&txq->ift_task); 8209 } 8210 } 8211 8212 /* 8213 * Reclaim completed descriptors and push out anything that was deferred while 8214 * the tx lock was held. Called from tx completion and from the timer. 8215 * A thread already holding the lock is draining, and will re-arm us if it 8216 * cannot finish, so never wait for it here. 8217 */ 8218 static void 8219 iflib_simple_txq_drain(iflib_txq_t txq) 8220 { 8221 if_t ifp; 8222 int bytes_sent = 0, pkt_sent = 0, mcast_sent = 0; 8223 8224 ifp = txq->ift_ctx->ifc_ifp; 8225 8226 if (!mtx_trylock(&txq->ift_mtx)) 8227 return; 8228 8229 if ((atomic_load_acq_int(&txq->ift_producers) & IFLIB_TXQ_QUIESCING) 8230 != 0) { 8231 mtx_unlock(&txq->ift_mtx); 8232 return; 8233 } 8234 8235 (void)iflib_completed_tx_reclaim(txq, NULL); 8236 if (!drbr_empty(ifp, txq->ift_drbr)) 8237 iflib_simple_drbr_drain(txq, iflib_simple_drain_quota, 8238 &bytes_sent, &pkt_sent, &mcast_sent); 8239 if (txq->ift_db_pending != 0) 8240 (void)iflib_txd_db_check(txq, true); 8241 mtx_unlock(&txq->ift_mtx); 8242 8243 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 8244 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 8245 if (mcast_sent) 8246 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 8247 } 8248 8249 /* 8250 * When nothing is queued ahead of us there is no ordering constraint, 8251 * so the mbuf goes straight to the hardware and the deferral ring is 8252 * never touched. 8253 */ 8254 static int 8255 iflib_simple_transmit_locked(iflib_txq_t txq, struct mbuf *m, int *bytes, 8256 int *pkts, int *mcasts) 8257 { 8258 if_ctx_t ctx; 8259 if_t ifp; 8260 int error; 8261 8262 mtx_assert(&txq->ift_mtx, MA_OWNED); 8263 ctx = txq->ift_ctx; 8264 ifp = ctx->ifc_ifp; 8265 8266 if (__predict_true(!drbr_needs_enqueue(ifp, txq->ift_drbr) && 8267 TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx))) { 8268 txq->ift_drbr_direct++; 8269 error = iflib_simple_encap(txq, m, bytes, pkts, mcasts); 8270 } else { 8271 error = buf_ring_enqueue(txq->ift_drbr, m); 8272 if (__predict_false(error != 0)) { 8273 m_freem(m); 8274 DBG_COUNTER_INC(tx_frees); 8275 counter_u64_add(txq->ift_drbr_drops, 1); 8276 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1); 8277 } 8278 } 8279 8280 /* 8281 * Other transmitters may have deferred to the ring while we were in 8282 * iflib_encap(), so always check again before dropping the lock. We 8283 * are the only thread that can drain it. 8284 */ 8285 if (!drbr_empty(ifp, txq->ift_drbr)) 8286 iflib_simple_drbr_drain(txq, iflib_simple_drain_quota_thread, 8287 bytes, pkts, mcasts); 8288 return (error); 8289 } 8290 8291 /* 8292 * Always inline the common transmit path so queue selection does not add a 8293 * function call to the default simple transmit path. 8294 */ 8295 static __always_inline int 8296 iflib_simple_transmit_impl(if_ctx_t ctx, if_t ifp, struct mbuf *m, 8297 iflib_txq_t txq) 8298 { 8299 struct mbuf **m_defer; 8300 enum iflib_txq_producer_status producer_status; 8301 bool pinned; 8302 int error, i, reclaimable; 8303 int bytes_sent = 0, pkt_sent = 0, mcast_sent = 0; 8304 8305 8306 #ifdef ALTQ 8307 if (if_altq_is_enabled(ifp)) { 8308 IFQ_ENQUEUE(&ifp->if_snd, m, error); /* XXX - DRVAPI */ 8309 if (error == 0) 8310 if_start(ifp); 8311 return (error); 8312 } 8313 #endif 8314 8315 ctx = if_getsoftc(ifp); 8316 if (__predict_false(!iflib_is_running(ctx) || !LINK_ACTIVE(ctx))) 8317 goto net_down; 8318 8319 /* 8320 * Avoid blocking behind another transmitter; the ring is drained by 8321 * whoever holds ift_mtx, by tx completion, or by the watchdog timer. 8322 */ 8323 if (__predict_false(!mtx_trylock(&txq->ift_mtx))) { 8324 producer_status = iflib_txq_producer_enter(txq, &pinned); 8325 if (producer_status == IFLIB_TXQ_PRODUCER_QUIESCING) 8326 goto net_down; 8327 8328 if (producer_status == IFLIB_TXQ_PRODUCER_ENTERED) { 8329 error = buf_ring_enqueue(txq->ift_drbr, m); 8330 iflib_txq_producer_exit(txq, pinned); 8331 if (__predict_true(error == 0)) { 8332 counter_u64_add(txq->ift_drbr_deferred, 1); 8333 return (0); 8334 } 8335 counter_u64_add(txq->ift_drbr_blocked, 1); 8336 } else { 8337 counter_u64_add(txq->ift_drbr_remote, 1); 8338 } 8339 mtx_lock(&txq->ift_mtx); 8340 } 8341 8342 if (__predict_false(atomic_load_acq_int(&txq->ift_producers) & 8343 IFLIB_TXQ_QUIESCING)) { 8344 mtx_unlock(&txq->ift_mtx); 8345 goto net_down; 8346 } 8347 8348 error = iflib_simple_transmit_locked(txq, m, &bytes_sent, &pkt_sent, 8349 &mcast_sent); 8350 if (txq->ift_db_pending != 0) 8351 (void)iflib_txd_db_check(txq, true); 8352 m_defer = NULL; 8353 reclaimable = iflib_txq_can_reclaim(txq); 8354 if (reclaimable != 0) { 8355 /* 8356 * Try to set m_defer to the deferred mbuf reclaim array. If 8357 * we can, the frees will happen outside the tx lock. If we 8358 * can't, it means another thread is still proccessing frees. 8359 */ 8360 if (txq->ift_defer_mfree && 8361 atomic_cmpset_acq_ptr((uintptr_t *)&txq->ift_sds.ifsd_m_defer, 8362 (uintptr_t )txq->ift_sds.ifsd_m_deferb, 0)) { 8363 m_defer = txq->ift_sds.ifsd_m_deferb; 8364 } 8365 _iflib_completed_tx_reclaim(txq, m_defer, reclaimable); 8366 } 8367 mtx_unlock(&txq->ift_mtx); 8368 8369 /* 8370 * Process mbuf frees outside the tx lock 8371 */ 8372 if (m_defer != NULL) { 8373 for (i = 0; m_defer[i] != NULL; i++) { 8374 m_freem(m_defer[i]); 8375 m_defer[i] = NULL; 8376 } 8377 atomic_store_rel_ptr((uintptr_t *)&txq->ift_sds.ifsd_m_defer, 8378 (uintptr_t)m_defer); 8379 } 8380 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 8381 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 8382 if (mcast_sent) 8383 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 8384 8385 return (error); 8386 8387 net_down: 8388 m_freem(m); 8389 DBG_COUNTER_INC(tx_frees); 8390 return (ENETDOWN); 8391 } 8392 8393 static int 8394 iflib_simple_transmit(if_t ifp, struct mbuf *m) 8395 { 8396 if_ctx_t ctx; 8397 iflib_txq_t txq; 8398 int qidx; 8399 8400 ctx = if_getsoftc(ifp); 8401 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 8402 qidx = QIDX(ctx, m); 8403 else 8404 qidx = NTXQSETS(ctx) + FIRST_QSET(ctx) - 1; 8405 MPASS(qidx < NTXQSETS(ctx)); 8406 txq = &ctx->ifc_txqs[qidx]; 8407 return (iflib_simple_transmit_impl(ctx, ifp, m, txq)); 8408 } 8409 8410 static int 8411 iflib_simple_transmit_txq_select(if_t ifp, struct mbuf *m) 8412 { 8413 if_ctx_t ctx; 8414 int qidx; 8415 8416 ctx = if_getsoftc(ifp); 8417 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 8418 MPASS(qidx < NTXQSETS(ctx)); 8419 return (iflib_simple_transmit_impl(ctx, ifp, m, 8420 &ctx->ifc_txqs[qidx])); 8421 } 8422 8423 static int 8424 iflib_simple_transmit_txq_select_v2(if_t ifp, struct mbuf *m) 8425 { 8426 struct if_pkt_info pi; 8427 if_ctx_t ctx; 8428 uint64_t early_pullups = 0; 8429 int error, qidx; 8430 8431 ctx = if_getsoftc(ifp); 8432 memset(&pi, 0, sizeof(pi)); 8433 error = iflib_parse_header_partial(&pi, &m, &early_pullups); 8434 if (error != 0) { 8435 /* Assign pullups for bad packets to the default queue. */ 8436 ctx->ifc_txqs[0].ift_pullups += early_pullups; 8437 DBG_COUNTER_INC(encap_txd_encap_fail); 8438 return (error); 8439 } 8440 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi); 8441 MPASS(qidx < NTXQSETS(ctx)); 8442 ctx->ifc_txqs[qidx].ift_pullups += early_pullups; 8443 return (iflib_simple_transmit_impl(ctx, ifp, m, 8444 &ctx->ifc_txqs[qidx])); 8445 } 8446 8447 /* 8448 * ALTQ entry point. drbr_dequeue() pulls from ifp->if_snd when a discipline 8449 * is attached, so the drain loop is shared with the if_transmit path. Only 8450 * queue zero is used, matching the queue ALTQ itself selects. 8451 */ 8452 static void 8453 iflib_simple_if_start(if_t ifp) 8454 { 8455 if_ctx_t ctx; 8456 iflib_txq_t txq; 8457 bool retry; 8458 int bytes_sent = 0, pkt_sent = 0, mcast_sent = 0; 8459 8460 ctx = if_getsoftc(ifp); 8461 txq = &ctx->ifc_txqs[0]; 8462 8463 mtx_lock(&txq->ift_mtx); 8464 (void)iflib_completed_tx_reclaim(txq, NULL); 8465 iflib_simple_drbr_drain(txq, UINT_MAX, &bytes_sent, &pkt_sent, 8466 &mcast_sent); 8467 if (txq->ift_db_pending != 0) 8468 (void)iflib_txd_db_check(txq, true); 8469 retry = !drbr_empty(ifp, txq->ift_drbr); 8470 mtx_unlock(&txq->ift_mtx); 8471 8472 if (retry) 8473 GROUPTASK_ENQUEUE(&txq->ift_task); 8474 8475 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 8476 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 8477 if (mcast_sent) 8478 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 8479 } 8480