1 //===- LoongArchFixupKinds.h - LoongArch Specific Fixup Entries -*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHFIXUPKINDS_H 10 #define LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHFIXUPKINDS_H 11 12 #include "llvm/BinaryFormat/ELF.h" 13 #include "llvm/MC/MCFixup.h" 14 15 #undef LoongArch 16 17 namespace llvm { 18 namespace LoongArch { 19 // 20 // This table *must* be in the same order of 21 // MCFixupKindInfo Infos[LoongArch::NumTargetFixupKinds] in 22 // LoongArchAsmBackend.cpp. 23 // 24 enum Fixups { 25 // Define fixups can be handled by LoongArchAsmBackend::applyFixup. 26 // 16-bit fixup corresponding to %b16(foo) for instructions like bne. 27 fixup_loongarch_b16 = FirstTargetFixupKind, 28 // 21-bit fixup corresponding to %b21(foo) for instructions like bnez. 29 fixup_loongarch_b21, 30 // 26-bit fixup corresponding to %b26(foo)/%plt(foo) for instructions b/bl. 31 fixup_loongarch_b26, 32 // 20-bit fixup corresponding to %abs_hi20(foo) for instruction lu12i.w. 33 fixup_loongarch_abs_hi20, 34 // 12-bit fixup corresponding to %abs_lo12(foo) for instruction ori. 35 fixup_loongarch_abs_lo12, 36 // 20-bit fixup corresponding to %abs64_lo20(foo) for instruction lu32i.d. 37 fixup_loongarch_abs64_lo20, 38 // 12-bit fixup corresponding to %abs_hi12(foo) for instruction lu52i.d. 39 fixup_loongarch_abs64_hi12, 40 // 20-bit fixup corresponding to %le_hi20(foo) for instruction lu12i.w. 41 fixup_loongarch_tls_le_hi20, 42 // 12-bit fixup corresponding to %le_lo12(foo) for instruction ori. 43 fixup_loongarch_tls_le_lo12, 44 // 20-bit fixup corresponding to %le64_lo20(foo) for instruction lu32i.d. 45 fixup_loongarch_tls_le64_lo20, 46 // 12-bit fixup corresponding to %le64_hi12(foo) for instruction lu52i.d. 47 fixup_loongarch_tls_le64_hi12, 48 // TODO: Add more fixup kind. 49 50 // Used as a sentinel, must be the last of the fixup which can be handled by 51 // LoongArchAsmBackend::applyFixup. 52 fixup_loongarch_invalid, 53 NumTargetFixupKinds = fixup_loongarch_invalid - FirstTargetFixupKind, 54 55 // Define fixups for force relocation as FirstLiteralRelocationKind+V 56 // represents the relocation type with number V. 57 // 20-bit fixup corresponding to %pc_hi20(foo) for instruction pcalau12i. 58 fixup_loongarch_pcala_hi20 = 59 FirstLiteralRelocationKind + ELF::R_LARCH_PCALA_HI20, 60 // 12-bit fixup corresponding to %pc_lo12(foo) for instructions like addi.w/d. 61 fixup_loongarch_pcala_lo12, 62 // 20-bit fixup corresponding to %pc64_lo20(foo) for instruction lu32i.d. 63 fixup_loongarch_pcala64_lo20, 64 // 12-bit fixup corresponding to %pc64_hi12(foo) for instruction lu52i.d. 65 fixup_loongarch_pcala64_hi12, 66 // 20-bit fixup corresponding to %got_pc_hi20(foo) for instruction pcalau12i. 67 fixup_loongarch_got_pc_hi20, 68 // 12-bit fixup corresponding to %got_pc_lo12(foo) for instructions 69 // ld.w/ld.d/add.d. 70 fixup_loongarch_got_pc_lo12, 71 // 20-bit fixup corresponding to %got64_pc_lo20(foo) for instruction lu32i.d. 72 fixup_loongarch_got64_pc_lo20, 73 // 12-bit fixup corresponding to %got64_pc_hi12(foo) for instruction lu52i.d. 74 fixup_loongarch_got64_pc_hi12, 75 // 20-bit fixup corresponding to %got_hi20(foo) for instruction lu12i.w. 76 fixup_loongarch_got_hi20, 77 // 12-bit fixup corresponding to %got_lo12(foo) for instruction ori. 78 fixup_loongarch_got_lo12, 79 // 20-bit fixup corresponding to %got64_lo20(foo) for instruction lu32i.d. 80 fixup_loongarch_got64_lo20, 81 // 12-bit fixup corresponding to %got64_hi12(foo) for instruction lu52i.d. 82 fixup_loongarch_got64_hi12, 83 // Skip R_LARCH_TLS_LE_*. 84 // 20-bit fixup corresponding to %ie_pc_hi20(foo) for instruction pcalau12i. 85 fixup_loongarch_tls_ie_pc_hi20 = 86 FirstLiteralRelocationKind + ELF::R_LARCH_TLS_IE_PC_HI20, 87 // 12-bit fixup corresponding to %ie_pc_lo12(foo) for instructions 88 // ld.w/ld.d/add.d. 89 fixup_loongarch_tls_ie_pc_lo12, 90 // 20-bit fixup corresponding to %ie64_pc_lo20(foo) for instruction lu32i.d. 91 fixup_loongarch_tls_ie64_pc_lo20, 92 // 12-bit fixup corresponding to %ie64_pc_hi12(foo) for instruction lu52i.d. 93 fixup_loongarch_tls_ie64_pc_hi12, 94 // 20-bit fixup corresponding to %ie_hi20(foo) for instruction lu12i.w. 95 fixup_loongarch_tls_ie_hi20, 96 // 12-bit fixup corresponding to %ie_lo12(foo) for instruction ori. 97 fixup_loongarch_tls_ie_lo12, 98 // 20-bit fixup corresponding to %ie64_lo20(foo) for instruction lu32i.d. 99 fixup_loongarch_tls_ie64_lo20, 100 // 12-bit fixup corresponding to %ie64_hi12(foo) for instruction lu52i.d. 101 fixup_loongarch_tls_ie64_hi12, 102 // 20-bit fixup corresponding to %ld_pc_hi20(foo) for instruction pcalau12i. 103 fixup_loongarch_tls_ld_pc_hi20, 104 // 20-bit fixup corresponding to %ld_hi20(foo) for instruction lu12i.w. 105 fixup_loongarch_tls_ld_hi20, 106 // 20-bit fixup corresponding to %gd_pc_hi20(foo) for instruction pcalau12i. 107 fixup_loongarch_tls_gd_pc_hi20, 108 // 20-bit fixup corresponding to %gd_hi20(foo) for instruction lu12i.w. 109 fixup_loongarch_tls_gd_hi20, 110 // Generate an R_LARCH_RELAX which indicates the linker may relax here. 111 fixup_loongarch_relax = FirstLiteralRelocationKind + ELF::R_LARCH_RELAX, 112 // Generate an R_LARCH_ALIGN which indicates the linker may fixup align here. 113 fixup_loongarch_align = FirstLiteralRelocationKind + ELF::R_LARCH_ALIGN, 114 // 20-bit fixup corresponding to %pcrel_20(foo) for instruction pcaddi. 115 fixup_loongarch_pcrel20_s2, 116 // 36-bit fixup corresponding to %call36(foo) for a pair instructions: 117 // pcaddu18i+jirl. 118 fixup_loongarch_call36 = FirstLiteralRelocationKind + ELF::R_LARCH_CALL36, 119 // 20-bit fixup corresponding to %desc_pc_hi20(foo) for instruction pcalau12i. 120 fixup_loongarch_tls_desc_pc_hi20 = 121 FirstLiteralRelocationKind + ELF::R_LARCH_TLS_DESC_PC_HI20, 122 // 12-bit fixup corresponding to %desc_pc_lo12(foo) for instructions like 123 // addi.w/d. 124 fixup_loongarch_tls_desc_pc_lo12, 125 // 20-bit fixup corresponding to %desc64_pc_lo20(foo) for instruction lu32i.d. 126 fixup_loongarch_tls_desc64_pc_lo20, 127 // 12-bit fixup corresponding to %desc64_pc_hi12(foo) for instruction lu52i.d. 128 fixup_loongarch_tls_desc64_pc_hi12, 129 // 20-bit fixup corresponding to %desc_hi20(foo) for instruction lu12i.w. 130 fixup_loongarch_tls_desc_hi20, 131 // 12-bit fixup corresponding to %desc_lo12(foo) for instruction ori. 132 fixup_loongarch_tls_desc_lo12, 133 // 20-bit fixup corresponding to %desc64_lo20(foo) for instruction lu32i.d. 134 fixup_loongarch_tls_desc64_lo20, 135 // 12-bit fixup corresponding to %desc64_hi12(foo) for instruction lu52i.d. 136 fixup_loongarch_tls_desc64_hi12, 137 // 12-bit fixup corresponding to %desc_ld(foo) for instruction ld.w/d. 138 fixup_loongarch_tls_desc_ld, 139 // 12-bit fixup corresponding to %desc_call(foo) for instruction jirl. 140 fixup_loongarch_tls_desc_call, 141 // 20-bit fixup corresponding to %le_hi20_r(foo) for instruction lu12i.w. 142 fixup_loongarch_tls_le_hi20_r, 143 // Fixup corresponding to %le_add_r(foo) for instruction PseudoAddTPRel_W/D. 144 fixup_loongarch_tls_le_add_r, 145 // 12-bit fixup corresponding to %le_lo12_r(foo) for instruction addi.w/d. 146 fixup_loongarch_tls_le_lo12_r, 147 // 20-bit fixup corresponding to %ld_pcrel_20(foo) for instruction pcaddi. 148 fixup_loongarch_tls_ld_pcrel20_s2, 149 // 20-bit fixup corresponding to %gd_pcrel_20(foo) for instruction pcaddi. 150 fixup_loongarch_tls_gd_pcrel20_s2, 151 // 20-bit fixup corresponding to %desc_pcrel_20(foo) for instruction pcaddi. 152 fixup_loongarch_tls_desc_pcrel20_s2, 153 }; 154 } // end namespace LoongArch 155 } // end namespace llvm 156 157 #endif 158