1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2024, Intel Corporation.
4 */
5
6 #include <linux/debugfs.h>
7
8 #include <drm/drm_print.h>
9
10 #include "intel_alpm.h"
11 #include "intel_crtc.h"
12 #include "intel_de.h"
13 #include "intel_display_types.h"
14 #include "intel_dp.h"
15 #include "intel_dp_aux.h"
16 #include "intel_psr.h"
17 #include "intel_psr_regs.h"
18
19 #define SILENCE_PERIOD_MIN_TIME 80
20 #define SILENCE_PERIOD_MAX_TIME 180
21 #define SILENCE_PERIOD_TIME (SILENCE_PERIOD_MIN_TIME + \
22 (SILENCE_PERIOD_MAX_TIME - \
23 SILENCE_PERIOD_MIN_TIME) / 2)
24
25 #define LFPS_CYCLE_COUNT 10
26
intel_alpm_aux_wake_supported(struct intel_dp * intel_dp)27 bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
28 {
29 return intel_dp->alpm_dpcd & DP_ALPM_CAP;
30 }
31
intel_alpm_aux_less_wake_supported(struct intel_dp * intel_dp)32 bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)
33 {
34 return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;
35 }
36
intel_alpm_is_alpm_aux_less(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)37 bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
38 const struct intel_crtc_state *crtc_state)
39 {
40 return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) ||
41 (crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
42 }
43
intel_alpm_init(struct intel_dp * intel_dp)44 void intel_alpm_init(struct intel_dp *intel_dp)
45 {
46 mutex_init(&intel_dp->alpm.lock);
47 }
48
get_silence_period_symbols(const struct intel_crtc_state * crtc_state)49 static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
50 {
51 return SILENCE_PERIOD_TIME * intel_dp_link_symbol_clock(crtc_state->port_clock) /
52 1000 / 1000;
53 }
54
get_lfps_cycle_min_max_time(const struct intel_crtc_state * crtc_state,int * min,int * max)55 static void get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state,
56 int *min, int *max)
57 {
58 if (crtc_state->port_clock < 540000) {
59 *min = 65 * LFPS_CYCLE_COUNT;
60 *max = 75 * LFPS_CYCLE_COUNT;
61 } else {
62 *min = 140;
63 *max = 800;
64 }
65 }
66
get_lfps_cycle_time(const struct intel_crtc_state * crtc_state)67 static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
68 {
69 int tlfps_cycle_min, tlfps_cycle_max;
70
71 get_lfps_cycle_min_max_time(crtc_state, &tlfps_cycle_min,
72 &tlfps_cycle_max);
73
74 return tlfps_cycle_min + (tlfps_cycle_max - tlfps_cycle_min) / 2;
75 }
76
get_lfps_half_cycle_clocks(const struct intel_crtc_state * crtc_state)77 static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
78 {
79 return get_lfps_cycle_time(crtc_state) * crtc_state->port_clock / 1000 /
80 1000 / (2 * LFPS_CYCLE_COUNT);
81 }
82
83 /*
84 * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
85 * tSilence, Max+ tPHY Establishment + tCDS) / tline)
86 * For the "PHY P2 to P0" latency see the PHY Power Control page
87 * (PHY P2 to P0) : https://gfxspecs.intel.com/Predator/Home/Index/68965
88 * : 12 us
89 * The tLFPS_Period, Max term is 800ns
90 * The tSilence, Max term is 180ns
91 * The tPHY Establishment (a.k.a. t1) term is 50us
92 * The tCDS term is 1 or 2 times t2
93 * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK
94 * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1)
95 * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and
96 * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start
97 * within the CDS period complete within the CDS period regardless of
98 * entry into the period
99 * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
100 * TPS4 Length = 252 Symbols
101 */
_lnl_compute_aux_less_wake_time(const struct intel_crtc_state * crtc_state)102 static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state)
103 {
104 int tphy2_p2_to_p0 = 12 * 1000;
105 int t1 = 50 * 1000;
106 int tps4 = 252;
107 /* port_clock is link rate in 10kbit/s units */
108 int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
109 int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
110 int t2 = num_ml_phy_lock * tml_phy_lock;
111 int tcds = 1 * t2;
112
113 return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
114 SILENCE_PERIOD_TIME + t1 + tcds, 1000);
115 }
116
117 static int
_lnl_compute_aux_less_alpm_params(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)118 _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
119 struct intel_crtc_state *crtc_state)
120 {
121 struct intel_display *display = to_intel_display(intel_dp);
122 int aux_less_wake_time, aux_less_wake_lines, silence_period,
123 lfps_half_cycle;
124
125 aux_less_wake_time =
126 _lnl_compute_aux_less_wake_time(crtc_state);
127 aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
128 aux_less_wake_time);
129 silence_period = get_silence_period_symbols(crtc_state);
130
131 lfps_half_cycle = get_lfps_half_cycle_clocks(crtc_state);
132
133 if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||
134 silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||
135 lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK)
136 return false;
137
138 if (display->params.psr_safest_params)
139 aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;
140
141 crtc_state->alpm_state.aux_less_wake_lines = aux_less_wake_lines;
142 crtc_state->alpm_state.silence_period_sym_clocks = silence_period;
143 crtc_state->alpm_state.lfps_half_cycle_num_of_syms = lfps_half_cycle;
144
145 return true;
146 }
147
_lnl_compute_alpm_params(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)148 static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,
149 struct intel_crtc_state *crtc_state)
150 {
151 struct intel_display *display = to_intel_display(intel_dp);
152 int check_entry_lines;
153
154 if (DISPLAY_VER(display) < 20)
155 return true;
156
157 /* ALPM Entry Check = 2 + CEILING( 5us /tline ) */
158 check_entry_lines = 2 +
159 intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 5);
160
161 if (check_entry_lines > 15)
162 return false;
163
164 if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state))
165 return false;
166
167 if (display->params.psr_safest_params)
168 check_entry_lines = 15;
169
170 crtc_state->alpm_state.check_entry_lines = check_entry_lines;
171
172 return true;
173 }
174
175 /*
176 * IO wake time for DISPLAY_VER < 12 is not directly mentioned in Bspec. There
177 * are 50 us io wake time and 32 us fast wake time. Clearly preharge pulses are
178 * not (improperly) included in 32 us fast wake time. 50 us - 32 us = 18 us.
179 */
skl_io_buffer_wake_time(void)180 static int skl_io_buffer_wake_time(void)
181 {
182 return 18;
183 }
184
tgl_io_buffer_wake_time(void)185 static int tgl_io_buffer_wake_time(void)
186 {
187 return 10;
188 }
189
io_buffer_wake_time(const struct intel_crtc_state * crtc_state)190 static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state)
191 {
192 struct intel_display *display = to_intel_display(crtc_state);
193
194 if (DISPLAY_VER(display) >= 12)
195 return tgl_io_buffer_wake_time();
196 else
197 return skl_io_buffer_wake_time();
198 }
199
intel_alpm_compute_params(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)200 bool intel_alpm_compute_params(struct intel_dp *intel_dp,
201 struct intel_crtc_state *crtc_state)
202 {
203 struct intel_display *display = to_intel_display(intel_dp);
204 int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time;
205 int tfw_exit_latency = 20; /* eDP spec */
206 int phy_wake = 4; /* eDP spec */
207 int preamble = 8; /* eDP spec */
208 int precharge = intel_dp_aux_fw_sync_len(intel_dp) - preamble;
209 u8 max_wake_lines;
210
211 io_wake_time = max(precharge, io_buffer_wake_time(crtc_state)) +
212 preamble + phy_wake + tfw_exit_latency;
213 fast_wake_time = precharge + preamble + phy_wake +
214 tfw_exit_latency;
215
216 if (DISPLAY_VER(display) >= 20)
217 max_wake_lines = 68;
218 else if (DISPLAY_VER(display) >= 12)
219 max_wake_lines = 12;
220 else
221 max_wake_lines = 8;
222
223 io_wake_lines = intel_usecs_to_scanlines(
224 &crtc_state->hw.adjusted_mode, io_wake_time);
225 fast_wake_lines = intel_usecs_to_scanlines(
226 &crtc_state->hw.adjusted_mode, fast_wake_time);
227
228 if (io_wake_lines > max_wake_lines ||
229 fast_wake_lines > max_wake_lines)
230 return false;
231
232 if (!_lnl_compute_alpm_params(intel_dp, crtc_state))
233 return false;
234
235 if (display->params.psr_safest_params)
236 io_wake_lines = fast_wake_lines = max_wake_lines;
237
238 /* According to Bspec lower limit should be set as 7 lines. */
239 crtc_state->alpm_state.io_wake_lines = max(io_wake_lines, 7);
240 crtc_state->alpm_state.fast_wake_lines = max(fast_wake_lines, 7);
241
242 return true;
243 }
244
intel_alpm_lobf_compute_config(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)245 void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
246 struct intel_crtc_state *crtc_state,
247 struct drm_connector_state *conn_state)
248 {
249 struct intel_display *display = to_intel_display(intel_dp);
250 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
251 int waketime_in_lines, first_sdp_position;
252 int context_latency, guardband;
253
254 if (intel_dp->alpm.lobf_disable_debug) {
255 drm_dbg_kms(display->drm, "LOBF is disabled by debug flag\n");
256 return;
257 }
258
259 if (intel_dp->alpm.sink_alpm_error)
260 return;
261
262 if (!intel_dp_is_edp(intel_dp))
263 return;
264
265 if (DISPLAY_VER(display) < 20)
266 return;
267
268 if (!intel_dp->as_sdp_supported)
269 return;
270
271 if (crtc_state->has_psr)
272 return;
273
274 if (crtc_state->vrr.vmin != crtc_state->vrr.vmax ||
275 crtc_state->vrr.vmin != crtc_state->vrr.flipline)
276 return;
277
278 if (!(intel_alpm_aux_wake_supported(intel_dp) ||
279 intel_alpm_aux_less_wake_supported(intel_dp)))
280 return;
281
282 if (!intel_alpm_compute_params(intel_dp, crtc_state))
283 return;
284
285 context_latency = adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
286 guardband = adjusted_mode->crtc_vtotal -
287 adjusted_mode->crtc_vdisplay - context_latency;
288 first_sdp_position = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
289 if (intel_alpm_aux_less_wake_supported(intel_dp))
290 waketime_in_lines = crtc_state->alpm_state.io_wake_lines;
291 else
292 waketime_in_lines = crtc_state->alpm_state.aux_less_wake_lines;
293
294 crtc_state->has_lobf = (context_latency + guardband) >
295 (first_sdp_position + waketime_in_lines);
296 }
297
lnl_alpm_configure(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)298 static void lnl_alpm_configure(struct intel_dp *intel_dp,
299 const struct intel_crtc_state *crtc_state)
300 {
301 struct intel_display *display = to_intel_display(intel_dp);
302 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
303 u32 alpm_ctl;
304
305 if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
306 !crtc_state->has_lobf))
307 return;
308
309 mutex_lock(&intel_dp->alpm.lock);
310 /*
311 * Panel Replay on eDP is always using ALPM aux less. I.e. no need to
312 * check panel support at this point.
313 */
314 if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
315 alpm_ctl = ALPM_CTL_ALPM_ENABLE |
316 ALPM_CTL_ALPM_AUX_LESS_ENABLE |
317 ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
318 ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
319
320 if (intel_dp->as_sdp_supported) {
321 u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
322
323 if (crtc_state->link_off_after_as_sdp_when_pr_active)
324 pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
325 if (crtc_state->disable_as_sdp_when_pr_active)
326 pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
327
328 intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
329 pr_alpm_ctl);
330 }
331
332 } else {
333 alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
334 ALPM_CTL_EXTENDED_FAST_WAKE_TIME(crtc_state->alpm_state.fast_wake_lines);
335 }
336
337 if (crtc_state->has_lobf) {
338 alpm_ctl |= ALPM_CTL_LOBF_ENABLE;
339 drm_dbg_kms(display->drm, "Link off between frames (LOBF) enabled\n");
340 }
341
342 alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state->alpm_state.check_entry_lines);
343
344 intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
345 mutex_unlock(&intel_dp->alpm.lock);
346 }
347
intel_alpm_configure(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)348 void intel_alpm_configure(struct intel_dp *intel_dp,
349 const struct intel_crtc_state *crtc_state)
350 {
351 lnl_alpm_configure(intel_dp, crtc_state);
352 intel_dp->alpm.transcoder = crtc_state->cpu_transcoder;
353 }
354
intel_alpm_port_configure(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)355 void intel_alpm_port_configure(struct intel_dp *intel_dp,
356 const struct intel_crtc_state *crtc_state)
357 {
358 struct intel_display *display = to_intel_display(intel_dp);
359 enum port port = dp_to_dig_port(intel_dp)->base.port;
360 u32 alpm_ctl_val = 0, lfps_ctl_val = 0;
361
362 if (DISPLAY_VER(display) < 20)
363 return;
364
365 if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
366 alpm_ctl_val = PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
367 PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
368 PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
369 PORT_ALPM_CTL_SILENCE_PERIOD(
370 crtc_state->alpm_state.silence_period_sym_clocks);
371 lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(LFPS_CYCLE_COUNT) |
372 PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
373 crtc_state->alpm_state.lfps_half_cycle_num_of_syms) |
374 PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
375 crtc_state->alpm_state.lfps_half_cycle_num_of_syms) |
376 PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
377 crtc_state->alpm_state.lfps_half_cycle_num_of_syms);
378 }
379
380 intel_de_write(display, PORT_ALPM_CTL(port), alpm_ctl_val);
381
382 intel_de_write(display, PORT_ALPM_LFPS_CTL(port), lfps_ctl_val);
383 }
384
intel_alpm_pre_plane_update(struct intel_atomic_state * state,struct intel_crtc * crtc)385 void intel_alpm_pre_plane_update(struct intel_atomic_state *state,
386 struct intel_crtc *crtc)
387 {
388 struct intel_display *display = to_intel_display(state);
389 const struct intel_crtc_state *crtc_state =
390 intel_atomic_get_new_crtc_state(state, crtc);
391 const struct intel_crtc_state *old_crtc_state =
392 intel_atomic_get_old_crtc_state(state, crtc);
393 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
394 struct intel_encoder *encoder;
395
396 if (DISPLAY_VER(display) < 20)
397 return;
398
399 if (crtc_state->has_lobf || crtc_state->has_lobf == old_crtc_state->has_lobf)
400 return;
401
402 for_each_intel_encoder_mask(display->drm, encoder,
403 crtc_state->uapi.encoder_mask) {
404 struct intel_dp *intel_dp;
405
406 if (!intel_encoder_is_dp(encoder))
407 continue;
408
409 intel_dp = enc_to_intel_dp(encoder);
410
411 if (!intel_dp_is_edp(intel_dp))
412 continue;
413
414 if (old_crtc_state->has_lobf) {
415 mutex_lock(&intel_dp->alpm.lock);
416 intel_de_write(display, ALPM_CTL(display, cpu_transcoder), 0);
417 drm_dbg_kms(display->drm, "Link off between frames (LOBF) disabled\n");
418 mutex_unlock(&intel_dp->alpm.lock);
419 }
420 }
421 }
422
intel_alpm_enable_sink(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)423 void intel_alpm_enable_sink(struct intel_dp *intel_dp,
424 const struct intel_crtc_state *crtc_state)
425 {
426 u8 val;
427
428 if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf)
429 return;
430
431 val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
432
433 if (crtc_state->has_panel_replay || (crtc_state->has_lobf &&
434 intel_alpm_aux_less_wake_supported(intel_dp)))
435 val |= DP_ALPM_MODE_AUX_LESS;
436
437 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val);
438 }
439
intel_alpm_post_plane_update(struct intel_atomic_state * state,struct intel_crtc * crtc)440 void intel_alpm_post_plane_update(struct intel_atomic_state *state,
441 struct intel_crtc *crtc)
442 {
443 struct intel_display *display = to_intel_display(state);
444 const struct intel_crtc_state *crtc_state =
445 intel_atomic_get_new_crtc_state(state, crtc);
446 const struct intel_crtc_state *old_crtc_state =
447 intel_atomic_get_old_crtc_state(state, crtc);
448 struct intel_encoder *encoder;
449
450 if (crtc_state->has_psr || !crtc_state->has_lobf ||
451 crtc_state->has_lobf == old_crtc_state->has_lobf)
452 return;
453
454 for_each_intel_encoder_mask(display->drm, encoder,
455 crtc_state->uapi.encoder_mask) {
456 struct intel_dp *intel_dp;
457
458 if (!intel_encoder_is_dp(encoder))
459 continue;
460
461 intel_dp = enc_to_intel_dp(encoder);
462
463 if (intel_dp_is_edp(intel_dp)) {
464 intel_alpm_enable_sink(intel_dp, crtc_state);
465 intel_alpm_configure(intel_dp, crtc_state);
466 }
467 }
468 }
469
i915_edp_lobf_info_show(struct seq_file * m,void * data)470 static int i915_edp_lobf_info_show(struct seq_file *m, void *data)
471 {
472 struct intel_connector *connector = m->private;
473 struct intel_display *display = to_intel_display(connector);
474 struct drm_crtc *crtc;
475 struct intel_crtc_state *crtc_state;
476 enum transcoder cpu_transcoder;
477 u32 alpm_ctl;
478 int ret;
479
480 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
481 if (ret)
482 return ret;
483
484 crtc = connector->base.state->crtc;
485 if (connector->base.status != connector_status_connected || !crtc) {
486 ret = -ENODEV;
487 goto out;
488 }
489
490 crtc_state = to_intel_crtc_state(crtc->state);
491 cpu_transcoder = crtc_state->cpu_transcoder;
492 alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder));
493 seq_printf(m, "LOBF status: %s\n", str_enabled_disabled(alpm_ctl & ALPM_CTL_LOBF_ENABLE));
494 seq_printf(m, "Aux-wake alpm status: %s\n",
495 str_enabled_disabled(!(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE)));
496 seq_printf(m, "Aux-less alpm status: %s\n",
497 str_enabled_disabled(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE));
498 out:
499 drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
500
501 return ret;
502 }
503
504 DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info);
505
506 static int
i915_edp_lobf_debug_get(void * data,u64 * val)507 i915_edp_lobf_debug_get(void *data, u64 *val)
508 {
509 struct intel_connector *connector = data;
510 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
511
512 *val = intel_dp->alpm.lobf_disable_debug;
513
514 return 0;
515 }
516
517 static int
i915_edp_lobf_debug_set(void * data,u64 val)518 i915_edp_lobf_debug_set(void *data, u64 val)
519 {
520 struct intel_connector *connector = data;
521 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
522
523 intel_dp->alpm.lobf_disable_debug = val;
524
525 return 0;
526 }
527
528 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_lobf_debug_fops,
529 i915_edp_lobf_debug_get, i915_edp_lobf_debug_set,
530 "%llu\n");
531
intel_alpm_lobf_debugfs_add(struct intel_connector * connector)532 void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
533 {
534 struct intel_display *display = to_intel_display(connector);
535 struct dentry *root = connector->base.debugfs_entry;
536
537 if (DISPLAY_VER(display) < 20 ||
538 connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
539 return;
540
541 debugfs_create_file("i915_edp_lobf_debug", 0644, root,
542 connector, &i915_edp_lobf_debug_fops);
543
544 debugfs_create_file("i915_edp_lobf_info", 0444, root,
545 connector, &i915_edp_lobf_info_fops);
546 }
547
intel_alpm_disable(struct intel_dp * intel_dp)548 void intel_alpm_disable(struct intel_dp *intel_dp)
549 {
550 struct intel_display *display = to_intel_display(intel_dp);
551 enum transcoder cpu_transcoder = intel_dp->alpm.transcoder;
552
553 if (DISPLAY_VER(display) < 20 || !intel_dp->alpm_dpcd)
554 return;
555
556 mutex_lock(&intel_dp->alpm.lock);
557
558 intel_de_rmw(display, ALPM_CTL(display, cpu_transcoder),
559 ALPM_CTL_ALPM_ENABLE | ALPM_CTL_LOBF_ENABLE, 0);
560
561 drm_dbg_kms(display->drm, "Disabling ALPM\n");
562 mutex_unlock(&intel_dp->alpm.lock);
563 }
564
intel_alpm_get_error(struct intel_dp * intel_dp)565 bool intel_alpm_get_error(struct intel_dp *intel_dp)
566 {
567 struct intel_display *display = to_intel_display(intel_dp);
568 struct drm_dp_aux *aux = &intel_dp->aux;
569 u8 val;
570 int r;
571
572 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
573 if (r != 1) {
574 drm_err(display->drm, "Error reading ALPM status\n");
575 return true;
576 }
577
578 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
579 drm_dbg_kms(display->drm, "ALPM lock timeout error\n");
580
581 /* Clearing error */
582 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);
583 return true;
584 }
585
586 return false;
587 }
588