xref: /linux/drivers/net/ethernet/wangxun/txgbe/txgbe_type.h (revision 1a9239bb4253f9076b5b4b2a1a4e8d7defd77a95)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3 
4 #ifndef _TXGBE_TYPE_H_
5 #define _TXGBE_TYPE_H_
6 
7 #include <linux/property.h>
8 #include <linux/irq.h>
9 
10 /* Device IDs */
11 #define TXGBE_DEV_ID_SP1000                     0x1001
12 #define TXGBE_DEV_ID_WX1820                     0x2001
13 #define TXGBE_DEV_ID_AML5010                    0x5010
14 #define TXGBE_DEV_ID_AML5110                    0x5110
15 #define TXGBE_DEV_ID_AML5025                    0x5025
16 #define TXGBE_DEV_ID_AML5125                    0x5125
17 #define TXGBE_DEV_ID_AML5040                    0x5040
18 #define TXGBE_DEV_ID_AML5140                    0x5140
19 
20 /* Subsystem IDs */
21 /* SFP */
22 #define TXGBE_ID_SP1000_SFP                     0x0000
23 #define TXGBE_ID_WX1820_SFP                     0x2000
24 #define TXGBE_ID_SFP                            0x00
25 
26 /* copper */
27 #define TXGBE_ID_SP1000_XAUI                    0x1010
28 #define TXGBE_ID_WX1820_XAUI                    0x2010
29 #define TXGBE_ID_XAUI                           0x10
30 #define TXGBE_ID_SP1000_SGMII                   0x1020
31 #define TXGBE_ID_WX1820_SGMII                   0x2020
32 #define TXGBE_ID_SGMII                          0x20
33 /* backplane */
34 #define TXGBE_ID_SP1000_KR_KX_KX4               0x1030
35 #define TXGBE_ID_WX1820_KR_KX_KX4               0x2030
36 #define TXGBE_ID_KR_KX_KX4                      0x30
37 /* MAC Interface */
38 #define TXGBE_ID_SP1000_MAC_XAUI                0x1040
39 #define TXGBE_ID_WX1820_MAC_XAUI                0x2040
40 #define TXGBE_ID_MAC_XAUI                       0x40
41 #define TXGBE_ID_SP1000_MAC_SGMII               0x1060
42 #define TXGBE_ID_WX1820_MAC_SGMII               0x2060
43 #define TXGBE_ID_MAC_SGMII                      0x60
44 
45 /* Combined interface*/
46 #define TXGBE_ID_SFI_XAUI			0x50
47 
48 /* Revision ID */
49 #define TXGBE_SP_MPW  1
50 
51 /**************** SP Registers ****************************/
52 /* chip control Registers */
53 #define TXGBE_MIS_PRB_CTL                       0x10010
54 #define TXGBE_MIS_PRB_CTL_LAN_UP(_i)            BIT(1 - (_i))
55 /* FMGR Registers */
56 #define TXGBE_SPI_ILDR_STATUS                   0x10120
57 #define TXGBE_SPI_ILDR_STATUS_PERST             BIT(0) /* PCIE_PERST is done */
58 #define TXGBE_SPI_ILDR_STATUS_PWRRST            BIT(1) /* Power on reset is done */
59 #define TXGBE_SPI_ILDR_STATUS_LAN_SW_RST(_i)    BIT((_i) + 9) /* lan soft reset done */
60 
61 /* Sensors for PVT(Process Voltage Temperature) */
62 #define TXGBE_TS_CTL                            0x10300
63 #define TXGBE_TS_CTL_EVAL_MD                    BIT(31)
64 
65 /* GPIO register bit */
66 #define TXGBE_GPIOBIT_0                         BIT(0) /* I:tx fault */
67 #define TXGBE_GPIOBIT_1                         BIT(1) /* O:tx disabled */
68 #define TXGBE_GPIOBIT_2                         BIT(2) /* I:sfp module absent */
69 #define TXGBE_GPIOBIT_3                         BIT(3) /* I:rx signal lost */
70 #define TXGBE_GPIOBIT_4                         BIT(4) /* O:rate select, 1G(0) 10G(1) */
71 #define TXGBE_GPIOBIT_5                         BIT(5) /* O:rate select, 1G(0) 10G(1) */
72 
73 /* Extended Interrupt Enable Set */
74 #define TXGBE_PX_MISC_ETH_LKDN                  BIT(8)
75 #define TXGBE_PX_MISC_DEV_RST                   BIT(10)
76 #define TXGBE_PX_MISC_ETH_EVENT                 BIT(17)
77 #define TXGBE_PX_MISC_ETH_LK                    BIT(18)
78 #define TXGBE_PX_MISC_ETH_AN                    BIT(19)
79 #define TXGBE_PX_MISC_INT_ERR                   BIT(20)
80 #define TXGBE_PX_MISC_GPIO                      BIT(26)
81 #define TXGBE_PX_MISC_IEN_MASK                            \
82 	(TXGBE_PX_MISC_ETH_LKDN | TXGBE_PX_MISC_DEV_RST | \
83 	 TXGBE_PX_MISC_ETH_EVENT | TXGBE_PX_MISC_ETH_LK | \
84 	 TXGBE_PX_MISC_ETH_AN | TXGBE_PX_MISC_INT_ERR)
85 
86 /* Port cfg registers */
87 #define TXGBE_CFG_PORT_ST                       0x14404
88 #define TXGBE_CFG_PORT_ST_LINK_UP               BIT(0)
89 
90 /* I2C registers */
91 #define TXGBE_I2C_BASE                          0x14900
92 
93 /************************************** ETH PHY ******************************/
94 #define TXGBE_XPCS_IDA_ADDR                     0x13000
95 #define TXGBE_XPCS_IDA_DATA                     0x13004
96 
97 /********************************* Flow Director *****************************/
98 #define TXGBE_RDB_FDIR_DROP_QUEUE               127
99 #define TXGBE_RDB_FDIR_CTL                      0x19500
100 #define TXGBE_RDB_FDIR_CTL_INIT_DONE            BIT(3)
101 #define TXGBE_RDB_FDIR_CTL_PERFECT_MATCH        BIT(4)
102 #define TXGBE_RDB_FDIR_CTL_DROP_Q(v)            FIELD_PREP(GENMASK(14, 8), v)
103 #define TXGBE_RDB_FDIR_CTL_HASH_BITS(v)         FIELD_PREP(GENMASK(23, 20), v)
104 #define TXGBE_RDB_FDIR_CTL_MAX_LENGTH(v)        FIELD_PREP(GENMASK(27, 24), v)
105 #define TXGBE_RDB_FDIR_CTL_FULL_THRESH(v)       FIELD_PREP(GENMASK(31, 28), v)
106 #define TXGBE_RDB_FDIR_IP6(_i)                  (0x1950C + ((_i) * 4)) /* 0-2 */
107 #define TXGBE_RDB_FDIR_SA                       0x19518
108 #define TXGBE_RDB_FDIR_DA                       0x1951C
109 #define TXGBE_RDB_FDIR_PORT                     0x19520
110 #define TXGBE_RDB_FDIR_PORT_DESTINATION_SHIFT   16
111 #define TXGBE_RDB_FDIR_FLEX                     0x19524
112 #define TXGBE_RDB_FDIR_FLEX_FLEX_SHIFT          16
113 #define TXGBE_RDB_FDIR_HASH                     0x19528
114 #define TXGBE_RDB_FDIR_HASH_SIG_SW_INDEX(v)     FIELD_PREP(GENMASK(31, 16), v)
115 #define TXGBE_RDB_FDIR_HASH_BUCKET_VALID        BIT(15)
116 #define TXGBE_RDB_FDIR_CMD                      0x1952C
117 #define TXGBE_RDB_FDIR_CMD_CMD_MASK             GENMASK(1, 0)
118 #define TXGBE_RDB_FDIR_CMD_CMD(v)               FIELD_PREP(GENMASK(1, 0), v)
119 #define TXGBE_RDB_FDIR_CMD_CMD_ADD_FLOW         TXGBE_RDB_FDIR_CMD_CMD(1)
120 #define TXGBE_RDB_FDIR_CMD_CMD_REMOVE_FLOW      TXGBE_RDB_FDIR_CMD_CMD(2)
121 #define TXGBE_RDB_FDIR_CMD_CMD_QUERY_REM_FILT   TXGBE_RDB_FDIR_CMD_CMD(3)
122 #define TXGBE_RDB_FDIR_CMD_FILTER_VALID         BIT(2)
123 #define TXGBE_RDB_FDIR_CMD_FILTER_UPDATE        BIT(3)
124 #define TXGBE_RDB_FDIR_CMD_FLOW_TYPE(v)         FIELD_PREP(GENMASK(6, 5), v)
125 #define TXGBE_RDB_FDIR_CMD_DROP                 BIT(9)
126 #define TXGBE_RDB_FDIR_CMD_LAST                 BIT(11)
127 #define TXGBE_RDB_FDIR_CMD_QUEUE_EN             BIT(15)
128 #define TXGBE_RDB_FDIR_CMD_RX_QUEUE(v)          FIELD_PREP(GENMASK(22, 16), v)
129 #define TXGBE_RDB_FDIR_CMD_VT_POOL(v)           FIELD_PREP(GENMASK(29, 24), v)
130 #define TXGBE_RDB_FDIR_DA4_MSK                  0x1953C
131 #define TXGBE_RDB_FDIR_SA4_MSK                  0x19540
132 #define TXGBE_RDB_FDIR_TCP_MSK                  0x19544
133 #define TXGBE_RDB_FDIR_UDP_MSK                  0x19548
134 #define TXGBE_RDB_FDIR_SCTP_MSK                 0x19560
135 #define TXGBE_RDB_FDIR_HKEY                     0x19568
136 #define TXGBE_RDB_FDIR_SKEY                     0x1956C
137 #define TXGBE_RDB_FDIR_OTHER_MSK                0x19570
138 #define TXGBE_RDB_FDIR_OTHER_MSK_POOL           BIT(2)
139 #define TXGBE_RDB_FDIR_OTHER_MSK_L4P            BIT(3)
140 #define TXGBE_RDB_FDIR_FLEX_CFG(_i)             (0x19580 + ((_i) * 4))
141 #define TXGBE_RDB_FDIR_FLEX_CFG_FIELD0          GENMASK(7, 0)
142 #define TXGBE_RDB_FDIR_FLEX_CFG_BASE_MAC        FIELD_PREP(GENMASK(1, 0), 0)
143 #define TXGBE_RDB_FDIR_FLEX_CFG_MSK             BIT(2)
144 #define TXGBE_RDB_FDIR_FLEX_CFG_OFST(v)         FIELD_PREP(GENMASK(7, 3), v)
145 
146 /*************************** Amber Lite Registers ****************************/
147 #define TXGBE_PX_PF_BME                         0x4B8
148 #define TXGBE_AML_MAC_TX_CFG                    0x11000
149 #define TXGBE_AML_MAC_TX_CFG_SPEED_MASK         GENMASK(30, 27)
150 #define TXGBE_AML_MAC_TX_CFG_SPEED_25G          BIT(28)
151 #define TXGBE_RDM_RSC_CTL                       0x1200C
152 #define TXGBE_RDM_RSC_CTL_FREE_CTL              BIT(7)
153 
154 /* Checksum and EEPROM pointers */
155 #define TXGBE_EEPROM_LAST_WORD                  0x800
156 #define TXGBE_EEPROM_CHECKSUM                   0x2F
157 #define TXGBE_EEPROM_SUM                        0xBABA
158 #define TXGBE_EEPROM_VERSION_L                  0x1D
159 #define TXGBE_EEPROM_VERSION_H                  0x1E
160 #define TXGBE_ISCSI_BOOT_CONFIG                 0x07
161 
162 #define TXGBE_MAX_MSIX_VECTORS          64
163 #define TXGBE_MAX_FDIR_INDICES          63
164 #define TXGBE_MAX_RSS_INDICES           63
165 
166 #define TXGBE_MAX_RX_QUEUES   (TXGBE_MAX_FDIR_INDICES + 1)
167 #define TXGBE_MAX_TX_QUEUES   (TXGBE_MAX_FDIR_INDICES + 1)
168 
169 #define TXGBE_SP_MAX_TX_QUEUES  128
170 #define TXGBE_SP_MAX_RX_QUEUES  128
171 #define TXGBE_SP_RAR_ENTRIES    128
172 #define TXGBE_SP_MC_TBL_SIZE    128
173 #define TXGBE_SP_VFT_TBL_SIZE   128
174 #define TXGBE_SP_RX_PB_SIZE     512
175 #define TXGBE_SP_TDB_PB_SZ      (160 * 1024) /* 160KB Packet Buffer */
176 
177 #define TXGBE_DEFAULT_ATR_SAMPLE_RATE           20
178 
179 /* Software ATR hash keys */
180 #define TXGBE_ATR_BUCKET_HASH_KEY               0x3DAD14E2
181 #define TXGBE_ATR_SIGNATURE_HASH_KEY            0x174D3614
182 
183 /* Software ATR input stream values and masks */
184 #define TXGBE_ATR_HASH_MASK                     0x7fff
185 #define TXGBE_ATR_L4TYPE_MASK                   0x3
186 #define TXGBE_ATR_L4TYPE_UDP                    0x1
187 #define TXGBE_ATR_L4TYPE_TCP                    0x2
188 #define TXGBE_ATR_L4TYPE_SCTP                   0x3
189 #define TXGBE_ATR_L4TYPE_IPV6_MASK              0x4
190 #define TXGBE_ATR_L4TYPE_TUNNEL_MASK            0x10
191 
192 enum txgbe_atr_flow_type {
193 	TXGBE_ATR_FLOW_TYPE_IPV4                = 0x0,
194 	TXGBE_ATR_FLOW_TYPE_UDPV4               = 0x1,
195 	TXGBE_ATR_FLOW_TYPE_TCPV4               = 0x2,
196 	TXGBE_ATR_FLOW_TYPE_SCTPV4              = 0x3,
197 	TXGBE_ATR_FLOW_TYPE_IPV6                = 0x4,
198 	TXGBE_ATR_FLOW_TYPE_UDPV6               = 0x5,
199 	TXGBE_ATR_FLOW_TYPE_TCPV6               = 0x6,
200 	TXGBE_ATR_FLOW_TYPE_SCTPV6              = 0x7,
201 	TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4       = 0x10,
202 	TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4      = 0x11,
203 	TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4      = 0x12,
204 	TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4     = 0x13,
205 	TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6       = 0x14,
206 	TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6      = 0x15,
207 	TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6      = 0x16,
208 	TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6     = 0x17,
209 };
210 
211 /* Flow Director ATR input struct. */
212 union txgbe_atr_input {
213 	/* Byte layout in order, all values with MSB first:
214 	 *
215 	 * vm_pool    - 1 byte
216 	 * flow_type  - 1 byte
217 	 * vlan_id    - 2 bytes
218 	 * dst_ip     - 16 bytes
219 	 * src_ip     - 16 bytes
220 	 * src_port   - 2 bytes
221 	 * dst_port   - 2 bytes
222 	 * flex_bytes - 2 bytes
223 	 * bkt_hash   - 2 bytes
224 	 */
225 	struct {
226 		u8 vm_pool;
227 		u8 flow_type;
228 		__be16 vlan_id;
229 		__be32 dst_ip[4];
230 		__be32 src_ip[4];
231 		__be16 src_port;
232 		__be16 dst_port;
233 		__be16 flex_bytes;
234 		__be16 bkt_hash;
235 	} formatted;
236 	__be32 dword_stream[11];
237 };
238 
239 /* Flow Director compressed ATR hash input struct */
240 union txgbe_atr_hash_dword {
241 	struct {
242 		u8 vm_pool;
243 		u8 flow_type;
244 		__be16 vlan_id;
245 	} formatted;
246 	__be32 ip;
247 	struct {
248 		__be16 src;
249 		__be16 dst;
250 	} port;
251 	__be16 flex_bytes;
252 	__be32 dword;
253 };
254 
255 enum txgbe_fdir_pballoc_type {
256 	TXGBE_FDIR_PBALLOC_NONE = 0,
257 	TXGBE_FDIR_PBALLOC_64K  = 1,
258 	TXGBE_FDIR_PBALLOC_128K = 2,
259 	TXGBE_FDIR_PBALLOC_256K = 3,
260 };
261 
262 struct txgbe_fdir_filter {
263 	struct hlist_node fdir_node;
264 	union txgbe_atr_input filter;
265 	u16 sw_idx;
266 	u16 action;
267 };
268 
269 /* TX/RX descriptor defines */
270 #define TXGBE_DEFAULT_TXD               512
271 #define TXGBE_DEFAULT_TX_WORK           256
272 
273 #if (PAGE_SIZE < 8192)
274 #define TXGBE_DEFAULT_RXD               512
275 #define TXGBE_DEFAULT_RX_WORK           256
276 #else
277 #define TXGBE_DEFAULT_RXD               256
278 #define TXGBE_DEFAULT_RX_WORK           128
279 #endif
280 
281 #define TXGBE_INTR_MISC       BIT(0)
282 #define TXGBE_INTR_QALL(A)    GENMASK((A)->num_q_vectors, 1)
283 
284 #define TXGBE_MAX_EITR        GENMASK(11, 3)
285 
286 extern char txgbe_driver_name[];
287 
288 void txgbe_down(struct wx *wx);
289 void txgbe_up(struct wx *wx);
290 int txgbe_setup_tc(struct net_device *dev, u8 tc);
291 void txgbe_do_reset(struct net_device *netdev);
292 
293 #define NODE_PROP(_NAME, _PROP)			\
294 	(const struct software_node) {		\
295 		.name = _NAME,			\
296 		.properties = _PROP,		\
297 	}
298 
299 enum txgbe_swnodes {
300 	SWNODE_GPIO = 0,
301 	SWNODE_I2C,
302 	SWNODE_SFP,
303 	SWNODE_PHYLINK,
304 	SWNODE_MAX
305 };
306 
307 struct txgbe_nodes {
308 	char gpio_name[32];
309 	char i2c_name[32];
310 	char sfp_name[32];
311 	char phylink_name[32];
312 	struct property_entry gpio_props[1];
313 	struct property_entry i2c_props[3];
314 	struct property_entry sfp_props[8];
315 	struct property_entry phylink_props[2];
316 	struct software_node_ref_args i2c_ref[1];
317 	struct software_node_ref_args gpio0_ref[1];
318 	struct software_node_ref_args gpio1_ref[1];
319 	struct software_node_ref_args gpio2_ref[1];
320 	struct software_node_ref_args gpio3_ref[1];
321 	struct software_node_ref_args gpio4_ref[1];
322 	struct software_node_ref_args gpio5_ref[1];
323 	struct software_node_ref_args sfp_ref[1];
324 	struct software_node swnodes[SWNODE_MAX];
325 	const struct software_node *group[SWNODE_MAX + 1];
326 };
327 
328 enum txgbe_misc_irqs {
329 	TXGBE_IRQ_LINK = 0,
330 	TXGBE_IRQ_MAX
331 };
332 
333 struct txgbe_irq {
334 	struct irq_chip chip;
335 	struct irq_domain *domain;
336 	int nirqs;
337 	int irq;
338 };
339 
340 struct txgbe {
341 	struct wx *wx;
342 	struct txgbe_nodes nodes;
343 	struct txgbe_irq misc;
344 	struct phylink_pcs *pcs;
345 	struct platform_device *sfp_dev;
346 	struct platform_device *i2c_dev;
347 	struct clk_lookup *clock;
348 	struct clk *clk;
349 	struct gpio_chip *gpio;
350 	unsigned int link_irq;
351 
352 	/* flow director */
353 	struct hlist_head fdir_filter_list;
354 	union txgbe_atr_input fdir_mask;
355 	int fdir_filter_count;
356 	spinlock_t fdir_perfect_lock; /* spinlock for FDIR */
357 };
358 
359 #endif /* _TXGBE_TYPE_H_ */
360