1 // SPDX-License-Identifier: GPL-2.0
2
3 #include <errno.h>
4 #include <string.h>
5 #include <regex.h>
6 #include <linux/zalloc.h>
7
8 #include "../debug.h"
9 #include "../event.h"
10 #include "../header.h"
11 #include "../perf_regs.h"
12 #include "../../perf-sys.h"
13 #include "../../arch/powerpc/util/utils_header.h"
14 #include "../../arch/powerpc/include/perf_regs.h"
15
16 #include <linux/kernel.h>
17
18 #define PVR_POWER9 0x004E
19 #define PVR_POWER10 0x0080
20 #define PVR_POWER11 0x0082
21
22 /* REG or %rREG */
23 #define SDT_OP_REGEX1 "^(%r)?([1-2]?[0-9]|3[0-1])$"
24
25 /* -NUM(REG) or NUM(REG) or -NUM(%rREG) or NUM(%rREG) */
26 #define SDT_OP_REGEX2 "^(\\-)?([0-9]+)\\((%r)?([1-2]?[0-9]|3[0-1])\\)$"
27
28 static regex_t sdt_op_regex1, sdt_op_regex2;
29
sdt_init_op_regex(void)30 static int sdt_init_op_regex(void)
31 {
32 static int initialized;
33 int ret = 0;
34
35 if (initialized)
36 return 0;
37
38 ret = regcomp(&sdt_op_regex1, SDT_OP_REGEX1, REG_EXTENDED);
39 if (ret)
40 goto error;
41
42 ret = regcomp(&sdt_op_regex2, SDT_OP_REGEX2, REG_EXTENDED);
43 if (ret)
44 goto free_regex1;
45
46 initialized = 1;
47 return 0;
48
49 free_regex1:
50 regfree(&sdt_op_regex1);
51 error:
52 pr_debug4("Regex compilation error.\n");
53 return ret;
54 }
55
56 /*
57 * Parse OP and convert it into uprobe format, which is, +/-NUM(%gprREG).
58 * Possible variants of OP are:
59 * Format Example
60 * -------------------------
61 * NUM(REG) 48(18)
62 * -NUM(REG) -48(18)
63 * NUM(%rREG) 48(%r18)
64 * -NUM(%rREG) -48(%r18)
65 * REG 18
66 * %rREG %r18
67 * iNUM i0
68 * i-NUM i-1
69 *
70 * SDT marker arguments on Powerpc uses %rREG form with -mregnames flag
71 * and REG form with -mno-regnames. Here REG is general purpose register,
72 * which is in 0 to 31 range.
73 */
__perf_sdt_arg_parse_op_powerpc(char * old_op,char ** new_op)74 int __perf_sdt_arg_parse_op_powerpc(char *old_op, char **new_op)
75 {
76 int ret, new_len;
77 regmatch_t rm[5];
78 char prefix;
79
80 /* Constant argument. Uprobe does not support it */
81 if (old_op[0] == 'i') {
82 pr_debug4("Skipping unsupported SDT argument: %s\n", old_op);
83 return SDT_ARG_SKIP;
84 }
85
86 ret = sdt_init_op_regex();
87 if (ret < 0)
88 return ret;
89
90 if (!regexec(&sdt_op_regex1, old_op, 3, rm, 0)) {
91 /* REG or %rREG --> %gprREG */
92
93 new_len = 5; /* % g p r NULL */
94 new_len += (int)(rm[2].rm_eo - rm[2].rm_so);
95
96 *new_op = zalloc(new_len);
97 if (!*new_op)
98 return -ENOMEM;
99
100 scnprintf(*new_op, new_len, "%%gpr%.*s",
101 (int)(rm[2].rm_eo - rm[2].rm_so), old_op + rm[2].rm_so);
102 } else if (!regexec(&sdt_op_regex2, old_op, 5, rm, 0)) {
103 /*
104 * -NUM(REG) or NUM(REG) or -NUM(%rREG) or NUM(%rREG) -->
105 * +/-NUM(%gprREG)
106 */
107 prefix = (rm[1].rm_so == -1) ? '+' : '-';
108
109 new_len = 8; /* +/- ( % g p r ) NULL */
110 new_len += (int)(rm[2].rm_eo - rm[2].rm_so);
111 new_len += (int)(rm[4].rm_eo - rm[4].rm_so);
112
113 *new_op = zalloc(new_len);
114 if (!*new_op)
115 return -ENOMEM;
116
117 scnprintf(*new_op, new_len, "%c%.*s(%%gpr%.*s)", prefix,
118 (int)(rm[2].rm_eo - rm[2].rm_so), old_op + rm[2].rm_so,
119 (int)(rm[4].rm_eo - rm[4].rm_so), old_op + rm[4].rm_so);
120 } else {
121 pr_debug4("Skipping unsupported SDT argument: %s\n", old_op);
122 return SDT_ARG_SKIP;
123 }
124
125 return SDT_ARG_VALID;
126 }
127
128 /*
129 * mfspr is a POWERPC specific instruction, ensure it's only
130 * built and called on POWERPC by guarding with __powerpc64__
131 * or __powerpc__.
132 */
133 #if defined(__powerpc64__) && defined(__powerpc__)
__perf_reg_mask_powerpc(bool intr)134 uint64_t __perf_reg_mask_powerpc(bool intr)
135 {
136 struct perf_event_attr attr = {
137 .type = PERF_TYPE_HARDWARE,
138 .config = PERF_COUNT_HW_CPU_CYCLES,
139 .sample_type = PERF_SAMPLE_REGS_INTR,
140 .precise_ip = 1,
141 .disabled = 1,
142 .exclude_kernel = 1,
143 };
144 int fd;
145 u32 version;
146 u64 extended_mask = 0, mask = PERF_REGS_MASK;
147
148 if (!intr)
149 return PERF_REGS_MASK;
150
151 /*
152 * Get the PVR value to set the extended
153 * mask specific to platform.
154 */
155 version = (((mfspr(SPRN_PVR)) >> 16) & 0xFFFF);
156 if (version == PVR_POWER9)
157 extended_mask = PERF_REG_PMU_MASK_300;
158 else if ((version == PVR_POWER10) || (version == PVR_POWER11))
159 extended_mask = PERF_REG_PMU_MASK_31;
160 else
161 return mask;
162
163 attr.sample_regs_intr = extended_mask;
164 attr.sample_period = 1;
165 event_attr_init(&attr);
166
167 /*
168 * Check if the pmu supports perf extended regs, before
169 * returning the register mask to sample. Open the event
170 * on the perf process to check this.
171 */
172 fd = sys_perf_event_open(&attr, /*pid=*/0, /*cpu=*/-1,
173 /*group_fd=*/-1, /*flags=*/0);
174 if (fd != -1) {
175 close(fd);
176 mask |= extended_mask;
177 }
178 return mask;
179 }
180 #else
__perf_reg_mask_powerpc(bool intr __maybe_unused)181 uint64_t __perf_reg_mask_powerpc(bool intr __maybe_unused)
182 {
183 return PERF_REGS_MASK;
184 }
185 #endif
186
__perf_reg_name_powerpc(int id)187 const char *__perf_reg_name_powerpc(int id)
188 {
189 switch (id) {
190 case PERF_REG_POWERPC_R0:
191 return "r0";
192 case PERF_REG_POWERPC_R1:
193 return "r1";
194 case PERF_REG_POWERPC_R2:
195 return "r2";
196 case PERF_REG_POWERPC_R3:
197 return "r3";
198 case PERF_REG_POWERPC_R4:
199 return "r4";
200 case PERF_REG_POWERPC_R5:
201 return "r5";
202 case PERF_REG_POWERPC_R6:
203 return "r6";
204 case PERF_REG_POWERPC_R7:
205 return "r7";
206 case PERF_REG_POWERPC_R8:
207 return "r8";
208 case PERF_REG_POWERPC_R9:
209 return "r9";
210 case PERF_REG_POWERPC_R10:
211 return "r10";
212 case PERF_REG_POWERPC_R11:
213 return "r11";
214 case PERF_REG_POWERPC_R12:
215 return "r12";
216 case PERF_REG_POWERPC_R13:
217 return "r13";
218 case PERF_REG_POWERPC_R14:
219 return "r14";
220 case PERF_REG_POWERPC_R15:
221 return "r15";
222 case PERF_REG_POWERPC_R16:
223 return "r16";
224 case PERF_REG_POWERPC_R17:
225 return "r17";
226 case PERF_REG_POWERPC_R18:
227 return "r18";
228 case PERF_REG_POWERPC_R19:
229 return "r19";
230 case PERF_REG_POWERPC_R20:
231 return "r20";
232 case PERF_REG_POWERPC_R21:
233 return "r21";
234 case PERF_REG_POWERPC_R22:
235 return "r22";
236 case PERF_REG_POWERPC_R23:
237 return "r23";
238 case PERF_REG_POWERPC_R24:
239 return "r24";
240 case PERF_REG_POWERPC_R25:
241 return "r25";
242 case PERF_REG_POWERPC_R26:
243 return "r26";
244 case PERF_REG_POWERPC_R27:
245 return "r27";
246 case PERF_REG_POWERPC_R28:
247 return "r28";
248 case PERF_REG_POWERPC_R29:
249 return "r29";
250 case PERF_REG_POWERPC_R30:
251 return "r30";
252 case PERF_REG_POWERPC_R31:
253 return "r31";
254 case PERF_REG_POWERPC_NIP:
255 return "nip";
256 case PERF_REG_POWERPC_MSR:
257 return "msr";
258 case PERF_REG_POWERPC_ORIG_R3:
259 return "orig_r3";
260 case PERF_REG_POWERPC_CTR:
261 return "ctr";
262 case PERF_REG_POWERPC_LINK:
263 return "link";
264 case PERF_REG_POWERPC_XER:
265 return "xer";
266 case PERF_REG_POWERPC_CCR:
267 return "ccr";
268 case PERF_REG_POWERPC_SOFTE:
269 return "softe";
270 case PERF_REG_POWERPC_TRAP:
271 return "trap";
272 case PERF_REG_POWERPC_DAR:
273 return "dar";
274 case PERF_REG_POWERPC_DSISR:
275 return "dsisr";
276 case PERF_REG_POWERPC_SIER:
277 return "sier";
278 case PERF_REG_POWERPC_MMCRA:
279 return "mmcra";
280 case PERF_REG_POWERPC_MMCR0:
281 return "mmcr0";
282 case PERF_REG_POWERPC_MMCR1:
283 return "mmcr1";
284 case PERF_REG_POWERPC_MMCR2:
285 return "mmcr2";
286 case PERF_REG_POWERPC_MMCR3:
287 return "mmcr3";
288 case PERF_REG_POWERPC_SIER2:
289 return "sier2";
290 case PERF_REG_POWERPC_SIER3:
291 return "sier3";
292 case PERF_REG_POWERPC_PMC1:
293 return "pmc1";
294 case PERF_REG_POWERPC_PMC2:
295 return "pmc2";
296 case PERF_REG_POWERPC_PMC3:
297 return "pmc3";
298 case PERF_REG_POWERPC_PMC4:
299 return "pmc4";
300 case PERF_REG_POWERPC_PMC5:
301 return "pmc5";
302 case PERF_REG_POWERPC_PMC6:
303 return "pmc6";
304 case PERF_REG_POWERPC_SDAR:
305 return "sdar";
306 case PERF_REG_POWERPC_SIAR:
307 return "siar";
308 default:
309 break;
310 }
311 return NULL;
312 }
313
__perf_reg_ip_powerpc(void)314 uint64_t __perf_reg_ip_powerpc(void)
315 {
316 return PERF_REG_POWERPC_NIP;
317 }
318
__perf_reg_sp_powerpc(void)319 uint64_t __perf_reg_sp_powerpc(void)
320 {
321 return PERF_REG_POWERPC_R1;
322 }
323