1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/device.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/interrupt.h> 9 #include <linux/string.h> 10 #include <crypto/internal/hash.h> 11 12 #include "common.h" 13 #include "core.h" 14 #include "sha.h" 15 16 struct qce_sha_saved_state { 17 u8 pending_buf[QCE_SHA_MAX_BLOCKSIZE]; 18 u8 partial_digest[QCE_SHA_MAX_DIGESTSIZE]; 19 __be32 byte_count[2]; 20 unsigned int pending_buflen; 21 unsigned int flags; 22 u64 count; 23 bool first_blk; 24 }; 25 26 static LIST_HEAD(ahash_algs); 27 28 static const u32 std_iv_sha1[SHA256_DIGEST_SIZE / sizeof(u32)] = { 29 SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4, 0, 0, 0 30 }; 31 32 static const u32 std_iv_sha256[SHA256_DIGEST_SIZE / sizeof(u32)] = { 33 SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3, 34 SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7 35 }; 36 37 static void qce_ahash_done(void *data) 38 { 39 struct crypto_async_request *async_req = data; 40 struct ahash_request *req = ahash_request_cast(async_req); 41 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); 42 struct qce_sha_reqctx *rctx = ahash_request_ctx_dma(req); 43 struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm); 44 struct qce_device *qce = tmpl->qce; 45 struct qce_result_dump *result = qce->dma.result_buf; 46 unsigned int digestsize = crypto_ahash_digestsize(ahash); 47 int error; 48 u32 status; 49 50 error = qce_dma_terminate_all(&qce->dma); 51 if (error) 52 dev_dbg(qce->dev, "ahash dma termination error (%d)\n", error); 53 54 dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE); 55 dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE); 56 57 memcpy(rctx->digest, result->auth_iv, digestsize); 58 if (req->result && rctx->last_blk) 59 memcpy(req->result, result->auth_iv, digestsize); 60 61 rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]); 62 rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]); 63 64 error = qce_check_status(qce, &status); 65 if (error < 0) 66 dev_dbg(qce->dev, "ahash operation error (%x)\n", status); 67 68 req->src = rctx->src_orig; 69 req->nbytes = rctx->nbytes_orig; 70 rctx->last_blk = false; 71 rctx->first_blk = false; 72 73 qce->async_req_done(tmpl->qce, error); 74 } 75 76 static int qce_ahash_async_req_handle(struct crypto_async_request *async_req) 77 { 78 struct ahash_request *req = ahash_request_cast(async_req); 79 struct qce_sha_reqctx *rctx = ahash_request_ctx_dma(req); 80 struct qce_sha_ctx *ctx = crypto_tfm_ctx(async_req->tfm); 81 struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm); 82 struct qce_device *qce = tmpl->qce; 83 unsigned long flags = rctx->flags; 84 int ret; 85 86 if (IS_SHA_HMAC(flags)) { 87 rctx->authkey = ctx->authkey; 88 rctx->authklen = QCE_SHA_HMAC_KEY_SIZE; 89 } else if (IS_CMAC(flags)) { 90 rctx->authkey = ctx->authkey; 91 rctx->authklen = AES_KEYSIZE_128; 92 } 93 94 rctx->src_nents = sg_nents_for_len(req->src, req->nbytes); 95 if (rctx->src_nents < 0) { 96 dev_err(qce->dev, "Invalid numbers of src SG.\n"); 97 return rctx->src_nents; 98 } 99 100 ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE); 101 if (!ret) 102 return -EIO; 103 104 sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ); 105 106 ret = dma_map_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE); 107 if (!ret) { 108 ret = -EIO; 109 goto error_unmap_src; 110 } 111 112 ret = qce_dma_prep_sgs(&qce->dma, req->src, rctx->src_nents, 113 &rctx->result_sg, 1, qce_ahash_done, async_req); 114 if (ret) 115 goto error_unmap_dst; 116 117 qce_dma_issue_pending(&qce->dma); 118 119 ret = qce_start(async_req, tmpl->crypto_alg_type); 120 if (ret) 121 goto error_terminate; 122 123 return 0; 124 125 error_terminate: 126 qce_dma_terminate_all(&qce->dma); 127 error_unmap_dst: 128 dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE); 129 error_unmap_src: 130 dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE); 131 return ret; 132 } 133 134 static int qce_ahash_init(struct ahash_request *req) 135 { 136 struct qce_sha_reqctx *rctx = ahash_request_ctx_dma(req); 137 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); 138 const u32 *std_iv = tmpl->std_iv; 139 140 memset(rctx, 0, sizeof(*rctx)); 141 rctx->first_blk = true; 142 rctx->last_blk = false; 143 rctx->flags = tmpl->alg_flags; 144 memcpy(rctx->digest, std_iv, sizeof(rctx->digest)); 145 146 return 0; 147 } 148 149 static int qce_ahash_export(struct ahash_request *req, void *out) 150 { 151 struct qce_sha_reqctx *rctx = ahash_request_ctx_dma(req); 152 struct qce_sha_saved_state *export_state = out; 153 154 memcpy(export_state->pending_buf, rctx->buf, rctx->buflen); 155 memcpy(export_state->partial_digest, rctx->digest, sizeof(rctx->digest)); 156 export_state->byte_count[0] = rctx->byte_count[0]; 157 export_state->byte_count[1] = rctx->byte_count[1]; 158 export_state->pending_buflen = rctx->buflen; 159 export_state->count = rctx->count; 160 export_state->first_blk = rctx->first_blk; 161 export_state->flags = rctx->flags; 162 163 return 0; 164 } 165 166 static int qce_ahash_import(struct ahash_request *req, const void *in) 167 { 168 struct qce_sha_reqctx *rctx = ahash_request_ctx_dma(req); 169 const struct qce_sha_saved_state *import_state = in; 170 171 memset(rctx, 0, sizeof(*rctx)); 172 rctx->count = import_state->count; 173 rctx->buflen = import_state->pending_buflen; 174 rctx->first_blk = import_state->first_blk; 175 rctx->flags = import_state->flags; 176 rctx->byte_count[0] = import_state->byte_count[0]; 177 rctx->byte_count[1] = import_state->byte_count[1]; 178 memcpy(rctx->buf, import_state->pending_buf, rctx->buflen); 179 memcpy(rctx->digest, import_state->partial_digest, sizeof(rctx->digest)); 180 181 return 0; 182 } 183 184 static int qce_ahash_update(struct ahash_request *req) 185 { 186 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 187 struct qce_sha_reqctx *rctx = ahash_request_ctx_dma(req); 188 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); 189 struct qce_device *qce = tmpl->qce; 190 struct scatterlist *sg_last, *sg; 191 unsigned int total, len; 192 unsigned int hash_later; 193 unsigned int nbytes; 194 unsigned int blocksize; 195 196 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); 197 rctx->count += req->nbytes; 198 199 /* check for buffer from previous updates and append it */ 200 total = req->nbytes + rctx->buflen; 201 202 if (total <= blocksize) { 203 scatterwalk_map_and_copy(rctx->buf + rctx->buflen, req->src, 204 0, req->nbytes, 0); 205 rctx->buflen += req->nbytes; 206 return 0; 207 } 208 209 /* save the original req structure fields */ 210 rctx->src_orig = req->src; 211 rctx->nbytes_orig = req->nbytes; 212 213 /* 214 * if we have data from previous update copy them on buffer. The old 215 * data will be combined with current request bytes. 216 */ 217 if (rctx->buflen) 218 memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen); 219 220 /* calculate how many bytes will be hashed later */ 221 hash_later = total % blocksize; 222 223 /* 224 * At this point, there is more than one block size of data. If 225 * the available data to transfer is exactly a multiple of block 226 * size, save the last block to be transferred in qce_ahash_final 227 * (with the last block bit set) if this is indeed the end of data 228 * stream. If not this saved block will be transferred as part of 229 * next update. If this block is not held back and if this is 230 * indeed the end of data stream, the digest obtained will be wrong 231 * since qce_ahash_final will see that rctx->buflen is 0 and return 232 * doing nothing which in turn means that a digest will not be 233 * copied to the destination result buffer. qce_ahash_final cannot 234 * be made to alter this behavior and allowed to proceed if 235 * rctx->buflen is 0 because the crypto engine BAM does not allow 236 * for zero length transfers. 237 */ 238 if (!hash_later) 239 hash_later = blocksize; 240 241 if (hash_later) { 242 unsigned int src_offset = req->nbytes - hash_later; 243 scatterwalk_map_and_copy(rctx->buf, req->src, src_offset, 244 hash_later, 0); 245 } 246 247 /* here nbytes is multiple of blocksize */ 248 nbytes = total - hash_later; 249 250 len = rctx->buflen; 251 sg = sg_last = req->src; 252 253 while (len < nbytes && sg) { 254 if (len + sg_dma_len(sg) > nbytes) 255 break; 256 len += sg_dma_len(sg); 257 sg_last = sg; 258 sg = sg_next(sg); 259 } 260 261 if (!sg_last) 262 return -EINVAL; 263 264 if (rctx->buflen) { 265 sg_init_table(rctx->sg, 2); 266 sg_set_buf(rctx->sg, rctx->tmpbuf, rctx->buflen); 267 sg_chain(rctx->sg, 2, req->src); 268 req->src = rctx->sg; 269 } 270 271 req->nbytes = nbytes; 272 rctx->buflen = hash_later; 273 274 return qce->async_req_enqueue(tmpl->qce, &req->base); 275 } 276 277 static int qce_ahash_final(struct ahash_request *req) 278 { 279 struct qce_sha_reqctx *rctx = ahash_request_ctx_dma(req); 280 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); 281 struct qce_device *qce = tmpl->qce; 282 283 if (!rctx->buflen) { 284 if (tmpl->hash_zero) 285 memcpy(req->result, tmpl->hash_zero, 286 tmpl->alg.ahash.halg.digestsize); 287 return 0; 288 } 289 290 rctx->last_blk = true; 291 292 rctx->src_orig = req->src; 293 rctx->nbytes_orig = req->nbytes; 294 295 memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen); 296 sg_init_one(rctx->sg, rctx->tmpbuf, rctx->buflen); 297 298 req->src = rctx->sg; 299 req->nbytes = rctx->buflen; 300 301 return qce->async_req_enqueue(tmpl->qce, &req->base); 302 } 303 304 static int qce_ahash_digest(struct ahash_request *req) 305 { 306 struct qce_sha_reqctx *rctx = ahash_request_ctx_dma(req); 307 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); 308 struct qce_device *qce = tmpl->qce; 309 int ret; 310 311 ret = qce_ahash_init(req); 312 if (ret) 313 return ret; 314 315 rctx->src_orig = req->src; 316 rctx->nbytes_orig = req->nbytes; 317 rctx->first_blk = true; 318 rctx->last_blk = true; 319 320 if (!rctx->nbytes_orig) { 321 if (tmpl->hash_zero) 322 memcpy(req->result, tmpl->hash_zero, 323 tmpl->alg.ahash.halg.digestsize); 324 return 0; 325 } 326 327 return qce->async_req_enqueue(tmpl->qce, &req->base); 328 } 329 330 static int qce_ahash_hmac_setkey(struct crypto_ahash *tfm, const u8 *key, 331 unsigned int keylen) 332 { 333 unsigned int digestsize = crypto_ahash_digestsize(tfm); 334 struct qce_sha_ctx *ctx = crypto_tfm_ctx(&tfm->base); 335 struct crypto_wait wait; 336 struct ahash_request *req; 337 struct scatterlist sg; 338 unsigned int blocksize; 339 struct crypto_ahash *ahash_tfm; 340 u8 *buf; 341 int ret; 342 const char *alg_name; 343 344 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); 345 memset(ctx->authkey, 0, sizeof(ctx->authkey)); 346 347 if (keylen <= blocksize) { 348 memcpy(ctx->authkey, key, keylen); 349 return 0; 350 } 351 352 if (digestsize == SHA1_DIGEST_SIZE) 353 alg_name = "sha1-qce"; 354 else if (digestsize == SHA256_DIGEST_SIZE) 355 alg_name = "sha256-qce"; 356 else 357 return -EINVAL; 358 359 ahash_tfm = crypto_alloc_ahash(alg_name, 0, 0); 360 if (IS_ERR(ahash_tfm)) 361 return PTR_ERR(ahash_tfm); 362 363 req = ahash_request_alloc(ahash_tfm, GFP_KERNEL); 364 if (!req) { 365 ret = -ENOMEM; 366 goto err_free_ahash; 367 } 368 369 crypto_init_wait(&wait); 370 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, 371 crypto_req_done, &wait); 372 crypto_ahash_clear_flags(ahash_tfm, ~0); 373 374 buf = kzalloc(keylen + QCE_MAX_ALIGN_SIZE, GFP_KERNEL); 375 if (!buf) { 376 ret = -ENOMEM; 377 goto err_free_req; 378 } 379 380 memcpy(buf, key, keylen); 381 sg_init_one(&sg, buf, keylen); 382 ahash_request_set_crypt(req, &sg, ctx->authkey, keylen); 383 384 ret = crypto_wait_req(crypto_ahash_digest(req), &wait); 385 386 kfree(buf); 387 err_free_req: 388 ahash_request_free(req); 389 err_free_ahash: 390 crypto_free_ahash(ahash_tfm); 391 return ret; 392 } 393 394 static int qce_ahash_cra_init(struct crypto_tfm *tfm) 395 { 396 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm); 397 struct qce_sha_ctx *ctx = crypto_tfm_ctx(tfm); 398 399 crypto_ahash_set_reqsize_dma(ahash, sizeof(struct qce_sha_reqctx)); 400 memset(ctx, 0, sizeof(*ctx)); 401 return 0; 402 } 403 404 struct qce_ahash_def { 405 unsigned long flags; 406 const char *name; 407 const char *drv_name; 408 unsigned int digestsize; 409 unsigned int blocksize; 410 unsigned int statesize; 411 const u32 *std_iv; 412 }; 413 414 static const struct qce_ahash_def ahash_def[] = { 415 { 416 .flags = QCE_HASH_SHA1, 417 .name = "sha1", 418 .drv_name = "sha1-qce", 419 .digestsize = SHA1_DIGEST_SIZE, 420 .blocksize = SHA1_BLOCK_SIZE, 421 .statesize = sizeof(struct qce_sha_saved_state), 422 .std_iv = std_iv_sha1, 423 }, 424 { 425 .flags = QCE_HASH_SHA256, 426 .name = "sha256", 427 .drv_name = "sha256-qce", 428 .digestsize = SHA256_DIGEST_SIZE, 429 .blocksize = SHA256_BLOCK_SIZE, 430 .statesize = sizeof(struct qce_sha_saved_state), 431 .std_iv = std_iv_sha256, 432 }, 433 { 434 .flags = QCE_HASH_SHA1_HMAC, 435 .name = "hmac(sha1)", 436 .drv_name = "hmac-sha1-qce", 437 .digestsize = SHA1_DIGEST_SIZE, 438 .blocksize = SHA1_BLOCK_SIZE, 439 .statesize = sizeof(struct qce_sha_saved_state), 440 .std_iv = std_iv_sha1, 441 }, 442 { 443 .flags = QCE_HASH_SHA256_HMAC, 444 .name = "hmac(sha256)", 445 .drv_name = "hmac-sha256-qce", 446 .digestsize = SHA256_DIGEST_SIZE, 447 .blocksize = SHA256_BLOCK_SIZE, 448 .statesize = sizeof(struct qce_sha_saved_state), 449 .std_iv = std_iv_sha256, 450 }, 451 }; 452 453 static int qce_ahash_register_one(const struct qce_ahash_def *def, 454 struct qce_device *qce) 455 { 456 struct qce_alg_template *tmpl; 457 struct ahash_alg *alg; 458 struct crypto_alg *base; 459 int ret; 460 461 tmpl = kzalloc_obj(*tmpl); 462 if (!tmpl) 463 return -ENOMEM; 464 465 tmpl->std_iv = def->std_iv; 466 467 alg = &tmpl->alg.ahash; 468 alg->init = qce_ahash_init; 469 alg->update = qce_ahash_update; 470 alg->final = qce_ahash_final; 471 alg->digest = qce_ahash_digest; 472 alg->export = qce_ahash_export; 473 alg->import = qce_ahash_import; 474 if (IS_SHA_HMAC(def->flags)) 475 alg->setkey = qce_ahash_hmac_setkey; 476 alg->halg.digestsize = def->digestsize; 477 alg->halg.statesize = def->statesize; 478 479 if (IS_SHA1(def->flags)) 480 tmpl->hash_zero = sha1_zero_message_hash; 481 else if (IS_SHA256(def->flags)) 482 tmpl->hash_zero = sha256_zero_message_hash; 483 484 base = &alg->halg.base; 485 base->cra_blocksize = def->blocksize; 486 base->cra_priority = 175; 487 base->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY; 488 base->cra_ctxsize = sizeof(struct qce_sha_ctx); 489 base->cra_alignmask = 0; 490 base->cra_module = THIS_MODULE; 491 base->cra_init = qce_ahash_cra_init; 492 493 strscpy(base->cra_name, def->name); 494 strscpy(base->cra_driver_name, def->drv_name); 495 496 INIT_LIST_HEAD(&tmpl->entry); 497 tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_AHASH; 498 tmpl->alg_flags = def->flags; 499 tmpl->qce = qce; 500 501 ret = crypto_register_ahash(alg); 502 if (ret) { 503 dev_err(qce->dev, "%s registration failed\n", base->cra_name); 504 kfree(tmpl); 505 return ret; 506 } 507 508 list_add_tail(&tmpl->entry, &ahash_algs); 509 dev_dbg(qce->dev, "%s is registered\n", base->cra_name); 510 return 0; 511 } 512 513 static void qce_ahash_unregister(struct qce_device *qce) 514 { 515 struct qce_alg_template *tmpl, *n; 516 517 list_for_each_entry_safe(tmpl, n, &ahash_algs, entry) { 518 crypto_unregister_ahash(&tmpl->alg.ahash); 519 list_del(&tmpl->entry); 520 kfree(tmpl); 521 } 522 } 523 524 static int qce_ahash_register(struct qce_device *qce) 525 { 526 int ret, i; 527 528 for (i = 0; i < ARRAY_SIZE(ahash_def); i++) { 529 ret = qce_ahash_register_one(&ahash_def[i], qce); 530 if (ret) 531 goto err; 532 } 533 534 return 0; 535 err: 536 qce_ahash_unregister(qce); 537 return ret; 538 } 539 540 const struct qce_algo_ops ahash_ops = { 541 .type = CRYPTO_ALG_TYPE_AHASH, 542 .register_algs = qce_ahash_register, 543 .unregister_algs = qce_ahash_unregister, 544 .async_req_handle = qce_ahash_async_req_handle, 545 }; 546