1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2023 MediaTek Inc. 4 * 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mediatek,mt8188-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/mailbox/mediatek,mt8188-gce.h> 12#include <dt-bindings/memory/mediatek,mt8188-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> 15#include <dt-bindings/power/mediatek,mt8188-power.h> 16#include <dt-bindings/reset/mt8188-resets.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 19 20/ { 21 compatible = "mediatek,mt8188"; 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 dp-intf0 = &dp_intf0; 28 dp-intf1 = &dp_intf1; 29 dsc0 = &dsc0; 30 ethdr0 = ðdr0; 31 gce0 = &gce0; 32 gce1 = &gce1; 33 merge0 = &merge0; 34 merge1 = &merge1; 35 merge2 = &merge2; 36 merge3 = &merge3; 37 merge4 = &merge4; 38 merge5 = &merge5; 39 mutex0 = &mutex0; 40 mutex1 = &mutex1; 41 padding0 = &padding0; 42 padding1 = &padding1; 43 padding2 = &padding2; 44 padding3 = &padding3; 45 padding4 = &padding4; 46 padding5 = &padding5; 47 padding6 = &padding6; 48 padding7 = &padding7; 49 vdo1-rdma0 = &vdo1_rdma0; 50 vdo1-rdma1 = &vdo1_rdma1; 51 vdo1-rdma2 = &vdo1_rdma2; 52 vdo1-rdma3 = &vdo1_rdma3; 53 vdo1-rdma4 = &vdo1_rdma4; 54 vdo1-rdma5 = &vdo1_rdma5; 55 vdo1-rdma6 = &vdo1_rdma6; 56 vdo1-rdma7 = &vdo1_rdma7; 57 }; 58 59 cpus { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 cpu0: cpu@0 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a55"; 66 reg = <0x000>; 67 enable-method = "psci"; 68 clock-frequency = <2000000000>; 69 capacity-dmips-mhz = <282>; 70 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 71 i-cache-size = <32768>; 72 i-cache-line-size = <64>; 73 i-cache-sets = <128>; 74 d-cache-size = <32768>; 75 d-cache-line-size = <64>; 76 d-cache-sets = <128>; 77 next-level-cache = <&l2_0>; 78 performance-domains = <&performance 0>; 79 #cooling-cells = <2>; 80 }; 81 82 cpu1: cpu@100 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a55"; 85 reg = <0x100>; 86 enable-method = "psci"; 87 clock-frequency = <2000000000>; 88 capacity-dmips-mhz = <282>; 89 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 90 i-cache-size = <32768>; 91 i-cache-line-size = <64>; 92 i-cache-sets = <128>; 93 d-cache-size = <32768>; 94 d-cache-line-size = <64>; 95 d-cache-sets = <128>; 96 next-level-cache = <&l2_0>; 97 performance-domains = <&performance 0>; 98 #cooling-cells = <2>; 99 }; 100 101 cpu2: cpu@200 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a55"; 104 reg = <0x200>; 105 enable-method = "psci"; 106 clock-frequency = <2000000000>; 107 capacity-dmips-mhz = <282>; 108 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 109 i-cache-size = <32768>; 110 i-cache-line-size = <64>; 111 i-cache-sets = <128>; 112 d-cache-size = <32768>; 113 d-cache-line-size = <64>; 114 d-cache-sets = <128>; 115 next-level-cache = <&l2_0>; 116 performance-domains = <&performance 0>; 117 #cooling-cells = <2>; 118 }; 119 120 cpu3: cpu@300 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a55"; 123 reg = <0x300>; 124 enable-method = "psci"; 125 clock-frequency = <2000000000>; 126 capacity-dmips-mhz = <282>; 127 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 128 i-cache-size = <32768>; 129 i-cache-line-size = <64>; 130 i-cache-sets = <128>; 131 d-cache-size = <32768>; 132 d-cache-line-size = <64>; 133 d-cache-sets = <128>; 134 next-level-cache = <&l2_0>; 135 performance-domains = <&performance 0>; 136 #cooling-cells = <2>; 137 }; 138 139 cpu4: cpu@400 { 140 device_type = "cpu"; 141 compatible = "arm,cortex-a55"; 142 reg = <0x400>; 143 enable-method = "psci"; 144 clock-frequency = <2000000000>; 145 capacity-dmips-mhz = <282>; 146 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 147 i-cache-size = <32768>; 148 i-cache-line-size = <64>; 149 i-cache-sets = <128>; 150 d-cache-size = <32768>; 151 d-cache-line-size = <64>; 152 d-cache-sets = <128>; 153 next-level-cache = <&l2_0>; 154 performance-domains = <&performance 0>; 155 #cooling-cells = <2>; 156 }; 157 158 cpu5: cpu@500 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a55"; 161 reg = <0x500>; 162 enable-method = "psci"; 163 clock-frequency = <2000000000>; 164 capacity-dmips-mhz = <282>; 165 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 166 i-cache-size = <32768>; 167 i-cache-line-size = <64>; 168 i-cache-sets = <128>; 169 d-cache-size = <32768>; 170 d-cache-line-size = <64>; 171 d-cache-sets = <128>; 172 next-level-cache = <&l2_0>; 173 performance-domains = <&performance 0>; 174 #cooling-cells = <2>; 175 }; 176 177 cpu6: cpu@600 { 178 device_type = "cpu"; 179 compatible = "arm,cortex-a78"; 180 reg = <0x600>; 181 enable-method = "psci"; 182 clock-frequency = <2600000000>; 183 capacity-dmips-mhz = <1024>; 184 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 185 i-cache-size = <65536>; 186 i-cache-line-size = <64>; 187 i-cache-sets = <256>; 188 d-cache-size = <65536>; 189 d-cache-line-size = <64>; 190 d-cache-sets = <256>; 191 next-level-cache = <&l2_1>; 192 performance-domains = <&performance 1>; 193 #cooling-cells = <2>; 194 }; 195 196 cpu7: cpu@700 { 197 device_type = "cpu"; 198 compatible = "arm,cortex-a78"; 199 reg = <0x700>; 200 enable-method = "psci"; 201 clock-frequency = <2600000000>; 202 capacity-dmips-mhz = <1024>; 203 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 204 i-cache-size = <65536>; 205 i-cache-line-size = <64>; 206 i-cache-sets = <256>; 207 d-cache-size = <65536>; 208 d-cache-line-size = <64>; 209 d-cache-sets = <256>; 210 next-level-cache = <&l2_1>; 211 performance-domains = <&performance 1>; 212 #cooling-cells = <2>; 213 }; 214 215 cpu-map { 216 cluster0 { 217 core0 { 218 cpu = <&cpu0>; 219 }; 220 221 core1 { 222 cpu = <&cpu1>; 223 }; 224 225 core2 { 226 cpu = <&cpu2>; 227 }; 228 229 core3 { 230 cpu = <&cpu3>; 231 }; 232 233 core4 { 234 cpu = <&cpu4>; 235 }; 236 237 core5 { 238 cpu = <&cpu5>; 239 }; 240 241 core6 { 242 cpu = <&cpu6>; 243 }; 244 245 core7 { 246 cpu = <&cpu7>; 247 }; 248 }; 249 }; 250 251 idle-states { 252 entry-method = "psci"; 253 254 cpu_off_l: cpu-off-l { 255 compatible = "arm,idle-state"; 256 arm,psci-suspend-param = <0x00010000>; 257 local-timer-stop; 258 entry-latency-us = <50>; 259 exit-latency-us = <95>; 260 min-residency-us = <580>; 261 }; 262 263 cpu_off_b: cpu-off-b { 264 compatible = "arm,idle-state"; 265 arm,psci-suspend-param = <0x00010000>; 266 local-timer-stop; 267 entry-latency-us = <45>; 268 exit-latency-us = <140>; 269 min-residency-us = <740>; 270 }; 271 272 cluster_off_l: cluster-off-l { 273 compatible = "arm,idle-state"; 274 arm,psci-suspend-param = <0x01010010>; 275 local-timer-stop; 276 entry-latency-us = <55>; 277 exit-latency-us = <155>; 278 min-residency-us = <840>; 279 }; 280 281 cluster_off_b: cluster-off-b { 282 compatible = "arm,idle-state"; 283 arm,psci-suspend-param = <0x01010010>; 284 local-timer-stop; 285 entry-latency-us = <50>; 286 exit-latency-us = <200>; 287 min-residency-us = <1000>; 288 }; 289 }; 290 291 l2_0: l2-cache0 { 292 compatible = "cache"; 293 cache-level = <2>; 294 cache-size = <131072>; 295 cache-line-size = <64>; 296 cache-sets = <512>; 297 next-level-cache = <&l3_0>; 298 cache-unified; 299 }; 300 301 l2_1: l2-cache1 { 302 compatible = "cache"; 303 cache-level = <2>; 304 cache-size = <262144>; 305 cache-line-size = <64>; 306 cache-sets = <512>; 307 next-level-cache = <&l3_0>; 308 cache-unified; 309 }; 310 311 l3_0: l3-cache { 312 compatible = "cache"; 313 cache-level = <3>; 314 cache-size = <2097152>; 315 cache-line-size = <64>; 316 cache-sets = <2048>; 317 cache-unified; 318 }; 319 }; 320 321 clk13m: oscillator-13m { 322 compatible = "fixed-clock"; 323 #clock-cells = <0>; 324 clock-frequency = <13000000>; 325 clock-output-names = "clk13m"; 326 }; 327 328 clk26m: oscillator-26m { 329 compatible = "fixed-clock"; 330 #clock-cells = <0>; 331 clock-frequency = <26000000>; 332 clock-output-names = "clk26m"; 333 }; 334 335 clk32k: oscillator-32k { 336 compatible = "fixed-clock"; 337 #clock-cells = <0>; 338 clock-frequency = <32768>; 339 clock-output-names = "clk32k"; 340 }; 341 342 gpu_opp_table: opp-table-gpu { 343 compatible = "operating-points-v2"; 344 opp-shared; 345 346 opp-390000000 { 347 opp-hz = /bits/ 64 <390000000>; 348 opp-microvolt = <575000>; 349 opp-supported-hw = <0xff>; 350 }; 351 opp-431000000 { 352 opp-hz = /bits/ 64 <431000000>; 353 opp-microvolt = <587500>; 354 opp-supported-hw = <0xff>; 355 }; 356 opp-473000000 { 357 opp-hz = /bits/ 64 <473000000>; 358 opp-microvolt = <600000>; 359 opp-supported-hw = <0xff>; 360 }; 361 opp-515000000 { 362 opp-hz = /bits/ 64 <515000000>; 363 opp-microvolt = <612500>; 364 opp-supported-hw = <0xff>; 365 }; 366 opp-556000000 { 367 opp-hz = /bits/ 64 <556000000>; 368 opp-microvolt = <625000>; 369 opp-supported-hw = <0xff>; 370 }; 371 opp-598000000 { 372 opp-hz = /bits/ 64 <598000000>; 373 opp-microvolt = <637500>; 374 opp-supported-hw = <0xff>; 375 }; 376 opp-640000000 { 377 opp-hz = /bits/ 64 <640000000>; 378 opp-microvolt = <650000>; 379 opp-supported-hw = <0xff>; 380 }; 381 opp-670000000 { 382 opp-hz = /bits/ 64 <670000000>; 383 opp-microvolt = <662500>; 384 opp-supported-hw = <0xff>; 385 }; 386 opp-700000000 { 387 opp-hz = /bits/ 64 <700000000>; 388 opp-microvolt = <675000>; 389 opp-supported-hw = <0xff>; 390 }; 391 opp-730000000 { 392 opp-hz = /bits/ 64 <730000000>; 393 opp-microvolt = <687500>; 394 opp-supported-hw = <0xff>; 395 }; 396 opp-760000000 { 397 opp-hz = /bits/ 64 <760000000>; 398 opp-microvolt = <700000>; 399 opp-supported-hw = <0xff>; 400 }; 401 opp-790000000 { 402 opp-hz = /bits/ 64 <790000000>; 403 opp-microvolt = <712500>; 404 opp-supported-hw = <0xff>; 405 }; 406 opp-835000000 { 407 opp-hz = /bits/ 64 <835000000>; 408 opp-microvolt = <731250>; 409 opp-supported-hw = <0xff>; 410 }; 411 opp-880000000 { 412 opp-hz = /bits/ 64 <880000000>; 413 opp-microvolt = <750000>; 414 opp-supported-hw = <0xff>; 415 }; 416 opp-915000000 { 417 opp-hz = /bits/ 64 <915000000>; 418 opp-microvolt = <775000>; 419 opp-supported-hw = <0x8f>; 420 }; 421 opp-915000000-5 { 422 opp-hz = /bits/ 64 <915000000>; 423 opp-microvolt = <762500>; 424 opp-supported-hw = <0x30>; 425 }; 426 opp-915000000-6 { 427 opp-hz = /bits/ 64 <915000000>; 428 opp-microvolt = <750000>; 429 opp-supported-hw = <0x70>; 430 }; 431 opp-950000000 { 432 opp-hz = /bits/ 64 <950000000>; 433 opp-microvolt = <800000>; 434 opp-supported-hw = <0x8f>; 435 }; 436 opp-950000000-5 { 437 opp-hz = /bits/ 64 <950000000>; 438 opp-microvolt = <775000>; 439 opp-supported-hw = <0x30>; 440 }; 441 opp-950000000-6 { 442 opp-hz = /bits/ 64 <950000000>; 443 opp-microvolt = <750000>; 444 opp-supported-hw = <0x70>; 445 }; 446 }; 447 448 pmu-a55 { 449 compatible = "arm,cortex-a55-pmu"; 450 interrupt-parent = <&gic>; 451 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 452 }; 453 454 pmu-a78 { 455 compatible = "arm,cortex-a78-pmu"; 456 interrupt-parent = <&gic>; 457 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 458 }; 459 460 psci { 461 compatible = "arm,psci-1.0"; 462 method = "smc"; 463 }; 464 465 sound: sound { 466 mediatek,platform = <&afe>; 467 status = "disabled"; 468 }; 469 470 thermal_zones: thermal-zones { 471 cpu-little0-thermal { 472 polling-delay = <1000>; 473 polling-delay-passive = <150>; 474 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU0>; 475 476 trips { 477 cpu_little0_alert0: trip-alert0 { 478 temperature = <85000>; 479 hysteresis = <2000>; 480 type = "passive"; 481 }; 482 483 cpu_little0_alert1: trip-alert1 { 484 temperature = <95000>; 485 hysteresis = <2000>; 486 type = "hot"; 487 }; 488 489 cpu_little0_crit: trip-crit { 490 temperature = <100000>; 491 hysteresis = <0>; 492 type = "critical"; 493 }; 494 }; 495 496 cooling-maps { 497 cpu_little0_cooling_map0: map0 { 498 trip = <&cpu_little0_alert0>; 499 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 500 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 501 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 502 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 503 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 504 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 505 }; 506 }; 507 }; 508 509 cpu-little1-thermal { 510 polling-delay = <1000>; 511 polling-delay-passive = <150>; 512 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU1>; 513 514 trips { 515 cpu_little1_alert0: trip-alert0 { 516 temperature = <85000>; 517 hysteresis = <2000>; 518 type = "passive"; 519 }; 520 521 cpu_little1_alert1: trip-alert1 { 522 temperature = <95000>; 523 hysteresis = <2000>; 524 type = "hot"; 525 }; 526 527 cpu_little1_crit: trip-crit { 528 temperature = <100000>; 529 hysteresis = <0>; 530 type = "critical"; 531 }; 532 }; 533 534 cooling-maps { 535 cpu_little1_cooling_map0: map0 { 536 trip = <&cpu_little1_alert0>; 537 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 538 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 539 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 540 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 541 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 542 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 543 }; 544 }; 545 }; 546 547 cpu-little2-thermal { 548 polling-delay = <1000>; 549 polling-delay-passive = <150>; 550 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU2>; 551 552 trips { 553 cpu_little2_alert0: trip-alert0 { 554 temperature = <85000>; 555 hysteresis = <2000>; 556 type = "passive"; 557 }; 558 559 cpu_little2_alert1: trip-alert1 { 560 temperature = <95000>; 561 hysteresis = <2000>; 562 type = "hot"; 563 }; 564 565 cpu_little2_crit: trip-crit { 566 temperature = <100000>; 567 hysteresis = <0>; 568 type = "critical"; 569 }; 570 }; 571 572 cooling-maps { 573 cpu_little2_cooling_map0: map0 { 574 trip = <&cpu_little2_alert0>; 575 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 576 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 577 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 578 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 579 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 580 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 581 }; 582 }; 583 }; 584 585 cpu-little3-thermal { 586 polling-delay = <1000>; 587 polling-delay-passive = <150>; 588 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU3>; 589 590 trips { 591 cpu_little3_alert0: trip-alert0 { 592 temperature = <85000>; 593 hysteresis = <2000>; 594 type = "passive"; 595 }; 596 597 cpu_little3_alert1: trip-alert1 { 598 temperature = <95000>; 599 hysteresis = <2000>; 600 type = "hot"; 601 }; 602 603 cpu_little3_crit: trip-crit { 604 temperature = <100000>; 605 hysteresis = <0>; 606 type = "critical"; 607 }; 608 }; 609 610 cooling-maps { 611 cpu_little3_cooling_map0: map0 { 612 trip = <&cpu_little3_alert0>; 613 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 614 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 615 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 616 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 617 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 618 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 619 }; 620 }; 621 }; 622 623 cpu-big0-thermal { 624 polling-delay = <1000>; 625 polling-delay-passive = <100>; 626 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU0>; 627 628 trips { 629 cpu_big0_alert0: trip-alert0 { 630 temperature = <85000>; 631 hysteresis = <2000>; 632 type = "passive"; 633 }; 634 635 cpu_big0_alert1: trip-alert1 { 636 temperature = <95000>; 637 hysteresis = <2000>; 638 type = "hot"; 639 }; 640 641 cpu_big0_crit: trip-crit { 642 temperature = <100000>; 643 hysteresis = <0>; 644 type = "critical"; 645 }; 646 }; 647 648 cooling-maps { 649 map0 { 650 trip = <&cpu_big0_alert0>; 651 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 652 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 653 }; 654 }; 655 }; 656 657 cpu-big1-thermal { 658 polling-delay = <1000>; 659 polling-delay-passive = <100>; 660 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU1>; 661 662 trips { 663 cpu_big1_alert0: trip-alert0 { 664 temperature = <85000>; 665 hysteresis = <2000>; 666 type = "passive"; 667 }; 668 669 cpu_big1_alert1: trip-alert1 { 670 temperature = <95000>; 671 hysteresis = <2000>; 672 type = "hot"; 673 }; 674 675 cpu_big1_crit: trip-crit { 676 temperature = <100000>; 677 hysteresis = <0>; 678 type = "critical"; 679 }; 680 }; 681 682 cooling-maps { 683 map0 { 684 trip = <&cpu_big1_alert0>; 685 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 686 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 687 }; 688 }; 689 }; 690 691 apu-thermal { 692 polling-delay = <1000>; 693 polling-delay-passive = <250>; 694 thermal-sensors = <&lvts_ap MT8188_AP_APU>; 695 696 trips { 697 apu_alert0: trip-alert0 { 698 temperature = <85000>; 699 hysteresis = <2000>; 700 type = "passive"; 701 }; 702 703 apu_alert1: trip-alert1 { 704 temperature = <95000>; 705 hysteresis = <2000>; 706 type = "hot"; 707 }; 708 709 apu_crit: trip-crit { 710 temperature = <100000>; 711 hysteresis = <0>; 712 type = "critical"; 713 }; 714 }; 715 }; 716 717 gpu-thermal { 718 polling-delay = <1000>; 719 polling-delay-passive = <250>; 720 thermal-sensors = <&lvts_ap MT8188_AP_GPU0>; 721 722 trips { 723 gpu_alert0: trip-alert0 { 724 temperature = <85000>; 725 hysteresis = <2000>; 726 type = "passive"; 727 }; 728 729 gpu_alert1: trip-alert1 { 730 temperature = <95000>; 731 hysteresis = <2000>; 732 type = "hot"; 733 }; 734 735 gpu_crit: trip-crit { 736 temperature = <100000>; 737 hysteresis = <0>; 738 type = "critical"; 739 }; 740 }; 741 742 cooling-maps { 743 map0 { 744 trip = <&gpu_alert0>; 745 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 746 }; 747 }; 748 }; 749 750 gpu1-thermal { 751 polling-delay = <1000>; 752 polling-delay-passive = <250>; 753 thermal-sensors = <&lvts_ap MT8188_AP_GPU1>; 754 755 trips { 756 gpu1_alert0: trip-alert0 { 757 temperature = <85000>; 758 hysteresis = <2000>; 759 type = "passive"; 760 }; 761 762 gpu1_alert1: trip-alert1 { 763 temperature = <95000>; 764 hysteresis = <2000>; 765 type = "hot"; 766 }; 767 768 gpu1_crit: trip-crit { 769 temperature = <100000>; 770 hysteresis = <0>; 771 type = "critical"; 772 }; 773 }; 774 775 cooling-maps { 776 map0 { 777 trip = <&gpu1_alert0>; 778 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 779 }; 780 }; 781 }; 782 783 adsp-thermal { 784 polling-delay = <1000>; 785 polling-delay-passive = <250>; 786 thermal-sensors = <&lvts_ap MT8188_AP_ADSP>; 787 788 trips { 789 soc_alert0: trip-alert0 { 790 temperature = <85000>; 791 hysteresis = <2000>; 792 type = "passive"; 793 }; 794 795 soc_alert1: trip-alert1 { 796 temperature = <95000>; 797 hysteresis = <2000>; 798 type = "hot"; 799 }; 800 801 soc_crit: trip-crit { 802 temperature = <100000>; 803 hysteresis = <0>; 804 type = "critical"; 805 }; 806 }; 807 }; 808 809 vdo-thermal { 810 polling-delay = <1000>; 811 polling-delay-passive = <250>; 812 thermal-sensors = <&lvts_ap MT8188_AP_VDO>; 813 814 trips { 815 soc1_alert0: trip-alert0 { 816 temperature = <85000>; 817 hysteresis = <2000>; 818 type = "passive"; 819 }; 820 821 soc1_alert1: trip-alert1 { 822 temperature = <95000>; 823 hysteresis = <2000>; 824 type = "hot"; 825 }; 826 827 soc1_crit: trip-crit { 828 temperature = <100000>; 829 hysteresis = <0>; 830 type = "critical"; 831 }; 832 }; 833 }; 834 835 infra-thermal { 836 polling-delay = <1000>; 837 polling-delay-passive = <250>; 838 thermal-sensors = <&lvts_ap MT8188_AP_INFRA>; 839 840 trips { 841 soc2_alert0: trip-alert0 { 842 temperature = <85000>; 843 hysteresis = <2000>; 844 type = "passive"; 845 }; 846 847 soc2_alert1: trip-alert1 { 848 temperature = <95000>; 849 hysteresis = <2000>; 850 type = "hot"; 851 }; 852 853 soc2_crit: trip-crit { 854 temperature = <100000>; 855 hysteresis = <0>; 856 type = "critical"; 857 }; 858 }; 859 }; 860 861 cam1-thermal { 862 polling-delay = <1000>; 863 polling-delay-passive = <250>; 864 thermal-sensors = <&lvts_ap MT8188_AP_CAM1>; 865 866 trips { 867 cam1_alert0: trip-alert0 { 868 temperature = <85000>; 869 hysteresis = <2000>; 870 type = "passive"; 871 }; 872 873 cam1_alert1: trip-alert1 { 874 temperature = <95000>; 875 hysteresis = <2000>; 876 type = "hot"; 877 }; 878 879 cam1_crit: trip-crit { 880 temperature = <100000>; 881 hysteresis = <0>; 882 type = "critical"; 883 }; 884 }; 885 }; 886 887 cam2-thermal { 888 polling-delay = <1000>; 889 polling-delay-passive = <250>; 890 thermal-sensors = <&lvts_ap MT8188_AP_CAM2>; 891 892 trips { 893 cam2_alert0: trip-alert0 { 894 temperature = <85000>; 895 hysteresis = <2000>; 896 type = "passive"; 897 }; 898 899 cam2_alert1: trip-alert1 { 900 temperature = <95000>; 901 hysteresis = <2000>; 902 type = "hot"; 903 }; 904 905 cam2_crit: trip-crit { 906 temperature = <100000>; 907 hysteresis = <0>; 908 type = "critical"; 909 }; 910 }; 911 }; 912 }; 913 914 timer: timer { 915 compatible = "arm,armv8-timer"; 916 interrupt-parent = <&gic>; 917 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 918 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 919 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 920 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 921 clock-frequency = <13000000>; 922 }; 923 924 soc { 925 #address-cells = <2>; 926 #size-cells = <2>; 927 compatible = "simple-bus"; 928 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 929 ranges; 930 931 performance: performance-controller@11bc10 { 932 compatible = "mediatek,cpufreq-hw"; 933 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 934 #performance-domain-cells = <1>; 935 }; 936 937 gic: interrupt-controller@c000000 { 938 compatible = "arm,gic-v3"; 939 #interrupt-cells = <4>; 940 #redistributor-regions = <1>; 941 interrupt-parent = <&gic>; 942 interrupt-controller; 943 reg = <0 0x0c000000 0 0x40000>, 944 <0 0x0c040000 0 0x200000>; 945 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 946 947 ppi-partitions { 948 ppi_cluster0: interrupt-partition-0 { 949 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 950 }; 951 952 ppi_cluster1: interrupt-partition-1 { 953 affinity = <&cpu6 &cpu7>; 954 }; 955 }; 956 }; 957 958 topckgen: syscon@10000000 { 959 compatible = "mediatek,mt8188-topckgen", "syscon"; 960 reg = <0 0x10000000 0 0x1000>; 961 #clock-cells = <1>; 962 }; 963 964 infracfg_ao: syscon@10001000 { 965 compatible = "mediatek,mt8188-infracfg-ao", "syscon"; 966 reg = <0 0x10001000 0 0x1000>; 967 #clock-cells = <1>; 968 #reset-cells = <1>; 969 }; 970 971 pericfg: syscon@10003000 { 972 compatible = "mediatek,mt8188-pericfg", "syscon"; 973 reg = <0 0x10003000 0 0x1000>; 974 #clock-cells = <1>; 975 }; 976 977 pio: pinctrl@10005000 { 978 compatible = "mediatek,mt8188-pinctrl"; 979 reg = <0 0x10005000 0 0x1000>, 980 <0 0x11c00000 0 0x1000>, 981 <0 0x11e10000 0 0x1000>, 982 <0 0x11e20000 0 0x1000>, 983 <0 0x11ea0000 0 0x1000>, 984 <0 0x1000b000 0 0x1000>; 985 reg-names = "iocfg0", "iocfg_rm", "iocfg_lt", 986 "iocfg_lm", "iocfg_rt", "eint"; 987 gpio-controller; 988 #gpio-cells = <2>; 989 gpio-ranges = <&pio 0 0 176>; 990 interrupt-controller; 991 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 992 #interrupt-cells = <2>; 993 }; 994 995 scpsys: syscon@10006000 { 996 compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd"; 997 reg = <0 0x10006000 0 0x1000>; 998 999 /* System Power Manager */ 1000 spm: power-controller { 1001 compatible = "mediatek,mt8188-power-controller"; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 #power-domain-cells = <1>; 1005 1006 /* power domain of the SoC */ 1007 mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 { 1008 reg = <MT8188_POWER_DOMAIN_MFG0>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 #power-domain-cells = <1>; 1012 1013 mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 { 1014 reg = <MT8188_POWER_DOMAIN_MFG1>; 1015 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, 1016 <&topckgen CLK_TOP_MFG_CORE_TMP>; 1017 clock-names = "mfg", "alt"; 1018 mediatek,infracfg = <&infracfg_ao>; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 #power-domain-cells = <1>; 1022 1023 power-domain@MT8188_POWER_DOMAIN_MFG2 { 1024 reg = <MT8188_POWER_DOMAIN_MFG2>; 1025 #power-domain-cells = <0>; 1026 }; 1027 1028 power-domain@MT8188_POWER_DOMAIN_MFG3 { 1029 reg = <MT8188_POWER_DOMAIN_MFG3>; 1030 #power-domain-cells = <0>; 1031 }; 1032 1033 power-domain@MT8188_POWER_DOMAIN_MFG4 { 1034 reg = <MT8188_POWER_DOMAIN_MFG4>; 1035 #power-domain-cells = <0>; 1036 }; 1037 }; 1038 }; 1039 1040 power-domain@MT8188_POWER_DOMAIN_VPPSYS0 { 1041 reg = <MT8188_POWER_DOMAIN_VPPSYS0>; 1042 clocks = <&topckgen CLK_TOP_VPP>, 1043 <&topckgen CLK_TOP_CAM>, 1044 <&topckgen CLK_TOP_CCU>, 1045 <&topckgen CLK_TOP_IMG>, 1046 <&topckgen CLK_TOP_VENC>, 1047 <&topckgen CLK_TOP_VDEC>, 1048 <&topckgen CLK_TOP_WPE_VPP>, 1049 <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>, 1050 <&topckgen CLK_TOP_CFGREG_F26M_VPP0>, 1051 <&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>, 1052 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>, 1053 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>, 1054 <&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>, 1055 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>, 1056 <&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>, 1057 <&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>, 1058 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>, 1059 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>, 1060 <&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>, 1061 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 1062 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 1063 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 1064 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 1065 <&vppsys0 CLK_VPP0_SMI_RSI>, 1066 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1067 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1068 <&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>, 1069 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 1070 clock-names = "top", "cam", "ccu", "img", "venc", 1071 "vdec", "wpe", "cfgck", "cfgxo", 1072 "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1", 1073 "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa", 1074 "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6", 1075 "ss-sram-rdr", "ss-iommu", "ss-imgcam", 1076 "ss-emi", "ss-subcmn-rdr", "ss-rsi", 1077 "ss-cmn-l4", "ss-vdec1", "ss-wpe", 1078 "ss-cvdo-ve1"; 1079 mediatek,infracfg = <&infracfg_ao>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 #power-domain-cells = <1>; 1083 1084 power-domain@MT8188_POWER_DOMAIN_VDOSYS0 { 1085 reg = <MT8188_POWER_DOMAIN_VDOSYS0>; 1086 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>, 1087 <&topckgen CLK_TOP_CFGREG_F26M_VDO0>, 1088 <&vdosys0 CLK_VDO0_SMI_GALS>, 1089 <&vdosys0 CLK_VDO0_SMI_COMMON>, 1090 <&vdosys0 CLK_VDO0_SMI_EMI>, 1091 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 1092 <&vdosys0 CLK_VDO0_SMI_LARB>, 1093 <&vdosys0 CLK_VDO0_SMI_RSI>, 1094 <&vdosys0 CLK_VDO0_APB_BUS>; 1095 clock-names = "cfgck", "cfgxo", "ss-gals", 1096 "ss-cmn", "ss-emi", "ss-iommu", 1097 "ss-larb", "ss-rsi", "ss-bus"; 1098 mediatek,infracfg = <&infracfg_ao>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 #power-domain-cells = <1>; 1102 1103 power-domain@MT8188_POWER_DOMAIN_VPPSYS1 { 1104 reg = <MT8188_POWER_DOMAIN_VPPSYS1>; 1105 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>, 1106 <&topckgen CLK_TOP_CFGREG_F26M_VPP1>, 1107 <&vppsys1 CLK_VPP1_GALS5>, 1108 <&vppsys1 CLK_VPP1_GALS6>, 1109 <&vppsys1 CLK_VPP1_LARB5>, 1110 <&vppsys1 CLK_VPP1_LARB6>; 1111 clock-names = "cfgck", "cfgxo", 1112 "ss-vpp1-g5", "ss-vpp1-g6", 1113 "ss-vpp1-l5", "ss-vpp1-l6"; 1114 mediatek,infracfg = <&infracfg_ao>; 1115 #power-domain-cells = <0>; 1116 }; 1117 1118 power-domain@MT8188_POWER_DOMAIN_VDEC0 { 1119 reg = <MT8188_POWER_DOMAIN_VDEC0>; 1120 clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; 1121 clock-names = "ss-vdec1-soc-l1"; 1122 mediatek,infracfg = <&infracfg_ao>; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 #power-domain-cells = <1>; 1126 1127 power-domain@MT8188_POWER_DOMAIN_VDEC1 { 1128 reg = <MT8188_POWER_DOMAIN_VDEC1>; 1129 clocks = <&vdecsys CLK_VDEC2_LARB1>; 1130 clock-names = "ss-vdec2-l1"; 1131 mediatek,infracfg = <&infracfg_ao>; 1132 #power-domain-cells = <0>; 1133 }; 1134 }; 1135 1136 cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE { 1137 reg = <MT8188_POWER_DOMAIN_CAM_VCORE>; 1138 clocks = <&topckgen CLK_TOP_CAM>, 1139 <&topckgen CLK_TOP_CCU>, 1140 <&topckgen CLK_TOP_CCU_AHB>, 1141 <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>; 1142 clock-names = "cam", "ccu", "bus", "cfgck"; 1143 mediatek,infracfg = <&infracfg_ao>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 #power-domain-cells = <1>; 1147 1148 power-domain@MT8188_POWER_DOMAIN_CAM_MAIN { 1149 reg = <MT8188_POWER_DOMAIN_CAM_MAIN>; 1150 clocks = <&camsys CLK_CAM_MAIN_LARB13>, 1151 <&camsys CLK_CAM_MAIN_LARB14>, 1152 <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>, 1153 <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>, 1154 <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>; 1155 clock-names= "ss-cam-l13", "ss-cam-l14", 1156 "ss-cam-mm0", "ss-cam-mm1", 1157 "ss-camsys"; 1158 mediatek,infracfg = <&infracfg_ao>; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 #power-domain-cells = <1>; 1162 1163 power-domain@MT8188_POWER_DOMAIN_CAM_SUBB { 1164 reg = <MT8188_POWER_DOMAIN_CAM_SUBB>; 1165 clocks = <&camsys CLK_CAM_MAIN_CAM_SUBB>, 1166 <&camsys_rawb CLK_CAM_RAWB_LARBX>, 1167 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 1168 clock-names = "ss-camb-sub", 1169 "ss-camb-raw", 1170 "ss-camb-yuv"; 1171 #power-domain-cells = <0>; 1172 }; 1173 1174 power-domain@MT8188_POWER_DOMAIN_CAM_SUBA { 1175 reg =<MT8188_POWER_DOMAIN_CAM_SUBA>; 1176 clocks = <&camsys CLK_CAM_MAIN_CAM_SUBA>, 1177 <&camsys_rawa CLK_CAM_RAWA_LARBX>, 1178 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 1179 clock-names = "ss-cama-sub", 1180 "ss-cama-raw", 1181 "ss-cama-yuv"; 1182 #power-domain-cells = <0>; 1183 }; 1184 }; 1185 }; 1186 1187 power-domain@MT8188_POWER_DOMAIN_VDOSYS1 { 1188 reg = <MT8188_POWER_DOMAIN_VDOSYS1>; 1189 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>, 1190 <&topckgen CLK_TOP_CFGREG_F26M_VDO1>, 1191 <&vdosys1 CLK_VDO1_SMI_LARB2>, 1192 <&vdosys1 CLK_VDO1_SMI_LARB3>, 1193 <&vdosys1 CLK_VDO1_GALS>; 1194 clock-names = "cfgck", "cfgxo", "ss-larb2", 1195 "ss-larb3", "ss-gals"; 1196 mediatek,infracfg = <&infracfg_ao>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 #power-domain-cells = <1>; 1200 1201 power-domain@MT8188_POWER_DOMAIN_HDMI_TX { 1202 reg = <MT8188_POWER_DOMAIN_HDMI_TX>; 1203 clocks = <&topckgen CLK_TOP_HDMI_APB>, 1204 <&topckgen CLK_TOP_HDCP_24M>; 1205 clock-names = "bus", "hdcp"; 1206 mediatek,infracfg = <&infracfg_ao>; 1207 #power-domain-cells = <0>; 1208 }; 1209 1210 power-domain@MT8188_POWER_DOMAIN_DP_TX { 1211 reg = <MT8188_POWER_DOMAIN_DP_TX>; 1212 mediatek,infracfg = <&infracfg_ao>; 1213 #power-domain-cells = <0>; 1214 }; 1215 1216 power-domain@MT8188_POWER_DOMAIN_EDP_TX { 1217 reg = <MT8188_POWER_DOMAIN_EDP_TX>; 1218 mediatek,infracfg = <&infracfg_ao>; 1219 #power-domain-cells = <0>; 1220 }; 1221 }; 1222 1223 power-domain@MT8188_POWER_DOMAIN_VENC { 1224 reg = <MT8188_POWER_DOMAIN_VENC>; 1225 clocks = <&vencsys CLK_VENC1_LARB>, 1226 <&vencsys CLK_VENC1_VENC>, 1227 <&vencsys CLK_VENC1_GALS>, 1228 <&vencsys CLK_VENC1_GALS_SRAM>; 1229 clock-names = "ss-ve1-larb", "ss-ve1-core", 1230 "ss-ve1-gals", "ss-ve1-sram"; 1231 mediatek,infracfg = <&infracfg_ao>; 1232 #power-domain-cells = <0>; 1233 }; 1234 1235 power-domain@MT8188_POWER_DOMAIN_WPE { 1236 reg = <MT8188_POWER_DOMAIN_WPE>; 1237 clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, 1238 <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>; 1239 clock-names = "ss-wpe-l7", "ss-wpe-l7pce"; 1240 mediatek,infracfg = <&infracfg_ao>; 1241 #power-domain-cells = <0>; 1242 }; 1243 }; 1244 }; 1245 1246 power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 { 1247 reg = <MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; 1248 mediatek,infracfg = <&infracfg_ao>; 1249 clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; 1250 clock-names = "ss-pextp-fmem"; 1251 #power-domain-cells = <0>; 1252 }; 1253 1254 power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP { 1255 reg = <MT8188_POWER_DOMAIN_CSIRX_TOP>; 1256 clocks = <&topckgen CLK_TOP_SENINF>, 1257 <&topckgen CLK_TOP_SENINF1>; 1258 clock-names = "seninf0", "seninf1"; 1259 #power-domain-cells = <0>; 1260 }; 1261 1262 power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP { 1263 reg = <MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; 1264 #power-domain-cells = <0>; 1265 }; 1266 1267 power-domain@MT8188_POWER_DOMAIN_ADSP_AO { 1268 reg = <MT8188_POWER_DOMAIN_ADSP_AO>; 1269 clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 1270 <&topckgen CLK_TOP_ADSP>; 1271 clock-names = "bus", "main"; 1272 mediatek,infracfg = <&infracfg_ao>; 1273 #address-cells = <1>; 1274 #size-cells = <0>; 1275 #power-domain-cells = <1>; 1276 1277 power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA { 1278 reg = <MT8188_POWER_DOMAIN_ADSP_INFRA>; 1279 mediatek,infracfg = <&infracfg_ao>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 #power-domain-cells = <1>; 1283 1284 power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC { 1285 reg = <MT8188_POWER_DOMAIN_AUDIO_ASRC>; 1286 clocks = <&topckgen CLK_TOP_ASM_H>; 1287 clock-names = "asm"; 1288 mediatek,infracfg = <&infracfg_ao>; 1289 #power-domain-cells = <0>; 1290 }; 1291 1292 power-domain@MT8188_POWER_DOMAIN_AUDIO { 1293 reg = <MT8188_POWER_DOMAIN_AUDIO>; 1294 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 1295 <&topckgen CLK_TOP_AUD_INTBUS>, 1296 <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>; 1297 clock-names = "a1sys", "intbus", "adspck"; 1298 mediatek,infracfg = <&infracfg_ao>; 1299 #power-domain-cells = <0>; 1300 }; 1301 1302 power-domain@MT8188_POWER_DOMAIN_ADSP { 1303 reg = <MT8188_POWER_DOMAIN_ADSP>; 1304 mediatek,infracfg = <&infracfg_ao>; 1305 #power-domain-cells = <0>; 1306 }; 1307 }; 1308 }; 1309 1310 power-domain@MT8188_POWER_DOMAIN_ETHER { 1311 reg = <MT8188_POWER_DOMAIN_ETHER>; 1312 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1313 clock-names = "ethermac"; 1314 mediatek,infracfg = <&infracfg_ao>; 1315 #power-domain-cells = <0>; 1316 }; 1317 }; 1318 }; 1319 1320 watchdog: watchdog@10007000 { 1321 compatible = "mediatek,mt8188-wdt"; 1322 reg = <0 0x10007000 0 0x100>; 1323 mediatek,disable-extrst; 1324 #reset-cells = <1>; 1325 }; 1326 1327 apmixedsys: syscon@1000c000 { 1328 compatible = "mediatek,mt8188-apmixedsys", "syscon"; 1329 reg = <0 0x1000c000 0 0x1000>; 1330 #clock-cells = <1>; 1331 }; 1332 1333 systimer: timer@10017000 { 1334 compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer"; 1335 reg = <0 0x10017000 0 0x1000>; 1336 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1337 clocks = <&clk13m>; 1338 }; 1339 1340 pwrap: pwrap@10024000 { 1341 compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon"; 1342 reg = <0 0x10024000 0 0x1000>; 1343 reg-names = "pwrap"; 1344 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 1345 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 1346 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 1347 clock-names = "spi", "wrap"; 1348 }; 1349 1350 spmi: spmi@10027000 { 1351 compatible = "mediatek,mt8188-spmi", "mediatek,mt8195-spmi"; 1352 reg = <0 0x10027000 0 0xe00>, <0 0x10029000 0 0x100>; 1353 reg-names = "pmif", "spmimst"; 1354 assigned-clocks = <&topckgen CLK_TOP_SPMI_M_MST>; 1355 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 1356 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 1357 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 1358 <&topckgen CLK_TOP_SPMI_M_MST>; 1359 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 1360 }; 1361 1362 infra_iommu: iommu@10315000 { 1363 compatible = "mediatek,mt8188-iommu-infra"; 1364 reg = <0 0x10315000 0 0x1000>; 1365 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>; 1366 #iommu-cells = <1>; 1367 }; 1368 1369 gce0: mailbox@10320000 { 1370 compatible = "mediatek,mt8188-gce"; 1371 reg = <0 0x10320000 0 0x4000>; 1372 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 1373 #mbox-cells = <2>; 1374 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 1375 }; 1376 1377 gce1: mailbox@10330000 { 1378 compatible = "mediatek,mt8188-gce"; 1379 reg = <0 0x10330000 0 0x4000>; 1380 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 1381 #mbox-cells = <2>; 1382 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 1383 }; 1384 1385 scp_cluster: scp@10720000 { 1386 compatible = "mediatek,mt8188-scp-dual"; 1387 reg = <0 0x10720000 0 0xe0000>; 1388 reg-names = "cfg"; 1389 #address-cells = <1>; 1390 #size-cells = <1>; 1391 ranges = <0 0 0x10500000 0x100000>; 1392 status = "disabled"; 1393 1394 scp_c0: scp@0 { 1395 compatible = "mediatek,scp-core"; 1396 reg = <0x0 0xd0000>; 1397 reg-names = "sram"; 1398 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 1399 status = "disabled"; 1400 }; 1401 1402 scp_c1: scp@d0000 { 1403 compatible = "mediatek,scp-core"; 1404 reg = <0xd0000 0x2f000>; 1405 reg-names = "sram"; 1406 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>; 1407 status = "disabled"; 1408 }; 1409 }; 1410 1411 afe: audio-controller@10b10000 { 1412 compatible = "mediatek,mt8188-afe"; 1413 reg = <0 0x10b10000 0 0x10000>; 1414 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>; 1415 assigned-clock-parents = <&topckgen CLK_TOP_APLL1_D4>; 1416 clocks = <&clk26m>, 1417 <&apmixedsys CLK_APMIXED_APLL1>, 1418 <&apmixedsys CLK_APMIXED_APLL2>, 1419 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 1420 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 1421 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 1422 <&topckgen CLK_TOP_APLL12_CK_DIV3>, 1423 <&topckgen CLK_TOP_APLL12_CK_DIV9>, 1424 <&topckgen CLK_TOP_A1SYS_HP>, 1425 <&topckgen CLK_TOP_AUD_INTBUS>, 1426 <&topckgen CLK_TOP_AUDIO_H>, 1427 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 1428 <&topckgen CLK_TOP_DPTX>, 1429 <&topckgen CLK_TOP_I2SO1>, 1430 <&topckgen CLK_TOP_I2SO2>, 1431 <&topckgen CLK_TOP_I2SI1>, 1432 <&topckgen CLK_TOP_I2SI2>, 1433 <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>, 1434 <&topckgen CLK_TOP_APLL1_D4>, 1435 <&topckgen CLK_TOP_APLL2_D4>, 1436 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 1437 <&topckgen CLK_TOP_A2SYS>, 1438 <&topckgen CLK_TOP_AUD_IEC>; 1439 clock-names = "clk26m", 1440 "apll1", 1441 "apll2", 1442 "apll12_div0", 1443 "apll12_div1", 1444 "apll12_div2", 1445 "apll12_div3", 1446 "apll12_div9", 1447 "top_a1sys_hp", 1448 "top_aud_intbus", 1449 "top_audio_h", 1450 "top_audio_local_bus", 1451 "top_dptx", 1452 "top_i2so1", 1453 "top_i2so2", 1454 "top_i2si1", 1455 "top_i2si2", 1456 "adsp_audio_26m", 1457 "apll1_d4", 1458 "apll2_d4", 1459 "apll12_div4", 1460 "top_a2sys", 1461 "top_aud_iec"; 1462 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 1463 power-domains = <&spm MT8188_POWER_DOMAIN_AUDIO>; 1464 resets = <&watchdog MT8188_TOPRGU_AUDIO_SW_RST>; 1465 reset-names = "audiosys"; 1466 mediatek,infracfg = <&infracfg_ao>; 1467 mediatek,topckgen = <&topckgen>; 1468 status = "disabled"; 1469 }; 1470 1471 adsp: adsp@10b80000 { 1472 compatible = "mediatek,mt8188-dsp"; 1473 reg = <0 0x10b80000 0 0x2000>, 1474 <0 0x10d00000 0 0x80000>, 1475 <0 0x10b8b000 0 0x100>, 1476 <0 0x10b8f000 0 0x1000>; 1477 reg-names = "cfg", "sram", "sec", "bus"; 1478 assigned-clocks = <&topckgen CLK_TOP_ADSP>; 1479 clocks = <&topckgen CLK_TOP_ADSP>, 1480 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 1481 clock-names = "audiodsp", "adsp_bus"; 1482 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 1483 mbox-names = "rx", "tx"; 1484 power-domains = <&spm MT8188_POWER_DOMAIN_ADSP>; 1485 status = "disabled"; 1486 }; 1487 1488 adsp_mailbox0: mailbox@10b86100 { 1489 compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox"; 1490 reg = <0 0x10b86100 0 0x1000>; 1491 interrupts = <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH 0>; 1492 #mbox-cells = <0>; 1493 }; 1494 1495 adsp_mailbox1: mailbox@10b87100 { 1496 compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox"; 1497 reg = <0 0x10b87100 0 0x1000>; 1498 interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH 0>; 1499 #mbox-cells = <0>; 1500 }; 1501 1502 adsp_audio26m: clock-controller@10b91100 { 1503 compatible = "mediatek,mt8188-adsp-audio26m"; 1504 reg = <0 0x10b91100 0 0x100>; 1505 #clock-cells = <1>; 1506 }; 1507 1508 uart0: serial@11001100 { 1509 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1510 reg = <0 0x11001100 0 0x100>; 1511 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 1512 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1513 clock-names = "baud", "bus"; 1514 status = "disabled"; 1515 }; 1516 1517 uart1: serial@11001200 { 1518 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1519 reg = <0 0x11001200 0 0x100>; 1520 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1521 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1522 clock-names = "baud", "bus"; 1523 status = "disabled"; 1524 }; 1525 1526 uart2: serial@11001300 { 1527 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1528 reg = <0 0x11001300 0 0x100>; 1529 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1530 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1531 clock-names = "baud", "bus"; 1532 status = "disabled"; 1533 }; 1534 1535 uart3: serial@11001400 { 1536 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1537 reg = <0 0x11001400 0 0x100>; 1538 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 1539 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 1540 clock-names = "baud", "bus"; 1541 status = "disabled"; 1542 }; 1543 1544 auxadc: adc@11002000 { 1545 compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc"; 1546 reg = <0 0x11002000 0 0x1000>; 1547 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1548 clock-names = "main"; 1549 #io-channel-cells = <1>; 1550 status = "disabled"; 1551 }; 1552 1553 pericfg_ao: syscon@11003000 { 1554 compatible = "mediatek,mt8188-pericfg-ao", "syscon"; 1555 reg = <0 0x11003000 0 0x1000>; 1556 #clock-cells = <1>; 1557 }; 1558 1559 spi0: spi@1100a000 { 1560 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 reg = <0 0x1100a000 0 0x1000>; 1564 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1565 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1566 <&topckgen CLK_TOP_SPI>, 1567 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1568 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1569 status = "disabled"; 1570 }; 1571 1572 lvts_ap: thermal-sensor@1100b000 { 1573 compatible = "mediatek,mt8188-lvts-ap"; 1574 reg = <0 0x1100b000 0 0xc00>; 1575 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 0>; 1576 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1577 resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST>; 1578 nvmem-cells = <&lvts_efuse_data1>; 1579 nvmem-cell-names = "lvts-calib-data-1"; 1580 #thermal-sensor-cells = <1>; 1581 }; 1582 1583 disp_pwm0: pwm@1100e000 { 1584 compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm"; 1585 reg = <0 0x1100e000 0 0x1000>; 1586 clocks = <&topckgen CLK_TOP_DISP_PWM0>, 1587 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1588 clock-names = "main", "mm"; 1589 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1590 #pwm-cells = <2>; 1591 status = "disabled"; 1592 }; 1593 1594 disp_pwm1: pwm@1100f000 { 1595 compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm"; 1596 reg = <0 0x1100f000 0 0x1000>; 1597 clocks = <&topckgen CLK_TOP_DISP_PWM1>, 1598 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; 1599 clock-names = "main", "mm"; 1600 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; 1601 #pwm-cells = <2>; 1602 status = "disabled"; 1603 }; 1604 1605 spi1: spi@11010000 { 1606 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1607 #address-cells = <1>; 1608 #size-cells = <0>; 1609 reg = <0 0x11010000 0 0x1000>; 1610 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1611 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1612 <&topckgen CLK_TOP_SPI>, 1613 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1614 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1615 status = "disabled"; 1616 }; 1617 1618 spi2: spi@11012000 { 1619 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 reg = <0 0x11012000 0 0x1000>; 1623 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1624 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1625 <&topckgen CLK_TOP_SPI>, 1626 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1627 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1628 status = "disabled"; 1629 }; 1630 1631 spi3: spi@11013000 { 1632 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 reg = <0 0x11013000 0 0x1000>; 1636 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1637 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1638 <&topckgen CLK_TOP_SPI>, 1639 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1640 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1641 status = "disabled"; 1642 }; 1643 1644 spi4: spi@11018000 { 1645 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 reg = <0 0x11018000 0 0x1000>; 1649 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1650 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1651 <&topckgen CLK_TOP_SPI>, 1652 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1653 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1654 status = "disabled"; 1655 }; 1656 1657 spi5: spi@11019000 { 1658 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 reg = <0 0x11019000 0 0x1000>; 1662 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1663 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1664 <&topckgen CLK_TOP_SPI>, 1665 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1666 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1667 status = "disabled"; 1668 }; 1669 1670 ssusb1: usb@11201000 { 1671 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; 1672 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1673 reg-names = "mac", "ippc"; 1674 ranges = <0 0 0 0x11200000 0 0x3f00>; 1675 #address-cells = <2>; 1676 #size-cells = <2>; 1677 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; 1678 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>; 1679 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1680 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>, 1681 <&topckgen CLK_TOP_SSUSB_TOP_REF>, 1682 <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; 1683 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1684 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1685 wakeup-source; 1686 mediatek,syscon-wakeup = <&pericfg 0x468 2>; 1687 status = "disabled"; 1688 1689 xhci1: usb@0 { 1690 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1691 reg = <0 0 0 0x1000>; 1692 reg-names = "mac"; 1693 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1694 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI>; 1695 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1696 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; 1697 clock-names = "sys_ck"; 1698 status = "disabled"; 1699 }; 1700 }; 1701 1702 eth: ethernet@11021000 { 1703 compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac", 1704 "snps,dwmac-5.10a"; 1705 reg = <0 0x11021000 0 0x4000>; 1706 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1707 interrupt-names = "macirq"; 1708 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1709 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1710 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1711 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1712 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1713 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1714 clock-names = "axi", "apb", "mac_main", "ptp_ref", 1715 "rmii_internal", "mac_cg"; 1716 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1717 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1718 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1719 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1720 <&topckgen CLK_TOP_ETHPLL_D8>, 1721 <&topckgen CLK_TOP_ETHPLL_D10>; 1722 power-domains = <&spm MT8188_POWER_DOMAIN_ETHER>; 1723 mediatek,pericfg = <&infracfg_ao>; 1724 snps,axi-config = <&stmmac_axi_setup>; 1725 snps,mtl-rx-config = <&mtl_rx_setup>; 1726 snps,mtl-tx-config = <&mtl_tx_setup>; 1727 snps,txpbl = <16>; 1728 snps,rxpbl = <16>; 1729 snps,clk-csr = <0>; 1730 status = "disabled"; 1731 1732 eth_mdio: mdio { 1733 compatible = "snps,dwmac-mdio"; 1734 #address-cells = <1>; 1735 #size-cells = <0>; 1736 }; 1737 1738 stmmac_axi_setup: stmmac-axi-config { 1739 snps,blen = <0 0 0 0 16 8 4>; 1740 snps,rd_osr_lmt = <0x7>; 1741 snps,wr_osr_lmt = <0x7>; 1742 }; 1743 1744 mtl_rx_setup: rx-queues-config { 1745 snps,rx-queues-to-use = <4>; 1746 snps,rx-sched-sp; 1747 1748 queue0 { 1749 snps,dcb-algorithm; 1750 snps,map-to-dma-channel = <0x0>; 1751 }; 1752 1753 queue1 { 1754 snps,dcb-algorithm; 1755 snps,map-to-dma-channel = <0x0>; 1756 }; 1757 1758 queue2 { 1759 snps,dcb-algorithm; 1760 snps,map-to-dma-channel = <0x0>; 1761 }; 1762 1763 queue3 { 1764 snps,dcb-algorithm; 1765 snps,map-to-dma-channel = <0x0>; 1766 }; 1767 }; 1768 1769 mtl_tx_setup: tx-queues-config { 1770 snps,tx-queues-to-use = <4>; 1771 snps,tx-sched-wrr; 1772 1773 queue0 { 1774 snps,dcb-algorithm; 1775 snps,priority = <0x0>; 1776 snps,weight = <0x10>; 1777 }; 1778 1779 queue1 { 1780 snps,dcb-algorithm; 1781 snps,priority = <0x1>; 1782 snps,weight = <0x11>; 1783 }; 1784 1785 queue2 { 1786 snps,dcb-algorithm; 1787 snps,priority = <0x2>; 1788 snps,weight = <0x12>; 1789 }; 1790 1791 queue3 { 1792 snps,dcb-algorithm; 1793 snps,priority = <0x3>; 1794 snps,weight = <0x13>; 1795 }; 1796 }; 1797 }; 1798 1799 mmc0: mmc@11230000 { 1800 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1801 reg = <0 0x11230000 0 0x10000>, 1802 <0 0x11f50000 0 0x1000>; 1803 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1804 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1805 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1806 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1807 <&infracfg_ao CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P>; 1808 clock-names = "source", "hclk", "source_cg", "crypto_clk"; 1809 status = "disabled"; 1810 }; 1811 1812 mmc1: mmc@11240000 { 1813 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1814 reg = <0 0x11240000 0 0x1000>, 1815 <0 0x11eb0000 0 0x1000>; 1816 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1817 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1818 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1819 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1820 clock-names = "source", "hclk", "source_cg"; 1821 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1822 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1823 status = "disabled"; 1824 }; 1825 1826 mmc2: mmc@11250000 { 1827 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1828 reg = <0 0x11250000 0 0x1000>, 1829 <0 0x11e60000 0 0x1000>; 1830 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1831 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1832 <&infracfg_ao CLK_INFRA_AO_MSDC2>, 1833 <&infracfg_ao CLK_INFRA_AO_MSDC30_2>; 1834 clock-names = "source", "hclk", "source_cg"; 1835 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1836 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1837 status = "disabled"; 1838 }; 1839 1840 lvts_mcu: thermal-sensor@11278000 { 1841 compatible = "mediatek,mt8188-lvts-mcu"; 1842 reg = <0 0x11278000 0 0x1000>; 1843 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 1844 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1845 resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST>; 1846 nvmem-cells = <&lvts_efuse_data1>; 1847 nvmem-cell-names = "lvts-calib-data-1"; 1848 #thermal-sensor-cells = <1>; 1849 }; 1850 1851 i2c0: i2c@11280000 { 1852 compatible = "mediatek,mt8188-i2c"; 1853 reg = <0 0x11280000 0 0x1000>, 1854 <0 0x10220080 0 0x80>; 1855 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>; 1856 clock-div = <1>; 1857 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0>, 1858 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1859 clock-names = "main", "dma"; 1860 #address-cells = <1>; 1861 #size-cells = <0>; 1862 status = "disabled"; 1863 }; 1864 1865 i2c2: i2c@11281000 { 1866 compatible = "mediatek,mt8188-i2c"; 1867 reg = <0 0x11281000 0 0x1000>, 1868 <0 0x10220180 0 0x80>; 1869 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 1870 clock-div = <1>; 1871 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2>, 1872 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1873 clock-names = "main", "dma"; 1874 #address-cells = <1>; 1875 #size-cells = <0>; 1876 status = "disabled"; 1877 }; 1878 1879 i2c3: i2c@11282000 { 1880 compatible = "mediatek,mt8188-i2c"; 1881 reg = <0 0x11282000 0 0x1000>, 1882 <0 0x10220280 0 0x80>; 1883 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1884 clock-div = <1>; 1885 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3>, 1886 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1887 clock-names = "main", "dma"; 1888 #address-cells = <1>; 1889 #size-cells = <0>; 1890 status = "disabled"; 1891 }; 1892 1893 imp_iic_wrap_c: clock-controller@11283000 { 1894 compatible = "mediatek,mt8188-imp-iic-wrap-c"; 1895 reg = <0 0x11283000 0 0x1000>; 1896 #clock-cells = <1>; 1897 }; 1898 1899 ssusb2: usb@112a1000 { 1900 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; 1901 reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>; 1902 reg-names = "mac", "ippc"; 1903 ranges = <0 0 0 0x112a0000 0 0x3f00>; 1904 #address-cells = <2>; 1905 #size-cells = <2>; 1906 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>; 1907 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>; 1908 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1909 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1910 <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>, 1911 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1912 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1913 phys = <&u2port2 PHY_TYPE_USB2>; 1914 wakeup-source; 1915 mediatek,syscon-wakeup = <&pericfg 0x470 2>; 1916 status = "disabled"; 1917 1918 xhci2: usb@0 { 1919 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1920 reg = <0 0 0 0x1000>; 1921 reg-names = "mac"; 1922 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1923 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1924 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1925 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1926 clock-names = "sys_ck"; 1927 status = "disabled"; 1928 }; 1929 }; 1930 1931 ssusb0: usb@112b1000 { 1932 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; 1933 reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>; 1934 reg-names = "mac", "ippc"; 1935 ranges = <0 0 0 0x112b0000 0 0x3f00>; 1936 #address-cells = <2>; 1937 #size-cells = <2>; 1938 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1939 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1940 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1941 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1942 <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>, 1943 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1944 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1945 phys = <&u2port0 PHY_TYPE_USB2>; 1946 wakeup-source; 1947 mediatek,syscon-wakeup = <&pericfg 0x460 2>; 1948 status = "disabled"; 1949 1950 xhci0: usb@0 { 1951 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1952 reg = <0 0 0 0x1000>; 1953 reg-names = "mac"; 1954 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1955 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>; 1956 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1957 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1958 clock-names = "sys_ck"; 1959 status = "disabled"; 1960 }; 1961 }; 1962 1963 pcie: pcie@112f0000 { 1964 compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie"; 1965 reg = <0 0x112f0000 0 0x2000>; 1966 reg-names = "pcie-mac"; 1967 ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>; 1968 bus-range = <0 0xff>; 1969 device_type = "pci"; 1970 linux,pci-domain = <0>; 1971 #address-cells = <3>; 1972 #size-cells = <2>; 1973 1974 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1975 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1976 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1977 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1978 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1979 <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; 1980 clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k", 1981 "peri_26m", "peri_mem"; 1982 1983 #interrupt-cells = <1>; 1984 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1985 interrupt-map = <0 0 0 1 &pcie_intc 0>, 1986 <0 0 0 2 &pcie_intc 1>, 1987 <0 0 0 3 &pcie_intc 2>, 1988 <0 0 0 4 &pcie_intc 3>; 1989 interrupt-map-mask = <0 0 0 7>; 1990 1991 iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>; 1992 iommu-map-mask = <0>; 1993 1994 phys = <&pcieport PHY_TYPE_PCIE>; 1995 phy-names = "pcie-phy"; 1996 1997 power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; 1998 1999 resets = <&watchdog MT8188_TOPRGU_PCIE_SW_RST>; 2000 reset-names = "mac"; 2001 2002 status = "disabled"; 2003 2004 pcie_intc: interrupt-controller { 2005 #address-cells = <0>; 2006 #interrupt-cells = <1>; 2007 interrupt-controller; 2008 }; 2009 }; 2010 2011 nor_flash: spi@1132c000 { 2012 compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor"; 2013 reg = <0 0x1132c000 0 0x1000>; 2014 clocks = <&topckgen CLK_TOP_SPINOR>, 2015 <&pericfg_ao CLK_PERI_AO_FLASHIFLASHCK>, 2016 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 2017 clock-names = "spi", "sf", "axi"; 2018 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 2019 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 2020 #address-cells = <1>; 2021 #size-cells = <0>; 2022 status = "disabled"; 2023 }; 2024 2025 pciephy: t-phy@11c20700 { 2026 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2027 ranges = <0 0 0x11c20700 0x700>; 2028 #address-cells = <1>; 2029 #size-cells = <1>; 2030 power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; 2031 status = "disabled"; 2032 2033 pcieport: pcie-phy@0 { 2034 reg = <0 0x700>; 2035 clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>; 2036 clock-names = "ref"; 2037 #phy-cells = <1>; 2038 }; 2039 }; 2040 2041 mipi_tx_config0: dsi-phy@11c80000 { 2042 compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; 2043 reg = <0 0x11c80000 0 0x1000>; 2044 clocks = <&clk26m>; 2045 clock-output-names = "mipi_tx0_pll"; 2046 #clock-cells = <0>; 2047 #phy-cells = <0>; 2048 status = "disabled"; 2049 }; 2050 2051 mipi_tx_config1: dsi-phy@11c90000 { 2052 compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; 2053 reg = <0 0x11c90000 0 0x1000>; 2054 clocks = <&clk26m>; 2055 clock-output-names = "mipi_tx0_pll"; 2056 #clock-cells = <0>; 2057 #phy-cells = <0>; 2058 status = "disabled"; 2059 }; 2060 2061 i2c1: i2c@11e00000 { 2062 compatible = "mediatek,mt8188-i2c"; 2063 reg = <0 0x11e00000 0 0x1000>, 2064 <0 0x10220100 0 0x80>; 2065 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 2066 clock-div = <1>; 2067 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1>, 2068 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2069 clock-names = "main", "dma"; 2070 #address-cells = <1>; 2071 #size-cells = <0>; 2072 status = "disabled"; 2073 }; 2074 2075 i2c4: i2c@11e01000 { 2076 compatible = "mediatek,mt8188-i2c"; 2077 reg = <0 0x11e01000 0 0x1000>, 2078 <0 0x10220380 0 0x80>; 2079 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>; 2080 clock-div = <1>; 2081 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4>, 2082 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2083 clock-names = "main", "dma"; 2084 #address-cells = <1>; 2085 #size-cells = <0>; 2086 status = "disabled"; 2087 }; 2088 2089 imp_iic_wrap_w: clock-controller@11e02000 { 2090 compatible = "mediatek,mt8188-imp-iic-wrap-w"; 2091 reg = <0 0x11e02000 0 0x1000>; 2092 #clock-cells = <1>; 2093 }; 2094 2095 u3phy0: t-phy@11e30000 { 2096 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2097 #address-cells = <1>; 2098 #size-cells = <1>; 2099 ranges = <0x0 0x0 0x11e30000 0x1000>; 2100 status = "disabled"; 2101 2102 u2port0: usb-phy@0 { 2103 reg = <0x0 0x700>; 2104 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>, 2105 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 2106 clock-names = "ref", "da_ref"; 2107 #phy-cells = <1>; 2108 }; 2109 }; 2110 2111 u3phy1: t-phy@11e40000 { 2112 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2113 #address-cells = <1>; 2114 #size-cells = <1>; 2115 ranges = <0x0 0x0 0x11e40000 0x1000>; 2116 status = "disabled"; 2117 2118 u2port1: usb-phy@0 { 2119 reg = <0x0 0x700>; 2120 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 2121 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 2122 clock-names = "ref", "da_ref"; 2123 #phy-cells = <1>; 2124 }; 2125 2126 u3port1: usb-phy@700 { 2127 reg = <0x700 0x700>; 2128 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>, 2129 <&clk26m>; 2130 clock-names = "ref", "da_ref"; 2131 #phy-cells = <1>; 2132 }; 2133 }; 2134 2135 u3phy2: t-phy@11e80000 { 2136 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2137 #address-cells = <1>; 2138 #size-cells = <1>; 2139 ranges = <0x0 0x0 0x11e80000 0x1000>; 2140 status = "disabled"; 2141 2142 u2port2: usb-phy@0 { 2143 reg = <0x0 0x700>; 2144 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>, 2145 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 2146 clock-names = "ref", "da_ref"; 2147 #phy-cells = <1>; 2148 }; 2149 }; 2150 2151 i2c5: i2c@11ec0000 { 2152 compatible = "mediatek,mt8188-i2c"; 2153 reg = <0 0x11ec0000 0 0x1000>, 2154 <0 0x10220480 0 0x80>; 2155 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>; 2156 clock-div = <1>; 2157 clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5>, 2158 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2159 clock-names = "main", "dma"; 2160 #address-cells = <1>; 2161 #size-cells = <0>; 2162 status = "disabled"; 2163 }; 2164 2165 i2c6: i2c@11ec1000 { 2166 compatible = "mediatek,mt8188-i2c"; 2167 reg = <0 0x11ec1000 0 0x1000>, 2168 <0 0x10220600 0 0x80>; 2169 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 2170 clock-div = <1>; 2171 clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6>, 2172 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2173 clock-names = "main", "dma"; 2174 #address-cells = <1>; 2175 #size-cells = <0>; 2176 status = "disabled"; 2177 }; 2178 2179 imp_iic_wrap_en: clock-controller@11ec2000 { 2180 compatible = "mediatek,mt8188-imp-iic-wrap-en"; 2181 reg = <0 0x11ec2000 0 0x1000>; 2182 #clock-cells = <1>; 2183 }; 2184 2185 efuse: efuse@11f20000 { 2186 compatible = "mediatek,mt8188-efuse", "mediatek,efuse"; 2187 reg = <0 0x11f20000 0 0x1000>; 2188 #address-cells = <1>; 2189 #size-cells = <1>; 2190 2191 dp_calib_data: dp-calib@1a0 { 2192 reg = <0x1a0 0xc>; 2193 }; 2194 2195 lvts_efuse_data1: lvts1-calib@1ac { 2196 reg = <0x1ac 0x40>; 2197 }; 2198 2199 gpu_speedbin: gpu-speedbin@581 { 2200 reg = <0x581 0x1>; 2201 bits = <0 3>; 2202 }; 2203 2204 socinfo-data1@7a0 { 2205 reg = <0x7a0 0x4>; 2206 }; 2207 2208 socinfo-data2@7e0 { 2209 reg = <0x7e0 0x4>; 2210 }; 2211 }; 2212 2213 gpu: gpu@13000000 { 2214 compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm"; 2215 reg = <0 0x13000000 0 0x4000>; 2216 2217 clocks = <&mfgcfg CLK_MFGCFG_BG3D>; 2218 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, 2219 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>, 2220 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>; 2221 interrupt-names = "job", "mmu", "gpu"; 2222 nvmem-cells = <&gpu_speedbin>; 2223 nvmem-cell-names = "speed-bin"; 2224 operating-points-v2 = <&gpu_opp_table>; 2225 power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>, 2226 <&spm MT8188_POWER_DOMAIN_MFG3>, 2227 <&spm MT8188_POWER_DOMAIN_MFG4>; 2228 power-domain-names = "core0", "core1", "core2"; 2229 #cooling-cells = <2>; 2230 status = "disabled"; 2231 }; 2232 2233 mfgcfg: clock-controller@13fbf000 { 2234 compatible = "mediatek,mt8188-mfgcfg"; 2235 reg = <0 0x13fbf000 0 0x1000>; 2236 #clock-cells = <1>; 2237 }; 2238 2239 vppsys0: syscon@14000000 { 2240 compatible = "mediatek,mt8188-vppsys0", "syscon"; 2241 reg = <0 0x14000000 0 0x1000>; 2242 #clock-cells = <1>; 2243 }; 2244 2245 dma-controller@14001000 { 2246 compatible = "mediatek,mt8188-mdp3-rdma"; 2247 reg = <0 0x14001000 0 0x1000>; 2248 #dma-cells = <1>; 2249 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>; 2250 mboxes = <&gce0 13 CMDQ_THR_PRIO_1>, 2251 <&gce0 14 CMDQ_THR_PRIO_1>, 2252 <&gce0 16 CMDQ_THR_PRIO_1>, 2253 <&gce0 21 CMDQ_THR_PRIO_1>, 2254 <&gce0 22 CMDQ_THR_PRIO_1>; 2255 iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>; 2256 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2257 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; 2258 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>, 2259 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>; 2260 mediatek,scp = <&scp_c0>; 2261 }; 2262 2263 display@14002000 { 2264 compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; 2265 reg = <0 0x14002000 0 0x1000>; 2266 clocks = <&vppsys0 CLK_VPP0_MDP_FG>; 2267 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; 2268 }; 2269 2270 display@14004000 { 2271 compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; 2272 reg = <0 0x14004000 0 0x1000>; 2273 clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; 2274 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; 2275 }; 2276 2277 display@14005000 { 2278 compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; 2279 reg = <0 0x14005000 0 0x1000>; 2280 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>; 2281 clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; 2282 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2283 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; 2284 }; 2285 2286 display@14006000 { 2287 compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2288 reg = <0 0x14006000 0 0x1000>; 2289 clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>; 2290 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; 2291 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>, 2292 <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>; 2293 }; 2294 2295 display@14007000 { 2296 compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; 2297 reg = <0 0x14007000 0 0x1000>; 2298 clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; 2299 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; 2300 }; 2301 2302 display@14008000 { 2303 compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; 2304 reg = <0 0x14008000 0 0x1000>; 2305 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2306 clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; 2307 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2308 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; 2309 }; 2310 2311 display@14009000 { 2312 compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl"; 2313 reg = <0 0x14009000 0 0x1000>; 2314 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2315 clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; 2316 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2317 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; 2318 iommus = <&vpp_iommu M4U_PORT_L4_MDP_OVL>; 2319 }; 2320 2321 display@1400a000 { 2322 compatible = "mediatek,mt8188-mdp3-padding", "mediatek,mt8195-mdp3-padding"; 2323 reg = <0 0x1400a000 0 0x1000>; 2324 clocks = <&vppsys0 CLK_VPP0_PADDING>; 2325 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2326 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; 2327 }; 2328 2329 display@1400b000 { 2330 compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc"; 2331 reg = <0 0x1400b000 0 0x1000>; 2332 clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; 2333 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; 2334 }; 2335 2336 display@1400c000 { 2337 compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2338 reg = <0 0x1400c000 0 0x1000>; 2339 #dma-cells = <1>; 2340 clocks = <&vppsys0 CLK_VPP0_MDP_WROT>; 2341 iommus = <&vpp_iommu M4U_PORT_L4_MDP_WROT>; 2342 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2343 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; 2344 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>, 2345 <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>; 2346 }; 2347 2348 mutex@1400f000 { 2349 compatible = "mediatek,mt8188-vpp-mutex"; 2350 reg = <0 0x1400f000 0 0x1000>; 2351 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; 2352 clocks = <&vppsys0 CLK_VPP0_MUTEX>; 2353 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2354 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; 2355 }; 2356 2357 vpp_smi_common: smi@14012000 { 2358 compatible = "mediatek,mt8188-smi-common-vpp"; 2359 reg = <0 0x14012000 0 0x1000>; 2360 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2361 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>; 2362 clock-names = "apb", "smi"; 2363 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2364 }; 2365 2366 larb4: smi@14013000 { 2367 compatible = "mediatek,mt8188-smi-larb"; 2368 reg = <0 0x14013000 0 0x1000>; 2369 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2370 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 2371 clock-names = "apb", "smi"; 2372 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2373 mediatek,larb-id = <SMI_L4_ID>; 2374 mediatek,smi = <&vpp_smi_common>; 2375 }; 2376 2377 vpp_iommu: iommu@14018000 { 2378 compatible = "mediatek,mt8188-iommu-vpp"; 2379 reg = <0 0x14018000 0 0x5000>; 2380 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 2381 clock-names = "bclk"; 2382 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 2383 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2384 #iommu-cells = <1>; 2385 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb7 &larb23>; 2386 }; 2387 2388 dma-controller@14f09000 { 2389 compatible = "mediatek,mt8188-mdp3-rdma"; 2390 reg = <0 0x14f09000 0 0x1000>; 2391 #dma-cells = <1>; 2392 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; 2393 iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>; 2394 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2395 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; 2396 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>, 2397 <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>; 2398 }; 2399 2400 dma-controller@14f0a000 { 2401 compatible = "mediatek,mt8188-mdp3-rdma"; 2402 reg = <0 0x14f0a000 0 0x1000>; 2403 #dma-cells = <1>; 2404 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; 2405 iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>; 2406 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2407 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; 2408 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>, 2409 <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>; 2410 }; 2411 2412 display@14f0c000 { 2413 compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; 2414 reg = <0 0x14f0c000 0 0x1000>; 2415 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; 2416 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; 2417 }; 2418 2419 display@14f0d000 { 2420 compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; 2421 reg = <0 0x14f0d000 0 0x1000>; 2422 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; 2423 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; 2424 }; 2425 2426 display@14f0f000 { 2427 compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; 2428 reg = <0 0x14f0f000 0 0x1000>; 2429 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; 2430 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; 2431 }; 2432 2433 display@14f10000 { 2434 compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; 2435 reg = <0 0x14f10000 0 0x1000>; 2436 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; 2437 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>; 2438 }; 2439 2440 display@14f12000 { 2441 compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; 2442 reg = <0 0x14f12000 0 0x1000>; 2443 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>; 2444 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; 2445 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2446 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; 2447 }; 2448 2449 display@14f13000 { 2450 compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; 2451 reg = <0 0x14f13000 0 0x1000>; 2452 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>; 2453 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; 2454 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2455 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; 2456 }; 2457 2458 display@14f15000 { 2459 compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2460 reg = <0 0x14f15000 0 0x1000>; 2461 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; 2462 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; 2463 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>, 2464 <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>; 2465 }; 2466 2467 display@14f16000 { 2468 compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2469 reg = <0 0x14f16000 0 0x1000>; 2470 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; 2471 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; 2472 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>, 2473 <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>; 2474 }; 2475 2476 display@14f18000 { 2477 compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; 2478 reg = <0 0x14f18000 0 0x1000>; 2479 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; 2480 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; 2481 }; 2482 2483 display@14f19000 { 2484 compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; 2485 reg = <0 0x14f19000 0 0x1000>; 2486 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; 2487 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; 2488 }; 2489 2490 display@14f1a000 { 2491 compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge"; 2492 reg = <0 0x14f1a000 0 0x1000>; 2493 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; 2494 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2495 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; 2496 }; 2497 2498 display@14f1b000 { 2499 compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge"; 2500 reg = <0 0x14f1b000 0 0x1000>; 2501 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; 2502 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2503 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; 2504 }; 2505 2506 display@14f1d000 { 2507 compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; 2508 reg = <0 0x14f1d000 0 0x1000>; 2509 interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>; 2510 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; 2511 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2512 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; 2513 }; 2514 2515 display@14f1e000 { 2516 compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; 2517 reg = <0 0x14f1e000 0 0x1000>; 2518 interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>; 2519 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; 2520 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2521 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; 2522 }; 2523 2524 display@14f21000 { 2525 compatible = "mediatek,mt8188-mdp3-padding", 2526 "mediatek,mt8195-mdp3-padding"; 2527 reg = <0 0x14f21000 0 0x1000>; 2528 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; 2529 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2530 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; 2531 }; 2532 2533 display@14f22000 { 2534 compatible = "mediatek,mt8188-mdp3-padding", 2535 "mediatek,mt8195-mdp3-padding"; 2536 reg = <0 0x14f22000 0 0x1000>; 2537 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; 2538 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2539 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; 2540 }; 2541 2542 display@14f24000 { 2543 compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2544 reg = <0 0x14f24000 0 0x1000>; 2545 #dma-cells = <1>; 2546 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; 2547 iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>; 2548 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2549 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; 2550 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>, 2551 <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>; 2552 }; 2553 2554 display@14f25000 { 2555 compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2556 reg = <0 0x14f25000 0 0x1000>; 2557 #dma-cells = <1>; 2558 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; 2559 iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>; 2560 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2561 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; 2562 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>, 2563 <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>; 2564 }; 2565 2566 wpesys: clock-controller@14e00000 { 2567 compatible = "mediatek,mt8188-wpesys"; 2568 reg = <0 0x14e00000 0 0x1000>; 2569 #clock-cells = <1>; 2570 }; 2571 2572 wpesys_vpp0: clock-controller@14e02000 { 2573 compatible = "mediatek,mt8188-wpesys-vpp0"; 2574 reg = <0 0x14e02000 0 0x1000>; 2575 #clock-cells = <1>; 2576 }; 2577 2578 larb7: smi@14e04000 { 2579 compatible = "mediatek,mt8188-smi-larb"; 2580 reg = <0 0x14e04000 0 0x1000>; 2581 clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, 2582 <&wpesys CLK_WPE_TOP_SMI_LARB7>; 2583 clock-names = "apb", "smi"; 2584 power-domains = <&spm MT8188_POWER_DOMAIN_WPE>; 2585 mediatek,larb-id = <SMI_L7_ID>; 2586 mediatek,smi = <&vpp_smi_common>; 2587 }; 2588 2589 vppsys1: syscon@14f00000 { 2590 compatible = "mediatek,mt8188-vppsys1", "syscon"; 2591 reg = <0 0x14f00000 0 0x1000>; 2592 #clock-cells = <1>; 2593 }; 2594 2595 mutex@14f01000 { 2596 compatible = "mediatek,mt8188-vpp-mutex"; 2597 reg = <0 0x14f01000 0 0x1000>; 2598 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 2599 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; 2600 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2601 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; 2602 }; 2603 2604 larb5: smi@14f02000 { 2605 compatible = "mediatek,mt8188-smi-larb"; 2606 reg = <0 0x14f02000 0 0x1000>; 2607 clocks = <&vppsys1 CLK_VPP1_GALS5>, 2608 <&vppsys1 CLK_VPP1_LARB5>; 2609 clock-names = "apb", "smi"; 2610 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2611 mediatek,larb-id = <SMI_L5_ID>; 2612 mediatek,smi = <&vdo_smi_common>; 2613 }; 2614 2615 larb6: smi@14f03000 { 2616 compatible = "mediatek,mt8188-smi-larb"; 2617 reg = <0 0x14f03000 0 0x1000>; 2618 clocks = <&vppsys1 CLK_VPP1_GALS6>, 2619 <&vppsys1 CLK_VPP1_LARB6>; 2620 clock-names = "apb", "smi"; 2621 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2622 mediatek,larb-id = <SMI_L6_ID>; 2623 mediatek,smi = <&vpp_smi_common>; 2624 }; 2625 2626 imgsys: clock-controller@15000000 { 2627 compatible = "mediatek,mt8188-imgsys"; 2628 reg = <0 0x15000000 0 0x1000>; 2629 #clock-cells = <1>; 2630 }; 2631 2632 imgsys1_dip_top: clock-controller@15110000 { 2633 compatible = "mediatek,mt8188-imgsys1-dip-top"; 2634 reg = <0 0x15110000 0 0x1000>; 2635 #clock-cells = <1>; 2636 #reset-cells = <1>; 2637 }; 2638 2639 imgsys1_dip_nr: clock-controller@15130000 { 2640 compatible = "mediatek,mt8188-imgsys1-dip-nr"; 2641 reg = <0 0x15130000 0 0x1000>; 2642 #clock-cells = <1>; 2643 #reset-cells = <1>; 2644 }; 2645 2646 imgsys_wpe1: clock-controller@15220000 { 2647 compatible = "mediatek,mt8188-imgsys-wpe1"; 2648 reg = <0 0x15220000 0 0x1000>; 2649 #clock-cells = <1>; 2650 #reset-cells = <1>; 2651 }; 2652 2653 ipesys: clock-controller@15330000 { 2654 compatible = "mediatek,mt8188-ipesys"; 2655 reg = <0 0x15330000 0 0x1000>; 2656 #clock-cells = <1>; 2657 #reset-cells = <1>; 2658 }; 2659 2660 imgsys_wpe2: clock-controller@15520000 { 2661 compatible = "mediatek,mt8188-imgsys-wpe2"; 2662 reg = <0 0x15520000 0 0x1000>; 2663 #clock-cells = <1>; 2664 #reset-cells = <1>; 2665 }; 2666 2667 imgsys_wpe3: clock-controller@15620000 { 2668 compatible = "mediatek,mt8188-imgsys-wpe3"; 2669 reg = <0 0x15620000 0 0x1000>; 2670 #clock-cells = <1>; 2671 #reset-cells = <1>; 2672 }; 2673 2674 camsys: clock-controller@16000000 { 2675 compatible = "mediatek,mt8188-camsys"; 2676 reg = <0 0x16000000 0 0x1000>; 2677 #clock-cells = <1>; 2678 }; 2679 2680 camsys_rawa: clock-controller@1604f000 { 2681 compatible = "mediatek,mt8188-camsys-rawa"; 2682 reg = <0 0x1604f000 0 0x1000>; 2683 #clock-cells = <1>; 2684 #reset-cells = <1>; 2685 }; 2686 2687 camsys_yuva: clock-controller@1606f000 { 2688 compatible = "mediatek,mt8188-camsys-yuva"; 2689 reg = <0 0x1606f000 0 0x1000>; 2690 #clock-cells = <1>; 2691 #reset-cells = <1>; 2692 }; 2693 2694 camsys_rawb: clock-controller@1608f000 { 2695 compatible = "mediatek,mt8188-camsys-rawb"; 2696 reg = <0 0x1608f000 0 0x1000>; 2697 #clock-cells = <1>; 2698 #reset-cells = <1>; 2699 }; 2700 2701 camsys_yuvb: clock-controller@160af000 { 2702 compatible = "mediatek,mt8188-camsys-yuvb"; 2703 reg = <0 0x160af000 0 0x1000>; 2704 #clock-cells = <1>; 2705 #reset-cells = <1>; 2706 }; 2707 2708 ccusys: clock-controller@17200000 { 2709 compatible = "mediatek,mt8188-ccusys"; 2710 reg = <0 0x17200000 0 0x1000>; 2711 #clock-cells = <1>; 2712 }; 2713 2714 video_decoder: video-decoder@18000000 { 2715 compatible = "mediatek,mt8188-vcodec-dec"; 2716 reg = <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>; 2717 ranges = <0 0 0 0x18000000 0 0x26000>; 2718 iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>; 2719 #address-cells = <2>; 2720 #size-cells = <2>; 2721 mediatek,scp = <&scp_c0>; 2722 2723 video-codec@10000 { 2724 compatible = "mediatek,mtk-vcodec-lat"; 2725 reg = <0 0x10000 0 0x800>; 2726 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2727 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 2728 clocks = <&topckgen CLK_TOP_VDEC>, 2729 <&vdecsys_soc CLK_VDEC1_SOC_VDEC>, 2730 <&vdecsys_soc CLK_VDEC1_SOC_LAT>, 2731 <&topckgen CLK_TOP_UNIVPLL_D6>; 2732 clock-names = "sel", "vdec", "lat", "top"; 2733 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; 2734 iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT>, 2735 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT>, 2736 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT>, 2737 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT>, 2738 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT>, 2739 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT>, 2740 <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>, 2741 <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C>, 2742 <&vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C>; 2743 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; 2744 }; 2745 2746 video-codec@25000 { 2747 compatible = "mediatek,mtk-vcodec-core"; 2748 reg = <0 0x25000 0 0x1000>; 2749 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2750 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 2751 clocks = <&topckgen CLK_TOP_VDEC>, 2752 <&vdecsys CLK_VDEC2_VDEC>, 2753 <&vdecsys CLK_VDEC2_LAT>, 2754 <&topckgen CLK_TOP_UNIVPLL_D6>; 2755 clock-names = "sel", "vdec", "lat", "top"; 2756 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; 2757 iommus = <&vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT>, 2758 <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT>, 2759 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT>, 2760 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT>, 2761 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT>, 2762 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT>, 2763 <&vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT>, 2764 <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT>, 2765 <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT>, 2766 <&vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT>, 2767 <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C>; 2768 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>; 2769 }; 2770 }; 2771 2772 larb23: smi@1800d000 { 2773 compatible = "mediatek,mt8188-smi-larb"; 2774 reg = <0 0x1800d000 0 0x1000>; 2775 clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>, 2776 <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; 2777 clock-names = "apb", "smi"; 2778 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; 2779 mediatek,larb-id = <SMI_L23_ID>; 2780 mediatek,smi = <&vpp_smi_common>; 2781 }; 2782 2783 vdecsys_soc: clock-controller@1800f000 { 2784 compatible = "mediatek,mt8188-vdecsys-soc"; 2785 reg = <0 0x1800f000 0 0x1000>; 2786 #clock-cells = <1>; 2787 }; 2788 2789 larb21: smi@1802e000 { 2790 compatible = "mediatek,mt8188-smi-larb"; 2791 reg = <0 0x1802e000 0 0x1000>; 2792 clocks = <&vdecsys CLK_VDEC2_LARB1>, 2793 <&vdecsys CLK_VDEC2_LARB1>; 2794 clock-names = "apb", "smi"; 2795 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>; 2796 mediatek,larb-id = <SMI_L21_ID>; 2797 mediatek,smi = <&vdo_smi_common>; 2798 }; 2799 2800 vdecsys: clock-controller@1802f000 { 2801 compatible = "mediatek,mt8188-vdecsys"; 2802 reg = <0 0x1802f000 0 0x1000>; 2803 #clock-cells = <1>; 2804 }; 2805 2806 vencsys: clock-controller@1a000000 { 2807 compatible = "mediatek,mt8188-vencsys"; 2808 reg = <0 0x1a000000 0 0x1000>; 2809 #clock-cells = <1>; 2810 }; 2811 2812 larb19: smi@1a010000 { 2813 compatible = "mediatek,mt8188-smi-larb"; 2814 reg = <0 0x1a010000 0 0x1000>; 2815 clocks = <&vencsys CLK_VENC1_VENC>, 2816 <&vencsys CLK_VENC1_VENC>; 2817 clock-names = "apb", "smi"; 2818 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; 2819 mediatek,larb-id = <SMI_L19_ID>; 2820 mediatek,smi = <&vdo_smi_common>; 2821 }; 2822 2823 video_encoder: video-encoder@1a020000 { 2824 compatible = "mediatek,mt8188-vcodec-enc"; 2825 reg = <0 0x1a020000 0 0x10000>; 2826 #address-cells = <2>; 2827 #size-cells = <2>; 2828 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2829 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2830 clocks = <&vencsys CLK_VENC1_VENC>; 2831 clock-names = "venc_sel"; 2832 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 2833 iommus = <&vdo_iommu M4U_PORT_L19_VENC_RCPU>, 2834 <&vdo_iommu M4U_PORT_L19_VENC_REC>, 2835 <&vdo_iommu M4U_PORT_L19_VENC_BSDMA>, 2836 <&vdo_iommu M4U_PORT_L19_VENC_SV_COMV>, 2837 <&vdo_iommu M4U_PORT_L19_VENC_RD_COMV>, 2838 <&vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA>, 2839 <&vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA>, 2840 <&vdo_iommu M4U_PORT_L19_VENC_REF_LUMA>, 2841 <&vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA>, 2842 <&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>, 2843 <&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>; 2844 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; 2845 mediatek,scp = <&scp_c0>; 2846 }; 2847 2848 jpeg_encoder: jpeg-encoder@1a030000 { 2849 compatible = "mediatek,mt8188-jpgenc", "mediatek,mtk-jpgenc"; 2850 reg = <0 0x1a030000 0 0x10000>; 2851 clocks = <&vencsys CLK_VENC1_JPGENC>; 2852 clock-names = "jpgenc"; 2853 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 2854 iommus = <&vdo_iommu M4U_PORT_L19_JPGENC_Y_RDMA>, 2855 <&vdo_iommu M4U_PORT_L19_JPGENC_C_RDMA>, 2856 <&vdo_iommu M4U_PORT_L19_JPGENC_Q_TABLE>, 2857 <&vdo_iommu M4U_PORT_L19_JPGENC_BSDMA>; 2858 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; 2859 }; 2860 2861 jpeg_decoder: jpeg-decoder@1a040000 { 2862 compatible = "mediatek,mt8188-jpgdec", "mediatek,mt2701-jpgdec"; 2863 reg = <0 0x1a040000 0 0x10000>; 2864 clocks = <&vencsys CLK_VENC1_LARB>, 2865 <&vencsys CLK_VENC1_JPGDEC>; 2866 clock-names = "jpgdec-smi", "jpgdec"; 2867 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 2868 iommus = <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_0>, 2869 <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_0>, 2870 <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_1>, 2871 <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_1>, 2872 <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_1>, 2873 <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_0>; 2874 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; 2875 }; 2876 2877 ovl0: ovl@1c000000 { 2878 compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8195-disp-ovl"; 2879 reg = <0 0x1c000000 0 0x1000>; 2880 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 2881 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 2882 iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>; 2883 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2884 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 2885 2886 ports { 2887 #address-cells = <1>; 2888 #size-cells = <0>; 2889 2890 port@0 { 2891 reg = <0>; 2892 ovl0_in: endpoint { }; 2893 }; 2894 2895 port@1 { 2896 reg = <1>; 2897 ovl0_out: endpoint { 2898 remote-endpoint = <&rdma0_in>; 2899 }; 2900 }; 2901 }; 2902 }; 2903 2904 rdma0: rdma@1c002000 { 2905 compatible = "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma"; 2906 reg = <0 0x1c002000 0 0x1000>; 2907 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 2908 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 2909 iommus = <&vpp_iommu M4U_PORT_L1_DISP_RDMA0>; 2910 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2911 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 2912 2913 ports { 2914 #address-cells = <1>; 2915 #size-cells = <0>; 2916 2917 port@0 { 2918 reg = <0>; 2919 rdma0_in: endpoint { 2920 remote-endpoint = <&ovl0_out>; 2921 }; 2922 }; 2923 2924 port@1 { 2925 reg = <1>; 2926 rdma0_out: endpoint { 2927 remote-endpoint = <&color0_in>; 2928 }; 2929 }; 2930 }; 2931 }; 2932 2933 color0: color@1c003000 { 2934 compatible = "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-color"; 2935 reg = <0 0x1c003000 0 0x1000>; 2936 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 2937 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 2938 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2939 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 2940 2941 ports { 2942 #address-cells = <1>; 2943 #size-cells = <0>; 2944 2945 port@0 { 2946 reg = <0>; 2947 color0_in: endpoint { 2948 remote-endpoint = <&rdma0_out>; 2949 }; 2950 }; 2951 2952 port@1 { 2953 reg = <1>; 2954 color0_out: endpoint { 2955 remote-endpoint = <&ccorr0_in>; 2956 }; 2957 }; 2958 }; 2959 }; 2960 2961 ccorr0: ccorr@1c004000 { 2962 compatible = "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 2963 reg = <0 0x1c004000 0 0x1000>; 2964 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 2965 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 2966 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2967 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 2968 2969 ports { 2970 #address-cells = <1>; 2971 #size-cells = <0>; 2972 2973 port@0 { 2974 reg = <0>; 2975 ccorr0_in: endpoint { 2976 remote-endpoint = <&color0_out>; 2977 }; 2978 }; 2979 2980 port@1 { 2981 reg = <1>; 2982 ccorr0_out: endpoint { 2983 remote-endpoint = <&aal0_in>; 2984 }; 2985 }; 2986 }; 2987 }; 2988 2989 aal0: aal@1c005000 { 2990 compatible = "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal"; 2991 reg = <0 0x1c005000 0 0x1000>; 2992 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 2993 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 2994 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2995 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 2996 2997 ports { 2998 #address-cells = <1>; 2999 #size-cells = <0>; 3000 3001 port@0 { 3002 reg = <0>; 3003 aal0_in: endpoint { 3004 remote-endpoint = <&ccorr0_out>; 3005 }; 3006 }; 3007 3008 port@1 { 3009 reg = <1>; 3010 aal0_out: endpoint { 3011 remote-endpoint = <&gamma0_in>; 3012 }; 3013 }; 3014 }; 3015 }; 3016 3017 gamma0: gamma@1c006000 { 3018 compatible = "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamma"; 3019 reg = <0 0x1c006000 0 0x1000>; 3020 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 3021 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 3022 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3023 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 3024 3025 ports { 3026 #address-cells = <1>; 3027 #size-cells = <0>; 3028 3029 port@0 { 3030 reg = <0>; 3031 gamma0_in: endpoint { 3032 remote-endpoint = <&aal0_out>; 3033 }; 3034 }; 3035 3036 port@1 { 3037 reg = <1>; 3038 gamma0_out: endpoint { }; 3039 }; 3040 }; 3041 }; 3042 3043 dither0: dither@1c007000 { 3044 compatible = "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dither"; 3045 reg = <0 0x1c007000 0 0x1000>; 3046 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 3047 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 3048 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3049 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 3050 3051 ports { 3052 #address-cells = <1>; 3053 #size-cells = <0>; 3054 3055 port@0 { 3056 reg = <0>; 3057 dither0_in: endpoint { }; 3058 }; 3059 3060 port@1 { 3061 reg = <1>; 3062 dither0_out: endpoint { }; 3063 }; 3064 }; 3065 }; 3066 3067 disp_dsi0: dsi@1c008000 { 3068 compatible = "mediatek,mt8188-dsi"; 3069 reg = <0 0x1c008000 0 0x1000>; 3070 clocks = <&vdosys0 CLK_VDO0_DSI0>, 3071 <&vdosys0 CLK_VDO0_DSI0_DSI>, 3072 <&mipi_tx_config0>; 3073 clock-names = "engine", "digital", "hs"; 3074 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 3075 phys = <&mipi_tx_config0>; 3076 phy-names = "dphy"; 3077 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3078 resets = <&vdosys0 MT8188_VDO0_RST_DSI0>; 3079 status = "disabled"; 3080 }; 3081 3082 dsc0: dsc@1c009000 { 3083 compatible = "mediatek,mt8188-disp-dsc", "mediatek,mt8195-disp-dsc"; 3084 reg = <0 0x1c009000 0 0x1000>; 3085 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 3086 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 3087 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3088 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 3089 }; 3090 3091 disp_dsi1: dsi@1c012000 { 3092 compatible = "mediatek,mt8188-dsi"; 3093 reg = <0 0x1c012000 0 0x1000>; 3094 clocks = <&vdosys0 CLK_VDO0_DSI1>, 3095 <&vdosys0 CLK_VDO0_DSI1_DSI>, 3096 <&mipi_tx_config1>; 3097 clock-names = "engine", "digital", "hs"; 3098 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 3099 phys = <&mipi_tx_config1>; 3100 phy-names = "dphy"; 3101 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3102 resets = <&vdosys0 MT8188_VDO0_RST_DSI1>; 3103 status = "disabled"; 3104 }; 3105 3106 merge0: merge0@1c014000 { 3107 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3108 reg = <0 0x1c014000 0 0x1000>; 3109 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>, 3110 <&vdosys1 CLK_VDO1_MERGE_VDO1_DL_ASYNC>; 3111 clock-names = "merge", "merge_async"; 3112 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 3113 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3114 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 3115 }; 3116 3117 dp_intf0: dp-intf@1c015000 { 3118 compatible = "mediatek,mt8188-dp-intf"; 3119 reg = <0 0x1c015000 0 0x1000>; 3120 clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 3121 <&vdosys0 CLK_VDO0_DP_INTF0>, 3122 <&apmixedsys CLK_APMIXED_TVDPLL1>; 3123 clock-names = "pixel", "engine", "pll"; 3124 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 3125 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3126 status = "disabled"; 3127 }; 3128 3129 mutex0: mutex@1c016000 { 3130 compatible = "mediatek,mt8188-disp-mutex"; 3131 reg = <0 0x1c016000 0 0x1000>; 3132 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 3133 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 3134 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3135 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; 3136 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 3137 }; 3138 3139 postmask0: postmask@1c01a000 { 3140 compatible = "mediatek,mt8188-disp-postmask", 3141 "mediatek,mt8192-disp-postmask"; 3142 reg = <0 0x1c01a000 0 0x1000>; 3143 clocks = <&vdosys0 CLK_VDO0_DISP_POSTMASK0>; 3144 interrupts = <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>; 3145 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3146 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; 3147 3148 ports { 3149 #address-cells = <1>; 3150 #size-cells = <0>; 3151 3152 port@0 { 3153 reg = <0>; 3154 postmask0_in: endpoint { }; 3155 }; 3156 3157 port@1 { 3158 reg = <1>; 3159 postmask0_out: endpoint { }; 3160 }; 3161 }; 3162 }; 3163 3164 vdosys0: syscon@1c01d000 { 3165 compatible = "mediatek,mt8188-vdosys0", "syscon"; 3166 reg = <0 0x1c01d000 0 0x1000>; 3167 #clock-cells = <1>; 3168 #reset-cells = <1>; 3169 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 3170 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>; 3171 }; 3172 3173 larb0: smi@1c022000 { 3174 compatible = "mediatek,mt8188-smi-larb"; 3175 reg = <0 0x1c022000 0 0x1000>; 3176 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3177 <&vdosys0 CLK_VDO0_SMI_LARB>; 3178 clock-names = "apb", "smi"; 3179 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3180 mediatek,larb-id = <SMI_L0_ID>; 3181 mediatek,smi = <&vdo_smi_common>; 3182 }; 3183 3184 larb1: smi@1c023000 { 3185 compatible = "mediatek,mt8188-smi-larb"; 3186 reg = <0 0x1c023000 0 0x1000>; 3187 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3188 <&vdosys0 CLK_VDO0_SMI_LARB>; 3189 clock-names = "apb", "smi"; 3190 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3191 mediatek,larb-id = <SMI_L1_ID>; 3192 mediatek,smi = <&vpp_smi_common>; 3193 }; 3194 3195 vdo_smi_common: smi@1c024000 { 3196 compatible = "mediatek,mt8188-smi-common-vdo"; 3197 reg = <0 0x1c024000 0 0x1000>; 3198 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 3199 <&vdosys0 CLK_VDO0_SMI_GALS>; 3200 clock-names = "apb", "smi"; 3201 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3202 }; 3203 3204 vdo_iommu: iommu@1c028000 { 3205 compatible = "mediatek,mt8188-iommu-vdo"; 3206 reg = <0 0x1c028000 0 0x5000>; 3207 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 3208 clock-names = "bclk"; 3209 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>; 3210 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3211 #iommu-cells = <1>; 3212 mediatek,larbs = <&larb0 &larb2 &larb5 &larb19 &larb21>; 3213 }; 3214 3215 vdosys1: syscon@1c100000 { 3216 compatible = "mediatek,mt8188-vdosys1", "syscon"; 3217 reg = <0 0x1c100000 0 0x1000>; 3218 #clock-cells = <1>; 3219 #reset-cells = <1>; 3220 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 3221 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>; 3222 }; 3223 3224 mutex1: mutex@1c101000 { 3225 compatible = "mediatek,mt8188-disp-mutex"; 3226 reg = <0 0x1c101000 0 0x1000>; 3227 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; 3228 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; 3229 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3230 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; 3231 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; 3232 }; 3233 3234 larb2: smi@1c102000 { 3235 compatible = "mediatek,mt8188-smi-larb"; 3236 reg = <0 0x1c102000 0 0x1000>; 3237 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 3238 <&vdosys1 CLK_VDO1_SMI_LARB2>; 3239 clock-names = "apb", "smi"; 3240 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3241 mediatek,larb-id = <SMI_L2_ID>; 3242 mediatek,smi = <&vdo_smi_common>; 3243 }; 3244 3245 larb3: smi@1c103000 { 3246 compatible = "mediatek,mt8188-smi-larb"; 3247 reg = <0 0x1c103000 0 0x1000>; 3248 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 3249 <&vdosys1 CLK_VDO1_SMI_LARB3>; 3250 clock-names = "apb", "smi"; 3251 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3252 mediatek,larb-id = <SMI_L3_ID>; 3253 mediatek,smi = <&vpp_smi_common>; 3254 }; 3255 3256 vdo1_rdma0: rdma@1c104000 { 3257 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3258 reg = <0 0x1c104000 0 0x1000>; 3259 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 3260 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 3261 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA0>; 3262 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3263 #dma-cells = <1>; 3264 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 3265 }; 3266 3267 vdo1_rdma1: rdma@1c105000 { 3268 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3269 reg = <0 0x1c105000 0 0x1000>; 3270 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; 3271 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; 3272 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA1>; 3273 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3274 #dma-cells = <1>; 3275 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; 3276 }; 3277 3278 vdo1_rdma2: rdma@1c106000 { 3279 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3280 reg = <0 0x1c106000 0 0x1000>; 3281 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; 3282 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; 3283 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA2>; 3284 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3285 #dma-cells = <1>; 3286 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; 3287 }; 3288 3289 vdo1_rdma3: rdma@1c107000 { 3290 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3291 reg = <0 0x1c107000 0 0x1000>; 3292 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; 3293 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; 3294 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA3>; 3295 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3296 #dma-cells = <1>; 3297 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; 3298 }; 3299 3300 vdo1_rdma4: rdma@1c108000 { 3301 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3302 reg = <0 0x1c108000 0 0x1000>; 3303 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; 3304 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; 3305 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA4>; 3306 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3307 #dma-cells = <1>; 3308 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; 3309 }; 3310 3311 vdo1_rdma5: rdma@1c109000 { 3312 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3313 reg = <0 0x1c109000 0 0x1000>; 3314 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; 3315 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; 3316 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA5>; 3317 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3318 #dma-cells = <1>; 3319 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; 3320 }; 3321 3322 vdo1_rdma6: rdma@1c10a000 { 3323 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3324 reg = <0 0x1c10a000 0 0x1000>; 3325 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; 3326 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; 3327 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA6>; 3328 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3329 #dma-cells = <1>; 3330 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; 3331 }; 3332 3333 vdo1_rdma7: rdma@1c10b000 { 3334 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3335 reg = <0 0x1c10b000 0 0x1000>; 3336 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; 3337 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; 3338 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA7>; 3339 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3340 #dma-cells = <1>; 3341 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; 3342 }; 3343 3344 merge1: merge@1c10c000 { 3345 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3346 reg = <0 0x1c10c000 0 0x1000>; 3347 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, 3348 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; 3349 clock-names = "merge", "merge_async"; 3350 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 3351 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3352 resets = <&vdosys1 MT8188_VDO1_RST_MERGE0_DL_ASYNC>; 3353 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; 3354 mediatek,merge-mute; 3355 }; 3356 3357 merge2: merge@1c10d000 { 3358 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3359 reg = <0 0x1c10d000 0 0x1000>; 3360 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, 3361 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; 3362 clock-names = "merge", "merge_async"; 3363 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; 3364 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3365 resets = <&vdosys1 MT8188_VDO1_RST_MERGE1_DL_ASYNC>; 3366 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; 3367 mediatek,merge-mute; 3368 }; 3369 3370 merge3: merge@1c10e000 { 3371 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3372 reg = <0 0x1c10e000 0 0x1000>; 3373 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, 3374 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; 3375 clock-names = "merge", "merge_async"; 3376 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; 3377 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3378 resets = <&vdosys1 MT8188_VDO1_RST_MERGE2_DL_ASYNC>; 3379 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; 3380 mediatek,merge-mute; 3381 }; 3382 3383 merge4: merge@1c10f000 { 3384 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3385 reg = <0 0x1c10f000 0 0x1000>; 3386 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, 3387 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; 3388 clock-names = "merge", "merge_async"; 3389 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; 3390 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3391 resets = <&vdosys1 MT8188_VDO1_RST_MERGE3_DL_ASYNC>; 3392 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; 3393 mediatek,merge-mute; 3394 }; 3395 3396 merge5: merge@1c110000 { 3397 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3398 reg = <0 0x1c110000 0 0x1000>; 3399 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, 3400 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; 3401 clock-names = "merge", "merge_async"; 3402 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; 3403 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3404 resets = <&vdosys1 MT8188_VDO1_RST_MERGE4_DL_ASYNC>; 3405 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; 3406 mediatek,merge-fifo-en; 3407 }; 3408 3409 dp_intf1: dp-intf@1c113000 { 3410 compatible = "mediatek,mt8188-dp-intf"; 3411 reg = <0 0x1c113000 0 0x1000>; 3412 clocks = <&vdosys1 CLK_VDO1_DPINTF>, 3413 <&vdosys1 CLK_VDO1_DP_INTF0_MMCK>, 3414 <&apmixedsys CLK_APMIXED_TVDPLL2>; 3415 clock-names = "pixel", "engine", "pll"; 3416 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 3417 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3418 status = "disabled"; 3419 }; 3420 3421 ethdr0: ethdr@1c114000 { 3422 compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr"; 3423 reg = <0 0x1c114000 0 0x1000>, 3424 <0 0x1c115000 0 0x1000>, 3425 <0 0x1c117000 0 0x1000>, 3426 <0 0x1c119000 0 0x1000>, 3427 <0 0x1c11a000 0 0x1000>, 3428 <0 0x1c11b000 0 0x1000>, 3429 <0 0x1c11c000 0 0x1000>; 3430 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3431 "vdo_be", "adl_ds"; 3432 3433 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 3434 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 3435 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 3436 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 3437 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 3438 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 3439 <&vdosys1 CLK_VDO1_26M_SLOW>, 3440 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 3441 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 3442 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 3443 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 3444 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 3445 <&topckgen CLK_TOP_ETHDR>; 3446 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3447 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 3448 "gfx_fe0_async", "gfx_fe1_async", "vdo_be_async", "ethdr_top"; 3449 3450 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH 0>; 3451 iommus = <&vpp_iommu M4U_PORT_L3_HDR_DS_SMI>, 3452 <&vpp_iommu M4U_PORT_L3_HDR_ADL_SMI>; 3453 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3454 resets = <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC>, 3455 <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC>, 3456 <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC>, 3457 <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC>, 3458 <&vdosys1 MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC>; 3459 3460 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 3461 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 3462 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 3463 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 3464 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 3465 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 3466 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 3467 }; 3468 3469 padding0: padding@1c11d000 { 3470 compatible = "mediatek,mt8188-disp-padding"; 3471 reg = <0 0x1c11d000 0 0x1000>; 3472 clocks = <&vdosys1 CLK_VDO1_PADDING0>; 3473 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3474 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; 3475 }; 3476 3477 padding1: padding@1c11e000 { 3478 compatible = "mediatek,mt8188-disp-padding"; 3479 reg = <0 0x1c11e000 0 0x1000>; 3480 clocks = <&vdosys1 CLK_VDO1_PADDING1>; 3481 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3482 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>; 3483 }; 3484 3485 padding2: padding@1c11f000 { 3486 compatible = "mediatek,mt8188-disp-padding"; 3487 reg = <0 0x1c11f000 0 0x1000>; 3488 clocks = <&vdosys1 CLK_VDO1_PADDING2>; 3489 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3490 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>; 3491 }; 3492 3493 padding3: padding@1c120000 { 3494 compatible = "mediatek,mt8188-disp-padding"; 3495 reg = <0 0x1c120000 0 0x1000>; 3496 clocks = <&vdosys1 CLK_VDO1_PADDING3>; 3497 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3498 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>; 3499 }; 3500 3501 padding4: padding@1c121000 { 3502 compatible = "mediatek,mt8188-disp-padding"; 3503 reg = <0 0x1c121000 0 0x1000>; 3504 clocks = <&vdosys1 CLK_VDO1_PADDING4>; 3505 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3506 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>; 3507 }; 3508 3509 padding5: padding@1c122000 { 3510 compatible = "mediatek,mt8188-disp-padding"; 3511 reg = <0 0x1c122000 0 0x1000>; 3512 clocks = <&vdosys1 CLK_VDO1_PADDING5>; 3513 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3514 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>; 3515 }; 3516 3517 padding6: padding@1c123000 { 3518 compatible = "mediatek,mt8188-disp-padding"; 3519 reg = <0 0x1c123000 0 0x1000>; 3520 clocks = <&vdosys1 CLK_VDO1_PADDING6>; 3521 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3522 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>; 3523 }; 3524 3525 padding7: padding@1c124000 { 3526 compatible = "mediatek,mt8188-disp-padding"; 3527 reg = <0 0x1c124000 0 0x1000>; 3528 clocks = <&vdosys1 CLK_VDO1_PADDING7>; 3529 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3530 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; 3531 }; 3532 3533 edp_tx: edp-tx@1c500000 { 3534 compatible = "mediatek,mt8188-edp-tx"; 3535 reg = <0 0x1c500000 0 0x8000>; 3536 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 3537 nvmem-cells = <&dp_calib_data>; 3538 nvmem-cell-names = "dp_calibration_data"; 3539 power-domains = <&spm MT8188_POWER_DOMAIN_EDP_TX>; 3540 max-linkrate-mhz = <8100>; 3541 status = "disabled"; 3542 }; 3543 3544 dp_tx: dp-tx@1c600000 { 3545 compatible = "mediatek,mt8188-dp-tx"; 3546 reg = <0 0x1c600000 0 0x8000>; 3547 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 3548 nvmem-cells = <&dp_calib_data>; 3549 nvmem-cell-names = "dp_calibration_data"; 3550 power-domains = <&spm MT8188_POWER_DOMAIN_DP_TX>; 3551 max-linkrate-mhz = <5400>; 3552 status = "disabled"; 3553 }; 3554 }; 3555}; 3556