xref: /titanic_41/usr/src/uts/common/io/chxge/com/common.h (revision d39a76e7b087a3d0927cbe6898dc0a6770fa6c68)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (C) 2003-2005 Chelsio Communications.  All rights reserved.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"	/* common.h */
27 
28 #ifndef CHELSIO_COMMON_H
29 #define CHELSIO_COMMON_H
30 
31 #define DIMOF(x) (sizeof(x)/sizeof(x[0]))
32 
33 #define NMTUS      8
34 #define MAX_NPORTS 4
35 #define TCB_SIZE   128
36 
37 enum {
38 	CHBT_BOARD_7500,
39 	CHBT_BOARD_8000,
40 	CHBT_BOARD_CHT101,
41 	CHBT_BOARD_CHT110,
42 	CHBT_BOARD_CHT210,
43 	CHBT_BOARD_CHT204,
44 	CHBT_BOARD_CHT204V,
45 	CHBT_BOARD_N110,
46 	CHBT_BOARD_N210,
47 	CHBT_BOARD_COUGAR,
48 	CHBT_BOARD_6800,
49 	CHBT_BOARD_SIMUL
50 };
51 
52 enum {
53 	CHBT_TERM_FPGA,
54 	CHBT_TERM_T1,
55 	CHBT_TERM_T2,
56 	CHBT_TERM_T3
57 };
58 
59 enum {
60 	CHBT_MAC_CHELSIO_A,
61 	CHBT_MAC_IXF1010,
62 	CHBT_MAC_PM3393,
63 	CHBT_MAC_VSC7321,
64 	CHBT_MAC_DUMMY
65 };
66 
67 enum {
68 	CHBT_PHY_88E1041,
69 	CHBT_PHY_88E1111,
70 	CHBT_PHY_88X2010,
71 	CHBT_PHY_XPAK,
72 	CHBT_PHY_MY3126,
73 	CHBT_PHY_DUMMY
74 };
75 
76 enum {
77 	PAUSE_RX = 1,
78 	PAUSE_TX = 2,
79 	PAUSE_AUTONEG = 4
80 };
81 
82 /* Revisions of T1 chip */
83 #define TERM_T1A     0
84 #define TERM_T1B     1
85 #define TERM_T2      3
86 
87 struct tp_params {
88 	unsigned int pm_size;
89 	unsigned int cm_size;
90         unsigned int pm_rx_base;
91         unsigned int pm_tx_base;
92         unsigned int pm_rx_pg_size;
93         unsigned int pm_tx_pg_size;
94         unsigned int pm_rx_num_pgs;
95         unsigned int pm_tx_num_pgs;
96 	unsigned int use_5tuple_mode;
97 };
98 
99 struct sge_params {
100         unsigned int cmdQ_size[2];
101         unsigned int freelQ_size[2];
102 	unsigned int large_buf_capacity;
103 	unsigned int rx_coalesce_usecs;
104 	unsigned int last_rx_coalesce_raw;
105 	unsigned int default_rx_coalesce_usecs;
106 	unsigned int sample_interval_usecs;
107 	unsigned int coalesce_enable;
108 	unsigned int polling;
109 };
110 
111 struct mc5_params {
112 	unsigned int mode;       /* selects MC5 width */
113 	unsigned int nservers;   /* size of server region */
114 	unsigned int nroutes;    /* size of routing region */
115 };
116 
117 /* Default MC5 region sizes */
118 #define DEFAULT_SERVER_REGION_LEN 256
119 #define DEFAULT_RT_REGION_LEN 1024
120 
121 struct pci_params {
122 	unsigned short speed;
123 	unsigned char  width;
124 	unsigned char  is_pcix;
125 };
126 
127 struct adapter_params {
128 	struct sge_params sge;
129 	struct mc5_params mc5;
130 	struct tp_params  tp;
131 	struct pci_params pci;
132 
133 	const struct board_info *brd_info;
134 
135 	unsigned short mtus[NMTUS];
136 	unsigned int   nports;         /* # of ethernet ports */
137 	unsigned int   stats_update_period;
138 	unsigned short chip_revision;
139 	unsigned char  chip_version;
140 	unsigned char  is_asic;
141 };
142 
143 struct pci_err_cnt {
144 	unsigned int master_parity_err;
145 	unsigned int sig_target_abort;
146 	unsigned int rcv_target_abort;
147 	unsigned int rcv_master_abort;
148 	unsigned int sig_sys_err;
149 	unsigned int det_parity_err;
150 	unsigned int pio_parity_err;
151 	unsigned int wf_parity_err;
152 	unsigned int rf_parity_err;
153 	unsigned int cf_parity_err;
154 };
155 
156 struct link_config {
157 	unsigned int   supported;        /* link capabilities */
158 	unsigned int   advertising;      /* advertised capabilities */
159         unsigned short requested_speed;  /* speed user has requested */
160 	unsigned short speed;            /* actual link speed */
161         unsigned char  requested_duplex; /* duplex user has requested */
162 	unsigned char  duplex;           /* actual link duplex */
163 	unsigned char  requested_fc;     /* flow control user has requested */
164 	unsigned char  fc;               /* actual link flow control */
165 	unsigned char  autoneg;          /* autonegotiating? */
166 };
167 
168 #define SPEED_INVALID   0xffff
169 #define DUPLEX_INVALID  0xff
170 
171 struct mdio_ops;
172 struct gmac;
173 struct gphy;
174 
175 struct board_info {
176 	unsigned char           board;
177 	unsigned char           port_number;
178 	unsigned long           caps;
179 	unsigned char           chip_term;
180 	unsigned char           chip_mac;
181 	unsigned char           chip_phy;
182 	unsigned int            clock_core;
183 	unsigned int            clock_mc3;
184 	unsigned int            clock_mc4;
185 	unsigned int            espi_nports;
186 	unsigned int            clock_cspi;
187 	unsigned int            clock_elmer0;
188 	unsigned char           mdio_mdien;
189 	unsigned char           mdio_mdiinv;
190 	unsigned char           mdio_mdc;
191 	unsigned char           mdio_phybaseaddr;
192 	struct gmac            *gmac;
193 	struct gphy            *gphy;
194 	struct mdio_ops	       *mdio_ops;
195 	const char             *desc;
196 };
197 
198 #include "osdep.h"
199 
200 #ifndef PCI_VENDOR_ID_CHELSIO
201 #define PCI_VENDOR_ID_CHELSIO 0x1425
202 #endif
203 
204 extern struct pci_device_id t1_pci_tbl[];
205 
t1_is_asic(const adapter_t * adapter)206 static inline int t1_is_asic(const adapter_t *adapter)
207 {
208 	return adapter->params.is_asic;
209 }
210 
adapter_matches_type(const adapter_t * adapter,int version,int revision)211 static inline int adapter_matches_type(const adapter_t *adapter,
212 				       int version, int revision)
213 {
214 	return adapter->params.chip_version == version &&
215 		adapter->params.chip_revision == revision;
216 }
217 
218 #define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
219 #define is_T2(adap)     adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)
220 
221 /* Returns true if an adapter supports VLAN acceleration and TSO */
vlan_tso_capable(const adapter_t * adapter)222 static inline int vlan_tso_capable(const adapter_t *adapter)
223 {
224 	return !t1_is_T1B(adapter);
225 }
226 
227 #define for_each_port(adapter, iter) \
228 	for (iter = 0; iter < (adapter)->params.nports; ++iter)
229 
230 #define board_info(adapter) ((adapter)->params.brd_info)
231 #define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)
232 
core_ticks_per_usec(const adapter_t * adap)233 static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
234 {
235 	return board_info(adap)->clock_core / 1000000;
236 }
237 
238 int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp);
239 int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
240 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
241 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
242 int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
243                     int attempts, int delay);
244 
245 void t1_interrupts_enable(adapter_t *adapter);
246 void t1_interrupts_disable(adapter_t *adapter);
247 void t1_interrupts_clear(adapter_t *adapter);
248 int elmer0_ext_intr_handler(adapter_t *adapter);
249 int t1_slow_intr_handler(adapter_t *adapter);
250 
251 int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
252 const struct board_info *t1_get_board_info(unsigned int board_id);
253 const struct board_info *t1_get_board_info_from_ids(unsigned int devid,
254 						    unsigned short ssid);
255 int t1_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
256 int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
257 		     struct adapter_params *p);
258 int t1_init_hw_modules(adapter_t *adapter);
259 int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
260 void t1_free_sw_modules(adapter_t *adapter);
261 void t1_fatal_err(adapter_t *adapter);
262 void link_changed(adapter_t *adapter, int port_id);
263 void init_mtus(unsigned short mtus[]);
264 #endif /* CHELSIO_COMMON_H */
265