1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2014 Leon Dang <ldang@nahannisys.com>
5 * Copyright 2018 Joyent, Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29 /*
30 XHCI options:
31 -s <n>,xhci,{devices}
32
33 devices:
34 tablet USB tablet mouse
35 */
36 #include <sys/cdefs.h>
37
38 #include <sys/param.h>
39 #include <sys/uio.h>
40 #include <sys/types.h>
41 #include <sys/queue.h>
42
43 #include <stdio.h>
44 #include <stdlib.h>
45 #include <stdint.h>
46 #include <string.h>
47 #include <errno.h>
48 #include <pthread.h>
49 #include <unistd.h>
50
51 #include <dev/usb/usbdi.h>
52 #include <dev/usb/usb.h>
53 #include <dev/usb/usb_freebsd.h>
54 #include <xhcireg.h>
55
56 #include "bhyverun.h"
57 #include "config.h"
58 #include "debug.h"
59 #include "pci_emul.h"
60 #include "pci_xhci.h"
61 #include "usb_emul.h"
62
63
64 static int xhci_debug = 0;
65 #define DPRINTF(params) if (xhci_debug) PRINTLN params
66 #define WPRINTF(params) PRINTLN params
67
68
69 #define XHCI_NAME "xhci"
70 #define XHCI_MAX_DEVS 8 /* 4 USB3 + 4 USB2 devs */
71
72 #define XHCI_MAX_SLOTS 64 /* min allowed by Windows drivers */
73
74 /*
75 * XHCI data structures can be up to 64k, but limit paddr_guest2host mapping
76 * to 4k to avoid going over the guest physical memory barrier.
77 */
78 #define XHCI_PADDR_SZ 4096 /* paddr_guest2host max size */
79
80 #define XHCI_ERST_MAX 0 /* max 2^entries event ring seg tbl */
81
82 #define XHCI_CAPLEN (4*8) /* offset of op register space */
83 #define XHCI_HCCPRAMS2 0x1C /* offset of HCCPARAMS2 register */
84 #define XHCI_PORTREGS_START 0x400
85 #define XHCI_DOORBELL_MAX 256
86
87 #define XHCI_STREAMS_MAX 1 /* 4-15 in XHCI spec */
88
89 /* caplength and hci-version registers */
90 #define XHCI_SET_CAPLEN(x) ((x) & 0xFF)
91 #define XHCI_SET_HCIVERSION(x) (((x) & 0xFFFF) << 16)
92 #define XHCI_GET_HCIVERSION(x) (((x) >> 16) & 0xFFFF)
93
94 /* hcsparams1 register */
95 #define XHCI_SET_HCSP1_MAXSLOTS(x) ((x) & 0xFF)
96 #define XHCI_SET_HCSP1_MAXINTR(x) (((x) & 0x7FF) << 8)
97 #define XHCI_SET_HCSP1_MAXPORTS(x) (((x) & 0xFF) << 24)
98
99 /* hcsparams2 register */
100 #define XHCI_SET_HCSP2_IST(x) ((x) & 0x0F)
101 #define XHCI_SET_HCSP2_ERSTMAX(x) (((x) & 0x0F) << 4)
102 #define XHCI_SET_HCSP2_MAXSCRATCH_HI(x) (((x) & 0x1F) << 21)
103 #define XHCI_SET_HCSP2_MAXSCRATCH_LO(x) (((x) & 0x1F) << 27)
104
105 /* hcsparams3 register */
106 #define XHCI_SET_HCSP3_U1EXITLATENCY(x) ((x) & 0xFF)
107 #define XHCI_SET_HCSP3_U2EXITLATENCY(x) (((x) & 0xFFFF) << 16)
108
109 /* hccparams1 register */
110 #define XHCI_SET_HCCP1_AC64(x) ((x) & 0x01)
111 #define XHCI_SET_HCCP1_BNC(x) (((x) & 0x01) << 1)
112 #define XHCI_SET_HCCP1_CSZ(x) (((x) & 0x01) << 2)
113 #define XHCI_SET_HCCP1_PPC(x) (((x) & 0x01) << 3)
114 #define XHCI_SET_HCCP1_PIND(x) (((x) & 0x01) << 4)
115 #define XHCI_SET_HCCP1_LHRC(x) (((x) & 0x01) << 5)
116 #define XHCI_SET_HCCP1_LTC(x) (((x) & 0x01) << 6)
117 #define XHCI_SET_HCCP1_NSS(x) (((x) & 0x01) << 7)
118 #define XHCI_SET_HCCP1_PAE(x) (((x) & 0x01) << 8)
119 #define XHCI_SET_HCCP1_SPC(x) (((x) & 0x01) << 9)
120 #define XHCI_SET_HCCP1_SEC(x) (((x) & 0x01) << 10)
121 #define XHCI_SET_HCCP1_CFC(x) (((x) & 0x01) << 11)
122 #define XHCI_SET_HCCP1_MAXPSA(x) (((x) & 0x0F) << 12)
123 #define XHCI_SET_HCCP1_XECP(x) (((x) & 0xFFFF) << 16)
124
125 /* hccparams2 register */
126 #define XHCI_SET_HCCP2_U3C(x) ((x) & 0x01)
127 #define XHCI_SET_HCCP2_CMC(x) (((x) & 0x01) << 1)
128 #define XHCI_SET_HCCP2_FSC(x) (((x) & 0x01) << 2)
129 #define XHCI_SET_HCCP2_CTC(x) (((x) & 0x01) << 3)
130 #define XHCI_SET_HCCP2_LEC(x) (((x) & 0x01) << 4)
131 #define XHCI_SET_HCCP2_CIC(x) (((x) & 0x01) << 5)
132
133 /* other registers */
134 #define XHCI_SET_DOORBELL(x) ((x) & ~0x03)
135 #define XHCI_SET_RTSOFFSET(x) ((x) & ~0x0F)
136
137 /* register masks */
138 #define XHCI_PS_PLS_MASK (0xF << 5) /* port link state */
139 #define XHCI_PS_SPEED_MASK (0xF << 10) /* port speed */
140 #define XHCI_PS_PIC_MASK (0x3 << 14) /* port indicator */
141
142 /* port register set */
143 #define XHCI_PORTREGS_BASE 0x400 /* base offset */
144 #define XHCI_PORTREGS_PORT0 0x3F0
145 #define XHCI_PORTREGS_SETSZ 0x10 /* size of a set */
146
147 #define MASK_64_HI(x) ((x) & ~0xFFFFFFFFULL)
148 #define MASK_64_LO(x) ((x) & 0xFFFFFFFFULL)
149
150 #define FIELD_REPLACE(a,b,m,s) (((a) & ~((m) << (s))) | \
151 (((b) & (m)) << (s)))
152 #define FIELD_COPY(a,b,m,s) (((a) & ~((m) << (s))) | \
153 (((b) & ((m) << (s)))))
154
155 struct pci_xhci_trb_ring {
156 uint64_t ringaddr; /* current dequeue guest address */
157 uint32_t ccs; /* consumer cycle state */
158 };
159
160 /* device endpoint transfer/stream rings */
161 struct pci_xhci_dev_ep {
162 union {
163 struct xhci_trb *_epu_tr;
164 struct xhci_stream_ctx *_epu_sctx;
165 } _ep_trbsctx;
166 #define ep_tr _ep_trbsctx._epu_tr
167 #define ep_sctx _ep_trbsctx._epu_sctx
168
169 /*
170 * Caches the value of MaxPStreams from the endpoint context
171 * when an endpoint is initialized and is used to validate the
172 * use of ep_ringaddr vs ep_sctx_trbs[] as well as the length
173 * of ep_sctx_trbs[].
174 */
175 uint32_t ep_MaxPStreams;
176 union {
177 struct pci_xhci_trb_ring _epu_trb;
178 struct pci_xhci_trb_ring *_epu_sctx_trbs;
179 } _ep_trb_rings;
180 #define ep_ringaddr _ep_trb_rings._epu_trb.ringaddr
181 #define ep_ccs _ep_trb_rings._epu_trb.ccs
182 #define ep_sctx_trbs _ep_trb_rings._epu_sctx_trbs
183
184 struct usb_data_xfer *ep_xfer; /* transfer chain */
185 };
186
187 /* device context base address array: maps slot->device context */
188 struct xhci_dcbaa {
189 uint64_t dcba[USB_MAX_DEVICES+1]; /* xhci_dev_ctx ptrs */
190 };
191
192 /* port status registers */
193 struct pci_xhci_portregs {
194 uint32_t portsc; /* port status and control */
195 uint32_t portpmsc; /* port pwr mgmt status & control */
196 uint32_t portli; /* port link info */
197 uint32_t porthlpmc; /* port hardware LPM control */
198 } __packed;
199 #define XHCI_PS_SPEED_SET(x) (((x) & 0xF) << 10)
200
201 /* xHC operational registers */
202 struct pci_xhci_opregs {
203 uint32_t usbcmd; /* usb command */
204 uint32_t usbsts; /* usb status */
205 uint32_t pgsz; /* page size */
206 uint32_t dnctrl; /* device notification control */
207 uint64_t crcr; /* command ring control */
208 uint64_t dcbaap; /* device ctx base addr array ptr */
209 uint32_t config; /* configure */
210
211 /* guest mapped addresses: */
212 struct xhci_trb *cr_p; /* crcr dequeue */
213 struct xhci_dcbaa *dcbaa_p; /* dev ctx array ptr */
214 };
215
216 /* xHC runtime registers */
217 struct pci_xhci_rtsregs {
218 uint32_t mfindex; /* microframe index */
219 struct { /* interrupter register set */
220 uint32_t iman; /* interrupter management */
221 uint32_t imod; /* interrupter moderation */
222 uint32_t erstsz; /* event ring segment table size */
223 uint32_t rsvd;
224 uint64_t erstba; /* event ring seg-tbl base addr */
225 uint64_t erdp; /* event ring dequeue ptr */
226 } intrreg __packed;
227
228 /* guest mapped addresses */
229 struct xhci_event_ring_seg *erstba_p;
230 struct xhci_trb *erst_p; /* event ring segment tbl */
231 int er_deq_seg; /* event ring dequeue segment */
232 int er_enq_idx; /* event ring enqueue index - xHCI */
233 int er_enq_seg; /* event ring enqueue segment */
234 uint32_t er_events_cnt; /* number of events in ER */
235 uint32_t event_pcs; /* producer cycle state flag */
236 };
237
238
239 struct pci_xhci_softc;
240
241
242 /*
243 * USB device emulation container.
244 * This is referenced from usb_hci->hci_sc; 1 pci_xhci_dev_emu for each
245 * emulated device instance.
246 */
247 struct pci_xhci_dev_emu {
248 struct pci_xhci_softc *xsc;
249
250 /* XHCI contexts */
251 struct xhci_dev_ctx *dev_ctx;
252 struct pci_xhci_dev_ep eps[XHCI_MAX_ENDPOINTS];
253 int dev_slotstate;
254
255 struct usb_devemu *dev_ue; /* USB emulated dev */
256 void *dev_sc; /* device's softc */
257
258 struct usb_hci hci;
259 };
260
261 struct pci_xhci_softc {
262 struct pci_devinst *xsc_pi;
263
264 pthread_mutex_t mtx;
265
266 uint32_t caplength; /* caplen & hciversion */
267 uint32_t hcsparams1; /* structural parameters 1 */
268 uint32_t hcsparams2; /* structural parameters 2 */
269 uint32_t hcsparams3; /* structural parameters 3 */
270 uint32_t hccparams1; /* capability parameters 1 */
271 uint32_t dboff; /* doorbell offset */
272 uint32_t rtsoff; /* runtime register space offset */
273 uint32_t hccparams2; /* capability parameters 2 */
274
275 uint32_t regsend; /* end of configuration registers */
276
277 struct pci_xhci_opregs opregs;
278 struct pci_xhci_rtsregs rtsregs;
279
280 struct pci_xhci_portregs *portregs;
281 struct pci_xhci_dev_emu **devices; /* XHCI[port] = device */
282 struct pci_xhci_dev_emu **slots; /* slots assigned from 1 */
283
284 int usb2_port_start;
285 int usb3_port_start;
286 };
287
288
289 /* port and slot numbering start from 1 */
290 #define XHCI_PORTREG_PTR(x,n) &((x)->portregs[(n) - 1])
291 #define XHCI_DEVINST_PTR(x,n) ((x)->devices[(n) - 1])
292 #define XHCI_SLOTDEV_PTR(x,n) ((x)->slots[(n) - 1])
293
294 #define XHCI_HALTED(sc) ((sc)->opregs.usbsts & XHCI_STS_HCH)
295
296 #define XHCI_GADDR(sc,a) paddr_guest2host((sc)->xsc_pi->pi_vmctx, \
297 (a), \
298 XHCI_PADDR_SZ - ((a) & (XHCI_PADDR_SZ-1)))
299
300 static int xhci_in_use;
301
302 /* map USB errors to XHCI */
303 static const int xhci_usb_errors[USB_ERR_MAX] = {
304 [USB_ERR_NORMAL_COMPLETION] = XHCI_TRB_ERROR_SUCCESS,
305 [USB_ERR_PENDING_REQUESTS] = XHCI_TRB_ERROR_RESOURCE,
306 [USB_ERR_NOT_STARTED] = XHCI_TRB_ERROR_ENDP_NOT_ON,
307 [USB_ERR_INVAL] = XHCI_TRB_ERROR_INVALID,
308 [USB_ERR_NOMEM] = XHCI_TRB_ERROR_RESOURCE,
309 [USB_ERR_CANCELLED] = XHCI_TRB_ERROR_STOPPED,
310 [USB_ERR_BAD_ADDRESS] = XHCI_TRB_ERROR_PARAMETER,
311 [USB_ERR_BAD_BUFSIZE] = XHCI_TRB_ERROR_PARAMETER,
312 [USB_ERR_BAD_FLAG] = XHCI_TRB_ERROR_PARAMETER,
313 [USB_ERR_NO_CALLBACK] = XHCI_TRB_ERROR_STALL,
314 [USB_ERR_IN_USE] = XHCI_TRB_ERROR_RESOURCE,
315 [USB_ERR_NO_ADDR] = XHCI_TRB_ERROR_RESOURCE,
316 [USB_ERR_NO_PIPE] = XHCI_TRB_ERROR_RESOURCE,
317 [USB_ERR_ZERO_NFRAMES] = XHCI_TRB_ERROR_UNDEFINED,
318 [USB_ERR_ZERO_MAXP] = XHCI_TRB_ERROR_UNDEFINED,
319 [USB_ERR_SET_ADDR_FAILED] = XHCI_TRB_ERROR_RESOURCE,
320 [USB_ERR_NO_POWER] = XHCI_TRB_ERROR_ENDP_NOT_ON,
321 [USB_ERR_TOO_DEEP] = XHCI_TRB_ERROR_RESOURCE,
322 [USB_ERR_IOERROR] = XHCI_TRB_ERROR_TRB,
323 [USB_ERR_NOT_CONFIGURED] = XHCI_TRB_ERROR_ENDP_NOT_ON,
324 [USB_ERR_TIMEOUT] = XHCI_TRB_ERROR_CMD_ABORTED,
325 [USB_ERR_SHORT_XFER] = XHCI_TRB_ERROR_SHORT_PKT,
326 [USB_ERR_STALLED] = XHCI_TRB_ERROR_STALL,
327 [USB_ERR_INTERRUPTED] = XHCI_TRB_ERROR_CMD_ABORTED,
328 [USB_ERR_DMA_LOAD_FAILED] = XHCI_TRB_ERROR_DATA_BUF,
329 [USB_ERR_BAD_CONTEXT] = XHCI_TRB_ERROR_TRB,
330 [USB_ERR_NO_ROOT_HUB] = XHCI_TRB_ERROR_UNDEFINED,
331 [USB_ERR_NO_INTR_THREAD] = XHCI_TRB_ERROR_UNDEFINED,
332 [USB_ERR_NOT_LOCKED] = XHCI_TRB_ERROR_UNDEFINED,
333 };
334 #define USB_TO_XHCI_ERR(e) ((e) < USB_ERR_MAX ? xhci_usb_errors[(e)] : \
335 XHCI_TRB_ERROR_INVALID)
336
337 static int pci_xhci_insert_event(struct pci_xhci_softc *sc,
338 struct xhci_trb *evtrb, int do_intr);
339 static void pci_xhci_dump_trb(struct xhci_trb *trb);
340 static void pci_xhci_assert_interrupt(struct pci_xhci_softc *sc);
341 static void pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot);
342 static void pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm);
343 static void pci_xhci_update_ep_ring(struct pci_xhci_softc *sc,
344 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep,
345 struct xhci_endp_ctx *ep_ctx, uint32_t streamid,
346 uint64_t ringaddr, int ccs);
347
348 static void
pci_xhci_set_evtrb(struct xhci_trb * evtrb,uint64_t port,uint32_t errcode,uint32_t evtype)349 pci_xhci_set_evtrb(struct xhci_trb *evtrb, uint64_t port, uint32_t errcode,
350 uint32_t evtype)
351 {
352 evtrb->qwTrb0 = port << 24;
353 evtrb->dwTrb2 = XHCI_TRB_2_ERROR_SET(errcode);
354 evtrb->dwTrb3 = XHCI_TRB_3_TYPE_SET(evtype);
355 }
356
357
358 /* controller reset */
359 static void
pci_xhci_reset(struct pci_xhci_softc * sc)360 pci_xhci_reset(struct pci_xhci_softc *sc)
361 {
362 int i;
363
364 sc->rtsregs.er_enq_idx = 0;
365 sc->rtsregs.er_events_cnt = 0;
366 sc->rtsregs.event_pcs = 1;
367
368 for (i = 1; i <= XHCI_MAX_SLOTS; i++) {
369 pci_xhci_reset_slot(sc, i);
370 }
371 }
372
373 static uint32_t
pci_xhci_usbcmd_write(struct pci_xhci_softc * sc,uint32_t cmd)374 pci_xhci_usbcmd_write(struct pci_xhci_softc *sc, uint32_t cmd)
375 {
376 int do_intr = 0;
377 int i;
378
379 if (cmd & XHCI_CMD_RS) {
380 do_intr = (sc->opregs.usbcmd & XHCI_CMD_RS) == 0;
381
382 sc->opregs.usbcmd |= XHCI_CMD_RS;
383 sc->opregs.usbsts &= ~XHCI_STS_HCH;
384 sc->opregs.usbsts |= XHCI_STS_PCD;
385
386 /* Queue port change event on controller run from stop */
387 if (do_intr)
388 for (i = 1; i <= XHCI_MAX_DEVS; i++) {
389 struct pci_xhci_dev_emu *dev;
390 struct pci_xhci_portregs *port;
391 struct xhci_trb evtrb;
392
393 if ((dev = XHCI_DEVINST_PTR(sc, i)) == NULL)
394 continue;
395
396 port = XHCI_PORTREG_PTR(sc, i);
397 port->portsc |= XHCI_PS_CSC | XHCI_PS_CCS;
398 port->portsc &= ~XHCI_PS_PLS_MASK;
399
400 /*
401 * XHCI 4.19.3 USB2 RxDetect->Polling,
402 * USB3 Polling->U0
403 */
404 if (dev->dev_ue->ue_usbver == 2)
405 port->portsc |=
406 XHCI_PS_PLS_SET(UPS_PORT_LS_POLL);
407 else
408 port->portsc |=
409 XHCI_PS_PLS_SET(UPS_PORT_LS_U0);
410
411 pci_xhci_set_evtrb(&evtrb, i,
412 XHCI_TRB_ERROR_SUCCESS,
413 XHCI_TRB_EVENT_PORT_STS_CHANGE);
414
415 if (pci_xhci_insert_event(sc, &evtrb, 0) !=
416 XHCI_TRB_ERROR_SUCCESS)
417 break;
418 }
419 } else {
420 sc->opregs.usbcmd &= ~XHCI_CMD_RS;
421 sc->opregs.usbsts |= XHCI_STS_HCH;
422 sc->opregs.usbsts &= ~XHCI_STS_PCD;
423 }
424
425 /* start execution of schedule; stop when set to 0 */
426 cmd |= sc->opregs.usbcmd & XHCI_CMD_RS;
427
428 if (cmd & XHCI_CMD_HCRST) {
429 /* reset controller */
430 pci_xhci_reset(sc);
431 cmd &= ~XHCI_CMD_HCRST;
432 }
433
434 cmd &= ~(XHCI_CMD_CSS | XHCI_CMD_CRS);
435
436 if (do_intr)
437 pci_xhci_assert_interrupt(sc);
438
439 return (cmd);
440 }
441
442 static void
pci_xhci_portregs_write(struct pci_xhci_softc * sc,uint64_t offset,uint64_t value)443 pci_xhci_portregs_write(struct pci_xhci_softc *sc, uint64_t offset,
444 uint64_t value)
445 {
446 struct xhci_trb evtrb;
447 struct pci_xhci_portregs *p;
448 int port;
449 uint32_t oldpls, newpls;
450
451 if (sc->portregs == NULL)
452 return;
453
454 port = (offset - XHCI_PORTREGS_PORT0) / XHCI_PORTREGS_SETSZ;
455 offset = (offset - XHCI_PORTREGS_PORT0) % XHCI_PORTREGS_SETSZ;
456
457 DPRINTF(("pci_xhci: portregs wr offset 0x%lx, port %u: 0x%lx",
458 offset, port, value));
459
460 assert(port >= 0);
461
462 if (port > XHCI_MAX_DEVS) {
463 DPRINTF(("pci_xhci: portregs_write port %d > ndevices",
464 port));
465 return;
466 }
467
468 if (XHCI_DEVINST_PTR(sc, port) == NULL) {
469 DPRINTF(("pci_xhci: portregs_write to unattached port %d",
470 port));
471 }
472
473 p = XHCI_PORTREG_PTR(sc, port);
474 switch (offset) {
475 case 0:
476 /* port reset or warm reset */
477 if (value & (XHCI_PS_PR | XHCI_PS_WPR)) {
478 pci_xhci_reset_port(sc, port, value & XHCI_PS_WPR);
479 break;
480 }
481
482 if ((p->portsc & XHCI_PS_PP) == 0) {
483 WPRINTF(("pci_xhci: portregs_write to unpowered "
484 "port %d", port));
485 break;
486 }
487
488 /* Port status and control register */
489 oldpls = XHCI_PS_PLS_GET(p->portsc);
490 newpls = XHCI_PS_PLS_GET(value);
491
492 #ifndef __FreeBSD__
493 p->portsc &= XHCI_PS_PED | XHCI_PS_PP | XHCI_PS_PLS_MASK |
494 XHCI_PS_SPEED_MASK | XHCI_PS_PIC_MASK;
495 #else
496 p->portsc &= XHCI_PS_PED | XHCI_PS_PLS_MASK |
497 XHCI_PS_SPEED_MASK | XHCI_PS_PIC_MASK;
498 #endif
499
500 if (XHCI_DEVINST_PTR(sc, port))
501 p->portsc |= XHCI_PS_CCS;
502
503 p->portsc |= (value &
504 ~(XHCI_PS_OCA |
505 XHCI_PS_PR |
506 XHCI_PS_PED |
507 XHCI_PS_PLS_MASK | /* link state */
508 XHCI_PS_SPEED_MASK |
509 XHCI_PS_PIC_MASK | /* port indicator */
510 XHCI_PS_LWS | XHCI_PS_DR | XHCI_PS_WPR));
511
512 /* clear control bits */
513 p->portsc &= ~(value &
514 (XHCI_PS_CSC |
515 XHCI_PS_PEC |
516 XHCI_PS_WRC |
517 XHCI_PS_OCC |
518 XHCI_PS_PRC |
519 XHCI_PS_PLC |
520 XHCI_PS_CEC |
521 XHCI_PS_CAS));
522
523 /* port disable request; for USB3, don't care */
524 if (value & XHCI_PS_PED)
525 DPRINTF(("Disable port %d request", port));
526
527 if (!(value & XHCI_PS_LWS))
528 break;
529
530 DPRINTF(("Port new PLS: %d", newpls));
531 switch (newpls) {
532 case 0: /* U0 */
533 case 3: /* U3 */
534 if (oldpls != newpls) {
535 p->portsc &= ~XHCI_PS_PLS_MASK;
536 p->portsc |= XHCI_PS_PLS_SET(newpls) |
537 XHCI_PS_PLC;
538
539 if (oldpls != 0 && newpls == 0) {
540 pci_xhci_set_evtrb(&evtrb, port,
541 XHCI_TRB_ERROR_SUCCESS,
542 XHCI_TRB_EVENT_PORT_STS_CHANGE);
543
544 pci_xhci_insert_event(sc, &evtrb, 1);
545 }
546 }
547 break;
548
549 default:
550 DPRINTF(("Unhandled change port %d PLS %u",
551 port, newpls));
552 break;
553 }
554 break;
555 case 4:
556 /* Port power management status and control register */
557 p->portpmsc = value;
558 break;
559 case 8:
560 /* Port link information register */
561 DPRINTF(("pci_xhci attempted write to PORTLI, port %d",
562 port));
563 break;
564 case 12:
565 /*
566 * Port hardware LPM control register.
567 * For USB3, this register is reserved.
568 */
569 p->porthlpmc = value;
570 break;
571 default:
572 DPRINTF(("pci_xhci: unaligned portreg write offset %#lx",
573 offset));
574 break;
575 }
576 }
577
578 static struct xhci_dev_ctx *
pci_xhci_get_dev_ctx(struct pci_xhci_softc * sc,uint32_t slot)579 pci_xhci_get_dev_ctx(struct pci_xhci_softc *sc, uint32_t slot)
580 {
581 uint64_t devctx_addr;
582 struct xhci_dev_ctx *devctx;
583
584 assert(slot > 0 && slot <= XHCI_MAX_DEVS);
585 assert(XHCI_SLOTDEV_PTR(sc, slot) != NULL);
586 assert(sc->opregs.dcbaa_p != NULL);
587
588 devctx_addr = sc->opregs.dcbaa_p->dcba[slot];
589
590 if (devctx_addr == 0) {
591 DPRINTF(("get_dev_ctx devctx_addr == 0"));
592 return (NULL);
593 }
594
595 DPRINTF(("pci_xhci: get dev ctx, slot %u devctx addr %016lx",
596 slot, devctx_addr));
597 devctx = XHCI_GADDR(sc, devctx_addr & ~0x3FUL);
598
599 return (devctx);
600 }
601
602 static struct xhci_trb *
pci_xhci_trb_next(struct pci_xhci_softc * sc,struct xhci_trb * curtrb,uint64_t * guestaddr)603 pci_xhci_trb_next(struct pci_xhci_softc *sc, struct xhci_trb *curtrb,
604 uint64_t *guestaddr)
605 {
606 struct xhci_trb *next;
607
608 assert(curtrb != NULL);
609
610 if (XHCI_TRB_3_TYPE_GET(curtrb->dwTrb3) == XHCI_TRB_TYPE_LINK) {
611 if (guestaddr)
612 *guestaddr = curtrb->qwTrb0 & ~0xFUL;
613
614 next = XHCI_GADDR(sc, curtrb->qwTrb0 & ~0xFUL);
615 } else {
616 if (guestaddr)
617 *guestaddr += sizeof(struct xhci_trb) & ~0xFUL;
618
619 next = curtrb + 1;
620 }
621
622 return (next);
623 }
624
625 static void
pci_xhci_assert_interrupt(struct pci_xhci_softc * sc)626 pci_xhci_assert_interrupt(struct pci_xhci_softc *sc)
627 {
628
629 sc->rtsregs.intrreg.erdp |= XHCI_ERDP_LO_BUSY;
630 sc->rtsregs.intrreg.iman |= XHCI_IMAN_INTR_PEND;
631 sc->opregs.usbsts |= XHCI_STS_EINT;
632
633 /* only trigger interrupt if permitted */
634 if ((sc->opregs.usbcmd & XHCI_CMD_INTE) &&
635 (sc->rtsregs.intrreg.iman & XHCI_IMAN_INTR_ENA)) {
636 if (pci_msi_enabled(sc->xsc_pi))
637 pci_generate_msi(sc->xsc_pi, 0);
638 else
639 pci_lintr_assert(sc->xsc_pi);
640 }
641 }
642
643 static void
pci_xhci_deassert_interrupt(struct pci_xhci_softc * sc)644 pci_xhci_deassert_interrupt(struct pci_xhci_softc *sc)
645 {
646
647 if (!pci_msi_enabled(sc->xsc_pi))
648 pci_lintr_assert(sc->xsc_pi);
649 }
650
651 static void
pci_xhci_init_ep(struct pci_xhci_dev_emu * dev,int epid)652 pci_xhci_init_ep(struct pci_xhci_dev_emu *dev, int epid)
653 {
654 struct xhci_dev_ctx *dev_ctx;
655 struct pci_xhci_dev_ep *devep;
656 struct xhci_endp_ctx *ep_ctx;
657 uint32_t i, pstreams;
658
659 dev_ctx = dev->dev_ctx;
660 ep_ctx = &dev_ctx->ctx_ep[epid];
661 devep = &dev->eps[epid];
662 pstreams = XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0);
663 if (pstreams > 0) {
664 DPRINTF(("init_ep %d with pstreams %d", epid, pstreams));
665 assert(devep->ep_sctx_trbs == NULL);
666
667 devep->ep_sctx = XHCI_GADDR(dev->xsc, ep_ctx->qwEpCtx2 &
668 XHCI_EPCTX_2_TR_DQ_PTR_MASK);
669 devep->ep_sctx_trbs = calloc(pstreams,
670 sizeof(struct pci_xhci_trb_ring));
671 for (i = 0; i < pstreams; i++) {
672 devep->ep_sctx_trbs[i].ringaddr =
673 devep->ep_sctx[i].qwSctx0 &
674 XHCI_SCTX_0_TR_DQ_PTR_MASK;
675 devep->ep_sctx_trbs[i].ccs =
676 XHCI_SCTX_0_DCS_GET(devep->ep_sctx[i].qwSctx0);
677 }
678 } else {
679 DPRINTF(("init_ep %d with no pstreams", epid));
680 devep->ep_ringaddr = ep_ctx->qwEpCtx2 &
681 XHCI_EPCTX_2_TR_DQ_PTR_MASK;
682 devep->ep_ccs = XHCI_EPCTX_2_DCS_GET(ep_ctx->qwEpCtx2);
683 devep->ep_tr = XHCI_GADDR(dev->xsc, devep->ep_ringaddr);
684 DPRINTF(("init_ep tr DCS %x", devep->ep_ccs));
685 }
686 devep->ep_MaxPStreams = pstreams;
687
688 if (devep->ep_xfer == NULL) {
689 devep->ep_xfer = malloc(sizeof(struct usb_data_xfer));
690 USB_DATA_XFER_INIT(devep->ep_xfer);
691 }
692 }
693
694 static void
pci_xhci_disable_ep(struct pci_xhci_dev_emu * dev,int epid)695 pci_xhci_disable_ep(struct pci_xhci_dev_emu *dev, int epid)
696 {
697 struct xhci_dev_ctx *dev_ctx;
698 struct pci_xhci_dev_ep *devep;
699 struct xhci_endp_ctx *ep_ctx;
700
701 DPRINTF(("pci_xhci disable_ep %d", epid));
702
703 dev_ctx = dev->dev_ctx;
704 ep_ctx = &dev_ctx->ctx_ep[epid];
705 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_DISABLED;
706
707 devep = &dev->eps[epid];
708 if (devep->ep_MaxPStreams > 0)
709 free(devep->ep_sctx_trbs);
710
711 if (devep->ep_xfer != NULL) {
712 free(devep->ep_xfer);
713 devep->ep_xfer = NULL;
714 }
715
716 memset(devep, 0, sizeof(struct pci_xhci_dev_ep));
717 }
718
719
720 /* reset device at slot and data structures related to it */
721 static void
pci_xhci_reset_slot(struct pci_xhci_softc * sc,int slot)722 pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot)
723 {
724 struct pci_xhci_dev_emu *dev;
725
726 dev = XHCI_SLOTDEV_PTR(sc, slot);
727
728 if (!dev) {
729 DPRINTF(("xhci reset unassigned slot (%d)?", slot));
730 } else {
731 dev->dev_slotstate = XHCI_ST_DISABLED;
732 }
733
734 /* TODO: reset ring buffer pointers */
735 }
736
737 static int
pci_xhci_insert_event(struct pci_xhci_softc * sc,struct xhci_trb * evtrb,int do_intr)738 pci_xhci_insert_event(struct pci_xhci_softc *sc, struct xhci_trb *evtrb,
739 int do_intr)
740 {
741 struct pci_xhci_rtsregs *rts;
742 uint64_t erdp;
743 int erdp_idx;
744 int err;
745 struct xhci_trb *evtrbptr;
746
747 err = XHCI_TRB_ERROR_SUCCESS;
748
749 rts = &sc->rtsregs;
750
751 erdp = rts->intrreg.erdp & ~0xF;
752 erdp_idx = (erdp - rts->erstba_p[rts->er_deq_seg].qwEvrsTablePtr) /
753 sizeof(struct xhci_trb);
754
755 DPRINTF(("pci_xhci: insert event 0[%lx] 2[%x] 3[%x]",
756 evtrb->qwTrb0, evtrb->dwTrb2, evtrb->dwTrb3));
757 DPRINTF(("\terdp idx %d/seg %d, enq idx %d/seg %d, pcs %u",
758 erdp_idx, rts->er_deq_seg, rts->er_enq_idx,
759 rts->er_enq_seg, rts->event_pcs));
760 DPRINTF(("\t(erdp=0x%lx, erst=0x%lx, tblsz=%u, do_intr %d)",
761 erdp, rts->erstba_p->qwEvrsTablePtr,
762 rts->erstba_p->dwEvrsTableSize, do_intr));
763
764 evtrbptr = &rts->erst_p[rts->er_enq_idx];
765
766 /* TODO: multi-segment table */
767 if (rts->er_events_cnt >= rts->erstba_p->dwEvrsTableSize) {
768 DPRINTF(("pci_xhci[%d] cannot insert event; ring full",
769 __LINE__));
770 err = XHCI_TRB_ERROR_EV_RING_FULL;
771 goto done;
772 }
773
774 if (rts->er_events_cnt == rts->erstba_p->dwEvrsTableSize - 1) {
775 struct xhci_trb errev;
776
777 if ((evtrbptr->dwTrb3 & 0x1) == (rts->event_pcs & 0x1)) {
778
779 DPRINTF(("pci_xhci[%d] insert evt err: ring full",
780 __LINE__));
781
782 errev.qwTrb0 = 0;
783 errev.dwTrb2 = XHCI_TRB_2_ERROR_SET(
784 XHCI_TRB_ERROR_EV_RING_FULL);
785 errev.dwTrb3 = XHCI_TRB_3_TYPE_SET(
786 XHCI_TRB_EVENT_HOST_CTRL) |
787 rts->event_pcs;
788 rts->er_events_cnt++;
789 memcpy(&rts->erst_p[rts->er_enq_idx], &errev,
790 sizeof(struct xhci_trb));
791 rts->er_enq_idx = (rts->er_enq_idx + 1) %
792 rts->erstba_p->dwEvrsTableSize;
793 err = XHCI_TRB_ERROR_EV_RING_FULL;
794 do_intr = 1;
795
796 goto done;
797 }
798 } else {
799 rts->er_events_cnt++;
800 }
801
802 evtrb->dwTrb3 &= ~XHCI_TRB_3_CYCLE_BIT;
803 evtrb->dwTrb3 |= rts->event_pcs;
804
805 memcpy(&rts->erst_p[rts->er_enq_idx], evtrb, sizeof(struct xhci_trb));
806 rts->er_enq_idx = (rts->er_enq_idx + 1) %
807 rts->erstba_p->dwEvrsTableSize;
808
809 if (rts->er_enq_idx == 0)
810 rts->event_pcs ^= 1;
811
812 done:
813 if (do_intr)
814 pci_xhci_assert_interrupt(sc);
815
816 return (err);
817 }
818
819 static uint32_t
pci_xhci_cmd_enable_slot(struct pci_xhci_softc * sc,uint32_t * slot)820 pci_xhci_cmd_enable_slot(struct pci_xhci_softc *sc, uint32_t *slot)
821 {
822 struct pci_xhci_dev_emu *dev;
823 uint32_t cmderr;
824 int i;
825
826 cmderr = XHCI_TRB_ERROR_NO_SLOTS;
827 if (sc->portregs != NULL)
828 for (i = 1; i <= XHCI_MAX_SLOTS; i++) {
829 dev = XHCI_SLOTDEV_PTR(sc, i);
830 if (dev && dev->dev_slotstate == XHCI_ST_DISABLED) {
831 *slot = i;
832 dev->dev_slotstate = XHCI_ST_ENABLED;
833 cmderr = XHCI_TRB_ERROR_SUCCESS;
834 dev->hci.hci_address = i;
835 break;
836 }
837 }
838
839 DPRINTF(("pci_xhci enable slot (error=%d) slot %u",
840 cmderr != XHCI_TRB_ERROR_SUCCESS, *slot));
841
842 return (cmderr);
843 }
844
845 static uint32_t
pci_xhci_cmd_disable_slot(struct pci_xhci_softc * sc,uint32_t slot)846 pci_xhci_cmd_disable_slot(struct pci_xhci_softc *sc, uint32_t slot)
847 {
848 struct pci_xhci_dev_emu *dev;
849 uint32_t cmderr;
850
851 DPRINTF(("pci_xhci disable slot %u", slot));
852
853 cmderr = XHCI_TRB_ERROR_NO_SLOTS;
854 if (sc->portregs == NULL)
855 goto done;
856
857 if (slot > XHCI_MAX_SLOTS) {
858 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
859 goto done;
860 }
861
862 dev = XHCI_SLOTDEV_PTR(sc, slot);
863 if (dev) {
864 if (dev->dev_slotstate == XHCI_ST_DISABLED) {
865 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
866 } else {
867 dev->dev_slotstate = XHCI_ST_DISABLED;
868 cmderr = XHCI_TRB_ERROR_SUCCESS;
869 /* TODO: reset events and endpoints */
870 }
871 } else
872 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
873
874 done:
875 return (cmderr);
876 }
877
878 static uint32_t
pci_xhci_cmd_reset_device(struct pci_xhci_softc * sc,uint32_t slot)879 pci_xhci_cmd_reset_device(struct pci_xhci_softc *sc, uint32_t slot)
880 {
881 struct pci_xhci_dev_emu *dev;
882 struct xhci_dev_ctx *dev_ctx;
883 struct xhci_endp_ctx *ep_ctx;
884 uint32_t cmderr;
885 int i;
886
887 cmderr = XHCI_TRB_ERROR_NO_SLOTS;
888 if (sc->portregs == NULL)
889 goto done;
890
891 DPRINTF(("pci_xhci reset device slot %u", slot));
892
893 dev = XHCI_SLOTDEV_PTR(sc, slot);
894 if (!dev || dev->dev_slotstate == XHCI_ST_DISABLED)
895 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
896 else {
897 dev->dev_slotstate = XHCI_ST_DEFAULT;
898
899 dev->hci.hci_address = 0;
900 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
901
902 /* slot state */
903 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE(
904 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_DEFAULT,
905 0x1F, 27);
906
907 /* number of contexts */
908 dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE(
909 dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27);
910
911 /* reset all eps other than ep-0 */
912 for (i = 2; i <= 31; i++) {
913 ep_ctx = &dev_ctx->ctx_ep[i];
914 ep_ctx->dwEpCtx0 = FIELD_REPLACE( ep_ctx->dwEpCtx0,
915 XHCI_ST_EPCTX_DISABLED, 0x7, 0);
916 }
917
918 cmderr = XHCI_TRB_ERROR_SUCCESS;
919 }
920
921 pci_xhci_reset_slot(sc, slot);
922
923 done:
924 return (cmderr);
925 }
926
927 static uint32_t
pci_xhci_cmd_address_device(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)928 pci_xhci_cmd_address_device(struct pci_xhci_softc *sc, uint32_t slot,
929 struct xhci_trb *trb)
930 {
931 struct pci_xhci_dev_emu *dev;
932 struct xhci_input_dev_ctx *input_ctx;
933 struct xhci_slot_ctx *islot_ctx;
934 struct xhci_dev_ctx *dev_ctx;
935 struct xhci_endp_ctx *ep0_ctx;
936 uint32_t cmderr;
937
938 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);
939 islot_ctx = &input_ctx->ctx_slot;
940 ep0_ctx = &input_ctx->ctx_ep[1];
941
942 cmderr = XHCI_TRB_ERROR_SUCCESS;
943
944 DPRINTF(("pci_xhci: address device, input ctl: D 0x%08x A 0x%08x,",
945 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1));
946 DPRINTF((" slot %08x %08x %08x %08x",
947 islot_ctx->dwSctx0, islot_ctx->dwSctx1,
948 islot_ctx->dwSctx2, islot_ctx->dwSctx3));
949 DPRINTF((" ep0 %08x %08x %016lx %08x",
950 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
951 ep0_ctx->dwEpCtx4));
952
953 /* when setting address: drop-ctx=0, add-ctx=slot+ep0 */
954 if ((input_ctx->ctx_input.dwInCtx0 != 0) ||
955 (input_ctx->ctx_input.dwInCtx1 & 0x03) != 0x03) {
956 DPRINTF(("pci_xhci: address device, input ctl invalid"));
957 cmderr = XHCI_TRB_ERROR_TRB;
958 goto done;
959 }
960
961 /* assign address to slot */
962 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
963
964 DPRINTF(("pci_xhci: address device, dev ctx"));
965 DPRINTF((" slot %08x %08x %08x %08x",
966 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
967 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
968
969 dev = XHCI_SLOTDEV_PTR(sc, slot);
970 assert(dev != NULL);
971
972 dev->hci.hci_address = slot;
973 dev->dev_ctx = dev_ctx;
974
975 if (dev->dev_ue->ue_reset == NULL ||
976 dev->dev_ue->ue_reset(dev->dev_sc) < 0) {
977 cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON;
978 goto done;
979 }
980
981 memcpy(&dev_ctx->ctx_slot, islot_ctx, sizeof(struct xhci_slot_ctx));
982
983 dev_ctx->ctx_slot.dwSctx3 =
984 XHCI_SCTX_3_SLOT_STATE_SET(XHCI_ST_SLCTX_ADDRESSED) |
985 XHCI_SCTX_3_DEV_ADDR_SET(slot);
986
987 memcpy(&dev_ctx->ctx_ep[1], ep0_ctx, sizeof(struct xhci_endp_ctx));
988 ep0_ctx = &dev_ctx->ctx_ep[1];
989 ep0_ctx->dwEpCtx0 = (ep0_ctx->dwEpCtx0 & ~0x7) |
990 XHCI_EPCTX_0_EPSTATE_SET(XHCI_ST_EPCTX_RUNNING);
991
992 pci_xhci_init_ep(dev, 1);
993
994 dev->dev_slotstate = XHCI_ST_ADDRESSED;
995
996 DPRINTF(("pci_xhci: address device, output ctx"));
997 DPRINTF((" slot %08x %08x %08x %08x",
998 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
999 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1000 DPRINTF((" ep0 %08x %08x %016lx %08x",
1001 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
1002 ep0_ctx->dwEpCtx4));
1003
1004 done:
1005 return (cmderr);
1006 }
1007
1008 static uint32_t
pci_xhci_cmd_config_ep(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)1009 pci_xhci_cmd_config_ep(struct pci_xhci_softc *sc, uint32_t slot,
1010 struct xhci_trb *trb)
1011 {
1012 struct xhci_input_dev_ctx *input_ctx;
1013 struct pci_xhci_dev_emu *dev;
1014 struct xhci_dev_ctx *dev_ctx;
1015 struct xhci_endp_ctx *ep_ctx, *iep_ctx;
1016 uint32_t cmderr;
1017 int i;
1018
1019 cmderr = XHCI_TRB_ERROR_SUCCESS;
1020
1021 DPRINTF(("pci_xhci config_ep slot %u", slot));
1022
1023 dev = XHCI_SLOTDEV_PTR(sc, slot);
1024 assert(dev != NULL);
1025
1026 if ((trb->dwTrb3 & XHCI_TRB_3_DCEP_BIT) != 0) {
1027 DPRINTF(("pci_xhci config_ep - deconfigure ep slot %u",
1028 slot));
1029 if (dev->dev_ue->ue_stop != NULL)
1030 dev->dev_ue->ue_stop(dev->dev_sc);
1031
1032 dev->dev_slotstate = XHCI_ST_ADDRESSED;
1033
1034 dev->hci.hci_address = 0;
1035 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1036
1037 /* number of contexts */
1038 dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE(
1039 dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27);
1040
1041 /* slot state */
1042 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE(
1043 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_ADDRESSED,
1044 0x1F, 27);
1045
1046 /* disable endpoints */
1047 for (i = 2; i < 32; i++)
1048 pci_xhci_disable_ep(dev, i);
1049
1050 cmderr = XHCI_TRB_ERROR_SUCCESS;
1051
1052 goto done;
1053 }
1054
1055 if (dev->dev_slotstate < XHCI_ST_ADDRESSED) {
1056 DPRINTF(("pci_xhci: config_ep slotstate x%x != addressed",
1057 dev->dev_slotstate));
1058 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
1059 goto done;
1060 }
1061
1062 /* In addressed/configured state;
1063 * for each drop endpoint ctx flag:
1064 * ep->state = DISABLED
1065 * for each add endpoint ctx flag:
1066 * cp(ep-in, ep-out)
1067 * ep->state = RUNNING
1068 * for each drop+add endpoint flag:
1069 * reset ep resources
1070 * cp(ep-in, ep-out)
1071 * ep->state = RUNNING
1072 * if input->DisabledCtx[2-31] < 30: (at least 1 ep not disabled)
1073 * slot->state = configured
1074 */
1075
1076 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);
1077 dev_ctx = dev->dev_ctx;
1078 DPRINTF(("pci_xhci: config_ep inputctx: D:x%08x A:x%08x 7:x%08x",
1079 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1,
1080 input_ctx->ctx_input.dwInCtx7));
1081
1082 for (i = 2; i <= 31; i++) {
1083 ep_ctx = &dev_ctx->ctx_ep[i];
1084
1085 if (input_ctx->ctx_input.dwInCtx0 &
1086 XHCI_INCTX_0_DROP_MASK(i)) {
1087 DPRINTF((" config ep - dropping ep %d", i));
1088 pci_xhci_disable_ep(dev, i);
1089 }
1090
1091 if (input_ctx->ctx_input.dwInCtx1 &
1092 XHCI_INCTX_1_ADD_MASK(i)) {
1093 iep_ctx = &input_ctx->ctx_ep[i];
1094
1095 DPRINTF((" enable ep[%d] %08x %08x %016lx %08x",
1096 i, iep_ctx->dwEpCtx0, iep_ctx->dwEpCtx1,
1097 iep_ctx->qwEpCtx2, iep_ctx->dwEpCtx4));
1098
1099 memcpy(ep_ctx, iep_ctx, sizeof(struct xhci_endp_ctx));
1100
1101 pci_xhci_init_ep(dev, i);
1102
1103 /* ep state */
1104 ep_ctx->dwEpCtx0 = FIELD_REPLACE(
1105 ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0);
1106 }
1107 }
1108
1109 /* slot state to configured */
1110 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE(
1111 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_CONFIGURED, 0x1F, 27);
1112 dev_ctx->ctx_slot.dwSctx0 = FIELD_COPY(
1113 dev_ctx->ctx_slot.dwSctx0, input_ctx->ctx_slot.dwSctx0, 0x1F, 27);
1114 dev->dev_slotstate = XHCI_ST_CONFIGURED;
1115
1116 DPRINTF(("EP configured; slot %u [0]=0x%08x [1]=0x%08x [2]=0x%08x "
1117 "[3]=0x%08x",
1118 slot, dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
1119 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1120
1121 done:
1122 return (cmderr);
1123 }
1124
1125 static uint32_t
pci_xhci_cmd_reset_ep(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)1126 pci_xhci_cmd_reset_ep(struct pci_xhci_softc *sc, uint32_t slot,
1127 struct xhci_trb *trb)
1128 {
1129 struct pci_xhci_dev_emu *dev;
1130 struct pci_xhci_dev_ep *devep;
1131 struct xhci_dev_ctx *dev_ctx;
1132 struct xhci_endp_ctx *ep_ctx;
1133 uint32_t cmderr, epid;
1134 uint32_t type;
1135
1136 epid = XHCI_TRB_3_EP_GET(trb->dwTrb3);
1137
1138 DPRINTF(("pci_xhci: reset ep %u: slot %u", epid, slot));
1139
1140 cmderr = XHCI_TRB_ERROR_SUCCESS;
1141
1142 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);
1143
1144 dev = XHCI_SLOTDEV_PTR(sc, slot);
1145 assert(dev != NULL);
1146
1147 if (type == XHCI_TRB_TYPE_STOP_EP &&
1148 (trb->dwTrb3 & XHCI_TRB_3_SUSP_EP_BIT) != 0) {
1149 /* XXX suspend endpoint for 10ms */
1150 }
1151
1152 if (epid < 1 || epid > 31) {
1153 DPRINTF(("pci_xhci: reset ep: invalid epid %u", epid));
1154 cmderr = XHCI_TRB_ERROR_TRB;
1155 goto done;
1156 }
1157
1158 devep = &dev->eps[epid];
1159 if (devep->ep_xfer != NULL)
1160 USB_DATA_XFER_RESET(devep->ep_xfer);
1161
1162 dev_ctx = dev->dev_ctx;
1163 assert(dev_ctx != NULL);
1164
1165 ep_ctx = &dev_ctx->ctx_ep[epid];
1166
1167 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED;
1168
1169 if (devep->ep_MaxPStreams == 0)
1170 ep_ctx->qwEpCtx2 = devep->ep_ringaddr | devep->ep_ccs;
1171
1172 DPRINTF(("pci_xhci: reset ep[%u] %08x %08x %016lx %08x",
1173 epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2,
1174 ep_ctx->dwEpCtx4));
1175
1176 if (type == XHCI_TRB_TYPE_RESET_EP &&
1177 (dev->dev_ue->ue_reset == NULL ||
1178 dev->dev_ue->ue_reset(dev->dev_sc) < 0)) {
1179 cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON;
1180 goto done;
1181 }
1182
1183 done:
1184 return (cmderr);
1185 }
1186
1187
1188 static uint32_t
pci_xhci_find_stream(struct pci_xhci_softc * sc,struct xhci_endp_ctx * ep,struct pci_xhci_dev_ep * devep,uint32_t streamid)1189 pci_xhci_find_stream(struct pci_xhci_softc *sc, struct xhci_endp_ctx *ep,
1190 struct pci_xhci_dev_ep *devep, uint32_t streamid)
1191 {
1192 struct xhci_stream_ctx *sctx;
1193
1194 if (devep->ep_MaxPStreams == 0)
1195 return (XHCI_TRB_ERROR_TRB);
1196
1197 if (devep->ep_MaxPStreams > XHCI_STREAMS_MAX)
1198 return (XHCI_TRB_ERROR_INVALID_SID);
1199
1200 if (XHCI_EPCTX_0_LSA_GET(ep->dwEpCtx0) == 0) {
1201 DPRINTF(("pci_xhci: find_stream; LSA bit not set"));
1202 return (XHCI_TRB_ERROR_INVALID_SID);
1203 }
1204
1205 /* only support primary stream */
1206 if (streamid > devep->ep_MaxPStreams)
1207 return (XHCI_TRB_ERROR_STREAM_TYPE);
1208
1209 sctx = (struct xhci_stream_ctx *)XHCI_GADDR(sc, ep->qwEpCtx2 & ~0xFUL) +
1210 streamid;
1211 if (!XHCI_SCTX_0_SCT_GET(sctx->qwSctx0))
1212 return (XHCI_TRB_ERROR_STREAM_TYPE);
1213
1214 return (XHCI_TRB_ERROR_SUCCESS);
1215 }
1216
1217
1218 static uint32_t
pci_xhci_cmd_set_tr(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)1219 pci_xhci_cmd_set_tr(struct pci_xhci_softc *sc, uint32_t slot,
1220 struct xhci_trb *trb)
1221 {
1222 struct pci_xhci_dev_emu *dev;
1223 struct pci_xhci_dev_ep *devep;
1224 struct xhci_dev_ctx *dev_ctx;
1225 struct xhci_endp_ctx *ep_ctx;
1226 uint32_t cmderr, epid;
1227 uint32_t streamid;
1228
1229 cmderr = XHCI_TRB_ERROR_SUCCESS;
1230
1231 dev = XHCI_SLOTDEV_PTR(sc, slot);
1232 assert(dev != NULL);
1233
1234 DPRINTF(("pci_xhci set_tr: new-tr x%016lx, SCT %u DCS %u",
1235 (trb->qwTrb0 & ~0xF), (uint32_t)((trb->qwTrb0 >> 1) & 0x7),
1236 (uint32_t)(trb->qwTrb0 & 0x1)));
1237 DPRINTF((" stream-id %u, slot %u, epid %u, C %u",
1238 (trb->dwTrb2 >> 16) & 0xFFFF,
1239 XHCI_TRB_3_SLOT_GET(trb->dwTrb3),
1240 XHCI_TRB_3_EP_GET(trb->dwTrb3), trb->dwTrb3 & 0x1));
1241
1242 epid = XHCI_TRB_3_EP_GET(trb->dwTrb3);
1243 if (epid < 1 || epid > 31) {
1244 DPRINTF(("pci_xhci: set_tr_deq: invalid epid %u", epid));
1245 cmderr = XHCI_TRB_ERROR_TRB;
1246 goto done;
1247 }
1248
1249 dev_ctx = dev->dev_ctx;
1250 assert(dev_ctx != NULL);
1251
1252 ep_ctx = &dev_ctx->ctx_ep[epid];
1253 devep = &dev->eps[epid];
1254
1255 switch (XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0)) {
1256 case XHCI_ST_EPCTX_STOPPED:
1257 case XHCI_ST_EPCTX_ERROR:
1258 break;
1259 default:
1260 DPRINTF(("pci_xhci cmd set_tr invalid state %x",
1261 XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0)));
1262 cmderr = XHCI_TRB_ERROR_CONTEXT_STATE;
1263 goto done;
1264 }
1265
1266 streamid = XHCI_TRB_2_STREAM_GET(trb->dwTrb2);
1267 if (devep->ep_MaxPStreams > 0) {
1268 cmderr = pci_xhci_find_stream(sc, ep_ctx, devep, streamid);
1269 if (cmderr == XHCI_TRB_ERROR_SUCCESS) {
1270 assert(devep->ep_sctx != NULL);
1271
1272 devep->ep_sctx[streamid].qwSctx0 = trb->qwTrb0;
1273 devep->ep_sctx_trbs[streamid].ringaddr =
1274 trb->qwTrb0 & ~0xF;
1275 devep->ep_sctx_trbs[streamid].ccs =
1276 XHCI_EPCTX_2_DCS_GET(trb->qwTrb0);
1277 }
1278 } else {
1279 if (streamid != 0) {
1280 DPRINTF(("pci_xhci cmd set_tr streamid %x != 0",
1281 streamid));
1282 }
1283 ep_ctx->qwEpCtx2 = trb->qwTrb0 & ~0xFUL;
1284 devep->ep_ringaddr = ep_ctx->qwEpCtx2 & ~0xFUL;
1285 devep->ep_ccs = trb->qwTrb0 & 0x1;
1286 devep->ep_tr = XHCI_GADDR(sc, devep->ep_ringaddr);
1287
1288 DPRINTF(("pci_xhci set_tr first TRB:"));
1289 pci_xhci_dump_trb(devep->ep_tr);
1290 }
1291 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED;
1292
1293 done:
1294 return (cmderr);
1295 }
1296
1297 static uint32_t
pci_xhci_cmd_eval_ctx(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)1298 pci_xhci_cmd_eval_ctx(struct pci_xhci_softc *sc, uint32_t slot,
1299 struct xhci_trb *trb)
1300 {
1301 struct xhci_input_dev_ctx *input_ctx;
1302 struct xhci_slot_ctx *islot_ctx;
1303 struct xhci_dev_ctx *dev_ctx;
1304 struct xhci_endp_ctx *ep0_ctx;
1305 uint32_t cmderr;
1306
1307 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);
1308 islot_ctx = &input_ctx->ctx_slot;
1309 ep0_ctx = &input_ctx->ctx_ep[1];
1310
1311 cmderr = XHCI_TRB_ERROR_SUCCESS;
1312 DPRINTF(("pci_xhci: eval ctx, input ctl: D 0x%08x A 0x%08x,",
1313 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1));
1314 DPRINTF((" slot %08x %08x %08x %08x",
1315 islot_ctx->dwSctx0, islot_ctx->dwSctx1,
1316 islot_ctx->dwSctx2, islot_ctx->dwSctx3));
1317 DPRINTF((" ep0 %08x %08x %016lx %08x",
1318 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
1319 ep0_ctx->dwEpCtx4));
1320
1321 /* this command expects drop-ctx=0 & add-ctx=slot+ep0 */
1322 if ((input_ctx->ctx_input.dwInCtx0 != 0) ||
1323 (input_ctx->ctx_input.dwInCtx1 & 0x03) == 0) {
1324 DPRINTF(("pci_xhci: eval ctx, input ctl invalid"));
1325 cmderr = XHCI_TRB_ERROR_TRB;
1326 goto done;
1327 }
1328
1329 /* assign address to slot; in this emulation, slot_id = address */
1330 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1331
1332 DPRINTF(("pci_xhci: eval ctx, dev ctx"));
1333 DPRINTF((" slot %08x %08x %08x %08x",
1334 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
1335 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1336
1337 if (input_ctx->ctx_input.dwInCtx1 & 0x01) { /* slot ctx */
1338 /* set max exit latency */
1339 dev_ctx->ctx_slot.dwSctx1 = FIELD_COPY(
1340 dev_ctx->ctx_slot.dwSctx1, input_ctx->ctx_slot.dwSctx1,
1341 0xFFFF, 0);
1342
1343 /* set interrupter target */
1344 dev_ctx->ctx_slot.dwSctx2 = FIELD_COPY(
1345 dev_ctx->ctx_slot.dwSctx2, input_ctx->ctx_slot.dwSctx2,
1346 0x3FF, 22);
1347 }
1348 if (input_ctx->ctx_input.dwInCtx1 & 0x02) { /* control ctx */
1349 /* set max packet size */
1350 dev_ctx->ctx_ep[1].dwEpCtx1 = FIELD_COPY(
1351 dev_ctx->ctx_ep[1].dwEpCtx1, ep0_ctx->dwEpCtx1,
1352 0xFFFF, 16);
1353
1354 ep0_ctx = &dev_ctx->ctx_ep[1];
1355 }
1356
1357 DPRINTF(("pci_xhci: eval ctx, output ctx"));
1358 DPRINTF((" slot %08x %08x %08x %08x",
1359 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
1360 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1361 DPRINTF((" ep0 %08x %08x %016lx %08x",
1362 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
1363 ep0_ctx->dwEpCtx4));
1364
1365 done:
1366 return (cmderr);
1367 }
1368
1369 static int
pci_xhci_complete_commands(struct pci_xhci_softc * sc)1370 pci_xhci_complete_commands(struct pci_xhci_softc *sc)
1371 {
1372 struct xhci_trb evtrb;
1373 struct xhci_trb *trb;
1374 uint64_t crcr;
1375 uint32_t ccs; /* cycle state (XHCI 4.9.2) */
1376 uint32_t type;
1377 uint32_t slot;
1378 uint32_t cmderr;
1379 int error;
1380
1381 error = 0;
1382 sc->opregs.crcr |= XHCI_CRCR_LO_CRR;
1383
1384 trb = sc->opregs.cr_p;
1385 ccs = sc->opregs.crcr & XHCI_CRCR_LO_RCS;
1386 crcr = sc->opregs.crcr & ~0xF;
1387
1388 while (1) {
1389 sc->opregs.cr_p = trb;
1390
1391 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);
1392
1393 if ((trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT) !=
1394 (ccs & XHCI_TRB_3_CYCLE_BIT))
1395 break;
1396
1397 DPRINTF(("pci_xhci: cmd type 0x%x, Trb0 x%016lx dwTrb2 x%08x"
1398 " dwTrb3 x%08x, TRB_CYCLE %u/ccs %u",
1399 type, trb->qwTrb0, trb->dwTrb2, trb->dwTrb3,
1400 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT, ccs));
1401
1402 cmderr = XHCI_TRB_ERROR_SUCCESS;
1403 evtrb.dwTrb2 = 0;
1404 evtrb.dwTrb3 = (ccs & XHCI_TRB_3_CYCLE_BIT) |
1405 XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_CMD_COMPLETE);
1406 slot = 0;
1407
1408 switch (type) {
1409 case XHCI_TRB_TYPE_LINK: /* 0x06 */
1410 if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT)
1411 ccs ^= XHCI_CRCR_LO_RCS;
1412 break;
1413
1414 case XHCI_TRB_TYPE_ENABLE_SLOT: /* 0x09 */
1415 cmderr = pci_xhci_cmd_enable_slot(sc, &slot);
1416 break;
1417
1418 case XHCI_TRB_TYPE_DISABLE_SLOT: /* 0x0A */
1419 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1420 cmderr = pci_xhci_cmd_disable_slot(sc, slot);
1421 break;
1422
1423 case XHCI_TRB_TYPE_ADDRESS_DEVICE: /* 0x0B */
1424 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1425 cmderr = pci_xhci_cmd_address_device(sc, slot, trb);
1426 break;
1427
1428 case XHCI_TRB_TYPE_CONFIGURE_EP: /* 0x0C */
1429 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1430 cmderr = pci_xhci_cmd_config_ep(sc, slot, trb);
1431 break;
1432
1433 case XHCI_TRB_TYPE_EVALUATE_CTX: /* 0x0D */
1434 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1435 cmderr = pci_xhci_cmd_eval_ctx(sc, slot, trb);
1436 break;
1437
1438 case XHCI_TRB_TYPE_RESET_EP: /* 0x0E */
1439 DPRINTF(("Reset Endpoint on slot %d", slot));
1440 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1441 cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb);
1442 break;
1443
1444 case XHCI_TRB_TYPE_STOP_EP: /* 0x0F */
1445 DPRINTF(("Stop Endpoint on slot %d", slot));
1446 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1447 cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb);
1448 break;
1449
1450 case XHCI_TRB_TYPE_SET_TR_DEQUEUE: /* 0x10 */
1451 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1452 cmderr = pci_xhci_cmd_set_tr(sc, slot, trb);
1453 break;
1454
1455 case XHCI_TRB_TYPE_RESET_DEVICE: /* 0x11 */
1456 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1457 cmderr = pci_xhci_cmd_reset_device(sc, slot);
1458 break;
1459
1460 case XHCI_TRB_TYPE_FORCE_EVENT: /* 0x12 */
1461 /* TODO: */
1462 break;
1463
1464 case XHCI_TRB_TYPE_NEGOTIATE_BW: /* 0x13 */
1465 break;
1466
1467 case XHCI_TRB_TYPE_SET_LATENCY_TOL: /* 0x14 */
1468 break;
1469
1470 case XHCI_TRB_TYPE_GET_PORT_BW: /* 0x15 */
1471 break;
1472
1473 case XHCI_TRB_TYPE_FORCE_HEADER: /* 0x16 */
1474 break;
1475
1476 case XHCI_TRB_TYPE_NOOP_CMD: /* 0x17 */
1477 break;
1478
1479 default:
1480 DPRINTF(("pci_xhci: unsupported cmd %x", type));
1481 break;
1482 }
1483
1484 if (type != XHCI_TRB_TYPE_LINK) {
1485 /*
1486 * insert command completion event and assert intr
1487 */
1488 evtrb.qwTrb0 = crcr;
1489 evtrb.dwTrb2 |= XHCI_TRB_2_ERROR_SET(cmderr);
1490 evtrb.dwTrb3 |= XHCI_TRB_3_SLOT_SET(slot);
1491 DPRINTF(("pci_xhci: command 0x%x result: 0x%x",
1492 type, cmderr));
1493 pci_xhci_insert_event(sc, &evtrb, 1);
1494 }
1495
1496 trb = pci_xhci_trb_next(sc, trb, &crcr);
1497 }
1498
1499 sc->opregs.crcr = crcr | (sc->opregs.crcr & XHCI_CRCR_LO_CA) | ccs;
1500 sc->opregs.crcr &= ~XHCI_CRCR_LO_CRR;
1501 return (error);
1502 }
1503
1504 static void
pci_xhci_dump_trb(struct xhci_trb * trb)1505 pci_xhci_dump_trb(struct xhci_trb *trb)
1506 {
1507 static const char *trbtypes[] = {
1508 "RESERVED",
1509 "NORMAL",
1510 "SETUP_STAGE",
1511 "DATA_STAGE",
1512 "STATUS_STAGE",
1513 "ISOCH",
1514 "LINK",
1515 "EVENT_DATA",
1516 "NOOP",
1517 "ENABLE_SLOT",
1518 "DISABLE_SLOT",
1519 "ADDRESS_DEVICE",
1520 "CONFIGURE_EP",
1521 "EVALUATE_CTX",
1522 "RESET_EP",
1523 "STOP_EP",
1524 "SET_TR_DEQUEUE",
1525 "RESET_DEVICE",
1526 "FORCE_EVENT",
1527 "NEGOTIATE_BW",
1528 "SET_LATENCY_TOL",
1529 "GET_PORT_BW",
1530 "FORCE_HEADER",
1531 "NOOP_CMD"
1532 };
1533 uint32_t type;
1534
1535 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);
1536 DPRINTF(("pci_xhci: trb[@%p] type x%02x %s 0:x%016lx 2:x%08x 3:x%08x",
1537 trb, type,
1538 type <= XHCI_TRB_TYPE_NOOP_CMD ? trbtypes[type] : "INVALID",
1539 trb->qwTrb0, trb->dwTrb2, trb->dwTrb3));
1540 }
1541
1542 static int
pci_xhci_xfer_complete(struct pci_xhci_softc * sc,struct usb_data_xfer * xfer,uint32_t slot,uint32_t epid,int * do_intr)1543 pci_xhci_xfer_complete(struct pci_xhci_softc *sc, struct usb_data_xfer *xfer,
1544 uint32_t slot, uint32_t epid, int *do_intr)
1545 {
1546 struct pci_xhci_dev_emu *dev;
1547 struct pci_xhci_dev_ep *devep;
1548 struct xhci_dev_ctx *dev_ctx;
1549 struct xhci_endp_ctx *ep_ctx;
1550 struct xhci_trb *trb;
1551 struct xhci_trb evtrb;
1552 uint32_t trbflags;
1553 uint32_t edtla;
1554 int i, err;
1555
1556 dev = XHCI_SLOTDEV_PTR(sc, slot);
1557 devep = &dev->eps[epid];
1558 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1559
1560 assert(dev_ctx != NULL);
1561
1562 ep_ctx = &dev_ctx->ctx_ep[epid];
1563
1564 err = XHCI_TRB_ERROR_SUCCESS;
1565 *do_intr = 0;
1566 edtla = 0;
1567
1568 /* go through list of TRBs and insert event(s) */
1569 for (i = xfer->head; xfer->ndata > 0; ) {
1570 evtrb.qwTrb0 = (uint64_t)xfer->data[i].hci_data;
1571 trb = XHCI_GADDR(sc, evtrb.qwTrb0);
1572 trbflags = trb->dwTrb3;
1573
1574 DPRINTF(("pci_xhci: xfer[%d] done?%u:%d trb %x %016lx %x "
1575 "(err %d) IOC?%d",
1576 i, xfer->data[i].processed, xfer->data[i].blen,
1577 XHCI_TRB_3_TYPE_GET(trbflags), evtrb.qwTrb0,
1578 trbflags, err,
1579 trb->dwTrb3 & XHCI_TRB_3_IOC_BIT ? 1 : 0));
1580
1581 if (!xfer->data[i].processed) {
1582 xfer->head = i;
1583 break;
1584 }
1585
1586 xfer->ndata--;
1587 edtla += xfer->data[i].bdone;
1588
1589 trb->dwTrb3 = (trb->dwTrb3 & ~0x1) | (xfer->data[i].ccs);
1590
1591 pci_xhci_update_ep_ring(sc, dev, devep, ep_ctx,
1592 xfer->data[i].streamid, xfer->data[i].trbnext,
1593 xfer->data[i].ccs);
1594
1595 /* Only interrupt if IOC or short packet */
1596 if (!(trb->dwTrb3 & XHCI_TRB_3_IOC_BIT) &&
1597 !((err == XHCI_TRB_ERROR_SHORT_PKT) &&
1598 (trb->dwTrb3 & XHCI_TRB_3_ISP_BIT))) {
1599
1600 i = (i + 1) % USB_MAX_XFER_BLOCKS;
1601 continue;
1602 }
1603
1604 evtrb.dwTrb2 = XHCI_TRB_2_ERROR_SET(err) |
1605 XHCI_TRB_2_REM_SET(xfer->data[i].blen);
1606
1607 evtrb.dwTrb3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_TRANSFER) |
1608 XHCI_TRB_3_SLOT_SET(slot) | XHCI_TRB_3_EP_SET(epid);
1609
1610 if (XHCI_TRB_3_TYPE_GET(trbflags) == XHCI_TRB_TYPE_EVENT_DATA) {
1611 DPRINTF(("pci_xhci EVENT_DATA edtla %u", edtla));
1612 evtrb.qwTrb0 = trb->qwTrb0;
1613 evtrb.dwTrb2 = (edtla & 0xFFFFF) |
1614 XHCI_TRB_2_ERROR_SET(err);
1615 evtrb.dwTrb3 |= XHCI_TRB_3_ED_BIT;
1616 edtla = 0;
1617 }
1618
1619 *do_intr = 1;
1620
1621 err = pci_xhci_insert_event(sc, &evtrb, 0);
1622 if (err != XHCI_TRB_ERROR_SUCCESS) {
1623 break;
1624 }
1625
1626 i = (i + 1) % USB_MAX_XFER_BLOCKS;
1627 }
1628
1629 return (err);
1630 }
1631
1632 static void
pci_xhci_update_ep_ring(struct pci_xhci_softc * sc,struct pci_xhci_dev_emu * dev __unused,struct pci_xhci_dev_ep * devep,struct xhci_endp_ctx * ep_ctx,uint32_t streamid,uint64_t ringaddr,int ccs)1633 pci_xhci_update_ep_ring(struct pci_xhci_softc *sc,
1634 struct pci_xhci_dev_emu *dev __unused, struct pci_xhci_dev_ep *devep,
1635 struct xhci_endp_ctx *ep_ctx, uint32_t streamid, uint64_t ringaddr, int ccs)
1636 {
1637
1638 if (devep->ep_MaxPStreams != 0) {
1639 devep->ep_sctx[streamid].qwSctx0 = (ringaddr & ~0xFUL) |
1640 (ccs & 0x1);
1641
1642 devep->ep_sctx_trbs[streamid].ringaddr = ringaddr & ~0xFUL;
1643 devep->ep_sctx_trbs[streamid].ccs = ccs & 0x1;
1644 ep_ctx->qwEpCtx2 = (ep_ctx->qwEpCtx2 & ~0x1) | (ccs & 0x1);
1645
1646 DPRINTF(("xhci update ep-ring stream %d, addr %lx",
1647 streamid, devep->ep_sctx[streamid].qwSctx0));
1648 } else {
1649 devep->ep_ringaddr = ringaddr & ~0xFUL;
1650 devep->ep_ccs = ccs & 0x1;
1651 devep->ep_tr = XHCI_GADDR(sc, ringaddr & ~0xFUL);
1652 ep_ctx->qwEpCtx2 = (ringaddr & ~0xFUL) | (ccs & 0x1);
1653
1654 DPRINTF(("xhci update ep-ring, addr %lx",
1655 (devep->ep_ringaddr | devep->ep_ccs)));
1656 }
1657 }
1658
1659 /*
1660 * Outstanding transfer still in progress (device NAK'd earlier) so retry
1661 * the transfer again to see if it succeeds.
1662 */
1663 static int
pci_xhci_try_usb_xfer(struct pci_xhci_softc * sc,struct pci_xhci_dev_emu * dev,struct pci_xhci_dev_ep * devep,struct xhci_endp_ctx * ep_ctx,uint32_t slot,uint32_t epid)1664 pci_xhci_try_usb_xfer(struct pci_xhci_softc *sc,
1665 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep,
1666 struct xhci_endp_ctx *ep_ctx, uint32_t slot, uint32_t epid)
1667 {
1668 struct usb_data_xfer *xfer;
1669 int err;
1670 int do_intr;
1671
1672 ep_ctx->dwEpCtx0 = FIELD_REPLACE(
1673 ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0);
1674
1675 err = 0;
1676 do_intr = 0;
1677
1678 xfer = devep->ep_xfer;
1679 #ifdef __FreeBSD__
1680 USB_DATA_XFER_LOCK(xfer);
1681 #else
1682 /*
1683 * At least one caller needs to hold this lock across the call to this
1684 * function and other code. To avoid deadlock from a recursive mutex
1685 * enter, we ensure that all callers hold this lock.
1686 */
1687 assert(USB_DATA_XFER_LOCK_HELD(xfer));
1688 #endif
1689
1690 /* outstanding requests queued up */
1691 if (dev->dev_ue->ue_data != NULL) {
1692 err = dev->dev_ue->ue_data(dev->dev_sc, xfer,
1693 epid & 0x1 ? USB_XFER_IN : USB_XFER_OUT, epid/2);
1694 if (err == USB_ERR_CANCELLED) {
1695 if (USB_DATA_GET_ERRCODE(&xfer->data[xfer->head]) ==
1696 USB_NAK)
1697 err = XHCI_TRB_ERROR_SUCCESS;
1698 } else {
1699 err = pci_xhci_xfer_complete(sc, xfer, slot, epid,
1700 &do_intr);
1701 if (err == XHCI_TRB_ERROR_SUCCESS && do_intr) {
1702 pci_xhci_assert_interrupt(sc);
1703 }
1704
1705
1706 /* XXX should not do it if error? */
1707 USB_DATA_XFER_RESET(xfer);
1708 }
1709 }
1710
1711 #ifdef __FreeBSD__
1712 USB_DATA_XFER_UNLOCK(xfer);
1713 #endif
1714
1715 return (err);
1716 }
1717
1718
1719 static int
pci_xhci_handle_transfer(struct pci_xhci_softc * sc,struct pci_xhci_dev_emu * dev,struct pci_xhci_dev_ep * devep,struct xhci_endp_ctx * ep_ctx,struct xhci_trb * trb,uint32_t slot,uint32_t epid,uint64_t addr,uint32_t ccs,uint32_t streamid)1720 pci_xhci_handle_transfer(struct pci_xhci_softc *sc,
1721 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep,
1722 struct xhci_endp_ctx *ep_ctx, struct xhci_trb *trb, uint32_t slot,
1723 uint32_t epid, uint64_t addr, uint32_t ccs, uint32_t streamid)
1724 {
1725 struct xhci_trb *setup_trb;
1726 struct usb_data_xfer *xfer;
1727 struct usb_data_xfer_block *xfer_block;
1728 uint64_t val;
1729 uint32_t trbflags;
1730 int do_intr, err;
1731 int do_retry;
1732
1733 ep_ctx->dwEpCtx0 = FIELD_REPLACE(ep_ctx->dwEpCtx0,
1734 XHCI_ST_EPCTX_RUNNING, 0x7, 0);
1735
1736 xfer = devep->ep_xfer;
1737 USB_DATA_XFER_LOCK(xfer);
1738
1739 DPRINTF(("pci_xhci handle_transfer slot %u", slot));
1740
1741 retry:
1742 err = XHCI_TRB_ERROR_INVALID;
1743 do_retry = 0;
1744 do_intr = 0;
1745 setup_trb = NULL;
1746
1747 while (1) {
1748 pci_xhci_dump_trb(trb);
1749
1750 trbflags = trb->dwTrb3;
1751
1752 if (XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK &&
1753 (trbflags & XHCI_TRB_3_CYCLE_BIT) !=
1754 (ccs & XHCI_TRB_3_CYCLE_BIT)) {
1755 DPRINTF(("Cycle-bit changed trbflags %x, ccs %x",
1756 trbflags & XHCI_TRB_3_CYCLE_BIT, ccs));
1757 break;
1758 }
1759
1760 xfer_block = NULL;
1761
1762 switch (XHCI_TRB_3_TYPE_GET(trbflags)) {
1763 case XHCI_TRB_TYPE_LINK:
1764 if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT)
1765 ccs ^= 0x1;
1766
1767 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1768 (void *)addr, ccs);
1769 xfer_block->processed = 1;
1770 break;
1771
1772 case XHCI_TRB_TYPE_SETUP_STAGE:
1773 if ((trbflags & XHCI_TRB_3_IDT_BIT) == 0 ||
1774 XHCI_TRB_2_BYTES_GET(trb->dwTrb2) != 8) {
1775 DPRINTF(("pci_xhci: invalid setup trb"));
1776 err = XHCI_TRB_ERROR_TRB;
1777 goto errout;
1778 }
1779 setup_trb = trb;
1780
1781 val = trb->qwTrb0;
1782 if (!xfer->ureq)
1783 xfer->ureq = malloc(
1784 sizeof(struct usb_device_request));
1785 memcpy(xfer->ureq, &val,
1786 sizeof(struct usb_device_request));
1787
1788 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1789 (void *)addr, ccs);
1790 xfer_block->processed = 1;
1791 break;
1792
1793 case XHCI_TRB_TYPE_NORMAL:
1794 case XHCI_TRB_TYPE_ISOCH:
1795 if (setup_trb != NULL) {
1796 DPRINTF(("pci_xhci: trb not supposed to be in "
1797 "ctl scope"));
1798 err = XHCI_TRB_ERROR_TRB;
1799 goto errout;
1800 }
1801 /* fall through */
1802
1803 case XHCI_TRB_TYPE_DATA_STAGE:
1804 xfer_block = usb_data_xfer_append(xfer,
1805 (void *)(trbflags & XHCI_TRB_3_IDT_BIT ?
1806 &trb->qwTrb0 : XHCI_GADDR(sc, trb->qwTrb0)),
1807 trb->dwTrb2 & 0x1FFFF, (void *)addr, ccs);
1808 break;
1809
1810 case XHCI_TRB_TYPE_STATUS_STAGE:
1811 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1812 (void *)addr, ccs);
1813 break;
1814
1815 case XHCI_TRB_TYPE_NOOP:
1816 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1817 (void *)addr, ccs);
1818 xfer_block->processed = 1;
1819 break;
1820
1821 case XHCI_TRB_TYPE_EVENT_DATA:
1822 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1823 (void *)addr, ccs);
1824 if ((epid > 1) && (trbflags & XHCI_TRB_3_IOC_BIT)) {
1825 xfer_block->processed = 1;
1826 }
1827 break;
1828
1829 default:
1830 DPRINTF(("pci_xhci: handle xfer unexpected trb type "
1831 "0x%x",
1832 XHCI_TRB_3_TYPE_GET(trbflags)));
1833 err = XHCI_TRB_ERROR_TRB;
1834 goto errout;
1835 }
1836
1837 trb = pci_xhci_trb_next(sc, trb, &addr);
1838
1839 DPRINTF(("pci_xhci: next trb: 0x%lx", (uint64_t)trb));
1840
1841 if (xfer_block) {
1842 xfer_block->trbnext = addr;
1843 xfer_block->streamid = streamid;
1844 }
1845
1846 if (!setup_trb && !(trbflags & XHCI_TRB_3_CHAIN_BIT) &&
1847 XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK) {
1848 break;
1849 }
1850
1851 /* handle current batch that requires interrupt on complete */
1852 if (trbflags & XHCI_TRB_3_IOC_BIT) {
1853 DPRINTF(("pci_xhci: trb IOC bit set"));
1854 if (epid == 1)
1855 do_retry = 1;
1856 break;
1857 }
1858 }
1859
1860 DPRINTF(("pci_xhci[%d]: xfer->ndata %u", __LINE__, xfer->ndata));
1861
1862 if (xfer->ndata <= 0)
1863 goto errout;
1864
1865 if (epid == 1) {
1866 int usberr;
1867
1868 if (dev->dev_ue->ue_request != NULL)
1869 usberr = dev->dev_ue->ue_request(dev->dev_sc, xfer);
1870 else
1871 usberr = USB_ERR_NOT_STARTED;
1872 err = USB_TO_XHCI_ERR(usberr);
1873 if (err == XHCI_TRB_ERROR_SUCCESS ||
1874 err == XHCI_TRB_ERROR_STALL ||
1875 err == XHCI_TRB_ERROR_SHORT_PKT) {
1876 err = pci_xhci_xfer_complete(sc, xfer, slot, epid,
1877 &do_intr);
1878 if (err != XHCI_TRB_ERROR_SUCCESS)
1879 do_retry = 0;
1880 }
1881
1882 } else {
1883 /* handle data transfer */
1884 pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid);
1885 err = XHCI_TRB_ERROR_SUCCESS;
1886 }
1887
1888 errout:
1889 if (err == XHCI_TRB_ERROR_EV_RING_FULL)
1890 DPRINTF(("pci_xhci[%d]: event ring full", __LINE__));
1891
1892 if (!do_retry)
1893 USB_DATA_XFER_UNLOCK(xfer);
1894
1895 if (do_intr)
1896 pci_xhci_assert_interrupt(sc);
1897
1898 if (do_retry) {
1899 USB_DATA_XFER_RESET(xfer);
1900 DPRINTF(("pci_xhci[%d]: retry:continuing with next TRBs",
1901 __LINE__));
1902 goto retry;
1903 }
1904
1905 if (epid == 1)
1906 USB_DATA_XFER_RESET(xfer);
1907
1908 return (err);
1909 }
1910
1911 static void
pci_xhci_device_doorbell(struct pci_xhci_softc * sc,uint32_t slot,uint32_t epid,uint32_t streamid)1912 pci_xhci_device_doorbell(struct pci_xhci_softc *sc, uint32_t slot,
1913 uint32_t epid, uint32_t streamid)
1914 {
1915 struct pci_xhci_dev_emu *dev;
1916 struct pci_xhci_dev_ep *devep;
1917 struct xhci_dev_ctx *dev_ctx;
1918 struct xhci_endp_ctx *ep_ctx;
1919 struct pci_xhci_trb_ring *sctx_tr;
1920 struct xhci_trb *trb;
1921 uint64_t ringaddr;
1922 uint32_t ccs;
1923 int error;
1924
1925 DPRINTF(("pci_xhci doorbell slot %u epid %u stream %u",
1926 slot, epid, streamid));
1927
1928 if (slot == 0 || slot > XHCI_MAX_SLOTS) {
1929 DPRINTF(("pci_xhci: invalid doorbell slot %u", slot));
1930 return;
1931 }
1932
1933 if (epid == 0 || epid >= XHCI_MAX_ENDPOINTS) {
1934 DPRINTF(("pci_xhci: invalid endpoint %u", epid));
1935 return;
1936 }
1937
1938 dev = XHCI_SLOTDEV_PTR(sc, slot);
1939 devep = &dev->eps[epid];
1940 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1941 if (!dev_ctx) {
1942 return;
1943 }
1944 ep_ctx = &dev_ctx->ctx_ep[epid];
1945
1946 sctx_tr = NULL;
1947
1948 DPRINTF(("pci_xhci: device doorbell ep[%u] %08x %08x %016lx %08x",
1949 epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2,
1950 ep_ctx->dwEpCtx4));
1951
1952 if (ep_ctx->qwEpCtx2 == 0)
1953 return;
1954
1955 /* handle pending transfers */
1956 if (devep->ep_xfer->ndata > 0) {
1957 #ifndef __FreeBSD__
1958 USB_DATA_XFER_LOCK(devep->ep_xfer);
1959 #endif
1960 pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid);
1961 #ifndef __FreeBSD__
1962 USB_DATA_XFER_UNLOCK(devep->ep_xfer);
1963 #endif
1964 return;
1965 }
1966
1967 /* get next trb work item */
1968 if (devep->ep_MaxPStreams != 0) {
1969 /*
1970 * Stream IDs of 0, 65535 (any stream), and 65534
1971 * (prime) are invalid.
1972 */
1973 if (streamid == 0 || streamid == 65534 || streamid == 65535) {
1974 DPRINTF(("pci_xhci: invalid stream %u", streamid));
1975 return;
1976 }
1977
1978 error = pci_xhci_find_stream(sc, ep_ctx, devep, streamid);
1979 if (error != XHCI_TRB_ERROR_SUCCESS) {
1980 DPRINTF(("pci_xhci: invalid stream %u: %d",
1981 streamid, error));
1982 return;
1983 }
1984 sctx_tr = &devep->ep_sctx_trbs[streamid];
1985 ringaddr = sctx_tr->ringaddr;
1986 ccs = sctx_tr->ccs;
1987 trb = XHCI_GADDR(sc, sctx_tr->ringaddr & ~0xFUL);
1988 DPRINTF(("doorbell, stream %u, ccs %lx, trb ccs %x",
1989 streamid, ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT,
1990 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT));
1991 } else {
1992 if (streamid != 0) {
1993 DPRINTF(("pci_xhci: invalid stream %u", streamid));
1994 return;
1995 }
1996 ringaddr = devep->ep_ringaddr;
1997 ccs = devep->ep_ccs;
1998 trb = devep->ep_tr;
1999 DPRINTF(("doorbell, ccs %lx, trb ccs %x",
2000 ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT,
2001 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT));
2002 }
2003
2004 if (XHCI_TRB_3_TYPE_GET(trb->dwTrb3) == 0) {
2005 DPRINTF(("pci_xhci: ring %lx trb[%lx] EP %u is RESERVED?",
2006 ep_ctx->qwEpCtx2, devep->ep_ringaddr, epid));
2007 return;
2008 }
2009
2010 pci_xhci_handle_transfer(sc, dev, devep, ep_ctx, trb, slot, epid,
2011 ringaddr, ccs, streamid);
2012 }
2013
2014 static void
pci_xhci_dbregs_write(struct pci_xhci_softc * sc,uint64_t offset,uint64_t value)2015 pci_xhci_dbregs_write(struct pci_xhci_softc *sc, uint64_t offset,
2016 uint64_t value)
2017 {
2018
2019 offset = (offset - sc->dboff) / sizeof(uint32_t);
2020
2021 DPRINTF(("pci_xhci: doorbell write offset 0x%lx: 0x%lx",
2022 offset, value));
2023
2024 if (XHCI_HALTED(sc)) {
2025 DPRINTF(("pci_xhci: controller halted"));
2026 return;
2027 }
2028
2029 if (offset == 0)
2030 pci_xhci_complete_commands(sc);
2031 else if (sc->portregs != NULL)
2032 pci_xhci_device_doorbell(sc, offset,
2033 XHCI_DB_TARGET_GET(value), XHCI_DB_SID_GET(value));
2034 }
2035
2036 static void
pci_xhci_rtsregs_write(struct pci_xhci_softc * sc,uint64_t offset,uint64_t value)2037 pci_xhci_rtsregs_write(struct pci_xhci_softc *sc, uint64_t offset,
2038 uint64_t value)
2039 {
2040 struct pci_xhci_rtsregs *rts;
2041
2042 offset -= sc->rtsoff;
2043
2044 if (offset == 0) {
2045 DPRINTF(("pci_xhci attempted write to MFINDEX"));
2046 return;
2047 }
2048
2049 DPRINTF(("pci_xhci: runtime regs write offset 0x%lx: 0x%lx",
2050 offset, value));
2051
2052 offset -= 0x20; /* start of intrreg */
2053
2054 rts = &sc->rtsregs;
2055
2056 switch (offset) {
2057 case 0x00:
2058 if (value & XHCI_IMAN_INTR_PEND)
2059 rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND;
2060 rts->intrreg.iman = (value & XHCI_IMAN_INTR_ENA) |
2061 (rts->intrreg.iman & XHCI_IMAN_INTR_PEND);
2062
2063 if (!(value & XHCI_IMAN_INTR_ENA))
2064 pci_xhci_deassert_interrupt(sc);
2065
2066 break;
2067
2068 case 0x04:
2069 rts->intrreg.imod = value;
2070 break;
2071
2072 case 0x08:
2073 rts->intrreg.erstsz = value & 0xFFFF;
2074 break;
2075
2076 case 0x10:
2077 /* ERSTBA low bits */
2078 rts->intrreg.erstba = MASK_64_HI(sc->rtsregs.intrreg.erstba) |
2079 (value & ~0x3F);
2080 break;
2081
2082 case 0x14:
2083 /* ERSTBA high bits */
2084 rts->intrreg.erstba = (value << 32) |
2085 MASK_64_LO(sc->rtsregs.intrreg.erstba);
2086
2087 rts->erstba_p = XHCI_GADDR(sc,
2088 sc->rtsregs.intrreg.erstba & ~0x3FUL);
2089
2090 rts->erst_p = XHCI_GADDR(sc,
2091 sc->rtsregs.erstba_p->qwEvrsTablePtr & ~0x3FUL);
2092
2093 rts->er_enq_idx = 0;
2094 rts->er_events_cnt = 0;
2095
2096 DPRINTF(("pci_xhci: wr erstba erst (%p) ptr 0x%lx, sz %u",
2097 rts->erstba_p,
2098 rts->erstba_p->qwEvrsTablePtr,
2099 rts->erstba_p->dwEvrsTableSize));
2100 break;
2101
2102 case 0x18:
2103 /* ERDP low bits */
2104 rts->intrreg.erdp =
2105 MASK_64_HI(sc->rtsregs.intrreg.erdp) |
2106 (rts->intrreg.erdp & XHCI_ERDP_LO_BUSY) |
2107 (value & ~0xF);
2108 if (value & XHCI_ERDP_LO_BUSY) {
2109 rts->intrreg.erdp &= ~XHCI_ERDP_LO_BUSY;
2110 rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND;
2111 }
2112
2113 rts->er_deq_seg = XHCI_ERDP_LO_SINDEX(value);
2114
2115 break;
2116
2117 case 0x1C:
2118 /* ERDP high bits */
2119 rts->intrreg.erdp = (value << 32) |
2120 MASK_64_LO(sc->rtsregs.intrreg.erdp);
2121
2122 if (rts->er_events_cnt > 0) {
2123 uint64_t erdp;
2124 int erdp_i;
2125
2126 erdp = rts->intrreg.erdp & ~0xF;
2127 erdp_i = (erdp - rts->erstba_p->qwEvrsTablePtr) /
2128 sizeof(struct xhci_trb);
2129
2130 if (erdp_i <= rts->er_enq_idx)
2131 rts->er_events_cnt = rts->er_enq_idx - erdp_i;
2132 else
2133 rts->er_events_cnt =
2134 rts->erstba_p->dwEvrsTableSize -
2135 (erdp_i - rts->er_enq_idx);
2136
2137 DPRINTF(("pci_xhci: erdp 0x%lx, events cnt %u",
2138 erdp, rts->er_events_cnt));
2139 }
2140
2141 break;
2142
2143 default:
2144 DPRINTF(("pci_xhci attempted write to RTS offset 0x%lx",
2145 offset));
2146 break;
2147 }
2148 }
2149
2150 static uint64_t
pci_xhci_portregs_read(struct pci_xhci_softc * sc,uint64_t offset)2151 pci_xhci_portregs_read(struct pci_xhci_softc *sc, uint64_t offset)
2152 {
2153 struct pci_xhci_portregs *portregs;
2154 int port;
2155 uint32_t reg;
2156
2157 if (sc->portregs == NULL)
2158 return (0);
2159
2160 port = (offset - XHCI_PORTREGS_PORT0) / XHCI_PORTREGS_SETSZ;
2161 offset = (offset - XHCI_PORTREGS_PORT0) % XHCI_PORTREGS_SETSZ;
2162
2163 if (port > XHCI_MAX_DEVS) {
2164 DPRINTF(("pci_xhci: portregs_read port %d >= XHCI_MAX_DEVS",
2165 port));
2166
2167 /* return default value for unused port */
2168 return (XHCI_PS_SPEED_SET(3));
2169 }
2170
2171 portregs = XHCI_PORTREG_PTR(sc, port);
2172 switch (offset) {
2173 case 0:
2174 reg = portregs->portsc;
2175 break;
2176 case 4:
2177 reg = portregs->portpmsc;
2178 break;
2179 case 8:
2180 reg = portregs->portli;
2181 break;
2182 case 12:
2183 reg = portregs->porthlpmc;
2184 break;
2185 default:
2186 DPRINTF(("pci_xhci: unaligned portregs read offset %#lx",
2187 offset));
2188 reg = 0xffffffff;
2189 break;
2190 }
2191
2192 DPRINTF(("pci_xhci: portregs read offset 0x%lx port %u -> 0x%x",
2193 offset, port, reg));
2194
2195 return (reg);
2196 }
2197
2198 static void
pci_xhci_hostop_write(struct pci_xhci_softc * sc,uint64_t offset,uint64_t value)2199 pci_xhci_hostop_write(struct pci_xhci_softc *sc, uint64_t offset,
2200 uint64_t value)
2201 {
2202 offset -= XHCI_CAPLEN;
2203
2204 if (offset < 0x400)
2205 DPRINTF(("pci_xhci: hostop write offset 0x%lx: 0x%lx",
2206 offset, value));
2207
2208 switch (offset) {
2209 case XHCI_USBCMD:
2210 sc->opregs.usbcmd = pci_xhci_usbcmd_write(sc, value & 0x3F0F);
2211 break;
2212
2213 case XHCI_USBSTS:
2214 /* clear bits on write */
2215 sc->opregs.usbsts &= ~(value &
2216 (XHCI_STS_HSE|XHCI_STS_EINT|XHCI_STS_PCD|XHCI_STS_SSS|
2217 XHCI_STS_RSS|XHCI_STS_SRE|XHCI_STS_CNR));
2218 break;
2219
2220 case XHCI_PAGESIZE:
2221 /* read only */
2222 break;
2223
2224 case XHCI_DNCTRL:
2225 sc->opregs.dnctrl = value & 0xFFFF;
2226 break;
2227
2228 case XHCI_CRCR_LO:
2229 if (sc->opregs.crcr & XHCI_CRCR_LO_CRR) {
2230 sc->opregs.crcr &= ~(XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA);
2231 sc->opregs.crcr |= value &
2232 (XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA);
2233 } else {
2234 sc->opregs.crcr = MASK_64_HI(sc->opregs.crcr) |
2235 (value & (0xFFFFFFC0 | XHCI_CRCR_LO_RCS));
2236 }
2237 break;
2238
2239 case XHCI_CRCR_HI:
2240 if (!(sc->opregs.crcr & XHCI_CRCR_LO_CRR)) {
2241 sc->opregs.crcr = MASK_64_LO(sc->opregs.crcr) |
2242 (value << 32);
2243
2244 sc->opregs.cr_p = XHCI_GADDR(sc,
2245 sc->opregs.crcr & ~0xF);
2246 }
2247
2248 if (sc->opregs.crcr & XHCI_CRCR_LO_CS) {
2249 /* Stop operation of Command Ring */
2250 }
2251
2252 if (sc->opregs.crcr & XHCI_CRCR_LO_CA) {
2253 /* Abort command */
2254 }
2255
2256 break;
2257
2258 case XHCI_DCBAAP_LO:
2259 sc->opregs.dcbaap = MASK_64_HI(sc->opregs.dcbaap) |
2260 (value & 0xFFFFFFC0);
2261 break;
2262
2263 case XHCI_DCBAAP_HI:
2264 sc->opregs.dcbaap = MASK_64_LO(sc->opregs.dcbaap) |
2265 (value << 32);
2266 sc->opregs.dcbaa_p = XHCI_GADDR(sc, sc->opregs.dcbaap & ~0x3FUL);
2267
2268 DPRINTF(("pci_xhci: opregs dcbaap = 0x%lx (vaddr 0x%lx)",
2269 sc->opregs.dcbaap, (uint64_t)sc->opregs.dcbaa_p));
2270 break;
2271
2272 case XHCI_CONFIG:
2273 sc->opregs.config = value & 0x03FF;
2274 break;
2275
2276 default:
2277 if (offset >= 0x400)
2278 pci_xhci_portregs_write(sc, offset, value);
2279
2280 break;
2281 }
2282 }
2283
2284
2285 static void
pci_xhci_write(struct pci_devinst * pi,int baridx,uint64_t offset,int size __unused,uint64_t value)2286 pci_xhci_write(struct pci_devinst *pi, int baridx, uint64_t offset,
2287 int size __unused, uint64_t value)
2288 {
2289 struct pci_xhci_softc *sc;
2290
2291 sc = pi->pi_arg;
2292
2293 assert(baridx == 0);
2294
2295
2296 pthread_mutex_lock(&sc->mtx);
2297 if (offset < XHCI_CAPLEN) /* read only registers */
2298 WPRINTF(("pci_xhci: write RO-CAPs offset %ld", offset));
2299 else if (offset < sc->dboff)
2300 pci_xhci_hostop_write(sc, offset, value);
2301 else if (offset < sc->rtsoff)
2302 pci_xhci_dbregs_write(sc, offset, value);
2303 else if (offset < sc->regsend)
2304 pci_xhci_rtsregs_write(sc, offset, value);
2305 else
2306 WPRINTF(("pci_xhci: write invalid offset %ld", offset));
2307
2308 pthread_mutex_unlock(&sc->mtx);
2309 }
2310
2311 static uint64_t
pci_xhci_hostcap_read(struct pci_xhci_softc * sc,uint64_t offset)2312 pci_xhci_hostcap_read(struct pci_xhci_softc *sc, uint64_t offset)
2313 {
2314 uint64_t value;
2315
2316 switch (offset) {
2317 case XHCI_CAPLENGTH: /* 0x00 */
2318 value = sc->caplength;
2319 break;
2320
2321 case XHCI_HCSPARAMS1: /* 0x04 */
2322 value = sc->hcsparams1;
2323 break;
2324
2325 case XHCI_HCSPARAMS2: /* 0x08 */
2326 value = sc->hcsparams2;
2327 break;
2328
2329 case XHCI_HCSPARAMS3: /* 0x0C */
2330 value = sc->hcsparams3;
2331 break;
2332
2333 case XHCI_HCSPARAMS0: /* 0x10 */
2334 value = sc->hccparams1;
2335 break;
2336
2337 case XHCI_DBOFF: /* 0x14 */
2338 value = sc->dboff;
2339 break;
2340
2341 case XHCI_RTSOFF: /* 0x18 */
2342 value = sc->rtsoff;
2343 break;
2344
2345 case XHCI_HCCPRAMS2: /* 0x1C */
2346 value = sc->hccparams2;
2347 break;
2348
2349 default:
2350 value = 0;
2351 break;
2352 }
2353
2354 DPRINTF(("pci_xhci: hostcap read offset 0x%lx -> 0x%lx",
2355 offset, value));
2356
2357 return (value);
2358 }
2359
2360 static uint64_t
pci_xhci_hostop_read(struct pci_xhci_softc * sc,uint64_t offset)2361 pci_xhci_hostop_read(struct pci_xhci_softc *sc, uint64_t offset)
2362 {
2363 uint64_t value;
2364
2365 offset = (offset - XHCI_CAPLEN);
2366
2367 switch (offset) {
2368 case XHCI_USBCMD: /* 0x00 */
2369 value = sc->opregs.usbcmd;
2370 break;
2371
2372 case XHCI_USBSTS: /* 0x04 */
2373 value = sc->opregs.usbsts;
2374 break;
2375
2376 case XHCI_PAGESIZE: /* 0x08 */
2377 value = sc->opregs.pgsz;
2378 break;
2379
2380 case XHCI_DNCTRL: /* 0x14 */
2381 value = sc->opregs.dnctrl;
2382 break;
2383
2384 case XHCI_CRCR_LO: /* 0x18 */
2385 value = sc->opregs.crcr & XHCI_CRCR_LO_CRR;
2386 break;
2387
2388 case XHCI_CRCR_HI: /* 0x1C */
2389 value = 0;
2390 break;
2391
2392 case XHCI_DCBAAP_LO: /* 0x30 */
2393 value = sc->opregs.dcbaap & 0xFFFFFFFF;
2394 break;
2395
2396 case XHCI_DCBAAP_HI: /* 0x34 */
2397 value = (sc->opregs.dcbaap >> 32) & 0xFFFFFFFF;
2398 break;
2399
2400 case XHCI_CONFIG: /* 0x38 */
2401 value = sc->opregs.config;
2402 break;
2403
2404 default:
2405 if (offset >= 0x400)
2406 value = pci_xhci_portregs_read(sc, offset);
2407 else
2408 value = 0;
2409
2410 break;
2411 }
2412
2413 if (offset < 0x400)
2414 DPRINTF(("pci_xhci: hostop read offset 0x%lx -> 0x%lx",
2415 offset, value));
2416
2417 return (value);
2418 }
2419
2420 static uint64_t
pci_xhci_dbregs_read(struct pci_xhci_softc * sc __unused,uint64_t offset __unused)2421 pci_xhci_dbregs_read(struct pci_xhci_softc *sc __unused,
2422 uint64_t offset __unused)
2423 {
2424 /* read doorbell always returns 0 */
2425 return (0);
2426 }
2427
2428 static uint64_t
pci_xhci_rtsregs_read(struct pci_xhci_softc * sc,uint64_t offset)2429 pci_xhci_rtsregs_read(struct pci_xhci_softc *sc, uint64_t offset)
2430 {
2431 uint32_t value;
2432
2433 offset -= sc->rtsoff;
2434 value = 0;
2435
2436 if (offset == XHCI_MFINDEX) {
2437 value = sc->rtsregs.mfindex;
2438 } else if (offset >= 0x20) {
2439 int item;
2440 uint32_t *p;
2441
2442 offset -= 0x20;
2443 item = offset % 32;
2444
2445 assert(offset < sizeof(sc->rtsregs.intrreg));
2446
2447 p = &sc->rtsregs.intrreg.iman;
2448 p += item / sizeof(uint32_t);
2449 value = *p;
2450 }
2451
2452 DPRINTF(("pci_xhci: rtsregs read offset 0x%lx -> 0x%x",
2453 offset, value));
2454
2455 return (value);
2456 }
2457
2458 static uint64_t
pci_xhci_xecp_read(struct pci_xhci_softc * sc,uint64_t offset)2459 pci_xhci_xecp_read(struct pci_xhci_softc *sc, uint64_t offset)
2460 {
2461 uint32_t value;
2462
2463 offset -= sc->regsend;
2464 value = 0;
2465
2466 switch (offset) {
2467 case 0:
2468 /* rev major | rev minor | next-cap | cap-id */
2469 value = (0x02 << 24) | (4 << 8) | XHCI_ID_PROTOCOLS;
2470 break;
2471 case 4:
2472 /* name string = "USB" */
2473 value = 0x20425355;
2474 break;
2475 case 8:
2476 /* psic | proto-defined | compat # | compat offset */
2477 value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb2_port_start;
2478 break;
2479 case 12:
2480 break;
2481 case 16:
2482 /* rev major | rev minor | next-cap | cap-id */
2483 value = (0x03 << 24) | XHCI_ID_PROTOCOLS;
2484 break;
2485 case 20:
2486 /* name string = "USB" */
2487 value = 0x20425355;
2488 break;
2489 case 24:
2490 /* psic | proto-defined | compat # | compat offset */
2491 value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb3_port_start;
2492 break;
2493 case 28:
2494 break;
2495 default:
2496 DPRINTF(("pci_xhci: xecp invalid offset 0x%lx", offset));
2497 break;
2498 }
2499
2500 DPRINTF(("pci_xhci: xecp read offset 0x%lx -> 0x%x",
2501 offset, value));
2502
2503 return (value);
2504 }
2505
2506
2507 static uint64_t
pci_xhci_read(struct pci_devinst * pi,int baridx,uint64_t offset,int size)2508 pci_xhci_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
2509 {
2510 struct pci_xhci_softc *sc;
2511 uint32_t value;
2512
2513 sc = pi->pi_arg;
2514
2515 assert(baridx == 0);
2516
2517 pthread_mutex_lock(&sc->mtx);
2518 if (offset < XHCI_CAPLEN)
2519 value = pci_xhci_hostcap_read(sc, offset);
2520 else if (offset < sc->dboff)
2521 value = pci_xhci_hostop_read(sc, offset);
2522 else if (offset < sc->rtsoff)
2523 value = pci_xhci_dbregs_read(sc, offset);
2524 else if (offset < sc->regsend)
2525 value = pci_xhci_rtsregs_read(sc, offset);
2526 else if (offset < (sc->regsend + 4*32))
2527 value = pci_xhci_xecp_read(sc, offset);
2528 else {
2529 value = 0;
2530 WPRINTF(("pci_xhci: read invalid offset %ld", offset));
2531 }
2532
2533 pthread_mutex_unlock(&sc->mtx);
2534
2535 switch (size) {
2536 case 1:
2537 value &= 0xFF;
2538 break;
2539 case 2:
2540 value &= 0xFFFF;
2541 break;
2542 case 4:
2543 value &= 0xFFFFFFFF;
2544 break;
2545 }
2546
2547 return (value);
2548 }
2549
2550 static void
pci_xhci_reset_port(struct pci_xhci_softc * sc,int portn,int warm)2551 pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm)
2552 {
2553 struct pci_xhci_portregs *port;
2554 struct pci_xhci_dev_emu *dev;
2555 struct xhci_trb evtrb;
2556 int error;
2557
2558 assert(portn <= XHCI_MAX_DEVS);
2559
2560 DPRINTF(("xhci reset port %d", portn));
2561
2562 port = XHCI_PORTREG_PTR(sc, portn);
2563 dev = XHCI_DEVINST_PTR(sc, portn);
2564 if (dev) {
2565 port->portsc &= ~(XHCI_PS_PLS_MASK | XHCI_PS_PR | XHCI_PS_PRC);
2566 port->portsc |= XHCI_PS_PED |
2567 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
2568
2569 if (warm && dev->dev_ue->ue_usbver == 3) {
2570 port->portsc |= XHCI_PS_WRC;
2571 }
2572
2573 if ((port->portsc & XHCI_PS_PRC) == 0) {
2574 port->portsc |= XHCI_PS_PRC;
2575
2576 pci_xhci_set_evtrb(&evtrb, portn,
2577 XHCI_TRB_ERROR_SUCCESS,
2578 XHCI_TRB_EVENT_PORT_STS_CHANGE);
2579 error = pci_xhci_insert_event(sc, &evtrb, 1);
2580 if (error != XHCI_TRB_ERROR_SUCCESS)
2581 DPRINTF(("xhci reset port insert event "
2582 "failed"));
2583 }
2584 }
2585 }
2586
2587 static void
pci_xhci_init_port(struct pci_xhci_softc * sc,int portn)2588 pci_xhci_init_port(struct pci_xhci_softc *sc, int portn)
2589 {
2590 struct pci_xhci_portregs *port;
2591 struct pci_xhci_dev_emu *dev;
2592
2593 port = XHCI_PORTREG_PTR(sc, portn);
2594 dev = XHCI_DEVINST_PTR(sc, portn);
2595 if (dev) {
2596 port->portsc = XHCI_PS_CCS | /* connected */
2597 XHCI_PS_PP; /* port power */
2598
2599 if (dev->dev_ue->ue_usbver == 2) {
2600 port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_POLL) |
2601 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
2602 } else {
2603 port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_U0) |
2604 XHCI_PS_PED | /* enabled */
2605 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
2606 }
2607
2608 DPRINTF(("Init port %d 0x%x", portn, port->portsc));
2609 } else {
2610 port->portsc = XHCI_PS_PLS_SET(UPS_PORT_LS_RX_DET) | XHCI_PS_PP;
2611 DPRINTF(("Init empty port %d 0x%x", portn, port->portsc));
2612 }
2613 }
2614
2615 static int
pci_xhci_dev_intr(struct usb_hci * hci,int epctx)2616 pci_xhci_dev_intr(struct usb_hci *hci, int epctx)
2617 {
2618 struct pci_xhci_dev_emu *dev;
2619 struct xhci_dev_ctx *dev_ctx;
2620 struct xhci_trb evtrb;
2621 struct pci_xhci_softc *sc;
2622 struct pci_xhci_portregs *p;
2623 struct xhci_endp_ctx *ep_ctx;
2624 int error = 0;
2625 int dir_in;
2626 int epid;
2627
2628 dir_in = epctx & 0x80;
2629 epid = epctx & ~0x80;
2630
2631 /* HW endpoint contexts are 0-15; convert to epid based on dir */
2632 epid = (epid * 2) + (dir_in ? 1 : 0);
2633
2634 assert(epid >= 1 && epid <= 31);
2635
2636 dev = hci->hci_sc;
2637 sc = dev->xsc;
2638
2639 /* check if device is ready; OS has to initialise it */
2640 if (sc->rtsregs.erstba_p == NULL ||
2641 (sc->opregs.usbcmd & XHCI_CMD_RS) == 0 ||
2642 dev->dev_ctx == NULL)
2643 return (0);
2644
2645 p = XHCI_PORTREG_PTR(sc, hci->hci_port);
2646
2647 /* raise event if link U3 (suspended) state */
2648 if (XHCI_PS_PLS_GET(p->portsc) == 3) {
2649 p->portsc &= ~XHCI_PS_PLS_MASK;
2650 p->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_RESUME);
2651 if ((p->portsc & XHCI_PS_PLC) != 0)
2652 return (0);
2653
2654 p->portsc |= XHCI_PS_PLC;
2655
2656 pci_xhci_set_evtrb(&evtrb, hci->hci_port,
2657 XHCI_TRB_ERROR_SUCCESS, XHCI_TRB_EVENT_PORT_STS_CHANGE);
2658 error = pci_xhci_insert_event(sc, &evtrb, 0);
2659 if (error != XHCI_TRB_ERROR_SUCCESS)
2660 goto done;
2661 }
2662
2663 dev_ctx = dev->dev_ctx;
2664 ep_ctx = &dev_ctx->ctx_ep[epid];
2665 if ((ep_ctx->dwEpCtx0 & 0x7) == XHCI_ST_EPCTX_DISABLED) {
2666 DPRINTF(("xhci device interrupt on disabled endpoint %d",
2667 epid));
2668 return (0);
2669 }
2670
2671 DPRINTF(("xhci device interrupt on endpoint %d", epid));
2672
2673 pci_xhci_device_doorbell(sc, hci->hci_port, epid, 0);
2674
2675 done:
2676 return (error);
2677 }
2678
2679 static int
pci_xhci_dev_event(struct usb_hci * hci,enum hci_usbev evid __unused,void * param __unused)2680 pci_xhci_dev_event(struct usb_hci *hci, enum hci_usbev evid __unused,
2681 void *param __unused)
2682 {
2683 DPRINTF(("xhci device event port %d", hci->hci_port));
2684 return (0);
2685 }
2686
2687 /*
2688 * Each controller contains a "slot" node which contains a list of
2689 * child nodes each of which is a device. Each slot node's name
2690 * corresponds to a specific controller slot. These nodes
2691 * contain a "device" variable identifying the device model of the
2692 * USB device. For example:
2693 *
2694 * pci.0.1.0
2695 * .device="xhci"
2696 * .slot
2697 * .1
2698 * .device="tablet"
2699 */
2700 static int
pci_xhci_legacy_config(nvlist_t * nvl,const char * opts)2701 pci_xhci_legacy_config(nvlist_t *nvl, const char *opts)
2702 {
2703 char node_name[16];
2704 nvlist_t *slots_nvl, *slot_nvl;
2705 char *cp, *opt, *str, *tofree;
2706 int slot;
2707
2708 if (opts == NULL)
2709 return (0);
2710
2711 slots_nvl = create_relative_config_node(nvl, "slot");
2712 slot = 1;
2713 tofree = str = strdup(opts);
2714 while ((opt = strsep(&str, ",")) != NULL) {
2715 /* device[=<config>] */
2716 cp = strchr(opt, '=');
2717 if (cp != NULL) {
2718 *cp = '\0';
2719 cp++;
2720 }
2721
2722 snprintf(node_name, sizeof(node_name), "%d", slot);
2723 slot++;
2724 slot_nvl = create_relative_config_node(slots_nvl, node_name);
2725 set_config_value_node(slot_nvl, "device", opt);
2726
2727 /*
2728 * NB: Given that we split on commas above, the legacy
2729 * format only supports a single option.
2730 */
2731 if (cp != NULL && *cp != '\0')
2732 pci_parse_legacy_config(slot_nvl, cp);
2733 }
2734 free(tofree);
2735 return (0);
2736 }
2737
2738 static int
pci_xhci_parse_devices(struct pci_xhci_softc * sc,nvlist_t * nvl)2739 pci_xhci_parse_devices(struct pci_xhci_softc *sc, nvlist_t *nvl)
2740 {
2741 struct pci_xhci_dev_emu *dev;
2742 struct usb_devemu *ue;
2743 const nvlist_t *slots_nvl, *slot_nvl;
2744 const char *name, *device;
2745 char *cp;
2746 void *devsc, *cookie;
2747 long slot;
2748 int type, usb3_port, usb2_port, i, ndevices;
2749
2750 usb3_port = sc->usb3_port_start;
2751 usb2_port = sc->usb2_port_start;
2752
2753 sc->devices = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_dev_emu *));
2754 sc->slots = calloc(XHCI_MAX_SLOTS, sizeof(struct pci_xhci_dev_emu *));
2755
2756 ndevices = 0;
2757
2758 slots_nvl = find_relative_config_node(nvl, "slot");
2759 if (slots_nvl == NULL)
2760 goto portsfinal;
2761
2762 cookie = NULL;
2763 while ((name = nvlist_next(slots_nvl, &type, &cookie)) != NULL) {
2764 if (usb2_port == ((sc->usb2_port_start) + XHCI_MAX_DEVS/2) ||
2765 usb3_port == ((sc->usb3_port_start) + XHCI_MAX_DEVS/2)) {
2766 WPRINTF(("pci_xhci max number of USB 2 or 3 "
2767 "devices reached, max %d", XHCI_MAX_DEVS/2));
2768 goto bad;
2769 }
2770
2771 if (type != NV_TYPE_NVLIST) {
2772 EPRINTLN(
2773 "pci_xhci: config variable '%s' under slot node",
2774 name);
2775 goto bad;
2776 }
2777
2778 slot = strtol(name, &cp, 0);
2779 if (*cp != '\0' || slot <= 0 || slot > XHCI_MAX_SLOTS) {
2780 EPRINTLN("pci_xhci: invalid slot '%s'", name);
2781 goto bad;
2782 }
2783
2784 if (XHCI_SLOTDEV_PTR(sc, slot) != NULL) {
2785 EPRINTLN("pci_xhci: duplicate slot '%s'", name);
2786 goto bad;
2787 }
2788
2789 slot_nvl = nvlist_get_nvlist(slots_nvl, name);
2790 device = get_config_value_node(slot_nvl, "device");
2791 if (device == NULL) {
2792 EPRINTLN(
2793 "pci_xhci: missing \"device\" value for slot '%s'",
2794 name);
2795 goto bad;
2796 }
2797
2798 ue = usb_emu_finddev(device);
2799 if (ue == NULL) {
2800 EPRINTLN("pci_xhci: unknown device model \"%s\"",
2801 device);
2802 goto bad;
2803 }
2804
2805 DPRINTF(("pci_xhci adding device %s", device));
2806
2807 dev = calloc(1, sizeof(struct pci_xhci_dev_emu));
2808 dev->xsc = sc;
2809 dev->hci.hci_sc = dev;
2810 dev->hci.hci_intr = pci_xhci_dev_intr;
2811 dev->hci.hci_event = pci_xhci_dev_event;
2812
2813 if (ue->ue_usbver == 2) {
2814 if (usb2_port == sc->usb2_port_start +
2815 XHCI_MAX_DEVS / 2) {
2816 WPRINTF(("pci_xhci max number of USB 2 devices "
2817 "reached, max %d", XHCI_MAX_DEVS / 2));
2818 goto bad;
2819 }
2820 dev->hci.hci_port = usb2_port;
2821 usb2_port++;
2822 } else {
2823 if (usb3_port == sc->usb3_port_start +
2824 XHCI_MAX_DEVS / 2) {
2825 WPRINTF(("pci_xhci max number of USB 3 devices "
2826 "reached, max %d", XHCI_MAX_DEVS / 2));
2827 goto bad;
2828 }
2829 dev->hci.hci_port = usb3_port;
2830 usb3_port++;
2831 }
2832 XHCI_DEVINST_PTR(sc, dev->hci.hci_port) = dev;
2833
2834 dev->hci.hci_address = 0;
2835 devsc = ue->ue_init(&dev->hci, nvl);
2836 if (devsc == NULL) {
2837 goto bad;
2838 }
2839
2840 dev->dev_ue = ue;
2841 dev->dev_sc = devsc;
2842
2843 XHCI_SLOTDEV_PTR(sc, slot) = dev;
2844 ndevices++;
2845 }
2846
2847 portsfinal:
2848 sc->portregs = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_portregs));
2849
2850 if (ndevices > 0) {
2851 for (i = 1; i <= XHCI_MAX_DEVS; i++) {
2852 pci_xhci_init_port(sc, i);
2853 }
2854 } else {
2855 WPRINTF(("pci_xhci no USB devices configured"));
2856 }
2857 return (0);
2858
2859 bad:
2860 for (i = 1; i <= XHCI_MAX_DEVS; i++) {
2861 free(XHCI_DEVINST_PTR(sc, i));
2862 }
2863
2864 free(sc->devices);
2865 free(sc->slots);
2866
2867 return (-1);
2868 }
2869
2870 static int
pci_xhci_init(struct pci_devinst * pi,nvlist_t * nvl)2871 pci_xhci_init(struct pci_devinst *pi, nvlist_t *nvl)
2872 {
2873 struct pci_xhci_softc *sc;
2874 int error;
2875
2876 #ifndef __FreeBSD__
2877 if (get_config_bool_default("xhci.debug", false))
2878 xhci_debug = 1;
2879 #endif
2880
2881 if (xhci_in_use) {
2882 WPRINTF(("pci_xhci controller already defined"));
2883 return (-1);
2884 }
2885 xhci_in_use = 1;
2886
2887 sc = calloc(1, sizeof(struct pci_xhci_softc));
2888 pi->pi_arg = sc;
2889 sc->xsc_pi = pi;
2890
2891 sc->usb2_port_start = (XHCI_MAX_DEVS/2) + 1;
2892 sc->usb3_port_start = 1;
2893
2894 /* discover devices */
2895 error = pci_xhci_parse_devices(sc, nvl);
2896 if (error < 0)
2897 goto done;
2898 else
2899 error = 0;
2900
2901 sc->caplength = XHCI_SET_CAPLEN(XHCI_CAPLEN) |
2902 XHCI_SET_HCIVERSION(0x0100);
2903 sc->hcsparams1 = XHCI_SET_HCSP1_MAXPORTS(XHCI_MAX_DEVS) |
2904 XHCI_SET_HCSP1_MAXINTR(1) | /* interrupters */
2905 XHCI_SET_HCSP1_MAXSLOTS(XHCI_MAX_SLOTS);
2906 sc->hcsparams2 = XHCI_SET_HCSP2_ERSTMAX(XHCI_ERST_MAX) |
2907 XHCI_SET_HCSP2_IST(0x04);
2908 sc->hcsparams3 = 0; /* no latency */
2909 sc->hccparams1 = XHCI_SET_HCCP1_AC64(1) | /* 64-bit addrs */
2910 XHCI_SET_HCCP1_NSS(1) | /* no 2nd-streams */
2911 XHCI_SET_HCCP1_SPC(1) | /* short packet */
2912 XHCI_SET_HCCP1_MAXPSA(XHCI_STREAMS_MAX);
2913 sc->hccparams2 = XHCI_SET_HCCP2_LEC(1) |
2914 XHCI_SET_HCCP2_U3C(1);
2915 sc->dboff = XHCI_SET_DOORBELL(XHCI_CAPLEN + XHCI_PORTREGS_START +
2916 XHCI_MAX_DEVS * sizeof(struct pci_xhci_portregs));
2917
2918 /* dboff must be 32-bit aligned */
2919 if (sc->dboff & 0x3)
2920 sc->dboff = (sc->dboff + 0x3) & ~0x3;
2921
2922 /* rtsoff must be 32-bytes aligned */
2923 sc->rtsoff = XHCI_SET_RTSOFFSET(sc->dboff + (XHCI_MAX_SLOTS+1) * 32);
2924 if (sc->rtsoff & 0x1F)
2925 sc->rtsoff = (sc->rtsoff + 0x1F) & ~0x1F;
2926
2927 DPRINTF(("pci_xhci dboff: 0x%x, rtsoff: 0x%x", sc->dboff,
2928 sc->rtsoff));
2929
2930 sc->opregs.usbsts = XHCI_STS_HCH;
2931 sc->opregs.pgsz = XHCI_PAGESIZE_4K;
2932
2933 pci_xhci_reset(sc);
2934
2935 sc->regsend = sc->rtsoff + 0x20 + 32; /* only 1 intrpter */
2936
2937 /*
2938 * Set extended capabilities pointer to be after regsend;
2939 * value of xecp field is 32-bit offset.
2940 */
2941 sc->hccparams1 |= XHCI_SET_HCCP1_XECP(sc->regsend/4);
2942
2943 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x1E31);
2944 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2945 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_SERIALBUS);
2946 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_SERIALBUS_USB);
2947 pci_set_cfgdata8(pi, PCIR_PROGIF,PCIP_SERIALBUS_USB_XHCI);
2948 pci_set_cfgdata8(pi, PCI_USBREV, PCI_USB_REV_3_0);
2949
2950 pci_emul_add_msicap(pi, 1);
2951
2952 /* regsend + xecp registers */
2953 pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, sc->regsend + 4*32);
2954 DPRINTF(("pci_xhci pci_emu_alloc: %d", sc->regsend + 4*32));
2955
2956
2957 pci_lintr_request(pi);
2958
2959 pthread_mutex_init(&sc->mtx, NULL);
2960
2961 done:
2962 if (error) {
2963 free(sc);
2964 }
2965
2966 return (error);
2967 }
2968
2969 static const struct pci_devemu pci_de_xhci = {
2970 .pe_emu = "xhci",
2971 .pe_init = pci_xhci_init,
2972 .pe_legacy_config = pci_xhci_legacy_config,
2973 .pe_barwrite = pci_xhci_write,
2974 .pe_barread = pci_xhci_read
2975 };
2976 PCI_EMUL_SET(pci_de_xhci);
2977