1 /*
2 * SPDX-License-Identifier: GPL-2.0
3 *
4 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
5 *
6 * Authors:
7 * Md Sadre Alam <quic_mdalam@quicinc.com>
8 * Sricharan R <quic_srichara@quicinc.com>
9 * Varadarajan Narayanan <quic_varada@quicinc.com>
10 */
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dma/qcom_adm.h>
17 #include <linux/dma/qcom_bam_dma.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <linux/mtd/nand-qpic-common.h>
23 #include <linux/mtd/spinand.h>
24 #include <linux/bitfield.h>
25
26 #define NAND_FLASH_SPI_CFG 0xc0
27 #define NAND_NUM_ADDR_CYCLES 0xc4
28 #define NAND_BUSY_CHECK_WAIT_CNT 0xc8
29 #define NAND_FLASH_FEATURES 0xf64
30
31 /* QSPI NAND config reg bits */
32 #define LOAD_CLK_CNTR_INIT_EN BIT(28)
33 #define CLK_CNTR_INIT_VAL_VEC 0x924
34 #define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16)
35 #define FEA_STATUS_DEV_ADDR 0xc0
36 #define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8)
37 #define SPI_CFG BIT(0)
38 #define SPI_NUM_ADDR 0xDA4DB
39 #define SPI_WAIT_CNT 0x10
40 #define QPIC_QSPI_NUM_CS 1
41 #define SPI_TRANSFER_MODE_x1 BIT(29)
42 #define SPI_TRANSFER_MODE_x4 (3 << 29)
43 #define SPI_WP BIT(28)
44 #define SPI_HOLD BIT(27)
45 #define QPIC_SET_FEATURE BIT(31)
46
47 #define SPINAND_RESET 0xff
48 #define SPINAND_READID 0x9f
49 #define SPINAND_GET_FEATURE 0x0f
50 #define SPINAND_SET_FEATURE 0x1f
51 #define SPINAND_READ 0x13
52 #define SPINAND_ERASE 0xd8
53 #define SPINAND_WRITE_EN 0x06
54 #define SPINAND_PROGRAM_EXECUTE 0x10
55 #define SPINAND_PROGRAM_LOAD 0x84
56
57 #define ACC_FEATURE 0xe
58 #define BAD_BLOCK_MARKER_SIZE 0x2
59 #define OOB_BUF_SIZE 128
60 #define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng)
61
62 struct qpic_snand_op {
63 u32 cmd_reg;
64 u32 addr1_reg;
65 u32 addr2_reg;
66 };
67
68 struct snandc_read_status {
69 __le32 snandc_flash;
70 __le32 snandc_buffer;
71 __le32 snandc_erased_cw;
72 };
73
74 /*
75 * ECC state struct
76 * @corrected: ECC corrected
77 * @bitflips: Max bit flip
78 * @failed: ECC failed
79 */
80 struct qcom_ecc_stats {
81 u32 corrected;
82 u32 bitflips;
83 u32 failed;
84 };
85
86 struct qpic_ecc {
87 struct device *dev;
88 int ecc_bytes_hw;
89 int spare_bytes;
90 int bbm_size;
91 int ecc_mode;
92 int bytes;
93 int steps;
94 int step_size;
95 int strength;
96 int cw_size;
97 int cw_data;
98 u32 cfg0;
99 u32 cfg1;
100 u32 cfg0_raw;
101 u32 cfg1_raw;
102 u32 ecc_buf_cfg;
103 u32 ecc_bch_cfg;
104 u32 clrflashstatus;
105 u32 clrreadstatus;
106 bool bch_enabled;
107 };
108
109 struct qpic_spi_nand {
110 struct qcom_nand_controller *snandc;
111 struct spi_controller *ctlr;
112 struct mtd_info *mtd;
113 struct clk *iomacro_clk;
114 struct qpic_ecc *ecc;
115 struct qcom_ecc_stats ecc_stats;
116 struct nand_ecc_engine ecc_eng;
117 u8 *data_buf;
118 u8 *oob_buf;
119 __le32 addr1;
120 __le32 addr2;
121 __le32 cmd;
122 u32 num_cw;
123 bool oob_rw;
124 bool page_rw;
125 bool raw_rw;
126 };
127
qcom_spi_set_read_loc_first(struct qcom_nand_controller * snandc,int reg,int cw_offset,int read_size,int is_last_read_loc)128 static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc,
129 int reg, int cw_offset, int read_size,
130 int is_last_read_loc)
131 {
132 __le32 locreg_val;
133 u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
134 FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
135 FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
136
137 locreg_val = cpu_to_le32(val);
138
139 if (reg == NAND_READ_LOCATION_0)
140 snandc->regs->read_location0 = locreg_val;
141 else if (reg == NAND_READ_LOCATION_1)
142 snandc->regs->read_location1 = locreg_val;
143 else if (reg == NAND_READ_LOCATION_2)
144 snandc->regs->read_location2 = locreg_val;
145 else if (reg == NAND_READ_LOCATION_3)
146 snandc->regs->read_location3 = locreg_val;
147 }
148
qcom_spi_set_read_loc_last(struct qcom_nand_controller * snandc,int reg,int cw_offset,int read_size,int is_last_read_loc)149 static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc,
150 int reg, int cw_offset, int read_size,
151 int is_last_read_loc)
152 {
153 __le32 locreg_val;
154 u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
155 FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
156 FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
157
158 locreg_val = cpu_to_le32(val);
159
160 if (reg == NAND_READ_LOCATION_LAST_CW_0)
161 snandc->regs->read_location_last0 = locreg_val;
162 else if (reg == NAND_READ_LOCATION_LAST_CW_1)
163 snandc->regs->read_location_last1 = locreg_val;
164 else if (reg == NAND_READ_LOCATION_LAST_CW_2)
165 snandc->regs->read_location_last2 = locreg_val;
166 else if (reg == NAND_READ_LOCATION_LAST_CW_3)
167 snandc->regs->read_location_last3 = locreg_val;
168 }
169
nand_to_qcom_snand(struct nand_device * nand)170 static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand)
171 {
172 struct nand_ecc_engine *eng = nand->ecc.engine;
173 struct qpic_spi_nand *qspi = ecceng_to_qspi(eng);
174
175 return qspi->snandc;
176 }
177
qcom_spi_init(struct qcom_nand_controller * snandc)178 static int qcom_spi_init(struct qcom_nand_controller *snandc)
179 {
180 u32 snand_cfg_val = 0x0;
181 int ret;
182
183 snand_cfg_val = FIELD_PREP(CLK_CNTR_INIT_VAL_VEC_MASK, CLK_CNTR_INIT_VAL_VEC) |
184 FIELD_PREP(LOAD_CLK_CNTR_INIT_EN, 0) |
185 FIELD_PREP(FEA_STATUS_DEV_ADDR_MASK, FEA_STATUS_DEV_ADDR) |
186 FIELD_PREP(SPI_CFG, 0);
187
188 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
189 snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR);
190 snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT);
191
192 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
193
194 snand_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN;
195 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
196
197 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
198
199 qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0);
200 qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1,
201 NAND_BAM_NEXT_SGL);
202
203 ret = qcom_submit_descs(snandc);
204 if (ret) {
205 dev_err(snandc->dev, "failure in submitting spi init descriptor\n");
206 return ret;
207 }
208
209 return ret;
210 }
211
qcom_spi_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)212 static int qcom_spi_ooblayout_ecc(struct mtd_info *mtd, int section,
213 struct mtd_oob_region *oobregion)
214 {
215 struct nand_device *nand = mtd_to_nanddev(mtd);
216 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
217 struct qpic_ecc *qecc = snandc->qspi->ecc;
218
219 if (section > 1)
220 return -ERANGE;
221
222 oobregion->length = qecc->ecc_bytes_hw + qecc->spare_bytes;
223 oobregion->offset = mtd->oobsize - oobregion->length;
224
225 return 0;
226 }
227
qcom_spi_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)228 static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section,
229 struct mtd_oob_region *oobregion)
230 {
231 struct nand_device *nand = mtd_to_nanddev(mtd);
232 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
233 struct qpic_ecc *qecc = snandc->qspi->ecc;
234
235 if (section)
236 return -ERANGE;
237
238 oobregion->length = qecc->steps * 4;
239 oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size;
240
241 return 0;
242 }
243
244 static const struct mtd_ooblayout_ops qcom_spi_ooblayout = {
245 .ecc = qcom_spi_ooblayout_ecc,
246 .free = qcom_spi_ooblayout_free,
247 };
248
qcom_spi_ecc_init_ctx_pipelined(struct nand_device * nand)249 static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand)
250 {
251 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
252 struct nand_ecc_props *reqs = &nand->ecc.requirements;
253 struct nand_ecc_props *user = &nand->ecc.user_conf;
254 struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
255 struct mtd_info *mtd = nanddev_to_mtd(nand);
256 int cwperpage, bad_block_byte, ret;
257 struct qpic_ecc *ecc_cfg;
258
259 cwperpage = mtd->writesize / NANDC_STEP_SIZE;
260 snandc->qspi->num_cw = cwperpage;
261
262 ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
263 if (!ecc_cfg)
264 return -ENOMEM;
265
266 if (user->step_size && user->strength) {
267 ecc_cfg->step_size = user->step_size;
268 ecc_cfg->strength = user->strength;
269 } else if (reqs->step_size && reqs->strength) {
270 ecc_cfg->step_size = reqs->step_size;
271 ecc_cfg->strength = reqs->strength;
272 } else {
273 /* use defaults */
274 ecc_cfg->step_size = NANDC_STEP_SIZE;
275 ecc_cfg->strength = 4;
276 }
277
278 if (ecc_cfg->step_size != NANDC_STEP_SIZE) {
279 dev_err(snandc->dev,
280 "only %u bytes ECC step size is supported\n",
281 NANDC_STEP_SIZE);
282 ret = -EOPNOTSUPP;
283 goto err_free_ecc_cfg;
284 }
285
286 if (ecc_cfg->strength != 4) {
287 dev_err(snandc->dev,
288 "only 4 bits ECC strength is supported\n");
289 ret = -EOPNOTSUPP;
290 goto err_free_ecc_cfg;
291 }
292
293 snandc->qspi->oob_buf = kmalloc(mtd->writesize + mtd->oobsize,
294 GFP_KERNEL);
295 if (!snandc->qspi->oob_buf) {
296 ret = -ENOMEM;
297 goto err_free_ecc_cfg;
298 }
299
300 memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize);
301
302 nand->ecc.ctx.priv = ecc_cfg;
303 snandc->qspi->mtd = mtd;
304
305 ecc_cfg->ecc_bytes_hw = 7;
306 ecc_cfg->spare_bytes = 4;
307 ecc_cfg->bbm_size = 1;
308 ecc_cfg->bch_enabled = true;
309 ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
310
311 ecc_cfg->steps = 4;
312 ecc_cfg->cw_data = 516;
313 ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes;
314 bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1;
315
316 mtd_set_ooblayout(mtd, &qcom_spi_ooblayout);
317
318 /*
319 * Free the temporary BAM transaction allocated initially by
320 * qcom_nandc_alloc(), and allocate a new one based on the
321 * updated max_cwperpage value.
322 */
323 qcom_free_bam_transaction(snandc);
324
325 snandc->max_cwperpage = cwperpage;
326
327 snandc->bam_txn = qcom_alloc_bam_transaction(snandc);
328 if (!snandc->bam_txn) {
329 dev_err(snandc->dev, "failed to allocate BAM transaction\n");
330 ret = -ENOMEM;
331 goto err_free_ecc_cfg;
332 }
333
334 ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
335 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) |
336 FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) |
337 FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
338 FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) |
339 FIELD_PREP(STATUS_BFR_READ, 0) |
340 FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) |
341 FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes);
342
343 ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
344 FIELD_PREP(CS_ACTIVE_BSY, 0) |
345 FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) |
346 FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) |
347 FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
348 FIELD_PREP(WIDE_FLASH, 0) |
349 FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled);
350
351 ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
352 FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
353 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) |
354 FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
355
356 ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
357 FIELD_PREP(CS_ACTIVE_BSY, 0) |
358 FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
359 FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
360 FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
361 FIELD_PREP(WIDE_FLASH, 0) |
362 FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
363
364 ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) |
365 FIELD_PREP(ECC_SW_RESET, 0) |
366 FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
367 FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
368 FIELD_PREP(ECC_MODE_MASK, 0) |
369 FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
370
371 ecc_cfg->ecc_buf_cfg = FIELD_PREP(NUM_STEPS_MASK, 0x203);
372 ecc_cfg->clrflashstatus = FS_READY_BSY_N;
373 ecc_cfg->clrreadstatus = 0xc0;
374
375 conf->step_size = ecc_cfg->step_size;
376 conf->strength = ecc_cfg->strength;
377
378 snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET);
379 snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET);
380
381 dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n",
382 ecc_cfg->strength, ecc_cfg->step_size);
383
384 return 0;
385
386 err_free_ecc_cfg:
387 kfree(ecc_cfg);
388 return ret;
389 }
390
qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device * nand)391 static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand)
392 {
393 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
394
395 kfree(ecc_cfg);
396 }
397
qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device * nand,struct nand_page_io_req * req)398 static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand,
399 struct nand_page_io_req *req)
400 {
401 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
402 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
403
404 snandc->qspi->ecc = ecc_cfg;
405 snandc->qspi->raw_rw = false;
406 snandc->qspi->oob_rw = false;
407 snandc->qspi->page_rw = false;
408
409 if (req->datalen)
410 snandc->qspi->page_rw = true;
411
412 if (req->ooblen)
413 snandc->qspi->oob_rw = true;
414
415 if (req->mode == MTD_OPS_RAW)
416 snandc->qspi->raw_rw = true;
417
418 return 0;
419 }
420
qcom_spi_ecc_finish_io_req_pipelined(struct nand_device * nand,struct nand_page_io_req * req)421 static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand,
422 struct nand_page_io_req *req)
423 {
424 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
425 struct mtd_info *mtd = nanddev_to_mtd(nand);
426
427 if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ)
428 return 0;
429
430 if (snandc->qspi->ecc_stats.failed)
431 mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed;
432 else
433 mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected;
434
435 if (snandc->qspi->ecc_stats.failed)
436 return -EBADMSG;
437 else
438 return snandc->qspi->ecc_stats.bitflips;
439 }
440
441 static struct nand_ecc_engine_ops qcom_spi_ecc_engine_ops_pipelined = {
442 .init_ctx = qcom_spi_ecc_init_ctx_pipelined,
443 .cleanup_ctx = qcom_spi_ecc_cleanup_ctx_pipelined,
444 .prepare_io_req = qcom_spi_ecc_prepare_io_req_pipelined,
445 .finish_io_req = qcom_spi_ecc_finish_io_req_pipelined,
446 };
447
448 /* helper to configure location register values */
qcom_spi_set_read_loc(struct qcom_nand_controller * snandc,int cw,int reg,int cw_offset,int read_size,int is_last_read_loc)449 static void qcom_spi_set_read_loc(struct qcom_nand_controller *snandc, int cw, int reg,
450 int cw_offset, int read_size, int is_last_read_loc)
451 {
452 int reg_base = NAND_READ_LOCATION_0;
453 int num_cw = snandc->qspi->num_cw;
454
455 if (cw == (num_cw - 1))
456 reg_base = NAND_READ_LOCATION_LAST_CW_0;
457
458 reg_base += reg * 4;
459
460 if (cw == (num_cw - 1))
461 return qcom_spi_set_read_loc_last(snandc, reg_base, cw_offset,
462 read_size, is_last_read_loc);
463 else
464 return qcom_spi_set_read_loc_first(snandc, reg_base, cw_offset,
465 read_size, is_last_read_loc);
466 }
467
468 static void
qcom_spi_config_cw_read(struct qcom_nand_controller * snandc,bool use_ecc,int cw)469 qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int cw)
470 {
471 __le32 *reg = &snandc->regs->read_location0;
472 int num_cw = snandc->qspi->num_cw;
473
474 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL);
475 if (cw == (num_cw - 1)) {
476 reg = &snandc->regs->read_location_last0;
477 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4,
478 NAND_BAM_NEXT_SGL);
479 }
480
481 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
482 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
483
484 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
485 qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
486 NAND_BAM_NEXT_SGL);
487 }
488
qcom_spi_block_erase(struct qcom_nand_controller * snandc)489 static int qcom_spi_block_erase(struct qcom_nand_controller *snandc)
490 {
491 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
492 int ret;
493
494 snandc->buf_count = 0;
495 snandc->buf_start = 0;
496 qcom_clear_read_regs(snandc);
497 qcom_clear_bam_transaction(snandc);
498
499 snandc->regs->cmd = snandc->qspi->cmd;
500 snandc->regs->addr0 = snandc->qspi->addr1;
501 snandc->regs->addr1 = snandc->qspi->addr2;
502 snandc->regs->cfg0 = cpu_to_le32((ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
503 FIELD_PREP(CW_PER_PAGE_MASK, 0));
504 snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw);
505 snandc->regs->exec = cpu_to_le32(1);
506
507 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
508 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
509 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
510
511 ret = qcom_submit_descs(snandc);
512 if (ret) {
513 dev_err(snandc->dev, "failure to erase block\n");
514 return ret;
515 }
516
517 return 0;
518 }
519
qcom_spi_config_single_cw_page_read(struct qcom_nand_controller * snandc,bool use_ecc,int cw)520 static void qcom_spi_config_single_cw_page_read(struct qcom_nand_controller *snandc,
521 bool use_ecc, int cw)
522 {
523 __le32 *reg = &snandc->regs->read_location0;
524 int num_cw = snandc->qspi->num_cw;
525
526 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
527 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
528 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
529 NAND_ERASED_CW_DETECT_CFG, 1, 0);
530 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
531 NAND_ERASED_CW_DETECT_CFG, 1,
532 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
533
534 if (cw == (num_cw - 1)) {
535 reg = &snandc->regs->read_location_last0;
536 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, NAND_BAM_NEXT_SGL);
537 }
538 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
539 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
540
541 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 0);
542 }
543
qcom_spi_check_raw_flash_errors(struct qcom_nand_controller * snandc,int cw_cnt)544 static int qcom_spi_check_raw_flash_errors(struct qcom_nand_controller *snandc, int cw_cnt)
545 {
546 int i;
547
548 qcom_nandc_dev_to_mem(snandc, true);
549
550 for (i = 0; i < cw_cnt; i++) {
551 u32 flash = le32_to_cpu(snandc->reg_read_buf[i]);
552
553 if (flash & (FS_OP_ERR | FS_MPU_ERR))
554 return -EIO;
555 }
556
557 return 0;
558 }
559
qcom_spi_read_last_cw(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)560 static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc,
561 const struct spi_mem_op *op)
562 {
563 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
564 struct mtd_info *mtd = snandc->qspi->mtd;
565 int size, ret = 0;
566 int col, bbpos;
567 u32 cfg0, cfg1, ecc_bch_cfg;
568 u32 num_cw = snandc->qspi->num_cw;
569
570 qcom_clear_bam_transaction(snandc);
571 qcom_clear_read_regs(snandc);
572
573 size = ecc_cfg->cw_size;
574 col = ecc_cfg->cw_size * (num_cw - 1);
575
576 memset(snandc->data_buffer, 0xff, size);
577 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
578 snandc->regs->addr1 = snandc->qspi->addr2;
579
580 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
581 FIELD_PREP(CW_PER_PAGE_MASK, 0);
582 cfg1 = ecc_cfg->cfg1_raw;
583 ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
584
585 snandc->regs->cmd = snandc->qspi->cmd;
586 snandc->regs->cfg0 = cpu_to_le32(cfg0);
587 snandc->regs->cfg1 = cpu_to_le32(cfg1);
588 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
589 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
590 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
591 snandc->regs->exec = cpu_to_le32(1);
592
593 qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1);
594
595 qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1);
596
597 qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0);
598
599 ret = qcom_submit_descs(snandc);
600 if (ret) {
601 dev_err(snandc->dev, "failed to read last cw\n");
602 return ret;
603 }
604
605 ret = qcom_spi_check_raw_flash_errors(snandc, 1);
606 if (ret)
607 return ret;
608
609 bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
610
611 if (snandc->data_buffer[bbpos] == 0xff)
612 snandc->data_buffer[bbpos + 1] = 0xff;
613 if (snandc->data_buffer[bbpos] != 0xff)
614 snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos];
615
616 memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes);
617
618 return ret;
619 }
620
qcom_spi_check_error(struct qcom_nand_controller * snandc)621 static int qcom_spi_check_error(struct qcom_nand_controller *snandc)
622 {
623 struct snandc_read_status *buf;
624 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
625 int i, num_cw = snandc->qspi->num_cw;
626 bool flash_op_err = false, erased;
627 unsigned int max_bitflips = 0;
628 unsigned int uncorrectable_cws = 0;
629
630 snandc->qspi->ecc_stats.failed = 0;
631 snandc->qspi->ecc_stats.corrected = 0;
632
633 qcom_nandc_dev_to_mem(snandc, true);
634 buf = (struct snandc_read_status *)snandc->reg_read_buf;
635
636 for (i = 0; i < num_cw; i++, buf++) {
637 u32 flash, buffer, erased_cw;
638
639 flash = le32_to_cpu(buf->snandc_flash);
640 buffer = le32_to_cpu(buf->snandc_buffer);
641 erased_cw = le32_to_cpu(buf->snandc_erased_cw);
642
643 if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) {
644 if (ecc_cfg->bch_enabled)
645 erased = (erased_cw & ERASED_CW) == ERASED_CW;
646 else
647 erased = false;
648
649 if (!erased)
650 uncorrectable_cws |= BIT(i);
651
652 } else if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
653 flash_op_err = true;
654 } else {
655 unsigned int stat;
656
657 stat = buffer & BS_CORRECTABLE_ERR_MSK;
658
659 /*
660 * The exact number of the corrected bits is
661 * unknown because the hardware only reports the
662 * number of the corrected bytes.
663 *
664 * Since we have no better solution at the moment,
665 * report that value as the number of bit errors
666 * despite that it is inaccurate in most cases.
667 */
668 if (stat && stat != ecc_cfg->strength)
669 dev_warn_once(snandc->dev,
670 "Warning: due to hw limitation, the reported number of the corrected bits may be inaccurate\n");
671
672 snandc->qspi->ecc_stats.corrected += stat;
673 max_bitflips = max(max_bitflips, stat);
674 }
675 }
676
677 if (flash_op_err)
678 return -EIO;
679
680 if (!uncorrectable_cws)
681 snandc->qspi->ecc_stats.bitflips = max_bitflips;
682 else
683 snandc->qspi->ecc_stats.failed++;
684
685 return 0;
686 }
687
qcom_spi_read_cw_raw(struct qcom_nand_controller * snandc,u8 * data_buf,u8 * oob_buf,int cw)688 static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *data_buf,
689 u8 *oob_buf, int cw)
690 {
691 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
692 struct mtd_info *mtd = snandc->qspi->mtd;
693 int data_size1, data_size2, oob_size1, oob_size2;
694 int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
695 int raw_cw = cw;
696 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
697 int col;
698
699 snandc->buf_count = 0;
700 snandc->buf_start = 0;
701 qcom_clear_read_regs(snandc);
702 qcom_clear_bam_transaction(snandc);
703 raw_cw = num_cw - 1;
704
705 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
706 FIELD_PREP(CW_PER_PAGE_MASK, 0);
707 cfg1 = ecc_cfg->cfg1_raw;
708 ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
709
710 col = ecc_cfg->cw_size * cw;
711
712 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
713 snandc->regs->addr1 = snandc->qspi->addr2;
714 snandc->regs->cmd = snandc->qspi->cmd;
715 snandc->regs->cfg0 = cpu_to_le32(cfg0);
716 snandc->regs->cfg1 = cpu_to_le32(cfg1);
717 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
718 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
719 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
720 snandc->regs->exec = cpu_to_le32(1);
721
722 qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1);
723
724 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
725 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
726 qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0);
727
728 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
729 NAND_ERASED_CW_DETECT_CFG, 1, 0);
730 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
731 NAND_ERASED_CW_DETECT_CFG, 1,
732 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
733
734 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
735 oob_size1 = ecc_cfg->bbm_size;
736
737 if (cw == (num_cw - 1)) {
738 data_size2 = NANDC_STEP_SIZE - data_size1 -
739 ((num_cw - 1) * 4);
740 oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw +
741 ecc_cfg->spare_bytes;
742 } else {
743 data_size2 = ecc_cfg->cw_data - data_size1;
744 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
745 }
746
747 qcom_spi_set_read_loc(snandc, cw, 0, read_loc, data_size1, 0);
748 read_loc += data_size1;
749
750 qcom_spi_set_read_loc(snandc, cw, 1, read_loc, oob_size1, 0);
751 read_loc += oob_size1;
752
753 qcom_spi_set_read_loc(snandc, cw, 2, read_loc, data_size2, 0);
754 read_loc += data_size2;
755
756 qcom_spi_set_read_loc(snandc, cw, 3, read_loc, oob_size2, 1);
757
758 qcom_spi_config_cw_read(snandc, false, raw_cw);
759
760 qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0);
761 reg_off += data_size1;
762
763 qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0);
764 reg_off += oob_size1;
765
766 qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0);
767 reg_off += data_size2;
768
769 qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
770
771 ret = qcom_submit_descs(snandc);
772 if (ret) {
773 dev_err(snandc->dev, "failure to read raw cw %d\n", cw);
774 return ret;
775 }
776
777 return qcom_spi_check_raw_flash_errors(snandc, 1);
778 }
779
qcom_spi_read_page_raw(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)780 static int qcom_spi_read_page_raw(struct qcom_nand_controller *snandc,
781 const struct spi_mem_op *op)
782 {
783 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
784 u8 *data_buf = NULL, *oob_buf = NULL;
785 int ret, cw;
786 u32 num_cw = snandc->qspi->num_cw;
787
788 if (snandc->qspi->page_rw)
789 data_buf = op->data.buf.in;
790
791 oob_buf = snandc->qspi->oob_buf;
792 memset(oob_buf, 0xff, OOB_BUF_SIZE);
793
794 for (cw = 0; cw < num_cw; cw++) {
795 ret = qcom_spi_read_cw_raw(snandc, data_buf, oob_buf, cw);
796 if (ret)
797 return ret;
798
799 if (data_buf)
800 data_buf += ecc_cfg->cw_data;
801 if (oob_buf)
802 oob_buf += ecc_cfg->bytes;
803 }
804
805 return 0;
806 }
807
qcom_spi_read_page_ecc(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)808 static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc,
809 const struct spi_mem_op *op)
810 {
811 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
812 u8 *data_buf = NULL, *oob_buf = NULL;
813 int ret, i;
814 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
815
816 data_buf = op->data.buf.in;
817 oob_buf = snandc->qspi->oob_buf;
818
819 snandc->buf_count = 0;
820 snandc->buf_start = 0;
821 qcom_clear_read_regs(snandc);
822
823 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
824 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
825 cfg1 = ecc_cfg->cfg1;
826 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
827
828 snandc->regs->addr0 = snandc->qspi->addr1;
829 snandc->regs->addr1 = snandc->qspi->addr2;
830 snandc->regs->cmd = snandc->qspi->cmd;
831 snandc->regs->cfg0 = cpu_to_le32(cfg0);
832 snandc->regs->cfg1 = cpu_to_le32(cfg1);
833 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
834 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
835 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
836 snandc->regs->exec = cpu_to_le32(1);
837
838 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
839
840 qcom_clear_bam_transaction(snandc);
841
842 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
843 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
844 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
845 NAND_ERASED_CW_DETECT_CFG, 1, 0);
846 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
847 NAND_ERASED_CW_DETECT_CFG, 1,
848 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
849
850 for (i = 0; i < num_cw; i++) {
851 int data_size, oob_size;
852
853 if (i == (num_cw - 1)) {
854 data_size = 512 - ((num_cw - 1) << 2);
855 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
856 ecc_cfg->spare_bytes;
857 } else {
858 data_size = ecc_cfg->cw_data;
859 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
860 }
861
862 if (data_buf && oob_buf) {
863 qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 0);
864 qcom_spi_set_read_loc(snandc, i, 1, data_size, oob_size, 1);
865 } else if (data_buf) {
866 qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 1);
867 } else {
868 qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
869 }
870
871 qcom_spi_config_cw_read(snandc, true, i);
872
873 if (data_buf)
874 qcom_read_data_dma(snandc, FLASH_BUF_ACC, data_buf,
875 data_size, 0);
876 if (oob_buf) {
877 int j;
878
879 for (j = 0; j < ecc_cfg->bbm_size; j++)
880 *oob_buf++ = 0xff;
881
882 qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
883 oob_buf, oob_size, 0);
884 }
885
886 if (data_buf)
887 data_buf += data_size;
888 if (oob_buf)
889 oob_buf += oob_size;
890 }
891
892 ret = qcom_submit_descs(snandc);
893 if (ret) {
894 dev_err(snandc->dev, "failure to read page\n");
895 return ret;
896 }
897
898 return qcom_spi_check_error(snandc);
899 }
900
qcom_spi_read_page_oob(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)901 static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc,
902 const struct spi_mem_op *op)
903 {
904 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
905 u8 *oob_buf = NULL;
906 int ret, i;
907 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
908
909 oob_buf = op->data.buf.in;
910
911 snandc->buf_count = 0;
912 snandc->buf_start = 0;
913 qcom_clear_read_regs(snandc);
914 qcom_clear_bam_transaction(snandc);
915
916 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
917 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
918 cfg1 = ecc_cfg->cfg1;
919 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
920
921 snandc->regs->addr0 = snandc->qspi->addr1;
922 snandc->regs->addr1 = snandc->qspi->addr2;
923 snandc->regs->cmd = snandc->qspi->cmd;
924 snandc->regs->cfg0 = cpu_to_le32(cfg0);
925 snandc->regs->cfg1 = cpu_to_le32(cfg1);
926 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
927 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
928 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
929 snandc->regs->exec = cpu_to_le32(1);
930
931 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
932
933 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
934 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
935 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
936 NAND_ERASED_CW_DETECT_CFG, 1, 0);
937 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
938 NAND_ERASED_CW_DETECT_CFG, 1,
939 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
940
941 for (i = 0; i < num_cw; i++) {
942 int data_size, oob_size;
943
944 if (i == (num_cw - 1)) {
945 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
946 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
947 ecc_cfg->spare_bytes;
948 } else {
949 data_size = ecc_cfg->cw_data;
950 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
951 }
952
953 qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
954
955 qcom_spi_config_cw_read(snandc, true, i);
956
957 if (oob_buf) {
958 int j;
959
960 for (j = 0; j < ecc_cfg->bbm_size; j++)
961 *oob_buf++ = 0xff;
962
963 qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
964 oob_buf, oob_size, 0);
965 }
966
967 if (oob_buf)
968 oob_buf += oob_size;
969 }
970
971 ret = qcom_submit_descs(snandc);
972 if (ret) {
973 dev_err(snandc->dev, "failure to read oob\n");
974 return ret;
975 }
976
977 return qcom_spi_check_error(snandc);
978 }
979
qcom_spi_read_page(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)980 static int qcom_spi_read_page(struct qcom_nand_controller *snandc,
981 const struct spi_mem_op *op)
982 {
983 if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
984 return qcom_spi_read_page_raw(snandc, op);
985
986 if (snandc->qspi->page_rw)
987 return qcom_spi_read_page_ecc(snandc, op);
988
989 if (snandc->qspi->oob_rw && snandc->qspi->raw_rw)
990 return qcom_spi_read_last_cw(snandc, op);
991
992 if (snandc->qspi->oob_rw)
993 return qcom_spi_read_page_oob(snandc, op);
994
995 return 0;
996 }
997
qcom_spi_config_page_write(struct qcom_nand_controller * snandc)998 static void qcom_spi_config_page_write(struct qcom_nand_controller *snandc)
999 {
1000 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
1001 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
1002 qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG,
1003 1, NAND_BAM_NEXT_SGL);
1004 }
1005
qcom_spi_config_cw_write(struct qcom_nand_controller * snandc)1006 static void qcom_spi_config_cw_write(struct qcom_nand_controller *snandc)
1007 {
1008 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1009 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1010 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1011
1012 qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
1013 qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1,
1014 NAND_BAM_NEXT_SGL);
1015 }
1016
qcom_spi_program_raw(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1017 static int qcom_spi_program_raw(struct qcom_nand_controller *snandc,
1018 const struct spi_mem_op *op)
1019 {
1020 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1021 struct mtd_info *mtd = snandc->qspi->mtd;
1022 u8 *data_buf = NULL, *oob_buf = NULL;
1023 int i, ret;
1024 int num_cw = snandc->qspi->num_cw;
1025 u32 cfg0, cfg1, ecc_bch_cfg;
1026
1027 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
1028 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
1029 cfg1 = ecc_cfg->cfg1_raw;
1030 ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
1031
1032 data_buf = snandc->qspi->data_buf;
1033
1034 oob_buf = snandc->qspi->oob_buf;
1035 memset(oob_buf, 0xff, OOB_BUF_SIZE);
1036
1037 snandc->buf_count = 0;
1038 snandc->buf_start = 0;
1039 qcom_clear_read_regs(snandc);
1040 qcom_clear_bam_transaction(snandc);
1041
1042 snandc->regs->addr0 = snandc->qspi->addr1;
1043 snandc->regs->addr1 = snandc->qspi->addr2;
1044 snandc->regs->cmd = snandc->qspi->cmd;
1045 snandc->regs->cfg0 = cpu_to_le32(cfg0);
1046 snandc->regs->cfg1 = cpu_to_le32(cfg1);
1047 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1048 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
1049 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
1050 snandc->regs->exec = cpu_to_le32(1);
1051
1052 qcom_spi_config_page_write(snandc);
1053
1054 for (i = 0; i < num_cw; i++) {
1055 int data_size1, data_size2, oob_size1, oob_size2;
1056 int reg_off = FLASH_BUF_ACC;
1057
1058 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
1059 oob_size1 = ecc_cfg->bbm_size;
1060
1061 if (i == (num_cw - 1)) {
1062 data_size2 = NANDC_STEP_SIZE - data_size1 -
1063 ((num_cw - 1) << 2);
1064 oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1065 ecc_cfg->spare_bytes;
1066 } else {
1067 data_size2 = ecc_cfg->cw_data - data_size1;
1068 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
1069 }
1070
1071 qcom_write_data_dma(snandc, reg_off, data_buf, data_size1,
1072 NAND_BAM_NO_EOT);
1073 reg_off += data_size1;
1074 data_buf += data_size1;
1075
1076 qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1,
1077 NAND_BAM_NO_EOT);
1078 oob_buf += oob_size1;
1079 reg_off += oob_size1;
1080
1081 qcom_write_data_dma(snandc, reg_off, data_buf, data_size2,
1082 NAND_BAM_NO_EOT);
1083 reg_off += data_size2;
1084 data_buf += data_size2;
1085
1086 qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0);
1087 oob_buf += oob_size2;
1088
1089 qcom_spi_config_cw_write(snandc);
1090 }
1091
1092 ret = qcom_submit_descs(snandc);
1093 if (ret) {
1094 dev_err(snandc->dev, "failure to write raw page\n");
1095 return ret;
1096 }
1097
1098 return 0;
1099 }
1100
qcom_spi_program_ecc(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1101 static int qcom_spi_program_ecc(struct qcom_nand_controller *snandc,
1102 const struct spi_mem_op *op)
1103 {
1104 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1105 u8 *data_buf = NULL, *oob_buf = NULL;
1106 int i, ret;
1107 int num_cw = snandc->qspi->num_cw;
1108 u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1109
1110 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
1111 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
1112 cfg1 = ecc_cfg->cfg1;
1113 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1114 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1115
1116 if (snandc->qspi->data_buf)
1117 data_buf = snandc->qspi->data_buf;
1118
1119 oob_buf = snandc->qspi->oob_buf;
1120
1121 snandc->buf_count = 0;
1122 snandc->buf_start = 0;
1123 qcom_clear_read_regs(snandc);
1124 qcom_clear_bam_transaction(snandc);
1125
1126 snandc->regs->addr0 = snandc->qspi->addr1;
1127 snandc->regs->addr1 = snandc->qspi->addr2;
1128 snandc->regs->cmd = snandc->qspi->cmd;
1129 snandc->regs->cfg0 = cpu_to_le32(cfg0);
1130 snandc->regs->cfg1 = cpu_to_le32(cfg1);
1131 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1132 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1133 snandc->regs->exec = cpu_to_le32(1);
1134
1135 qcom_spi_config_page_write(snandc);
1136
1137 for (i = 0; i < num_cw; i++) {
1138 int data_size, oob_size;
1139
1140 if (i == (num_cw - 1)) {
1141 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1142 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1143 ecc_cfg->spare_bytes;
1144 } else {
1145 data_size = ecc_cfg->cw_data;
1146 oob_size = ecc_cfg->bytes;
1147 }
1148
1149 if (data_buf)
1150 qcom_write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size,
1151 i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0);
1152
1153 if (i == (num_cw - 1)) {
1154 if (oob_buf) {
1155 oob_buf += ecc_cfg->bbm_size;
1156 qcom_write_data_dma(snandc, FLASH_BUF_ACC + data_size,
1157 oob_buf, oob_size, 0);
1158 }
1159 }
1160
1161 qcom_spi_config_cw_write(snandc);
1162
1163 if (data_buf)
1164 data_buf += data_size;
1165 if (oob_buf)
1166 oob_buf += oob_size;
1167 }
1168
1169 ret = qcom_submit_descs(snandc);
1170 if (ret) {
1171 dev_err(snandc->dev, "failure to write page\n");
1172 return ret;
1173 }
1174
1175 return 0;
1176 }
1177
qcom_spi_program_oob(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1178 static int qcom_spi_program_oob(struct qcom_nand_controller *snandc,
1179 const struct spi_mem_op *op)
1180 {
1181 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1182 u8 *oob_buf = NULL;
1183 int ret, col, data_size, oob_size;
1184 int num_cw = snandc->qspi->num_cw;
1185 u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1186
1187 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
1188 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
1189 cfg1 = ecc_cfg->cfg1;
1190 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1191 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1192
1193 col = ecc_cfg->cw_size * (num_cw - 1);
1194
1195 oob_buf = snandc->qspi->data_buf;
1196
1197 snandc->buf_count = 0;
1198 snandc->buf_start = 0;
1199 qcom_clear_read_regs(snandc);
1200 qcom_clear_bam_transaction(snandc);
1201 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
1202 snandc->regs->addr1 = snandc->qspi->addr2;
1203 snandc->regs->cmd = snandc->qspi->cmd;
1204 snandc->regs->cfg0 = cpu_to_le32(cfg0);
1205 snandc->regs->cfg1 = cpu_to_le32(cfg1);
1206 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1207 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1208 snandc->regs->exec = cpu_to_le32(1);
1209
1210 /* calculate the data and oob size for the last codeword/step */
1211 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1212 oob_size = snandc->qspi->mtd->oobavail;
1213
1214 memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data);
1215 /* override new oob content to last codeword */
1216 mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size,
1217 oob_buf, 0, snandc->qspi->mtd->oobavail);
1218 qcom_spi_config_page_write(snandc);
1219 qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0);
1220 qcom_spi_config_cw_write(snandc);
1221
1222 ret = qcom_submit_descs(snandc);
1223 if (ret) {
1224 dev_err(snandc->dev, "failure to write oob\n");
1225 return ret;
1226 }
1227
1228 return 0;
1229 }
1230
qcom_spi_program_execute(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1231 static int qcom_spi_program_execute(struct qcom_nand_controller *snandc,
1232 const struct spi_mem_op *op)
1233 {
1234 if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
1235 return qcom_spi_program_raw(snandc, op);
1236
1237 if (snandc->qspi->page_rw)
1238 return qcom_spi_program_ecc(snandc, op);
1239
1240 if (snandc->qspi->oob_rw)
1241 return qcom_spi_program_oob(snandc, op);
1242
1243 return 0;
1244 }
1245
qcom_spi_cmd_mapping(struct qcom_nand_controller * snandc,u32 opcode,u32 * cmd)1246 static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, u32 *cmd)
1247 {
1248 switch (opcode) {
1249 case SPINAND_RESET:
1250 *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
1251 break;
1252 case SPINAND_READID:
1253 *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
1254 break;
1255 case SPINAND_GET_FEATURE:
1256 *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
1257 break;
1258 case SPINAND_SET_FEATURE:
1259 *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
1260 QPIC_SET_FEATURE);
1261 break;
1262 case SPINAND_READ:
1263 if (snandc->qspi->raw_rw) {
1264 *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1265 SPI_WP | SPI_HOLD | OP_PAGE_READ);
1266 } else {
1267 *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1268 SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
1269 }
1270
1271 break;
1272 case SPINAND_ERASE:
1273 *cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
1274 SPI_HOLD | SPI_TRANSFER_MODE_x1;
1275 break;
1276 case SPINAND_WRITE_EN:
1277 *cmd = SPINAND_WRITE_EN;
1278 break;
1279 case SPINAND_PROGRAM_EXECUTE:
1280 *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1281 SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
1282 break;
1283 case SPINAND_PROGRAM_LOAD:
1284 *cmd = SPINAND_PROGRAM_LOAD;
1285 break;
1286 default:
1287 dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
1288 return -EOPNOTSUPP;
1289 }
1290
1291 return 0;
1292 }
1293
qcom_spi_write_page(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1294 static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
1295 const struct spi_mem_op *op)
1296 {
1297 int ret;
1298 u32 cmd;
1299
1300 ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
1301 if (ret < 0)
1302 return ret;
1303
1304 if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
1305 snandc->qspi->data_buf = (u8 *)op->data.buf.out;
1306
1307 return 0;
1308 }
1309
qcom_spi_send_cmdaddr(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1310 static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
1311 const struct spi_mem_op *op)
1312 {
1313 struct qpic_snand_op s_op = {};
1314 u32 cmd;
1315 int ret, opcode;
1316
1317 ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
1318 if (ret < 0)
1319 return ret;
1320
1321 s_op.cmd_reg = cmd;
1322 s_op.addr1_reg = op->addr.val;
1323 s_op.addr2_reg = 0;
1324
1325 opcode = op->cmd.opcode;
1326
1327 switch (opcode) {
1328 case SPINAND_WRITE_EN:
1329 return 0;
1330 case SPINAND_PROGRAM_EXECUTE:
1331 s_op.addr1_reg = op->addr.val << 16;
1332 s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1333 snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1334 snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1335 snandc->qspi->cmd = cpu_to_le32(cmd);
1336 return qcom_spi_program_execute(snandc, op);
1337 case SPINAND_READ:
1338 s_op.addr1_reg = (op->addr.val << 16);
1339 s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1340 snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1341 snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1342 snandc->qspi->cmd = cpu_to_le32(cmd);
1343 return 0;
1344 case SPINAND_ERASE:
1345 s_op.addr2_reg = (op->addr.val >> 16) & 0xffff;
1346 s_op.addr1_reg = op->addr.val;
1347 snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg << 16);
1348 snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1349 snandc->qspi->cmd = cpu_to_le32(cmd);
1350 return qcom_spi_block_erase(snandc);
1351 default:
1352 break;
1353 }
1354
1355 snandc->buf_count = 0;
1356 snandc->buf_start = 0;
1357 qcom_clear_read_regs(snandc);
1358 qcom_clear_bam_transaction(snandc);
1359
1360 snandc->regs->cmd = cpu_to_le32(s_op.cmd_reg);
1361 snandc->regs->exec = cpu_to_le32(1);
1362 snandc->regs->addr0 = cpu_to_le32(s_op.addr1_reg);
1363 snandc->regs->addr1 = cpu_to_le32(s_op.addr2_reg);
1364
1365 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
1366 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1367
1368 ret = qcom_submit_descs(snandc);
1369 if (ret)
1370 dev_err(snandc->dev, "failure in submitting cmd descriptor\n");
1371
1372 return ret;
1373 }
1374
qcom_spi_io_op(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1375 static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_mem_op *op)
1376 {
1377 int ret, val, opcode;
1378 bool copy = false, copy_ftr = false;
1379
1380 ret = qcom_spi_send_cmdaddr(snandc, op);
1381 if (ret)
1382 return ret;
1383
1384 snandc->buf_count = 0;
1385 snandc->buf_start = 0;
1386 qcom_clear_read_regs(snandc);
1387 qcom_clear_bam_transaction(snandc);
1388 opcode = op->cmd.opcode;
1389
1390 switch (opcode) {
1391 case SPINAND_READID:
1392 snandc->buf_count = 4;
1393 qcom_read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1394 copy = true;
1395 break;
1396 case SPINAND_GET_FEATURE:
1397 snandc->buf_count = 4;
1398 qcom_read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1399 copy_ftr = true;
1400 break;
1401 case SPINAND_SET_FEATURE:
1402 snandc->regs->flash_feature = cpu_to_le32(*(u32 *)op->data.buf.out);
1403 qcom_write_reg_dma(snandc, &snandc->regs->flash_feature,
1404 NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1405 break;
1406 case SPINAND_PROGRAM_EXECUTE:
1407 case SPINAND_WRITE_EN:
1408 case SPINAND_RESET:
1409 case SPINAND_ERASE:
1410 case SPINAND_READ:
1411 return 0;
1412 default:
1413 return -EOPNOTSUPP;
1414 }
1415
1416 ret = qcom_submit_descs(snandc);
1417 if (ret) {
1418 dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode);
1419 return ret;
1420 }
1421
1422 if (copy) {
1423 qcom_nandc_dev_to_mem(snandc, true);
1424 memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
1425 }
1426
1427 if (copy_ftr) {
1428 qcom_nandc_dev_to_mem(snandc, true);
1429 val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf);
1430 val >>= 8;
1431 memcpy(op->data.buf.in, &val, snandc->buf_count);
1432 }
1433
1434 return 0;
1435 }
1436
qcom_spi_is_page_op(const struct spi_mem_op * op)1437 static bool qcom_spi_is_page_op(const struct spi_mem_op *op)
1438 {
1439 if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4)
1440 return false;
1441
1442 if (op->data.dir == SPI_MEM_DATA_IN) {
1443 if (op->addr.buswidth == 4 && op->data.buswidth == 4)
1444 return true;
1445
1446 if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1447 return true;
1448
1449 } else if (op->data.dir == SPI_MEM_DATA_OUT) {
1450 if (op->data.buswidth == 4)
1451 return true;
1452 if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1453 return true;
1454 }
1455
1456 return false;
1457 }
1458
qcom_spi_supports_op(struct spi_mem * mem,const struct spi_mem_op * op)1459 static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
1460 {
1461 if (!spi_mem_default_supports_op(mem, op))
1462 return false;
1463
1464 if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
1465 return false;
1466
1467 if (qcom_spi_is_page_op(op))
1468 return true;
1469
1470 return ((!op->addr.nbytes || op->addr.buswidth == 1) &&
1471 (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
1472 (!op->data.nbytes || op->data.buswidth == 1));
1473 }
1474
qcom_spi_exec_op(struct spi_mem * mem,const struct spi_mem_op * op)1475 static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
1476 {
1477 struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller);
1478
1479 dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
1480 op->addr.val, op->addr.buswidth, op->addr.nbytes,
1481 op->data.buswidth, op->data.nbytes);
1482
1483 if (qcom_spi_is_page_op(op)) {
1484 if (op->data.dir == SPI_MEM_DATA_IN)
1485 return qcom_spi_read_page(snandc, op);
1486 if (op->data.dir == SPI_MEM_DATA_OUT)
1487 return qcom_spi_write_page(snandc, op);
1488 } else {
1489 return qcom_spi_io_op(snandc, op);
1490 }
1491
1492 return 0;
1493 }
1494
1495 static const struct spi_controller_mem_ops qcom_spi_mem_ops = {
1496 .supports_op = qcom_spi_supports_op,
1497 .exec_op = qcom_spi_exec_op,
1498 };
1499
1500 static const struct spi_controller_mem_caps qcom_spi_mem_caps = {
1501 .ecc = true,
1502 };
1503
qcom_spi_probe(struct platform_device * pdev)1504 static int qcom_spi_probe(struct platform_device *pdev)
1505 {
1506 struct device *dev = &pdev->dev;
1507 struct spi_controller *ctlr;
1508 struct qcom_nand_controller *snandc;
1509 struct qpic_spi_nand *qspi;
1510 struct qpic_ecc *ecc;
1511 struct resource *res;
1512 const void *dev_data;
1513 int ret;
1514
1515 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
1516 if (!ecc)
1517 return -ENOMEM;
1518
1519 qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
1520 if (!qspi)
1521 return -ENOMEM;
1522
1523 ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false);
1524 if (!ctlr)
1525 return -ENOMEM;
1526
1527 platform_set_drvdata(pdev, ctlr);
1528
1529 snandc = spi_controller_get_devdata(ctlr);
1530 qspi->snandc = snandc;
1531
1532 snandc->dev = dev;
1533 snandc->qspi = qspi;
1534 snandc->qspi->ctlr = ctlr;
1535 snandc->qspi->ecc = ecc;
1536
1537 dev_data = of_device_get_match_data(dev);
1538 if (!dev_data) {
1539 dev_err(&pdev->dev, "failed to get device data\n");
1540 return -ENODEV;
1541 }
1542
1543 snandc->props = dev_data;
1544 snandc->dev = &pdev->dev;
1545
1546 snandc->core_clk = devm_clk_get(dev, "core");
1547 if (IS_ERR(snandc->core_clk))
1548 return PTR_ERR(snandc->core_clk);
1549
1550 snandc->aon_clk = devm_clk_get(dev, "aon");
1551 if (IS_ERR(snandc->aon_clk))
1552 return PTR_ERR(snandc->aon_clk);
1553
1554 snandc->qspi->iomacro_clk = devm_clk_get(dev, "iom");
1555 if (IS_ERR(snandc->qspi->iomacro_clk))
1556 return PTR_ERR(snandc->qspi->iomacro_clk);
1557
1558 snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1559 if (IS_ERR(snandc->base))
1560 return PTR_ERR(snandc->base);
1561
1562 snandc->base_phys = res->start;
1563 snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res),
1564 DMA_BIDIRECTIONAL, 0);
1565 if (dma_mapping_error(dev, snandc->base_dma))
1566 return -ENXIO;
1567
1568 ret = clk_prepare_enable(snandc->core_clk);
1569 if (ret)
1570 goto err_dis_core_clk;
1571
1572 ret = clk_prepare_enable(snandc->aon_clk);
1573 if (ret)
1574 goto err_dis_aon_clk;
1575
1576 ret = clk_prepare_enable(snandc->qspi->iomacro_clk);
1577 if (ret)
1578 goto err_dis_iom_clk;
1579
1580 ret = qcom_nandc_alloc(snandc);
1581 if (ret)
1582 goto err_snand_alloc;
1583
1584 ret = qcom_spi_init(snandc);
1585 if (ret)
1586 goto err_spi_init;
1587
1588 /* setup ECC engine */
1589 snandc->qspi->ecc_eng.dev = &pdev->dev;
1590 snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
1591 snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined;
1592 snandc->qspi->ecc_eng.priv = snandc;
1593
1594 ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng);
1595 if (ret) {
1596 dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret);
1597 goto err_spi_init;
1598 }
1599
1600 ctlr->num_chipselect = QPIC_QSPI_NUM_CS;
1601 ctlr->mem_ops = &qcom_spi_mem_ops;
1602 ctlr->mem_caps = &qcom_spi_mem_caps;
1603 ctlr->dev.of_node = pdev->dev.of_node;
1604 ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL |
1605 SPI_TX_QUAD | SPI_RX_QUAD;
1606
1607 ret = spi_register_controller(ctlr);
1608 if (ret) {
1609 dev_err(&pdev->dev, "spi_register_controller failed.\n");
1610 goto err_spi_init;
1611 }
1612
1613 return 0;
1614
1615 err_spi_init:
1616 qcom_nandc_unalloc(snandc);
1617 err_snand_alloc:
1618 clk_disable_unprepare(snandc->qspi->iomacro_clk);
1619 err_dis_iom_clk:
1620 clk_disable_unprepare(snandc->aon_clk);
1621 err_dis_aon_clk:
1622 clk_disable_unprepare(snandc->core_clk);
1623 err_dis_core_clk:
1624 dma_unmap_resource(dev, res->start, resource_size(res),
1625 DMA_BIDIRECTIONAL, 0);
1626 return ret;
1627 }
1628
qcom_spi_remove(struct platform_device * pdev)1629 static void qcom_spi_remove(struct platform_device *pdev)
1630 {
1631 struct spi_controller *ctlr = platform_get_drvdata(pdev);
1632 struct qcom_nand_controller *snandc = spi_controller_get_devdata(ctlr);
1633 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1634
1635 spi_unregister_controller(ctlr);
1636
1637 qcom_nandc_unalloc(snandc);
1638
1639 clk_disable_unprepare(snandc->aon_clk);
1640 clk_disable_unprepare(snandc->core_clk);
1641 clk_disable_unprepare(snandc->qspi->iomacro_clk);
1642
1643 dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res),
1644 DMA_BIDIRECTIONAL, 0);
1645 }
1646
1647 static const struct qcom_nandc_props ipq9574_snandc_props = {
1648 .dev_cmd_reg_start = 0x7000,
1649 .bam_offset = 0x30000,
1650 .supports_bam = true,
1651 };
1652
1653 static const struct of_device_id qcom_snandc_of_match[] = {
1654 {
1655 .compatible = "qcom,ipq9574-snand",
1656 .data = &ipq9574_snandc_props,
1657 },
1658 {}
1659 };
1660 MODULE_DEVICE_TABLE(of, qcom_snandc_of_match);
1661
1662 static struct platform_driver qcom_spi_driver = {
1663 .driver = {
1664 .name = "qcom_snand",
1665 .of_match_table = qcom_snandc_of_match,
1666 },
1667 .probe = qcom_spi_probe,
1668 .remove = qcom_spi_remove,
1669 };
1670 module_platform_driver(qcom_spi_driver);
1671
1672 MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores");
1673 MODULE_AUTHOR("Md Sadre Alam <quic_mdalam@quicinc.com>");
1674 MODULE_LICENSE("GPL");
1675
1676