1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2017-2019 NXP */
3
4 #include <linux/unaligned.h>
5 #include <linux/module.h>
6 #include <linux/of.h>
7 #include <linux/of_platform.h>
8 #include <linux/of_net.h>
9 #include <linux/pcs-lynx.h>
10 #include "enetc_ierb.h"
11 #include "enetc_pf_common.h"
12
13 #define ENETC_DRV_NAME_STR "ENETC PF driver"
14
enetc_pf_get_primary_mac_addr(struct enetc_hw * hw,int si,u8 * addr)15 static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)
16 {
17 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
18 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));
19
20 put_unaligned_le32(upper, addr);
21 put_unaligned_le16(lower, addr + 4);
22 }
23
enetc_pf_set_primary_mac_addr(struct enetc_hw * hw,int si,const u8 * addr)24 static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,
25 const u8 *addr)
26 {
27 u32 upper = get_unaligned_le32(addr);
28 u16 lower = get_unaligned_le16(addr + 4);
29
30 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
31 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
32 }
33
enetc_pf_create_pcs(struct enetc_pf * pf,struct mii_bus * bus)34 static struct phylink_pcs *enetc_pf_create_pcs(struct enetc_pf *pf,
35 struct mii_bus *bus)
36 {
37 return lynx_pcs_create_mdiodev(bus, 0);
38 }
39
enetc_pf_destroy_pcs(struct phylink_pcs * pcs)40 static void enetc_pf_destroy_pcs(struct phylink_pcs *pcs)
41 {
42 lynx_pcs_destroy(pcs);
43 }
44
enetc_set_vlan_promisc(struct enetc_hw * hw,char si_map)45 static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map)
46 {
47 u32 val = enetc_port_rd(hw, ENETC_PSIPVMR);
48
49 val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL);
50 enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);
51 }
52
enetc_enable_si_vlan_promisc(struct enetc_pf * pf,int si_idx)53 static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
54 {
55 pf->vlan_promisc_simap |= BIT(si_idx);
56 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
57 }
58
enetc_disable_si_vlan_promisc(struct enetc_pf * pf,int si_idx)59 static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
60 {
61 pf->vlan_promisc_simap &= ~BIT(si_idx);
62 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
63 }
64
enetc_set_isol_vlan(struct enetc_hw * hw,int si,u16 vlan,u8 qos)65 static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)
66 {
67 u32 val = 0;
68
69 if (vlan)
70 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;
71
72 enetc_port_wr(hw, ENETC_PSIVLANR(si), val);
73 }
74
enetc_mac_addr_hash_idx(const u8 * addr)75 static int enetc_mac_addr_hash_idx(const u8 *addr)
76 {
77 u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16;
78 u64 mask = 0;
79 int res = 0;
80 int i;
81
82 for (i = 0; i < 8; i++)
83 mask |= BIT_ULL(i * 6);
84
85 for (i = 0; i < 6; i++)
86 res |= (hweight64(fold & (mask << i)) & 0x1) << i;
87
88 return res;
89 }
90
enetc_reset_mac_addr_filter(struct enetc_mac_filter * filter)91 static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter)
92 {
93 filter->mac_addr_cnt = 0;
94
95 bitmap_zero(filter->mac_hash_table,
96 ENETC_MADDR_HASH_TBL_SZ);
97 }
98
enetc_add_mac_addr_em_filter(struct enetc_mac_filter * filter,const unsigned char * addr)99 static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,
100 const unsigned char *addr)
101 {
102 /* add exact match addr */
103 ether_addr_copy(filter->mac_addr, addr);
104 filter->mac_addr_cnt++;
105 }
106
enetc_add_mac_addr_ht_filter(struct enetc_mac_filter * filter,const unsigned char * addr)107 static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter,
108 const unsigned char *addr)
109 {
110 int idx = enetc_mac_addr_hash_idx(addr);
111
112 /* add hash table entry */
113 __set_bit(idx, filter->mac_hash_table);
114 filter->mac_addr_cnt++;
115 }
116
enetc_clear_mac_ht_flt(struct enetc_si * si,int si_idx,int type)117 static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type)
118 {
119 bool err = si->errata & ENETC_ERR_UCMCSWP;
120
121 if (type == UC) {
122 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);
123 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);
124 } else { /* MC */
125 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);
126 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);
127 }
128 }
129
enetc_set_mac_ht_flt(struct enetc_si * si,int si_idx,int type,unsigned long hash)130 static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type,
131 unsigned long hash)
132 {
133 bool err = si->errata & ENETC_ERR_UCMCSWP;
134
135 if (type == UC) {
136 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err),
137 lower_32_bits(hash));
138 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx),
139 upper_32_bits(hash));
140 } else { /* MC */
141 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err),
142 lower_32_bits(hash));
143 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx),
144 upper_32_bits(hash));
145 }
146 }
147
enetc_sync_mac_filters(struct enetc_pf * pf)148 static void enetc_sync_mac_filters(struct enetc_pf *pf)
149 {
150 struct enetc_mac_filter *f = pf->mac_filter;
151 struct enetc_si *si = pf->si;
152 int i, pos;
153
154 pos = EMETC_MAC_ADDR_FILT_RES;
155
156 for (i = 0; i < MADDR_TYPE; i++, f++) {
157 bool em = (f->mac_addr_cnt == 1) && (i == UC);
158 bool clear = !f->mac_addr_cnt;
159
160 if (clear) {
161 if (i == UC)
162 enetc_clear_mac_flt_entry(si, pos);
163
164 enetc_clear_mac_ht_flt(si, 0, i);
165 continue;
166 }
167
168 /* exact match filter */
169 if (em) {
170 int err;
171
172 enetc_clear_mac_ht_flt(si, 0, UC);
173
174 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,
175 BIT(0));
176 if (!err)
177 continue;
178
179 /* fallback to HT filtering */
180 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",
181 err);
182 }
183
184 /* hash table filter, clear EM filter for UC entries */
185 if (i == UC)
186 enetc_clear_mac_flt_entry(si, pos);
187
188 enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table);
189 }
190 }
191
enetc_pf_set_rx_mode(struct net_device * ndev)192 static void enetc_pf_set_rx_mode(struct net_device *ndev)
193 {
194 struct enetc_ndev_priv *priv = netdev_priv(ndev);
195 struct enetc_pf *pf = enetc_si_priv(priv->si);
196 struct enetc_hw *hw = &priv->si->hw;
197 bool uprom = false, mprom = false;
198 struct enetc_mac_filter *filter;
199 struct netdev_hw_addr *ha;
200 u32 psipmr = 0;
201 bool em;
202
203 if (ndev->flags & IFF_PROMISC) {
204 /* enable promisc mode for SI0 (PF) */
205 psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
206 uprom = true;
207 mprom = true;
208 } else if (ndev->flags & IFF_ALLMULTI) {
209 /* enable multi cast promisc mode for SI0 (PF) */
210 psipmr = ENETC_PSIPMR_SET_MP(0);
211 mprom = true;
212 }
213
214 /* first 2 filter entries belong to PF */
215 if (!uprom) {
216 /* Update unicast filters */
217 filter = &pf->mac_filter[UC];
218 enetc_reset_mac_addr_filter(filter);
219
220 em = (netdev_uc_count(ndev) == 1);
221 netdev_for_each_uc_addr(ha, ndev) {
222 if (em) {
223 enetc_add_mac_addr_em_filter(filter, ha->addr);
224 break;
225 }
226
227 enetc_add_mac_addr_ht_filter(filter, ha->addr);
228 }
229 }
230
231 if (!mprom) {
232 /* Update multicast filters */
233 filter = &pf->mac_filter[MC];
234 enetc_reset_mac_addr_filter(filter);
235
236 netdev_for_each_mc_addr(ha, ndev) {
237 if (!is_multicast_ether_addr(ha->addr))
238 continue;
239
240 enetc_add_mac_addr_ht_filter(filter, ha->addr);
241 }
242 }
243
244 if (!uprom || !mprom)
245 /* update PF entries */
246 enetc_sync_mac_filters(pf);
247
248 psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) &
249 ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0));
250 enetc_port_wr(hw, ENETC_PSIPMR, psipmr);
251 }
252
enetc_set_vlan_ht_filter(struct enetc_hw * hw,int si_idx,unsigned long hash)253 static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx,
254 unsigned long hash)
255 {
256 enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash));
257 enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash));
258 }
259
enetc_vid_hash_idx(unsigned int vid)260 static int enetc_vid_hash_idx(unsigned int vid)
261 {
262 int res = 0;
263 int i;
264
265 for (i = 0; i < 6; i++)
266 res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i;
267
268 return res;
269 }
270
enetc_sync_vlan_ht_filter(struct enetc_pf * pf,bool rehash)271 static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash)
272 {
273 int i;
274
275 if (rehash) {
276 bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE);
277
278 for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) {
279 int hidx = enetc_vid_hash_idx(i);
280
281 __set_bit(hidx, pf->vlan_ht_filter);
282 }
283 }
284
285 enetc_set_vlan_ht_filter(&pf->si->hw, 0, *pf->vlan_ht_filter);
286 }
287
enetc_vlan_rx_add_vid(struct net_device * ndev,__be16 prot,u16 vid)288 static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid)
289 {
290 struct enetc_ndev_priv *priv = netdev_priv(ndev);
291 struct enetc_pf *pf = enetc_si_priv(priv->si);
292 int idx;
293
294 __set_bit(vid, pf->active_vlans);
295
296 idx = enetc_vid_hash_idx(vid);
297 if (!__test_and_set_bit(idx, pf->vlan_ht_filter))
298 enetc_sync_vlan_ht_filter(pf, false);
299
300 return 0;
301 }
302
enetc_vlan_rx_del_vid(struct net_device * ndev,__be16 prot,u16 vid)303 static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid)
304 {
305 struct enetc_ndev_priv *priv = netdev_priv(ndev);
306 struct enetc_pf *pf = enetc_si_priv(priv->si);
307
308 __clear_bit(vid, pf->active_vlans);
309 enetc_sync_vlan_ht_filter(pf, true);
310
311 return 0;
312 }
313
enetc_set_loopback(struct net_device * ndev,bool en)314 static void enetc_set_loopback(struct net_device *ndev, bool en)
315 {
316 struct enetc_ndev_priv *priv = netdev_priv(ndev);
317 struct enetc_si *si = priv->si;
318 u32 reg;
319
320 reg = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
321 if (reg & ENETC_PM0_IFM_RG) {
322 /* RGMII mode */
323 reg = (reg & ~ENETC_PM0_IFM_RLP) |
324 (en ? ENETC_PM0_IFM_RLP : 0);
325 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, reg);
326 } else {
327 /* assume SGMII mode */
328 reg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
329 reg = (reg & ~ENETC_PM0_CMD_XGLP) |
330 (en ? ENETC_PM0_CMD_XGLP : 0);
331 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
332 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
333 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, reg);
334 }
335 }
336
enetc_pf_set_vf_mac(struct net_device * ndev,int vf,u8 * mac)337 static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)
338 {
339 struct enetc_ndev_priv *priv = netdev_priv(ndev);
340 struct enetc_pf *pf = enetc_si_priv(priv->si);
341 struct enetc_vf_state *vf_state;
342
343 if (vf >= pf->total_vfs)
344 return -EINVAL;
345
346 if (!is_valid_ether_addr(mac))
347 return -EADDRNOTAVAIL;
348
349 vf_state = &pf->vf_state[vf];
350 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;
351 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);
352 return 0;
353 }
354
enetc_pf_set_vf_vlan(struct net_device * ndev,int vf,u16 vlan,u8 qos,__be16 proto)355 static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,
356 u8 qos, __be16 proto)
357 {
358 struct enetc_ndev_priv *priv = netdev_priv(ndev);
359 struct enetc_pf *pf = enetc_si_priv(priv->si);
360
361 if (priv->si->errata & ENETC_ERR_VLAN_ISOL)
362 return -EOPNOTSUPP;
363
364 if (vf >= pf->total_vfs)
365 return -EINVAL;
366
367 if (proto != htons(ETH_P_8021Q))
368 /* only C-tags supported for now */
369 return -EPROTONOSUPPORT;
370
371 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);
372 return 0;
373 }
374
enetc_pf_set_vf_spoofchk(struct net_device * ndev,int vf,bool en)375 static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)
376 {
377 struct enetc_ndev_priv *priv = netdev_priv(ndev);
378 struct enetc_pf *pf = enetc_si_priv(priv->si);
379 u32 cfgr;
380
381 if (vf >= pf->total_vfs)
382 return -EINVAL;
383
384 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));
385 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);
386 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);
387
388 return 0;
389 }
390
enetc_port_assign_rfs_entries(struct enetc_si * si)391 static void enetc_port_assign_rfs_entries(struct enetc_si *si)
392 {
393 struct enetc_pf *pf = enetc_si_priv(si);
394 struct enetc_hw *hw = &si->hw;
395 int num_entries, vf_entries, i;
396 u32 val;
397
398 /* split RFS entries between functions */
399 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
400 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);
401 vf_entries = num_entries / (pf->total_vfs + 1);
402
403 for (i = 0; i < pf->total_vfs; i++)
404 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);
405 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),
406 num_entries - vf_entries * pf->total_vfs);
407
408 /* enable RFS on port */
409 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);
410 }
411
enetc_port_get_caps(struct enetc_si * si)412 static void enetc_port_get_caps(struct enetc_si *si)
413 {
414 struct enetc_hw *hw = &si->hw;
415 u32 val;
416
417 val = enetc_port_rd(hw, ENETC_PCAPR0);
418
419 if (val & ENETC_PCAPR0_QBV)
420 si->hw_features |= ENETC_SI_F_QBV;
421
422 if (val & ENETC_PCAPR0_QBU)
423 si->hw_features |= ENETC_SI_F_QBU;
424
425 if (val & ENETC_PCAPR0_PSFP)
426 si->hw_features |= ENETC_SI_F_PSFP;
427 }
428
enetc_port_si_configure(struct enetc_si * si)429 static void enetc_port_si_configure(struct enetc_si *si)
430 {
431 struct enetc_pf *pf = enetc_si_priv(si);
432 struct enetc_hw *hw = &si->hw;
433 int num_rings, i;
434 u32 val;
435
436 enetc_port_get_caps(si);
437
438 val = enetc_port_rd(hw, ENETC_PCAPR0);
439 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));
440
441 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);
442 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);
443
444 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {
445 val = ENETC_PSICFGR0_SET_TXBDR(num_rings);
446 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
447
448 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",
449 num_rings, ENETC_PF_NUM_RINGS);
450
451 num_rings = 0;
452 }
453
454 /* Add default one-time settings for SI0 (PF) */
455 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
456
457 enetc_port_wr(hw, ENETC_PSICFGR0(0), val);
458
459 if (num_rings)
460 num_rings -= ENETC_PF_NUM_RINGS;
461
462 /* Configure the SIs for each available VF */
463 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
464 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;
465
466 if (num_rings) {
467 num_rings /= pf->total_vfs;
468 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);
469 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
470 }
471
472 for (i = 0; i < pf->total_vfs; i++)
473 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);
474
475 /* Port level VLAN settings */
476 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
477 enetc_port_wr(hw, ENETC_PVCLCTR, val);
478 /* use outer tag for VLAN filtering */
479 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
480 }
481
enetc_set_ptcmsdur(struct enetc_hw * hw,u32 * max_sdu)482 void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *max_sdu)
483 {
484 int tc;
485
486 for (tc = 0; tc < 8; tc++) {
487 u32 val = ENETC_MAC_MAXFRM_SIZE;
488
489 if (max_sdu[tc])
490 val = max_sdu[tc] + VLAN_ETH_HLEN;
491
492 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), val);
493 }
494 }
495
enetc_reset_ptcmsdur(struct enetc_hw * hw)496 void enetc_reset_ptcmsdur(struct enetc_hw *hw)
497 {
498 int tc;
499
500 for (tc = 0; tc < 8; tc++)
501 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);
502 }
503
enetc_configure_port_mac(struct enetc_si * si)504 static void enetc_configure_port_mac(struct enetc_si *si)
505 {
506 struct enetc_hw *hw = &si->hw;
507
508 enetc_port_mac_wr(si, ENETC_PM0_MAXFRM,
509 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
510
511 enetc_reset_ptcmsdur(hw);
512
513 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
514 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
515
516 /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high
517 * and may lead to RX lock-up under traffic. Set it to 1 instead,
518 * as recommended by the hardware team.
519 */
520 enetc_port_mac_wr(si, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
521 }
522
enetc_mac_config(struct enetc_si * si,phy_interface_t phy_mode)523 static void enetc_mac_config(struct enetc_si *si, phy_interface_t phy_mode)
524 {
525 u32 val;
526
527 if (phy_interface_mode_is_rgmii(phy_mode)) {
528 val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
529 val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK);
530 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
531 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
532 }
533
534 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
535 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
536 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
537 }
538 }
539
enetc_mac_enable(struct enetc_si * si,bool en)540 static void enetc_mac_enable(struct enetc_si *si, bool en)
541 {
542 u32 val = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
543
544 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
545 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
546
547 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, val);
548 }
549
enetc_configure_port(struct enetc_pf * pf)550 static void enetc_configure_port(struct enetc_pf *pf)
551 {
552 u8 hash_key[ENETC_RSSHASH_KEY_SIZE];
553 struct enetc_hw *hw = &pf->si->hw;
554
555 enetc_configure_port_mac(pf->si);
556
557 enetc_port_si_configure(pf->si);
558
559 /* set up hash key */
560 get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE);
561 enetc_set_rss_key(hw, hash_key);
562
563 /* split up RFS entries */
564 enetc_port_assign_rfs_entries(pf->si);
565
566 /* enforce VLAN promisc mode for all SIs */
567 pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL;
568 enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap);
569
570 enetc_port_wr(hw, ENETC_PSIPMR, 0);
571
572 /* enable port */
573 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);
574 }
575
576 /* Messaging */
enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf * pf,int vf_id)577 static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf,
578 int vf_id)
579 {
580 struct enetc_vf_state *vf_state = &pf->vf_state[vf_id];
581 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
582 struct enetc_msg_cmd_set_primary_mac *cmd;
583 struct device *dev = &pf->si->pdev->dev;
584 u16 cmd_id;
585 char *addr;
586
587 cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr;
588 cmd_id = cmd->header.id;
589 if (cmd_id != ENETC_MSG_CMD_MNG_ADD)
590 return ENETC_MSG_CMD_STATUS_FAIL;
591
592 addr = cmd->mac.sa_data;
593 if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC)
594 dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n",
595 vf_id);
596 else
597 enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr);
598
599 return ENETC_MSG_CMD_STATUS_OK;
600 }
601
enetc_msg_handle_rxmsg(struct enetc_pf * pf,int vf_id,u16 * status)602 void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status)
603 {
604 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
605 struct device *dev = &pf->si->pdev->dev;
606 struct enetc_msg_cmd_header *cmd_hdr;
607 u16 cmd_type;
608
609 *status = ENETC_MSG_CMD_STATUS_OK;
610 cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr;
611 cmd_type = cmd_hdr->type;
612
613 switch (cmd_type) {
614 case ENETC_MSG_CMD_MNG_MAC:
615 *status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id);
616 break;
617 default:
618 dev_err(dev, "command not supported (cmd_type: 0x%x)\n",
619 cmd_type);
620 }
621 }
622
623 #ifdef CONFIG_PCI_IOV
enetc_sriov_configure(struct pci_dev * pdev,int num_vfs)624 static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs)
625 {
626 struct enetc_si *si = pci_get_drvdata(pdev);
627 struct enetc_pf *pf = enetc_si_priv(si);
628 int err;
629
630 if (!num_vfs) {
631 enetc_msg_psi_free(pf);
632 pf->num_vfs = 0;
633 pci_disable_sriov(pdev);
634 } else {
635 pf->num_vfs = num_vfs;
636
637 err = enetc_msg_psi_init(pf);
638 if (err) {
639 dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err);
640 goto err_msg_psi;
641 }
642
643 err = pci_enable_sriov(pdev, num_vfs);
644 if (err) {
645 dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err);
646 goto err_en_sriov;
647 }
648 }
649
650 return num_vfs;
651
652 err_en_sriov:
653 enetc_msg_psi_free(pf);
654 err_msg_psi:
655 pf->num_vfs = 0;
656
657 return err;
658 }
659 #else
660 #define enetc_sriov_configure(pdev, num_vfs) (void)0
661 #endif
662
enetc_pf_set_features(struct net_device * ndev,netdev_features_t features)663 static int enetc_pf_set_features(struct net_device *ndev,
664 netdev_features_t features)
665 {
666 netdev_features_t changed = ndev->features ^ features;
667 struct enetc_ndev_priv *priv = netdev_priv(ndev);
668 int err;
669
670 if (changed & NETIF_F_HW_TC) {
671 err = enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC));
672 if (err)
673 return err;
674 }
675
676 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
677 struct enetc_pf *pf = enetc_si_priv(priv->si);
678
679 if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER))
680 enetc_disable_si_vlan_promisc(pf, 0);
681 else
682 enetc_enable_si_vlan_promisc(pf, 0);
683 }
684
685 if (changed & NETIF_F_LOOPBACK)
686 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));
687
688 enetc_set_features(ndev, features);
689
690 return 0;
691 }
692
enetc_pf_setup_tc(struct net_device * ndev,enum tc_setup_type type,void * type_data)693 static int enetc_pf_setup_tc(struct net_device *ndev, enum tc_setup_type type,
694 void *type_data)
695 {
696 switch (type) {
697 case TC_QUERY_CAPS:
698 return enetc_qos_query_caps(ndev, type_data);
699 case TC_SETUP_QDISC_MQPRIO:
700 return enetc_setup_tc_mqprio(ndev, type_data);
701 case TC_SETUP_QDISC_TAPRIO:
702 return enetc_setup_tc_taprio(ndev, type_data);
703 case TC_SETUP_QDISC_CBS:
704 return enetc_setup_tc_cbs(ndev, type_data);
705 case TC_SETUP_QDISC_ETF:
706 return enetc_setup_tc_txtime(ndev, type_data);
707 case TC_SETUP_BLOCK:
708 return enetc_setup_tc_psfp(ndev, type_data);
709 default:
710 return -EOPNOTSUPP;
711 }
712 }
713
714 static const struct net_device_ops enetc_ndev_ops = {
715 .ndo_open = enetc_open,
716 .ndo_stop = enetc_close,
717 .ndo_start_xmit = enetc_xmit,
718 .ndo_get_stats = enetc_get_stats,
719 .ndo_set_mac_address = enetc_pf_set_mac_addr,
720 .ndo_set_rx_mode = enetc_pf_set_rx_mode,
721 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid,
722 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid,
723 .ndo_set_vf_mac = enetc_pf_set_vf_mac,
724 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan,
725 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk,
726 .ndo_set_features = enetc_pf_set_features,
727 .ndo_eth_ioctl = enetc_ioctl,
728 .ndo_setup_tc = enetc_pf_setup_tc,
729 .ndo_bpf = enetc_setup_bpf,
730 .ndo_xdp_xmit = enetc_xdp_xmit,
731 };
732
733 static struct phylink_pcs *
enetc_pl_mac_select_pcs(struct phylink_config * config,phy_interface_t iface)734 enetc_pl_mac_select_pcs(struct phylink_config *config, phy_interface_t iface)
735 {
736 struct enetc_pf *pf = phylink_to_enetc_pf(config);
737
738 return pf->pcs;
739 }
740
enetc_pl_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)741 static void enetc_pl_mac_config(struct phylink_config *config,
742 unsigned int mode,
743 const struct phylink_link_state *state)
744 {
745 struct enetc_pf *pf = phylink_to_enetc_pf(config);
746
747 enetc_mac_config(pf->si, state->interface);
748 }
749
enetc_force_rgmii_mac(struct enetc_si * si,int speed,int duplex)750 static void enetc_force_rgmii_mac(struct enetc_si *si, int speed, int duplex)
751 {
752 u32 old_val, val;
753
754 old_val = val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
755
756 if (speed == SPEED_1000) {
757 val &= ~ENETC_PM0_IFM_SSP_MASK;
758 val |= ENETC_PM0_IFM_SSP_1000;
759 } else if (speed == SPEED_100) {
760 val &= ~ENETC_PM0_IFM_SSP_MASK;
761 val |= ENETC_PM0_IFM_SSP_100;
762 } else if (speed == SPEED_10) {
763 val &= ~ENETC_PM0_IFM_SSP_MASK;
764 val |= ENETC_PM0_IFM_SSP_10;
765 }
766
767 if (duplex == DUPLEX_FULL)
768 val |= ENETC_PM0_IFM_FULL_DPX;
769 else
770 val &= ~ENETC_PM0_IFM_FULL_DPX;
771
772 if (val == old_val)
773 return;
774
775 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
776 }
777
enetc_pl_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)778 static void enetc_pl_mac_link_up(struct phylink_config *config,
779 struct phy_device *phy, unsigned int mode,
780 phy_interface_t interface, int speed,
781 int duplex, bool tx_pause, bool rx_pause)
782 {
783 struct enetc_pf *pf = phylink_to_enetc_pf(config);
784 u32 pause_off_thresh = 0, pause_on_thresh = 0;
785 u32 init_quanta = 0, refresh_quanta = 0;
786 struct enetc_hw *hw = &pf->si->hw;
787 struct enetc_si *si = pf->si;
788 struct enetc_ndev_priv *priv;
789 u32 rbmr, cmd_cfg;
790 int idx;
791
792 priv = netdev_priv(pf->si->ndev);
793
794 if (pf->si->hw_features & ENETC_SI_F_QBV)
795 enetc_sched_speed_set(priv, speed);
796
797 if (!phylink_autoneg_inband(mode) &&
798 phy_interface_mode_is_rgmii(interface))
799 enetc_force_rgmii_mac(si, speed, duplex);
800
801 /* Flow control */
802 for (idx = 0; idx < priv->num_rx_rings; idx++) {
803 rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
804
805 if (tx_pause)
806 rbmr |= ENETC_RBMR_CM;
807 else
808 rbmr &= ~ENETC_RBMR_CM;
809
810 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
811 }
812
813 if (tx_pause) {
814 /* When the port first enters congestion, send a PAUSE request
815 * with the maximum number of quanta. When the port exits
816 * congestion, it will automatically send a PAUSE frame with
817 * zero quanta.
818 */
819 init_quanta = 0xffff;
820
821 /* Also, set up the refresh timer to send follow-up PAUSE
822 * frames at half the quanta value, in case the congestion
823 * condition persists.
824 */
825 refresh_quanta = 0xffff / 2;
826
827 /* Start emitting PAUSE frames when 3 large frames (or more
828 * smaller frames) have accumulated in the FIFO waiting to be
829 * DMAed to the RX ring.
830 */
831 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE;
832 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;
833 }
834
835 enetc_port_mac_wr(si, ENETC_PM0_PAUSE_QUANTA, init_quanta);
836 enetc_port_mac_wr(si, ENETC_PM0_PAUSE_THRESH, refresh_quanta);
837 enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);
838 enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);
839
840 cmd_cfg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
841
842 if (rx_pause)
843 cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;
844 else
845 cmd_cfg |= ENETC_PM0_PAUSE_IGN;
846
847 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, cmd_cfg);
848
849 enetc_mac_enable(si, true);
850
851 if (si->hw_features & ENETC_SI_F_QBU)
852 enetc_mm_link_state_update(priv, true);
853 }
854
enetc_pl_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)855 static void enetc_pl_mac_link_down(struct phylink_config *config,
856 unsigned int mode,
857 phy_interface_t interface)
858 {
859 struct enetc_pf *pf = phylink_to_enetc_pf(config);
860 struct enetc_si *si = pf->si;
861 struct enetc_ndev_priv *priv;
862
863 priv = netdev_priv(si->ndev);
864
865 if (si->hw_features & ENETC_SI_F_QBU)
866 enetc_mm_link_state_update(priv, false);
867
868 enetc_mac_enable(si, false);
869 }
870
871 static const struct phylink_mac_ops enetc_mac_phylink_ops = {
872 .mac_select_pcs = enetc_pl_mac_select_pcs,
873 .mac_config = enetc_pl_mac_config,
874 .mac_link_up = enetc_pl_mac_link_up,
875 .mac_link_down = enetc_pl_mac_link_down,
876 };
877
878 /* Initialize the entire shared memory for the flow steering entries
879 * of this port (PF + VFs)
880 */
enetc_init_port_rfs_memory(struct enetc_si * si)881 static int enetc_init_port_rfs_memory(struct enetc_si *si)
882 {
883 struct enetc_cmd_rfse rfse = {0};
884 struct enetc_hw *hw = &si->hw;
885 int num_rfs, i, err = 0;
886 u32 val;
887
888 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
889 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
890
891 for (i = 0; i < num_rfs; i++) {
892 err = enetc_set_fs_entry(si, &rfse, i);
893 if (err)
894 break;
895 }
896
897 return err;
898 }
899
enetc_init_port_rss_memory(struct enetc_si * si)900 static int enetc_init_port_rss_memory(struct enetc_si *si)
901 {
902 struct enetc_hw *hw = &si->hw;
903 int num_rss, err;
904 int *rss_table;
905 u32 val;
906
907 val = enetc_port_rd(hw, ENETC_PRSSCAPR);
908 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
909 if (!num_rss)
910 return 0;
911
912 rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL);
913 if (!rss_table)
914 return -ENOMEM;
915
916 err = enetc_set_rss_table(si, rss_table, num_rss);
917
918 kfree(rss_table);
919
920 return err;
921 }
922
enetc_pf_register_with_ierb(struct pci_dev * pdev)923 static int enetc_pf_register_with_ierb(struct pci_dev *pdev)
924 {
925 struct platform_device *ierb_pdev;
926 struct device_node *ierb_node;
927
928 ierb_node = of_find_compatible_node(NULL, NULL,
929 "fsl,ls1028a-enetc-ierb");
930 if (!ierb_node || !of_device_is_available(ierb_node))
931 return -ENODEV;
932
933 ierb_pdev = of_find_device_by_node(ierb_node);
934 of_node_put(ierb_node);
935
936 if (!ierb_pdev)
937 return -EPROBE_DEFER;
938
939 return enetc_ierb_register_pf(ierb_pdev, pdev);
940 }
941
enetc_psi_create(struct pci_dev * pdev)942 static struct enetc_si *enetc_psi_create(struct pci_dev *pdev)
943 {
944 struct enetc_si *si;
945 int err;
946
947 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(struct enetc_pf));
948 if (err) {
949 dev_err_probe(&pdev->dev, err, "PCI probing failed\n");
950 goto out;
951 }
952
953 si = pci_get_drvdata(pdev);
954 if (!si->hw.port || !si->hw.global) {
955 err = -ENODEV;
956 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");
957 goto out_pci_remove;
958 }
959
960 si->revision = enetc_get_ip_revision(&si->hw);
961 err = enetc_get_driver_data(si);
962 if (err) {
963 dev_err(&pdev->dev, "Could not get PF driver data\n");
964 goto out_pci_remove;
965 }
966
967 err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE,
968 &si->cbd_ring);
969 if (err)
970 goto out_pci_remove;
971
972 err = enetc_init_port_rfs_memory(si);
973 if (err) {
974 dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
975 goto out_teardown_cbdr;
976 }
977
978 err = enetc_init_port_rss_memory(si);
979 if (err) {
980 dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
981 goto out_teardown_cbdr;
982 }
983
984 return si;
985
986 out_teardown_cbdr:
987 enetc_teardown_cbdr(&si->cbd_ring);
988 out_pci_remove:
989 enetc_pci_remove(pdev);
990 out:
991 return ERR_PTR(err);
992 }
993
enetc_psi_destroy(struct pci_dev * pdev)994 static void enetc_psi_destroy(struct pci_dev *pdev)
995 {
996 struct enetc_si *si = pci_get_drvdata(pdev);
997
998 enetc_teardown_cbdr(&si->cbd_ring);
999 enetc_pci_remove(pdev);
1000 }
1001
1002 static const struct enetc_pf_ops enetc_pf_ops = {
1003 .set_si_primary_mac = enetc_pf_set_primary_mac_addr,
1004 .get_si_primary_mac = enetc_pf_get_primary_mac_addr,
1005 .create_pcs = enetc_pf_create_pcs,
1006 .destroy_pcs = enetc_pf_destroy_pcs,
1007 .enable_psfp = enetc_psfp_enable,
1008 };
1009
enetc_pf_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1010 static int enetc_pf_probe(struct pci_dev *pdev,
1011 const struct pci_device_id *ent)
1012 {
1013 struct device_node *node = pdev->dev.of_node;
1014 struct enetc_ndev_priv *priv;
1015 struct net_device *ndev;
1016 struct enetc_si *si;
1017 struct enetc_pf *pf;
1018 int err;
1019
1020 err = enetc_pf_register_with_ierb(pdev);
1021 if (err == -EPROBE_DEFER)
1022 return err;
1023 if (err)
1024 dev_warn(&pdev->dev,
1025 "Could not register with IERB driver: %pe, please update the device tree\n",
1026 ERR_PTR(err));
1027
1028 si = enetc_psi_create(pdev);
1029 if (IS_ERR(si)) {
1030 err = PTR_ERR(si);
1031 goto err_psi_create;
1032 }
1033
1034 pf = enetc_si_priv(si);
1035 pf->si = si;
1036 pf->ops = &enetc_pf_ops;
1037
1038 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
1039 if (pf->total_vfs) {
1040 pf->vf_state = kcalloc(pf->total_vfs, sizeof(struct enetc_vf_state),
1041 GFP_KERNEL);
1042 if (!pf->vf_state)
1043 goto err_alloc_vf_state;
1044 }
1045
1046 err = enetc_setup_mac_addresses(node, pf);
1047 if (err)
1048 goto err_setup_mac_addresses;
1049
1050 enetc_configure_port(pf);
1051
1052 enetc_get_si_caps(si);
1053
1054 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);
1055 if (!ndev) {
1056 err = -ENOMEM;
1057 dev_err(&pdev->dev, "netdev creation failed\n");
1058 goto err_alloc_netdev;
1059 }
1060
1061 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);
1062
1063 priv = netdev_priv(ndev);
1064
1065 mutex_init(&priv->mm_lock);
1066
1067 enetc_init_si_rings_params(priv);
1068
1069 err = enetc_alloc_si_resources(priv);
1070 if (err) {
1071 dev_err(&pdev->dev, "SI resource alloc failed\n");
1072 goto err_alloc_si_res;
1073 }
1074
1075 err = enetc_configure_si(priv);
1076 if (err) {
1077 dev_err(&pdev->dev, "Failed to configure SI\n");
1078 goto err_config_si;
1079 }
1080
1081 err = enetc_alloc_msix(priv);
1082 if (err) {
1083 dev_err(&pdev->dev, "MSIX alloc failed\n");
1084 goto err_alloc_msix;
1085 }
1086
1087 err = of_get_phy_mode(node, &pf->if_mode);
1088 if (err) {
1089 dev_err(&pdev->dev, "Failed to read PHY mode\n");
1090 goto err_phy_mode;
1091 }
1092
1093 err = enetc_mdiobus_create(pf, node);
1094 if (err)
1095 goto err_mdiobus_create;
1096
1097 err = enetc_phylink_create(priv, node, &enetc_mac_phylink_ops);
1098 if (err)
1099 goto err_phylink_create;
1100
1101 err = register_netdev(ndev);
1102 if (err)
1103 goto err_reg_netdev;
1104
1105 return 0;
1106
1107 err_reg_netdev:
1108 enetc_phylink_destroy(priv);
1109 err_phylink_create:
1110 enetc_mdiobus_destroy(pf);
1111 err_mdiobus_create:
1112 err_phy_mode:
1113 enetc_free_msix(priv);
1114 err_config_si:
1115 err_alloc_msix:
1116 enetc_free_si_resources(priv);
1117 err_alloc_si_res:
1118 si->ndev = NULL;
1119 free_netdev(ndev);
1120 err_alloc_netdev:
1121 err_setup_mac_addresses:
1122 kfree(pf->vf_state);
1123 err_alloc_vf_state:
1124 enetc_psi_destroy(pdev);
1125 err_psi_create:
1126 return err;
1127 }
1128
enetc_pf_remove(struct pci_dev * pdev)1129 static void enetc_pf_remove(struct pci_dev *pdev)
1130 {
1131 struct enetc_si *si = pci_get_drvdata(pdev);
1132 struct enetc_pf *pf = enetc_si_priv(si);
1133 struct enetc_ndev_priv *priv;
1134
1135 priv = netdev_priv(si->ndev);
1136
1137 if (pf->num_vfs)
1138 enetc_sriov_configure(pdev, 0);
1139
1140 unregister_netdev(si->ndev);
1141
1142 enetc_phylink_destroy(priv);
1143 enetc_mdiobus_destroy(pf);
1144
1145 enetc_free_msix(priv);
1146
1147 enetc_free_si_resources(priv);
1148
1149 free_netdev(si->ndev);
1150 kfree(pf->vf_state);
1151
1152 enetc_psi_destroy(pdev);
1153 }
1154
enetc_fixup_clear_rss_rfs(struct pci_dev * pdev)1155 static void enetc_fixup_clear_rss_rfs(struct pci_dev *pdev)
1156 {
1157 struct device_node *node = pdev->dev.of_node;
1158 struct enetc_si *si;
1159
1160 /* Only apply quirk for disabled functions. For the ones
1161 * that are enabled, enetc_pf_probe() will apply it.
1162 */
1163 if (node && of_device_is_available(node))
1164 return;
1165
1166 si = enetc_psi_create(pdev);
1167 if (!IS_ERR(si))
1168 enetc_psi_destroy(pdev);
1169 }
1170 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF,
1171 enetc_fixup_clear_rss_rfs);
1172
1173 static const struct pci_device_id enetc_pf_id_table[] = {
1174 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },
1175 { 0, } /* End of table. */
1176 };
1177 MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);
1178
1179 static struct pci_driver enetc_pf_driver = {
1180 .name = KBUILD_MODNAME,
1181 .id_table = enetc_pf_id_table,
1182 .probe = enetc_pf_probe,
1183 .remove = enetc_pf_remove,
1184 #ifdef CONFIG_PCI_IOV
1185 .sriov_configure = enetc_sriov_configure,
1186 #endif
1187 };
1188 module_pci_driver(enetc_pf_driver);
1189
1190 MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);
1191 MODULE_LICENSE("Dual BSD/GPL");
1192