1 //===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISC-V target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
16 #include "MCTargetDesc/RISCVMCTargetDesc.h"
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/TargetParser/RISCVISAInfo.h"
23 #include "llvm/TargetParser/RISCVTargetParser.h"
24 #include "llvm/TargetParser/SubtargetFeature.h"
25
26 namespace llvm {
27
28 // RISCVII - This namespace holds all of the target specific flags that
29 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
30 namespace RISCVII {
31 enum {
32 InstFormatPseudo = 0,
33 InstFormatR = 1,
34 InstFormatR4 = 2,
35 InstFormatI = 3,
36 InstFormatS = 4,
37 InstFormatB = 5,
38 InstFormatU = 6,
39 InstFormatJ = 7,
40 InstFormatCR = 8,
41 InstFormatCI = 9,
42 InstFormatCSS = 10,
43 InstFormatCIW = 11,
44 InstFormatCL = 12,
45 InstFormatCS = 13,
46 InstFormatCA = 14,
47 InstFormatCB = 15,
48 InstFormatCJ = 16,
49 InstFormatCU = 17,
50 InstFormatCLB = 18,
51 InstFormatCLH = 19,
52 InstFormatCSB = 20,
53 InstFormatCSH = 21,
54 InstFormatQC_EAI = 22,
55 InstFormatQC_EI = 23,
56 InstFormatQC_EB = 24,
57 InstFormatQC_EJ = 25,
58 InstFormatQC_ES = 26,
59 InstFormatNDS_BRANCH_10 = 27,
60 InstFormatOther = 31,
61
62 InstFormatMask = 31,
63 InstFormatShift = 0,
64
65 ConstraintShift = InstFormatShift + 5,
66 VS2Constraint = 0b001 << ConstraintShift,
67 VS1Constraint = 0b010 << ConstraintShift,
68 VMConstraint = 0b100 << ConstraintShift,
69 ConstraintMask = 0b111 << ConstraintShift,
70
71 VLMulShift = ConstraintShift + 3,
72 VLMulMask = 0b111 << VLMulShift,
73
74 // Is this a _TIED vector pseudo instruction. For these instructions we
75 // shouldn't skip the tied operand when converting to MC instructions.
76 IsTiedPseudoShift = VLMulShift + 3,
77 IsTiedPseudoMask = 1 << IsTiedPseudoShift,
78
79 // Does this instruction have a SEW operand. It will be the last explicit
80 // operand unless there is a vector policy operand. Used by RVV Pseudos.
81 HasSEWOpShift = IsTiedPseudoShift + 1,
82 HasSEWOpMask = 1 << HasSEWOpShift,
83
84 // Does this instruction have a VL operand. It will be the second to last
85 // explicit operand unless there is a vector policy operand. Used by RVV
86 // Pseudos.
87 HasVLOpShift = HasSEWOpShift + 1,
88 HasVLOpMask = 1 << HasVLOpShift,
89
90 // Does this instruction have a vector policy operand. It will be the last
91 // explicit operand. Used by RVV Pseudos.
92 HasVecPolicyOpShift = HasVLOpShift + 1,
93 HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,
94
95 // Is this instruction a vector widening reduction instruction. Used by RVV
96 // Pseudos.
97 IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,
98 IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,
99
100 // Does this instruction care about mask policy. If it is not, the mask policy
101 // could be either agnostic or undisturbed. For example, unmasked, store, and
102 // reduction operations result would not be affected by mask policy, so
103 // compiler has free to select either one.
104 UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
105 UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
106
107 // Indicates that the result can be considered sign extended from bit 31. Some
108 // instructions with this flag aren't W instructions, but are either sign
109 // extended from a smaller size, always outputs a small integer, or put zeros
110 // in bits 63:31. Used by the SExtWRemoval pass.
111 IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,
112 IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,
113
114 HasRoundModeOpShift = IsSignExtendingOpWShift + 1,
115 HasRoundModeOpMask = 1 << HasRoundModeOpShift,
116
117 UsesVXRMShift = HasRoundModeOpShift + 1,
118 UsesVXRMMask = 1 << UsesVXRMShift,
119
120 // Indicates whether these instructions can partially overlap between source
121 // registers and destination registers according to the vector spec.
122 // 0 -> not a vector pseudo
123 // 1 -> default value for vector pseudos. not widening or narrowing.
124 // 2 -> narrowing case
125 // 3 -> widening case
126 TargetOverlapConstraintTypeShift = UsesVXRMShift + 1,
127 TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
128
129 ElementsDependOnVLShift = TargetOverlapConstraintTypeShift + 2,
130 ElementsDependOnVLMask = 1ULL << ElementsDependOnVLShift,
131
132 ElementsDependOnMaskShift = ElementsDependOnVLShift + 1,
133 ElementsDependOnMaskMask = 1ULL << ElementsDependOnMaskShift,
134
135 // Indicates the EEW of a vector instruction's destination operand.
136 // 0 -> 1
137 // 1 -> SEW
138 // 2 -> SEW * 2
139 // 3 -> SEW * 4
140 DestEEWShift = ElementsDependOnMaskShift + 1,
141 DestEEWMask = 3ULL << DestEEWShift,
142 };
143
144 // Helper functions to read TSFlags.
145 /// \returns the format of the instruction.
getFormat(uint64_t TSFlags)146 static inline unsigned getFormat(uint64_t TSFlags) {
147 return (TSFlags & InstFormatMask) >> InstFormatShift;
148 }
149 /// \returns the LMUL for the instruction.
getLMul(uint64_t TSFlags)150 static inline RISCVVType::VLMUL getLMul(uint64_t TSFlags) {
151 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
152 }
153 /// \returns true if this a _TIED pseudo.
isTiedPseudo(uint64_t TSFlags)154 static inline bool isTiedPseudo(uint64_t TSFlags) {
155 return TSFlags & IsTiedPseudoMask;
156 }
157 /// \returns true if there is a SEW operand for the instruction.
hasSEWOp(uint64_t TSFlags)158 static inline bool hasSEWOp(uint64_t TSFlags) {
159 return TSFlags & HasSEWOpMask;
160 }
161 /// \returns true if there is a VL operand for the instruction.
hasVLOp(uint64_t TSFlags)162 static inline bool hasVLOp(uint64_t TSFlags) {
163 return TSFlags & HasVLOpMask;
164 }
165 /// \returns true if there is a vector policy operand for this instruction.
hasVecPolicyOp(uint64_t TSFlags)166 static inline bool hasVecPolicyOp(uint64_t TSFlags) {
167 return TSFlags & HasVecPolicyOpMask;
168 }
169 /// \returns true if it is a vector widening reduction instruction.
isRVVWideningReduction(uint64_t TSFlags)170 static inline bool isRVVWideningReduction(uint64_t TSFlags) {
171 return TSFlags & IsRVVWideningReductionMask;
172 }
173 /// \returns true if mask policy is valid for the instruction.
usesMaskPolicy(uint64_t TSFlags)174 static inline bool usesMaskPolicy(uint64_t TSFlags) {
175 return TSFlags & UsesMaskPolicyMask;
176 }
177
178 /// \returns true if there is a rounding mode operand for this instruction
hasRoundModeOp(uint64_t TSFlags)179 static inline bool hasRoundModeOp(uint64_t TSFlags) {
180 return TSFlags & HasRoundModeOpMask;
181 }
182
183 /// \returns true if this instruction uses vxrm
usesVXRM(uint64_t TSFlags)184 static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
185
186 /// \returns true if the elements in the body are affected by VL,
187 /// e.g. vslide1down.vx/vredsum.vs/viota.m
elementsDependOnVL(uint64_t TSFlags)188 static inline bool elementsDependOnVL(uint64_t TSFlags) {
189 return TSFlags & ElementsDependOnVLMask;
190 }
191
192 /// \returns true if the elements in the body are affected by the mask,
193 /// e.g. vredsum.vs/viota.m
elementsDependOnMask(uint64_t TSFlags)194 static inline bool elementsDependOnMask(uint64_t TSFlags) {
195 return TSFlags & ElementsDependOnMaskMask;
196 }
197
getVLOpNum(const MCInstrDesc & Desc)198 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
199 const uint64_t TSFlags = Desc.TSFlags;
200 // This method is only called if we expect to have a VL operand, and all
201 // instructions with VL also have SEW.
202 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
203 unsigned Offset = 2;
204 if (hasVecPolicyOp(TSFlags))
205 Offset = 3;
206 return Desc.getNumOperands() - Offset;
207 }
208
209 static inline MCRegister
getTailExpandUseRegNo(const FeatureBitset & FeatureBits)210 getTailExpandUseRegNo(const FeatureBitset &FeatureBits) {
211 // For Zicfilp, PseudoTAIL should be expanded to a software guarded branch.
212 // It means to use t2(x7) as rs1 of JALR to expand PseudoTAIL.
213 return FeatureBits[RISCV::FeatureStdExtZicfilp] ? RISCV::X7 : RISCV::X6;
214 }
215
getSEWOpNum(const MCInstrDesc & Desc)216 static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
217 const uint64_t TSFlags = Desc.TSFlags;
218 assert(hasSEWOp(TSFlags));
219 unsigned Offset = 1;
220 if (hasVecPolicyOp(TSFlags))
221 Offset = 2;
222 return Desc.getNumOperands() - Offset;
223 }
224
getVecPolicyOpNum(const MCInstrDesc & Desc)225 static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
226 assert(hasVecPolicyOp(Desc.TSFlags));
227 return Desc.getNumOperands() - 1;
228 }
229
230 /// \returns the index to the rounding mode immediate value if any, otherwise
231 /// returns -1.
getFRMOpNum(const MCInstrDesc & Desc)232 static inline int getFRMOpNum(const MCInstrDesc &Desc) {
233 const uint64_t TSFlags = Desc.TSFlags;
234 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
235 return -1;
236
237 // The operand order
238 // --------------------------------------
239 // | n-1 (if any) | n-2 | n-3 | n-4 |
240 // | policy | sew | vl | frm |
241 // --------------------------------------
242 return getVLOpNum(Desc) - 1;
243 }
244
245 /// \returns the index to the rounding mode immediate value if any, otherwise
246 /// returns -1.
getVXRMOpNum(const MCInstrDesc & Desc)247 static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
248 const uint64_t TSFlags = Desc.TSFlags;
249 if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
250 return -1;
251 // The operand order
252 // --------------------------------------
253 // | n-1 (if any) | n-2 | n-3 | n-4 |
254 // | policy | sew | vl | vxrm |
255 // --------------------------------------
256 return getVLOpNum(Desc) - 1;
257 }
258
259 // Is the first def operand tied to the first use operand. This is true for
260 // vector pseudo instructions that have a merge operand for tail/mask
261 // undisturbed. It's also true for vector FMA instructions where one of the
262 // operands is also the destination register.
isFirstDefTiedToFirstUse(const MCInstrDesc & Desc)263 static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
264 return Desc.getNumDefs() < Desc.getNumOperands() &&
265 Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0;
266 }
267
268 // RISC-V Specific Machine Operand Flags
269 enum {
270 MO_None = 0,
271 MO_CALL = 1,
272 MO_LO = 3,
273 MO_HI = 4,
274 MO_PCREL_LO = 5,
275 MO_PCREL_HI = 6,
276 MO_GOT_HI = 7,
277 MO_TPREL_LO = 8,
278 MO_TPREL_HI = 9,
279 MO_TPREL_ADD = 10,
280 MO_TLS_GOT_HI = 11,
281 MO_TLS_GD_HI = 12,
282 MO_TLSDESC_HI = 13,
283 MO_TLSDESC_LOAD_LO = 14,
284 MO_TLSDESC_ADD_LO = 15,
285 MO_TLSDESC_CALL = 16,
286
287 // Used to differentiate between target-specific "direct" flags and "bitmask"
288 // flags. A machine operand can only have one "direct" flag, but can have
289 // multiple "bitmask" flags.
290 MO_DIRECT_FLAG_MASK = 31
291 };
292 } // namespace RISCVII
293
294 namespace RISCVOp {
295 enum OperandType : unsigned {
296 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
297 OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,
298 OPERAND_UIMM2,
299 OPERAND_UIMM2_LSB0,
300 OPERAND_UIMM3,
301 OPERAND_UIMM4,
302 OPERAND_UIMM5,
303 OPERAND_UIMM5_NONZERO,
304 OPERAND_UIMM5_GT3,
305 OPERAND_UIMM5_PLUS1,
306 OPERAND_UIMM5_GE6_PLUS1,
307 OPERAND_UIMM5_LSB0,
308 OPERAND_UIMM5_SLIST,
309 OPERAND_UIMM6,
310 OPERAND_UIMM6_LSB0,
311 OPERAND_UIMM7,
312 OPERAND_UIMM7_LSB00,
313 OPERAND_UIMM7_LSB000,
314 OPERAND_UIMM8_LSB00,
315 OPERAND_UIMM8,
316 OPERAND_UIMM8_LSB000,
317 OPERAND_UIMM8_GE32,
318 OPERAND_UIMM9_LSB000,
319 OPERAND_UIMM9,
320 OPERAND_UIMM10,
321 OPERAND_UIMM10_LSB00_NONZERO,
322 OPERAND_UIMM11,
323 OPERAND_UIMM12,
324 OPERAND_UIMM14_LSB00,
325 OPERAND_UIMM16,
326 OPERAND_UIMM16_NONZERO,
327 OPERAND_UIMM20,
328 OPERAND_UIMMLOG2XLEN,
329 OPERAND_UIMMLOG2XLEN_NONZERO,
330 OPERAND_UIMM32,
331 OPERAND_UIMM48,
332 OPERAND_UIMM64,
333 OPERAND_ZERO,
334 OPERAND_THREE,
335 OPERAND_FOUR,
336 OPERAND_SIMM5,
337 OPERAND_SIMM5_NONZERO,
338 OPERAND_SIMM5_PLUS1,
339 OPERAND_SIMM6,
340 OPERAND_SIMM6_NONZERO,
341 OPERAND_SIMM10,
342 OPERAND_SIMM10_LSB0000_NONZERO,
343 OPERAND_SIMM11,
344 OPERAND_SIMM12,
345 OPERAND_SIMM12_LSB00000,
346 OPERAND_SIMM16,
347 OPERAND_SIMM16_NONZERO,
348 OPERAND_SIMM20_LI,
349 OPERAND_SIMM26,
350 OPERAND_BARE_SIMM32,
351 OPERAND_CLUI_IMM,
352 OPERAND_VTYPEI10,
353 OPERAND_VTYPEI11,
354 OPERAND_RVKRNUM,
355 OPERAND_RVKRNUM_0_7,
356 OPERAND_RVKRNUM_1_10,
357 OPERAND_RVKRNUM_2_14,
358 OPERAND_RLIST,
359 OPERAND_RLIST_S0,
360 OPERAND_STACKADJ,
361 // Operand is a 3-bit rounding mode, '111' indicates FRM register.
362 // Represents 'frm' argument passing to floating-point operations.
363 OPERAND_FRMARG,
364 // Operand is a 3-bit rounding mode where only RTZ is valid.
365 OPERAND_RTZARG,
366 // Condition code used by select and short forward branch pseudos.
367 OPERAND_COND_CODE,
368 // Vector policy operand.
369 OPERAND_VEC_POLICY,
370 // Vector SEW operand. Stores in log2(SEW).
371 OPERAND_SEW,
372 // Special SEW for mask only instructions. Always 0.
373 OPERAND_SEW_MASK,
374 // Vector rounding mode for VXRM or FRM.
375 OPERAND_VEC_RM,
376 OPERAND_LAST_RISCV_IMM = OPERAND_VEC_RM,
377 // Operand is either a register or uimm5, this is used by V extension pseudo
378 // instructions to represent a value that be passed as AVL to either vsetvli
379 // or vsetivli.
380 OPERAND_AVL,
381 };
382 } // namespace RISCVOp
383
384 // Describes the predecessor/successor bits used in the FENCE instruction.
385 namespace RISCVFenceField {
386 enum FenceField {
387 I = 8,
388 O = 4,
389 R = 2,
390 W = 1
391 };
392 }
393
394 // Describes the supported floating point rounding mode encodings.
395 namespace RISCVFPRndMode {
396 enum RoundingMode {
397 RNE = 0,
398 RTZ = 1,
399 RDN = 2,
400 RUP = 3,
401 RMM = 4,
402 DYN = 7,
403 Invalid
404 };
405
roundingModeToString(RoundingMode RndMode)406 inline static StringRef roundingModeToString(RoundingMode RndMode) {
407 switch (RndMode) {
408 default:
409 llvm_unreachable("Unknown floating point rounding mode");
410 case RISCVFPRndMode::RNE:
411 return "rne";
412 case RISCVFPRndMode::RTZ:
413 return "rtz";
414 case RISCVFPRndMode::RDN:
415 return "rdn";
416 case RISCVFPRndMode::RUP:
417 return "rup";
418 case RISCVFPRndMode::RMM:
419 return "rmm";
420 case RISCVFPRndMode::DYN:
421 return "dyn";
422 }
423 }
424
stringToRoundingMode(StringRef Str)425 inline static RoundingMode stringToRoundingMode(StringRef Str) {
426 return StringSwitch<RoundingMode>(Str)
427 .Case("rne", RISCVFPRndMode::RNE)
428 .Case("rtz", RISCVFPRndMode::RTZ)
429 .Case("rdn", RISCVFPRndMode::RDN)
430 .Case("rup", RISCVFPRndMode::RUP)
431 .Case("rmm", RISCVFPRndMode::RMM)
432 .Case("dyn", RISCVFPRndMode::DYN)
433 .Default(RISCVFPRndMode::Invalid);
434 }
435
isValidRoundingMode(unsigned Mode)436 inline static bool isValidRoundingMode(unsigned Mode) {
437 switch (Mode) {
438 default:
439 return false;
440 case RISCVFPRndMode::RNE:
441 case RISCVFPRndMode::RTZ:
442 case RISCVFPRndMode::RDN:
443 case RISCVFPRndMode::RUP:
444 case RISCVFPRndMode::RMM:
445 case RISCVFPRndMode::DYN:
446 return true;
447 }
448 }
449 } // namespace RISCVFPRndMode
450
451 namespace RISCVVXRndMode {
452 enum RoundingMode {
453 RNU = 0,
454 RNE = 1,
455 RDN = 2,
456 ROD = 3,
457 Invalid
458 };
459
roundingModeToString(RoundingMode RndMode)460 inline static StringRef roundingModeToString(RoundingMode RndMode) {
461 switch (RndMode) {
462 default:
463 llvm_unreachable("Unknown vector fixed-point rounding mode");
464 case RISCVVXRndMode::RNU:
465 return "rnu";
466 case RISCVVXRndMode::RNE:
467 return "rne";
468 case RISCVVXRndMode::RDN:
469 return "rdn";
470 case RISCVVXRndMode::ROD:
471 return "rod";
472 }
473 }
474
stringToRoundingMode(StringRef Str)475 inline static RoundingMode stringToRoundingMode(StringRef Str) {
476 return StringSwitch<RoundingMode>(Str)
477 .Case("rnu", RISCVVXRndMode::RNU)
478 .Case("rne", RISCVVXRndMode::RNE)
479 .Case("rdn", RISCVVXRndMode::RDN)
480 .Case("rod", RISCVVXRndMode::ROD)
481 .Default(RISCVVXRndMode::Invalid);
482 }
483
isValidRoundingMode(unsigned Mode)484 inline static bool isValidRoundingMode(unsigned Mode) {
485 switch (Mode) {
486 default:
487 return false;
488 case RISCVVXRndMode::RNU:
489 case RISCVVXRndMode::RNE:
490 case RISCVVXRndMode::RDN:
491 case RISCVVXRndMode::ROD:
492 return true;
493 }
494 }
495 } // namespace RISCVVXRndMode
496
497 //===----------------------------------------------------------------------===//
498 // Floating-point Immediates
499 //
500
501 namespace RISCVLoadFPImm {
502 float getFPImm(unsigned Imm);
503
504 /// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
505 /// immediate value. If the value cannot be represented as a 5-bit binary
506 /// encoding, then return -1.
507 int getLoadFPImm(APFloat FPImm);
508 } // namespace RISCVLoadFPImm
509
510 namespace RISCVSysReg {
511 struct SysReg {
512 const char Name[32];
513 unsigned Encoding;
514 // FIXME: add these additional fields when needed.
515 // Privilege Access: Read, Write, Read-Only.
516 // unsigned ReadWrite;
517 // Privilege Mode: User, System or Machine.
518 // unsigned Mode;
519 // Check field name.
520 // unsigned Extra;
521 // Register number without the privilege bits.
522 // unsigned Number;
523 FeatureBitset FeaturesRequired;
524 bool IsRV32Only;
525 bool IsAltName;
526 bool IsDeprecatedName;
527
haveRequiredFeaturesSysReg528 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
529 // Not in 32-bit mode.
530 if (IsRV32Only && ActiveFeatures[RISCV::Feature64Bit])
531 return false;
532 // No required feature associated with the system register.
533 if (FeaturesRequired.none())
534 return true;
535 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
536 }
537 };
538
539 #define GET_SysRegEncodings_DECL
540 #define GET_SysRegsList_DECL
541 #include "RISCVGenSearchableTables.inc"
542 } // end namespace RISCVSysReg
543
544 namespace RISCVInsnOpcode {
545 struct RISCVOpcode {
546 char Name[10];
547 uint8_t Value;
548 };
549
550 #define GET_RISCVOpcodesList_DECL
551 #include "RISCVGenSearchableTables.inc"
552 } // end namespace RISCVInsnOpcode
553
554 namespace RISCVABI {
555
556 enum ABI {
557 ABI_ILP32,
558 ABI_ILP32F,
559 ABI_ILP32D,
560 ABI_ILP32E,
561 ABI_LP64,
562 ABI_LP64F,
563 ABI_LP64D,
564 ABI_LP64E,
565 ABI_Unknown
566 };
567
568 // Returns the target ABI, or else a StringError if the requested ABIName is
569 // not supported for the given TT and FeatureBits combination.
570 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
571 StringRef ABIName);
572
573 ABI getTargetABI(StringRef ABIName);
574
575 // Returns the register used to hold the stack pointer after realignment.
576 MCRegister getBPReg();
577
578 // Returns the register holding shadow call stack pointer.
579 MCRegister getSCSPReg();
580
581 } // namespace RISCVABI
582
583 namespace RISCVFeatures {
584
585 // Validates if the given combination of features are valid for the target
586 // triple. Exits with report_fatal_error if not.
587 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
588
589 llvm::Expected<std::unique_ptr<RISCVISAInfo>>
590 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
591
592 } // namespace RISCVFeatures
593
594 namespace RISCVRVC {
595 bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
596 bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
597 } // namespace RISCVRVC
598
599 namespace RISCVZC {
600 enum RLISTENCODE {
601 RA = 4,
602 RA_S0,
603 RA_S0_S1,
604 RA_S0_S2,
605 RA_S0_S3,
606 RA_S0_S4,
607 RA_S0_S5,
608 RA_S0_S6,
609 RA_S0_S7,
610 RA_S0_S8,
611 RA_S0_S9,
612 // note - to include s10, s11 must also be included
613 RA_S0_S11,
614 INVALID_RLIST,
615 };
616
617 inline unsigned encodeRegList(MCRegister EndReg, bool IsRVE = false) {
618 assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
619 switch (EndReg) {
620 case RISCV::X1:
621 return RLISTENCODE::RA;
622 case RISCV::X8:
623 return RLISTENCODE::RA_S0;
624 case RISCV::X9:
625 return RLISTENCODE::RA_S0_S1;
626 case RISCV::X18:
627 return RLISTENCODE::RA_S0_S2;
628 case RISCV::X19:
629 return RLISTENCODE::RA_S0_S3;
630 case RISCV::X20:
631 return RLISTENCODE::RA_S0_S4;
632 case RISCV::X21:
633 return RLISTENCODE::RA_S0_S5;
634 case RISCV::X22:
635 return RLISTENCODE::RA_S0_S6;
636 case RISCV::X23:
637 return RLISTENCODE::RA_S0_S7;
638 case RISCV::X24:
639 return RLISTENCODE::RA_S0_S8;
640 case RISCV::X25:
641 return RLISTENCODE::RA_S0_S9;
642 case RISCV::X27:
643 return RLISTENCODE::RA_S0_S11;
644 default:
645 llvm_unreachable("Undefined input.");
646 }
647 }
648
encodeRegListNumRegs(unsigned NumRegs)649 inline static unsigned encodeRegListNumRegs(unsigned NumRegs) {
650 assert(NumRegs > 0 && NumRegs < 14 && NumRegs != 12 &&
651 "Unexpected number of registers");
652 if (NumRegs == 13)
653 return RLISTENCODE::RA_S0_S11;
654
655 return RLISTENCODE::RA + (NumRegs - 1);
656 }
657
getStackAdjBase(unsigned RlistVal,bool IsRV64)658 inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
659 assert(RlistVal >= RLISTENCODE::RA && RlistVal <= RLISTENCODE::RA_S0_S11 &&
660 "Invalid Rlist");
661 unsigned NumRegs = (RlistVal - RLISTENCODE::RA) + 1;
662 // s10 and s11 are saved together.
663 if (RlistVal == RLISTENCODE::RA_S0_S11)
664 ++NumRegs;
665
666 unsigned RegSize = IsRV64 ? 8 : 4;
667 return alignTo(NumRegs * RegSize, 16);
668 }
669
670 void printRegList(unsigned RlistEncode, raw_ostream &OS);
671 } // namespace RISCVZC
672
673 namespace RISCVVInversePseudosTable {
674 struct PseudoInfo {
675 uint16_t Pseudo;
676 uint16_t BaseInstr;
677 uint8_t VLMul;
678 uint8_t SEW;
679 };
680
681 #define GET_RISCVVInversePseudosTable_DECL
682 #include "RISCVGenSearchableTables.inc"
683 } // namespace RISCVVInversePseudosTable
684
685 namespace RISCV {
686 struct VLSEGPseudo {
687 uint16_t NF : 4;
688 uint16_t Masked : 1;
689 uint16_t Strided : 1;
690 uint16_t FF : 1;
691 uint16_t Log2SEW : 3;
692 uint16_t LMUL : 3;
693 uint16_t Pseudo;
694 };
695
696 struct VLXSEGPseudo {
697 uint16_t NF : 4;
698 uint16_t Masked : 1;
699 uint16_t Ordered : 1;
700 uint16_t Log2SEW : 3;
701 uint16_t LMUL : 3;
702 uint16_t IndexLMUL : 3;
703 uint16_t Pseudo;
704 };
705
706 struct VSSEGPseudo {
707 uint16_t NF : 4;
708 uint16_t Masked : 1;
709 uint16_t Strided : 1;
710 uint16_t Log2SEW : 3;
711 uint16_t LMUL : 3;
712 uint16_t Pseudo;
713 };
714
715 struct VSXSEGPseudo {
716 uint16_t NF : 4;
717 uint16_t Masked : 1;
718 uint16_t Ordered : 1;
719 uint16_t Log2SEW : 3;
720 uint16_t LMUL : 3;
721 uint16_t IndexLMUL : 3;
722 uint16_t Pseudo;
723 };
724
725 struct VLEPseudo {
726 uint16_t Masked : 1;
727 uint16_t Strided : 1;
728 uint16_t FF : 1;
729 uint16_t Log2SEW : 3;
730 uint16_t LMUL : 3;
731 uint16_t Pseudo;
732 };
733
734 struct VSEPseudo {
735 uint16_t Masked : 1;
736 uint16_t Strided : 1;
737 uint16_t Log2SEW : 3;
738 uint16_t LMUL : 3;
739 uint16_t Pseudo;
740 };
741
742 struct VLX_VSXPseudo {
743 uint16_t Masked : 1;
744 uint16_t Ordered : 1;
745 uint16_t Log2SEW : 3;
746 uint16_t LMUL : 3;
747 uint16_t IndexLMUL : 3;
748 uint16_t Pseudo;
749 };
750
751 struct NDSVLNPseudo {
752 uint16_t Masked : 1;
753 uint16_t Unsigned : 1;
754 uint16_t Log2SEW : 3;
755 uint16_t LMUL : 3;
756 uint16_t Pseudo;
757 };
758
759 #define GET_RISCVVSSEGTable_DECL
760 #define GET_RISCVVLSEGTable_DECL
761 #define GET_RISCVVLXSEGTable_DECL
762 #define GET_RISCVVSXSEGTable_DECL
763 #define GET_RISCVVLETable_DECL
764 #define GET_RISCVVSETable_DECL
765 #define GET_RISCVVLXTable_DECL
766 #define GET_RISCVVSXTable_DECL
767 #define GET_RISCVNDSVLNTable_DECL
768 #include "RISCVGenSearchableTables.inc"
769 } // namespace RISCV
770
771 } // namespace llvm
772
773 #endif
774