1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2018, Google LLC. 4 */ 5 6 #include <asm/msr-index.h> 7 8 #include "test_util.h" 9 #include "kvm_util.h" 10 #include "processor.h" 11 #include "vmx.h" 12 13 #define KVM_EPT_PAGE_TABLE_MIN_PADDR 0x1c0000 14 15 #define EPTP_MT_SHIFT 0 /* EPTP memtype bits 2:0 */ 16 #define EPTP_PWL_SHIFT 3 /* EPTP page walk length bits 5:3 */ 17 #define EPTP_AD_ENABLED_SHIFT 6 /* EPTP AD enabled bit 6 */ 18 19 #define EPTP_WB (X86_MEMTYPE_WB << EPTP_MT_SHIFT) 20 #define EPTP_PWL_4 (3ULL << EPTP_PWL_SHIFT) /* PWL is (levels - 1) */ 21 #define EPTP_AD_ENABLED (1ULL << EPTP_AD_ENABLED_SHIFT) 22 23 bool enable_evmcs; 24 25 struct hv_enlightened_vmcs *current_evmcs; 26 struct hv_vp_assist_page *current_vp_assist; 27 28 int vcpu_enable_evmcs(struct kvm_vcpu *vcpu) 29 { 30 u16 evmcs_ver; 31 32 vcpu_enable_cap(vcpu, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 33 (unsigned long)&evmcs_ver); 34 35 /* KVM should return supported EVMCS version range */ 36 TEST_ASSERT(((evmcs_ver >> 8) >= (evmcs_ver & 0xff)) && 37 (evmcs_ver & 0xff) > 0, 38 "Incorrect EVMCS version range: %x:%x", 39 evmcs_ver & 0xff, evmcs_ver >> 8); 40 41 return evmcs_ver; 42 } 43 44 void vm_enable_ept(struct kvm_vm *vm) 45 { 46 struct pte_masks pte_masks; 47 48 TEST_ASSERT(kvm_cpu_has_ept(), "KVM doesn't support nested EPT"); 49 50 /* 51 * EPTs do not have 'present' or 'user' bits, instead bit 0 is the 52 * 'readable' bit. 53 */ 54 pte_masks = (struct pte_masks) { 55 .present = 0, 56 .user = 0, 57 .readable = BIT_ULL(0), 58 .writable = BIT_ULL(1), 59 .executable = BIT_ULL(2), 60 .huge = BIT_ULL(7), 61 .accessed = BIT_ULL(8), 62 .dirty = BIT_ULL(9), 63 .nx = 0, 64 }; 65 66 /* TODO: Add support for 5-level EPT. */ 67 tdp_mmu_init(vm, 4, &pte_masks); 68 } 69 70 /* Allocate memory regions for nested VMX tests. 71 * 72 * Input Args: 73 * vm - The VM to allocate guest-virtual addresses in. 74 * 75 * Output Args: 76 * p_vmx_gva - The guest virtual address for the struct vmx_pages. 77 * 78 * Return: 79 * Pointer to structure with the addresses of the VMX areas. 80 */ 81 struct vmx_pages * 82 vcpu_alloc_vmx(struct kvm_vm *vm, gva_t *p_vmx_gva) 83 { 84 gva_t vmx_gva = vm_alloc_page(vm); 85 struct vmx_pages *vmx = addr_gva2hva(vm, vmx_gva); 86 87 /* Setup of a region of guest memory for the vmxon region. */ 88 vmx->vmxon = (void *)vm_alloc_page(vm); 89 vmx->vmxon_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmxon); 90 vmx->vmxon_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmxon); 91 92 /* Setup of a region of guest memory for a vmcs. */ 93 vmx->vmcs = (void *)vm_alloc_page(vm); 94 vmx->vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmcs); 95 vmx->vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmcs); 96 97 /* Setup of a region of guest memory for the MSR bitmap. */ 98 vmx->msr = (void *)vm_alloc_page(vm); 99 vmx->msr_hva = addr_gva2hva(vm, (uintptr_t)vmx->msr); 100 vmx->msr_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->msr); 101 memset(vmx->msr_hva, 0, getpagesize()); 102 103 /* Setup of a region of guest memory for the shadow VMCS. */ 104 vmx->shadow_vmcs = (void *)vm_alloc_page(vm); 105 vmx->shadow_vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->shadow_vmcs); 106 vmx->shadow_vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->shadow_vmcs); 107 108 /* Setup of a region of guest memory for the VMREAD and VMWRITE bitmaps. */ 109 vmx->vmread = (void *)vm_alloc_page(vm); 110 vmx->vmread_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmread); 111 vmx->vmread_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmread); 112 memset(vmx->vmread_hva, 0, getpagesize()); 113 114 vmx->vmwrite = (void *)vm_alloc_page(vm); 115 vmx->vmwrite_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmwrite); 116 vmx->vmwrite_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmwrite); 117 memset(vmx->vmwrite_hva, 0, getpagesize()); 118 119 vmx->stack = (void *)vm_alloc_stack(vm, 1); 120 121 if (vm->stage2_mmu.pgd_created) 122 vmx->eptp_gpa = vm->stage2_mmu.pgd; 123 124 *p_vmx_gva = vmx_gva; 125 return vmx; 126 } 127 128 bool prepare_for_vmx_operation(struct vmx_pages *vmx) 129 { 130 u64 feature_control; 131 u64 required; 132 unsigned long cr0; 133 unsigned long cr4; 134 135 /* 136 * Ensure bits in CR0 and CR4 are valid in VMX operation: 137 * - Bit X is 1 in _FIXED0: bit X is fixed to 1 in CRx. 138 * - Bit X is 0 in _FIXED1: bit X is fixed to 0 in CRx. 139 */ 140 __asm__ __volatile__("mov %%cr0, %0" : "=r"(cr0) : : "memory"); 141 cr0 &= rdmsr(MSR_IA32_VMX_CR0_FIXED1); 142 cr0 |= rdmsr(MSR_IA32_VMX_CR0_FIXED0); 143 __asm__ __volatile__("mov %0, %%cr0" : : "r"(cr0) : "memory"); 144 145 __asm__ __volatile__("mov %%cr4, %0" : "=r"(cr4) : : "memory"); 146 cr4 &= rdmsr(MSR_IA32_VMX_CR4_FIXED1); 147 cr4 |= rdmsr(MSR_IA32_VMX_CR4_FIXED0); 148 /* Enable VMX operation */ 149 cr4 |= X86_CR4_VMXE; 150 __asm__ __volatile__("mov %0, %%cr4" : : "r"(cr4) : "memory"); 151 152 /* 153 * Configure IA32_FEATURE_CONTROL MSR to allow VMXON: 154 * Bit 0: Lock bit. If clear, VMXON causes a #GP. 155 * Bit 2: Enables VMXON outside of SMX operation. If clear, VMXON 156 * outside of SMX causes a #GP. 157 */ 158 required = FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 159 required |= FEAT_CTL_LOCKED; 160 feature_control = rdmsr(MSR_IA32_FEAT_CTL); 161 if ((feature_control & required) != required) 162 wrmsr(MSR_IA32_FEAT_CTL, feature_control | required); 163 164 /* Enter VMX root operation. */ 165 *(u32 *)(vmx->vmxon) = vmcs_revision(); 166 if (vmxon(vmx->vmxon_gpa)) 167 return false; 168 169 return true; 170 } 171 172 bool load_vmcs(struct vmx_pages *vmx) 173 { 174 /* Load a VMCS. */ 175 *(u32 *)(vmx->vmcs) = vmcs_revision(); 176 if (vmclear(vmx->vmcs_gpa)) 177 return false; 178 179 if (vmptrld(vmx->vmcs_gpa)) 180 return false; 181 182 /* Setup shadow VMCS, do not load it yet. */ 183 *(u32 *)(vmx->shadow_vmcs) = vmcs_revision() | 0x80000000ul; 184 if (vmclear(vmx->shadow_vmcs_gpa)) 185 return false; 186 187 return true; 188 } 189 190 static bool ept_vpid_cap_supported(u64 mask) 191 { 192 return rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & mask; 193 } 194 195 bool ept_1g_pages_supported(void) 196 { 197 return ept_vpid_cap_supported(VMX_EPT_VPID_CAP_1G_PAGES); 198 } 199 200 /* 201 * Initialize the control fields to the most basic settings possible. 202 */ 203 static inline void init_vmcs_control_fields(struct vmx_pages *vmx) 204 { 205 u32 sec_exec_ctl = 0; 206 207 vmwrite(VIRTUAL_PROCESSOR_ID, 0); 208 vmwrite(POSTED_INTR_NV, 0); 209 210 vmwrite(PIN_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS)); 211 212 if (vmx->eptp_gpa) { 213 u64 eptp = vmx->eptp_gpa | EPTP_WB | EPTP_PWL_4; 214 215 TEST_ASSERT((vmx->eptp_gpa & ~PHYSICAL_PAGE_MASK) == 0, 216 "Illegal bits set in vmx->eptp_gpa"); 217 218 if (ept_vpid_cap_supported(VMX_EPT_VPID_CAP_AD_BITS)) 219 eptp |= EPTP_AD_ENABLED; 220 221 vmwrite(EPT_POINTER, eptp); 222 sec_exec_ctl |= SECONDARY_EXEC_ENABLE_EPT; 223 } 224 225 if (!vmwrite(SECONDARY_VM_EXEC_CONTROL, sec_exec_ctl)) 226 vmwrite(CPU_BASED_VM_EXEC_CONTROL, 227 rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); 228 else { 229 vmwrite(CPU_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS)); 230 GUEST_ASSERT(!sec_exec_ctl); 231 } 232 233 vmwrite(EXCEPTION_BITMAP, 0); 234 vmwrite(PAGE_FAULT_ERROR_CODE_MASK, 0); 235 vmwrite(PAGE_FAULT_ERROR_CODE_MATCH, 0); 236 vmwrite(CR3_TARGET_COUNT, 0); 237 vmwrite(VM_EXIT_CONTROLS, rdmsr(MSR_IA32_VMX_EXIT_CTLS) | 238 VM_EXIT_HOST_ADDR_SPACE_SIZE); /* 64-bit host */ 239 vmwrite(VM_EXIT_MSR_STORE_COUNT, 0); 240 vmwrite(VM_EXIT_MSR_LOAD_COUNT, 0); 241 vmwrite(VM_ENTRY_CONTROLS, rdmsr(MSR_IA32_VMX_ENTRY_CTLS) | 242 VM_ENTRY_IA32E_MODE); /* 64-bit guest */ 243 vmwrite(VM_ENTRY_MSR_LOAD_COUNT, 0); 244 vmwrite(VM_ENTRY_INTR_INFO_FIELD, 0); 245 vmwrite(TPR_THRESHOLD, 0); 246 247 vmwrite(CR0_GUEST_HOST_MASK, 0); 248 vmwrite(CR4_GUEST_HOST_MASK, 0); 249 vmwrite(CR0_READ_SHADOW, get_cr0()); 250 vmwrite(CR4_READ_SHADOW, get_cr4()); 251 252 vmwrite(MSR_BITMAP, vmx->msr_gpa); 253 vmwrite(VMREAD_BITMAP, vmx->vmread_gpa); 254 vmwrite(VMWRITE_BITMAP, vmx->vmwrite_gpa); 255 } 256 257 /* 258 * Initialize the host state fields based on the current host state, with 259 * the exception of HOST_RSP and HOST_RIP, which should be set by vmlaunch 260 * or vmresume. 261 */ 262 static inline void init_vmcs_host_state(void) 263 { 264 u32 exit_controls = vmreadz(VM_EXIT_CONTROLS); 265 266 vmwrite(HOST_ES_SELECTOR, get_es()); 267 vmwrite(HOST_CS_SELECTOR, get_cs()); 268 vmwrite(HOST_SS_SELECTOR, get_ss()); 269 vmwrite(HOST_DS_SELECTOR, get_ds()); 270 vmwrite(HOST_FS_SELECTOR, get_fs()); 271 vmwrite(HOST_GS_SELECTOR, get_gs()); 272 vmwrite(HOST_TR_SELECTOR, get_tr()); 273 274 if (exit_controls & VM_EXIT_LOAD_IA32_PAT) 275 vmwrite(HOST_IA32_PAT, rdmsr(MSR_IA32_CR_PAT)); 276 if (exit_controls & VM_EXIT_LOAD_IA32_EFER) 277 vmwrite(HOST_IA32_EFER, rdmsr(MSR_EFER)); 278 if (exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 279 vmwrite(HOST_IA32_PERF_GLOBAL_CTRL, 280 rdmsr(MSR_CORE_PERF_GLOBAL_CTRL)); 281 282 vmwrite(HOST_IA32_SYSENTER_CS, rdmsr(MSR_IA32_SYSENTER_CS)); 283 284 vmwrite(HOST_CR0, get_cr0()); 285 vmwrite(HOST_CR3, get_cr3()); 286 vmwrite(HOST_CR4, get_cr4()); 287 vmwrite(HOST_FS_BASE, rdmsr(MSR_FS_BASE)); 288 vmwrite(HOST_GS_BASE, rdmsr(MSR_GS_BASE)); 289 vmwrite(HOST_TR_BASE, 290 get_desc64_base((struct desc64 *)(get_gdt().address + get_tr()))); 291 vmwrite(HOST_GDTR_BASE, get_gdt().address); 292 vmwrite(HOST_IDTR_BASE, get_idt().address); 293 vmwrite(HOST_IA32_SYSENTER_ESP, rdmsr(MSR_IA32_SYSENTER_ESP)); 294 vmwrite(HOST_IA32_SYSENTER_EIP, rdmsr(MSR_IA32_SYSENTER_EIP)); 295 } 296 297 /* 298 * Initialize the guest state fields essentially as a clone of 299 * the host state fields. Some host state fields have fixed 300 * values, and we set the corresponding guest state fields accordingly. 301 */ 302 static inline void init_vmcs_guest_state(void *rip, void *rsp) 303 { 304 vmwrite(GUEST_ES_SELECTOR, vmreadz(HOST_ES_SELECTOR)); 305 vmwrite(GUEST_CS_SELECTOR, vmreadz(HOST_CS_SELECTOR)); 306 vmwrite(GUEST_SS_SELECTOR, vmreadz(HOST_SS_SELECTOR)); 307 vmwrite(GUEST_DS_SELECTOR, vmreadz(HOST_DS_SELECTOR)); 308 vmwrite(GUEST_FS_SELECTOR, vmreadz(HOST_FS_SELECTOR)); 309 vmwrite(GUEST_GS_SELECTOR, vmreadz(HOST_GS_SELECTOR)); 310 vmwrite(GUEST_LDTR_SELECTOR, 0); 311 vmwrite(GUEST_TR_SELECTOR, vmreadz(HOST_TR_SELECTOR)); 312 vmwrite(GUEST_INTR_STATUS, 0); 313 vmwrite(GUEST_PML_INDEX, 0); 314 315 vmwrite(VMCS_LINK_POINTER, -1ll); 316 vmwrite(GUEST_IA32_DEBUGCTL, 0); 317 vmwrite(GUEST_IA32_PAT, vmreadz(HOST_IA32_PAT)); 318 vmwrite(GUEST_IA32_EFER, vmreadz(HOST_IA32_EFER)); 319 vmwrite(GUEST_IA32_PERF_GLOBAL_CTRL, 320 vmreadz(HOST_IA32_PERF_GLOBAL_CTRL)); 321 322 vmwrite(GUEST_ES_LIMIT, -1); 323 vmwrite(GUEST_CS_LIMIT, -1); 324 vmwrite(GUEST_SS_LIMIT, -1); 325 vmwrite(GUEST_DS_LIMIT, -1); 326 vmwrite(GUEST_FS_LIMIT, -1); 327 vmwrite(GUEST_GS_LIMIT, -1); 328 vmwrite(GUEST_LDTR_LIMIT, -1); 329 vmwrite(GUEST_TR_LIMIT, 0x67); 330 vmwrite(GUEST_GDTR_LIMIT, 0xffff); 331 vmwrite(GUEST_IDTR_LIMIT, 0xffff); 332 vmwrite(GUEST_ES_AR_BYTES, 333 vmreadz(GUEST_ES_SELECTOR) == 0 ? 0x10000 : 0xc093); 334 vmwrite(GUEST_CS_AR_BYTES, 0xa09b); 335 vmwrite(GUEST_SS_AR_BYTES, 0xc093); 336 vmwrite(GUEST_DS_AR_BYTES, 337 vmreadz(GUEST_DS_SELECTOR) == 0 ? 0x10000 : 0xc093); 338 vmwrite(GUEST_FS_AR_BYTES, 339 vmreadz(GUEST_FS_SELECTOR) == 0 ? 0x10000 : 0xc093); 340 vmwrite(GUEST_GS_AR_BYTES, 341 vmreadz(GUEST_GS_SELECTOR) == 0 ? 0x10000 : 0xc093); 342 vmwrite(GUEST_LDTR_AR_BYTES, 0x10000); 343 vmwrite(GUEST_TR_AR_BYTES, 0x8b); 344 vmwrite(GUEST_INTERRUPTIBILITY_INFO, 0); 345 vmwrite(GUEST_ACTIVITY_STATE, 0); 346 vmwrite(GUEST_SYSENTER_CS, vmreadz(HOST_IA32_SYSENTER_CS)); 347 vmwrite(VMX_PREEMPTION_TIMER_VALUE, 0); 348 349 vmwrite(GUEST_CR0, vmreadz(HOST_CR0)); 350 vmwrite(GUEST_CR3, vmreadz(HOST_CR3)); 351 vmwrite(GUEST_CR4, vmreadz(HOST_CR4)); 352 vmwrite(GUEST_ES_BASE, 0); 353 vmwrite(GUEST_CS_BASE, 0); 354 vmwrite(GUEST_SS_BASE, 0); 355 vmwrite(GUEST_DS_BASE, 0); 356 vmwrite(GUEST_FS_BASE, vmreadz(HOST_FS_BASE)); 357 vmwrite(GUEST_GS_BASE, vmreadz(HOST_GS_BASE)); 358 vmwrite(GUEST_LDTR_BASE, 0); 359 vmwrite(GUEST_TR_BASE, vmreadz(HOST_TR_BASE)); 360 vmwrite(GUEST_GDTR_BASE, vmreadz(HOST_GDTR_BASE)); 361 vmwrite(GUEST_IDTR_BASE, vmreadz(HOST_IDTR_BASE)); 362 vmwrite(GUEST_DR7, 0x400); 363 vmwrite(GUEST_RSP, (u64)rsp); 364 vmwrite(GUEST_RIP, (u64)rip); 365 vmwrite(GUEST_RFLAGS, X86_EFLAGS_FIXED); 366 vmwrite(GUEST_PENDING_DBG_EXCEPTIONS, 0); 367 vmwrite(GUEST_SYSENTER_ESP, vmreadz(HOST_IA32_SYSENTER_ESP)); 368 vmwrite(GUEST_SYSENTER_EIP, vmreadz(HOST_IA32_SYSENTER_EIP)); 369 } 370 371 void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip) 372 { 373 init_vmcs_control_fields(vmx); 374 init_vmcs_host_state(); 375 init_vmcs_guest_state(guest_rip, vmx->stack); 376 } 377 378 bool kvm_cpu_has_ept(void) 379 { 380 u64 ctrl; 381 382 if (!kvm_cpu_has(X86_FEATURE_VMX)) 383 return false; 384 385 ctrl = kvm_get_feature_msr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) >> 32; 386 if (!(ctrl & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) 387 return false; 388 389 ctrl = kvm_get_feature_msr(MSR_IA32_VMX_PROCBASED_CTLS2) >> 32; 390 return ctrl & SECONDARY_EXEC_ENABLE_EPT; 391 } 392 393 void prepare_virtualize_apic_accesses(struct vmx_pages *vmx, struct kvm_vm *vm) 394 { 395 vmx->apic_access = (void *)vm_alloc_page(vm); 396 vmx->apic_access_hva = addr_gva2hva(vm, (uintptr_t)vmx->apic_access); 397 vmx->apic_access_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->apic_access); 398 } 399