1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2009-2013, 2016 Chelsio, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33 #ifndef __IW_CXGB4_H__
34 #define __IW_CXGB4_H__
35
36 #include <linux/list.h>
37 #include <linux/spinlock.h>
38 #include <linux/completion.h>
39 #include <linux/sched.h>
40 #include <linux/pci.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/wait.h>
43 #include <linux/kref.h>
44 #include <linux/timer.h>
45 #include <linux/io.h>
46 #include <sys/vmem.h>
47
48 #include <asm/byteorder.h>
49
50 #include <netinet/in.h>
51 #include <netinet/toecore.h>
52
53 #include <rdma/ib_verbs.h>
54 #include <rdma/iw_cm.h>
55 #include <rdma/uverbs_ioctl.h>
56
57 #include "common/common.h"
58 #include "common/t4_msg.h"
59 #include "common/t4_regs.h"
60 #include "common/t4_tcb.h"
61 #include "t4_l2t.h"
62
63 #define DRV_NAME "iw_cxgbe"
64 #define MOD DRV_NAME ":"
65 #define KTR_IW_CXGBE KTR_SPARE3
66
67 extern int c4iw_debug;
68 extern int use_dsgl;
69 extern int inline_threshold;
70
71 #define PDBG(fmt, args...) \
72 do { \
73 if (c4iw_debug) \
74 printf(MOD fmt, ## args); \
75 } while (0)
76
77 #include "t4.h"
78
cplhdr(struct mbuf * m)79 static inline void *cplhdr(struct mbuf *m)
80 {
81 return mtod(m, void*);
82 }
83
84 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.pbl.start)
85 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start)
86
87 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
88 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
89 #define C4IW_MAX_PAGE_SIZE 0x8000000
90
91 struct c4iw_id_table {
92 u32 flags;
93 u32 start; /* logical minimal id */
94 u32 last; /* hint for find */
95 u32 max;
96 spinlock_t lock;
97 unsigned long *table;
98 };
99
100 struct c4iw_resource {
101 struct c4iw_id_table qid_table;
102 struct c4iw_id_table pdid_table;
103 };
104
105 struct c4iw_qid_list {
106 struct list_head entry;
107 u32 qid;
108 };
109
110 struct c4iw_dev_ucontext {
111 struct list_head qpids;
112 struct list_head cqids;
113 struct mutex lock;
114 };
115
116 enum c4iw_rdev_flags {
117 T4_IW_STOPPED = (1<<0),
118 T4_STATUS_PAGE_DISABLED = (1<<1),
119 };
120
121 struct c4iw_stat {
122 u64 total;
123 u64 cur;
124 u64 max;
125 u64 fail;
126 };
127
128 struct c4iw_stats {
129 struct mutex lock;
130 struct c4iw_stat qid;
131 struct c4iw_stat pd;
132 struct c4iw_stat stag;
133 struct c4iw_stat pbl;
134 struct c4iw_stat rqt;
135 };
136
137 struct c4iw_hw_queue {
138 int t4_eq_status_entries;
139 int t4_max_eq_size;
140 int t4_max_iq_size;
141 int t4_max_rq_size;
142 int t4_max_sq_size;
143 int t4_max_qp_depth;
144 int t4_max_cq_depth;
145 int t4_stat_len;
146 };
147
148 struct c4iw_rdev {
149 struct adapter *adap;
150 struct c4iw_resource resource;
151 unsigned long qpshift;
152 u32 qpmask;
153 unsigned long cqshift;
154 u32 cqmask;
155 struct c4iw_dev_ucontext uctx;
156 vmem_t *rqt_arena;
157 vmem_t *pbl_arena;
158 u32 flags;
159 struct c4iw_stats stats;
160 struct c4iw_hw_queue hw_queue;
161 struct t4_dev_status_page *status_page;
162 unsigned long bar2_pa;
163 void __iomem *bar2_kva;
164 unsigned int bar2_len;
165 struct workqueue_struct *free_workq;
166 };
167
c4iw_stopped(struct c4iw_rdev * rdev)168 static inline int c4iw_stopped(struct c4iw_rdev *rdev)
169 {
170 return rdev->flags & T4_IW_STOPPED;
171 }
172
c4iw_num_stags(struct c4iw_rdev * rdev)173 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
174 {
175 return (int)(rdev->adap->vres.stag.size >> 5);
176 }
177
t4_max_fr_depth(struct c4iw_rdev * rdev,bool use_dsgl)178 static inline int t4_max_fr_depth(struct c4iw_rdev *rdev, bool use_dsgl)
179 {
180 if (rdev->adap->params.ulptx_memwrite_dsgl && use_dsgl)
181 return rdev->adap->params.dev_512sgl_mr ? T4_MAX_FR_FW_DSGL_DEPTH : T4_MAX_FR_DSGL_DEPTH;
182 else
183 return T4_MAX_FR_IMMD_DEPTH;
184 }
185
186 #define C4IW_WR_TO (60*HZ)
187
188 struct c4iw_wr_wait {
189 int ret;
190 struct completion completion;
191 struct kref kref;
192 };
193
194 void _c4iw_free_wr_wait(struct kref *kref);
195
c4iw_put_wr_wait(struct c4iw_wr_wait * wr_waitp)196 static inline void c4iw_put_wr_wait(struct c4iw_wr_wait *wr_waitp)
197 {
198 CTR(KTR_IW_CXGBE, "wr_wait %p ref before put %u", wr_waitp,
199 kref_read(&wr_waitp->kref));
200 WARN_ON(kref_read(&wr_waitp->kref) == 0);
201 kref_put(&wr_waitp->kref, _c4iw_free_wr_wait);
202 }
203
c4iw_get_wr_wait(struct c4iw_wr_wait * wr_waitp)204 static inline void c4iw_get_wr_wait(struct c4iw_wr_wait *wr_waitp)
205 {
206 CTR(KTR_IW_CXGBE, "wr_wait %p ref before get %u", wr_waitp,
207 kref_read(&wr_waitp->kref));
208 WARN_ON(kref_read(&wr_waitp->kref) == 0);
209 kref_get(&wr_waitp->kref);
210 }
211
c4iw_init_wr_wait(struct c4iw_wr_wait * wr_waitp)212 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
213 {
214 wr_waitp->ret = 0;
215 init_completion(&wr_waitp->completion);
216 }
217
_c4iw_wake_up(struct c4iw_wr_wait * wr_waitp,int ret,bool deref)218 static inline void _c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret,
219 bool deref)
220 {
221 wr_waitp->ret = ret;
222 complete(&wr_waitp->completion);
223 if (deref)
224 c4iw_put_wr_wait(wr_waitp);
225 }
226
c4iw_wake_up_noref(struct c4iw_wr_wait * wr_waitp,int ret)227 static inline void c4iw_wake_up_noref(struct c4iw_wr_wait *wr_waitp, int ret)
228 {
229 _c4iw_wake_up(wr_waitp, ret, false);
230 }
231
c4iw_wake_up_deref(struct c4iw_wr_wait * wr_waitp,int ret)232 static inline void c4iw_wake_up_deref(struct c4iw_wr_wait *wr_waitp, int ret)
233 {
234 _c4iw_wake_up(wr_waitp, ret, true);
235 }
236
237 static inline int
c4iw_wait_for_reply(struct c4iw_rdev * rdev,struct c4iw_wr_wait * wr_waitp,u32 hwtid,u32 qpid,struct socket * so,const char * func)238 c4iw_wait_for_reply(struct c4iw_rdev *rdev, struct c4iw_wr_wait *wr_waitp,
239 u32 hwtid, u32 qpid, struct socket *so, const char *func)
240 {
241 struct adapter *sc = rdev->adap;
242 int ret;
243
244 if (c4iw_stopped(rdev)) {
245 wr_waitp->ret = -EIO;
246 goto out;
247 }
248
249 /* If waiting for reply in rdma_init()/rdma_fini() threads, then
250 * check if there are any connection errors.
251 */
252 if (so && so->so_error) {
253 wr_waitp->ret = -ECONNRESET;
254 CTR5(KTR_IW_CXGBE, "%s - Connection ERROR %u for sock %p"
255 "tid %u qpid %u", func,
256 so->so_error, so, hwtid, qpid);
257 goto out;
258 }
259
260 ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO);
261 if (!ret) {
262 printf("%s - Device %s not responding (disabling device) - "
263 "tid %u qpid %u\n", func, device_get_nameunit(sc->dev),
264 hwtid, qpid);
265 rdev->flags |= T4_IW_STOPPED;
266 wr_waitp->ret = -EIO;
267 goto out;
268 }
269
270 if (wr_waitp->ret)
271 CTR4(KTR_IW_CXGBE, "%p: FW reply %d tid %u qpid %u", sc,
272 wr_waitp->ret, hwtid, qpid);
273 out:
274 return (wr_waitp->ret);
275 }
276
c4iw_ref_send_wait(struct c4iw_rdev * rdev,struct wrqe * wr,struct c4iw_wr_wait * wr_waitp,u32 hwtid,u32 qpid,struct socket * so,const char * func)277 static inline int c4iw_ref_send_wait(struct c4iw_rdev *rdev, struct wrqe *wr,
278 struct c4iw_wr_wait *wr_waitp,
279 u32 hwtid, u32 qpid, struct socket *so,
280 const char *func)
281 {
282 struct adapter *sc = rdev->adap;
283
284 CTR(KTR_IW_CXGBE, "%s wr_wait %p hwtid %u qpid %u", func, wr_waitp,
285 hwtid, qpid);
286 c4iw_get_wr_wait(wr_waitp);
287
288 t4_wrq_tx(sc, wr);
289
290 return c4iw_wait_for_reply(rdev, wr_waitp, hwtid, qpid, so, func);
291 }
292
293 struct c4iw_dev {
294 struct ib_device ibdev;
295 struct pci_dev pdev;
296 struct c4iw_rdev rdev;
297 u32 device_cap_flags;
298 struct xarray cqs;
299 struct xarray qps;
300 struct xarray mrs;
301 spinlock_t lock;
302 struct dentry *debugfs_root;
303 u32 avail_ird;
304 };
305
to_c4iw_dev(struct ib_device * ibdev)306 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
307 {
308 return container_of(ibdev, struct c4iw_dev, ibdev);
309 }
310
rdev_to_c4iw_dev(struct c4iw_rdev * rdev)311 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
312 {
313 return container_of(rdev, struct c4iw_dev, rdev);
314 }
315
get_chp(struct c4iw_dev * rhp,u32 cqid)316 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
317 {
318 return xa_load(&rhp->cqs, cqid);
319 }
320
get_qhp(struct c4iw_dev * rhp,u32 qpid)321 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
322 {
323 return xa_load(&rhp->qps, qpid);
324 }
325
326 extern int c4iw_max_read_depth;
327
cur_max_read_depth(struct c4iw_dev * dev)328 static inline int cur_max_read_depth(struct c4iw_dev *dev)
329 {
330 return min(dev->rdev.adap->params.max_ordird_qp, c4iw_max_read_depth);
331 }
332
333 struct c4iw_pd {
334 struct ib_pd ibpd;
335 u32 pdid;
336 struct c4iw_dev *rhp;
337 };
338
to_c4iw_pd(struct ib_pd * ibpd)339 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
340 {
341 return container_of(ibpd, struct c4iw_pd, ibpd);
342 }
343
344 struct tpt_attributes {
345 u64 len;
346 u64 va_fbo;
347 enum fw_ri_mem_perms perms;
348 u32 stag;
349 u32 pdid;
350 u32 qpid;
351 u32 pbl_addr;
352 u32 pbl_size;
353 u32 state:1;
354 u32 type:2;
355 u32 rsvd:1;
356 u32 remote_invaliate_disable:1;
357 u32 zbva:1;
358 u32 mw_bind_enable:1;
359 u32 page_size:5;
360 };
361
362 struct c4iw_mr {
363 struct ib_mr ibmr;
364 struct ib_umem *umem;
365 struct c4iw_dev *rhp;
366 u64 kva;
367 struct tpt_attributes attr;
368 u64 *mpl;
369 dma_addr_t mpl_addr;
370 u32 max_mpl_len;
371 u32 mpl_len;
372 struct c4iw_wr_wait *wr_waitp;
373 };
374
to_c4iw_mr(struct ib_mr * ibmr)375 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
376 {
377 return container_of(ibmr, struct c4iw_mr, ibmr);
378 }
379
380 struct c4iw_mw {
381 struct ib_mw ibmw;
382 struct c4iw_dev *rhp;
383 u64 kva;
384 struct tpt_attributes attr;
385 struct c4iw_wr_wait *wr_waitp;
386 };
387
to_c4iw_mw(struct ib_mw * ibmw)388 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
389 {
390 return container_of(ibmw, struct c4iw_mw, ibmw);
391 }
392
393 struct c4iw_cq {
394 struct ib_cq ibcq;
395 struct c4iw_dev *rhp;
396 struct t4_cq cq;
397 spinlock_t lock;
398 spinlock_t comp_handler_lock;
399 atomic_t refcnt;
400 wait_queue_head_t wait;
401 struct c4iw_wr_wait *wr_waitp;
402 };
403
to_c4iw_cq(struct ib_cq * ibcq)404 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
405 {
406 return container_of(ibcq, struct c4iw_cq, ibcq);
407 }
408
409 struct c4iw_mpa_attributes {
410 u8 initiator;
411 u8 recv_marker_enabled;
412 u8 xmit_marker_enabled;
413 u8 crc_enabled;
414 u8 enhanced_rdma_conn;
415 u8 version;
416 u8 p2p_type;
417 };
418
419 struct c4iw_qp_attributes {
420 u32 scq;
421 u32 rcq;
422 u32 sq_num_entries;
423 u32 rq_num_entries;
424 u32 sq_max_sges;
425 u32 sq_max_sges_rdma_write;
426 u32 rq_max_sges;
427 u32 state;
428 u8 enable_rdma_read;
429 u8 enable_rdma_write;
430 u8 enable_bind;
431 u8 enable_mmid0_fastreg;
432 u32 max_ord;
433 u32 max_ird;
434 u32 pd;
435 u32 next_state;
436 char terminate_buffer[52];
437 u32 terminate_msg_len;
438 u8 is_terminate_local;
439 struct c4iw_mpa_attributes mpa_attr;
440 struct c4iw_ep *llp_stream_handle;
441 u8 layer_etype;
442 u8 ecode;
443 u16 sq_db_inc;
444 u16 rq_db_inc;
445 u8 send_term;
446 };
447
448 struct c4iw_ib_srq {
449 struct ib_srq ibsrq;
450 };
451
452 struct c4iw_ib_ah {
453 struct ib_ah ibah;
454 };
455
456 struct c4iw_qp {
457 struct ib_qp ibqp;
458 struct c4iw_dev *rhp;
459 struct c4iw_ep *ep;
460 struct c4iw_qp_attributes attr;
461 struct t4_wq wq;
462 spinlock_t lock;
463 struct mutex mutex;
464 wait_queue_head_t wait;
465 int sq_sig_all;
466 struct c4iw_ucontext *ucontext;
467 struct c4iw_wr_wait *wr_waitp;
468 struct completion qp_rel_comp;
469 refcount_t qp_refcnt;
470 };
471
to_c4iw_qp(struct ib_qp * ibqp)472 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
473 {
474 return container_of(ibqp, struct c4iw_qp, ibqp);
475 }
476
477 struct c4iw_ucontext {
478 struct ib_ucontext ibucontext;
479 struct c4iw_dev_ucontext uctx;
480 u32 key;
481 spinlock_t mmap_lock;
482 struct list_head mmaps;
483 };
484
to_c4iw_ucontext(struct ib_ucontext * c)485 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
486 {
487 return container_of(c, struct c4iw_ucontext, ibucontext);
488 }
489
490 struct c4iw_mm_entry {
491 struct list_head entry;
492 u64 addr;
493 u32 key;
494 unsigned len;
495 };
496
remove_mmap(struct c4iw_ucontext * ucontext,u32 key,unsigned len)497 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
498 u32 key, unsigned len)
499 {
500 struct list_head *pos, *nxt;
501 struct c4iw_mm_entry *mm;
502
503 spin_lock(&ucontext->mmap_lock);
504 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
505
506 mm = list_entry(pos, struct c4iw_mm_entry, entry);
507 if (mm->key == key && mm->len == len) {
508 list_del_init(&mm->entry);
509 spin_unlock(&ucontext->mmap_lock);
510 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d",
511 __func__, key, (unsigned long long) mm->addr,
512 mm->len);
513 return mm;
514 }
515 }
516 spin_unlock(&ucontext->mmap_lock);
517 return NULL;
518 }
519
insert_mmap(struct c4iw_ucontext * ucontext,struct c4iw_mm_entry * mm)520 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
521 struct c4iw_mm_entry *mm)
522 {
523 spin_lock(&ucontext->mmap_lock);
524 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", __func__, mm->key,
525 (unsigned long long) mm->addr, mm->len);
526 list_add_tail(&mm->entry, &ucontext->mmaps);
527 spin_unlock(&ucontext->mmap_lock);
528 }
529
530 enum c4iw_qp_attr_mask {
531 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
532 C4IW_QP_ATTR_SQ_DB = 1<<1,
533 C4IW_QP_ATTR_RQ_DB = 1<<2,
534 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
535 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
536 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
537 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
538 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
539 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
540 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
541 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
542 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
543 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
544 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
545 C4IW_QP_ATTR_MAX_ORD |
546 C4IW_QP_ATTR_MAX_IRD |
547 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
548 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
549 C4IW_QP_ATTR_MPA_ATTR |
550 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
551 };
552
553 int c4iw_modify_qp(struct c4iw_dev *rhp,
554 struct c4iw_qp *qhp,
555 enum c4iw_qp_attr_mask mask,
556 struct c4iw_qp_attributes *attrs,
557 int internal);
558
559 enum c4iw_qp_state {
560 C4IW_QP_STATE_IDLE,
561 C4IW_QP_STATE_RTS,
562 C4IW_QP_STATE_ERROR,
563 C4IW_QP_STATE_TERMINATE,
564 C4IW_QP_STATE_CLOSING,
565 C4IW_QP_STATE_TOT
566 };
567
568 /*
569 * IW_CXGBE event bits.
570 * These bits are used for handling all events for a particular 'ep' serially.
571 */
572 #define C4IW_EVENT_SOCKET 0x0001
573 #define C4IW_EVENT_TIMEOUT 0x0002
574 #define C4IW_EVENT_TERM 0x0004
575
c4iw_convert_state(enum ib_qp_state ib_state)576 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
577 {
578 switch (ib_state) {
579 case IB_QPS_RESET:
580 case IB_QPS_INIT:
581 return C4IW_QP_STATE_IDLE;
582 case IB_QPS_RTS:
583 return C4IW_QP_STATE_RTS;
584 case IB_QPS_SQD:
585 return C4IW_QP_STATE_CLOSING;
586 case IB_QPS_SQE:
587 return C4IW_QP_STATE_TERMINATE;
588 case IB_QPS_ERR:
589 return C4IW_QP_STATE_ERROR;
590 default:
591 return -1;
592 }
593 }
594
to_ib_qp_state(int c4iw_qp_state)595 static inline int to_ib_qp_state(int c4iw_qp_state)
596 {
597 switch (c4iw_qp_state) {
598 case C4IW_QP_STATE_IDLE:
599 return IB_QPS_INIT;
600 case C4IW_QP_STATE_RTS:
601 return IB_QPS_RTS;
602 case C4IW_QP_STATE_CLOSING:
603 return IB_QPS_SQD;
604 case C4IW_QP_STATE_TERMINATE:
605 return IB_QPS_SQE;
606 case C4IW_QP_STATE_ERROR:
607 return IB_QPS_ERR;
608 }
609 return IB_QPS_ERR;
610 }
611
c4iw_ib_to_tpt_access(int a)612 static inline u32 c4iw_ib_to_tpt_access(int a)
613 {
614 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
615 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
616 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
617 FW_RI_MEM_ACCESS_LOCAL_READ;
618 }
619
c4iw_ib_to_tpt_bind_access(int acc)620 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
621 {
622 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
623 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
624 }
625
626 enum c4iw_mmid_state {
627 C4IW_STAG_STATE_VALID,
628 C4IW_STAG_STATE_INVALID
629 };
630
631 #define C4IW_NODE_DESC "iw_cxgbe Chelsio Communications"
632
633 #define MPA_KEY_REQ "MPA ID Req Frame"
634 #define MPA_KEY_REP "MPA ID Rep Frame"
635
636 #define MPA_MAX_PRIVATE_DATA 256
637 #define MPA_ENHANCED_RDMA_CONN 0x10
638 #define MPA_REJECT 0x20
639 #define MPA_CRC 0x40
640 #define MPA_MARKERS 0x80
641 #define MPA_FLAGS_MASK 0xE0
642
643 #define MPA_V2_PEER2PEER_MODEL 0x8000
644 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
645 #define MPA_V2_RDMA_WRITE_RTR 0x8000
646 #define MPA_V2_RDMA_READ_RTR 0x4000
647 #define MPA_V2_IRD_ORD_MASK 0x3FFF
648
649 #define c4iw_put_ep(ep) { \
650 CTR4(KTR_IW_CXGBE, "put_ep (%s:%u) ep %p, refcnt %d", \
651 __func__, __LINE__, ep, kref_read(&(ep)->kref)); \
652 WARN_ON(kref_read(&(ep)->kref) < 1); \
653 kref_put(&((ep)->kref), _c4iw_free_ep); \
654 }
655
656 #define c4iw_get_ep(ep) { \
657 CTR4(KTR_IW_CXGBE, "get_ep (%s:%u) ep %p, refcnt %d", \
658 __func__, __LINE__, ep, kref_read(&(ep)->kref)); \
659 kref_get(&((ep)->kref)); \
660 }
661
662 void _c4iw_free_ep(struct kref *kref);
663
664 struct mpa_message {
665 u8 key[16];
666 u8 flags;
667 u8 revision;
668 __be16 private_data_size;
669 u8 private_data[0];
670 };
671
672 struct mpa_v2_conn_params {
673 __be16 ird;
674 __be16 ord;
675 };
676
677 struct terminate_message {
678 u8 layer_etype;
679 u8 ecode;
680 __be16 hdrct_rsvd;
681 u8 len_hdrs[0];
682 };
683
684 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
685
686 enum c4iw_layers_types {
687 LAYER_RDMAP = 0x00,
688 LAYER_DDP = 0x10,
689 LAYER_MPA = 0x20,
690 RDMAP_LOCAL_CATA = 0x00,
691 RDMAP_REMOTE_PROT = 0x01,
692 RDMAP_REMOTE_OP = 0x02,
693 DDP_LOCAL_CATA = 0x00,
694 DDP_TAGGED_ERR = 0x01,
695 DDP_UNTAGGED_ERR = 0x02,
696 DDP_LLP = 0x03
697 };
698
699 enum c4iw_rdma_ecodes {
700 RDMAP_INV_STAG = 0x00,
701 RDMAP_BASE_BOUNDS = 0x01,
702 RDMAP_ACC_VIOL = 0x02,
703 RDMAP_STAG_NOT_ASSOC = 0x03,
704 RDMAP_TO_WRAP = 0x04,
705 RDMAP_INV_VERS = 0x05,
706 RDMAP_INV_OPCODE = 0x06,
707 RDMAP_STREAM_CATA = 0x07,
708 RDMAP_GLOBAL_CATA = 0x08,
709 RDMAP_CANT_INV_STAG = 0x09,
710 RDMAP_UNSPECIFIED = 0xff
711 };
712
713 enum c4iw_ddp_ecodes {
714 DDPT_INV_STAG = 0x00,
715 DDPT_BASE_BOUNDS = 0x01,
716 DDPT_STAG_NOT_ASSOC = 0x02,
717 DDPT_TO_WRAP = 0x03,
718 DDPT_INV_VERS = 0x04,
719 DDPU_INV_QN = 0x01,
720 DDPU_INV_MSN_NOBUF = 0x02,
721 DDPU_INV_MSN_RANGE = 0x03,
722 DDPU_INV_MO = 0x04,
723 DDPU_MSG_TOOBIG = 0x05,
724 DDPU_INV_VERS = 0x06
725 };
726
727 enum c4iw_mpa_ecodes {
728 MPA_CRC_ERR = 0x02,
729 MPA_MARKER_ERR = 0x03,
730 MPA_LOCAL_CATA = 0x05,
731 MPA_INSUFF_IRD = 0x06,
732 MPA_NOMATCH_RTR = 0x07,
733 };
734
735 enum c4iw_ep_state {
736 IDLE = 0,
737 LISTEN,
738 CONNECTING,
739 MPA_REQ_WAIT,
740 MPA_REQ_SENT,
741 MPA_REQ_RCVD,
742 MPA_REP_SENT,
743 FPDU_MODE,
744 ABORTING,
745 CLOSING,
746 MORIBUND,
747 DEAD,
748 };
749
750 enum c4iw_ep_flags {
751 PEER_ABORT_IN_PROGRESS = 0,
752 ABORT_REQ_IN_PROGRESS = 1,
753 RELEASE_RESOURCES = 2,
754 CLOSE_SENT = 3,
755 TIMEOUT = 4,
756 QP_REFERENCED = 5,
757 STOP_MPA_TIMER = 7,
758 };
759
760 enum c4iw_ep_history {
761 ACT_OPEN_REQ = 0,
762 ACT_OFLD_CONN = 1,
763 ACT_OPEN_RPL = 2,
764 ACT_ESTAB = 3,
765 PASS_ACCEPT_REQ = 4,
766 PASS_ESTAB = 5,
767 ABORT_UPCALL = 6,
768 ESTAB_UPCALL = 7,
769 CLOSE_UPCALL = 8,
770 ULP_ACCEPT = 9,
771 ULP_REJECT = 10,
772 TIMEDOUT = 11,
773 PEER_ABORT = 12,
774 PEER_CLOSE = 13,
775 CONNREQ_UPCALL = 14,
776 ABORT_CONN = 15,
777 DISCONN_UPCALL = 16,
778 EP_DISC_CLOSE = 17,
779 EP_DISC_ABORT = 18,
780 CONN_RPL_UPCALL = 19,
781 ACT_RETRY_NOMEM = 20,
782 ACT_RETRY_INUSE = 21,
783 CLOSE_CON_RPL = 22,
784 EP_DISC_FAIL = 24,
785 QP_REFED = 25,
786 QP_DEREFED = 26,
787 CM_ID_REFED = 27,
788 CM_ID_DEREFED = 28
789 };
790
791 struct c4iw_ep_common {
792 TAILQ_ENTRY(c4iw_ep_common) entry; /* Work queue attachment */
793 struct iw_cm_id *cm_id;
794 struct c4iw_qp *qp;
795 struct c4iw_dev *dev;
796 enum c4iw_ep_state state;
797 struct kref kref;
798 struct mutex mutex;
799 struct sockaddr_storage local_addr;
800 struct sockaddr_storage remote_addr;
801 struct c4iw_wr_wait *wr_waitp;
802 unsigned long flags;
803 unsigned long history;
804 int rpl_err;
805 int rpl_done;
806 struct thread *thread;
807 struct socket *so;
808 int ep_events;
809 };
810
811 struct c4iw_listen_ep {
812 struct c4iw_ep_common com;
813 unsigned int stid;
814 int backlog;
815 struct list_head listen_ep_list; /* list of all listener ep's bound
816 to one port address */
817 };
818
819 struct c4iw_ep {
820 struct c4iw_ep_common com;
821 struct c4iw_listen_ep *parent_ep;
822 struct timer_list timer;
823 unsigned int atid;
824 u32 hwtid;
825 u32 snd_seq;
826 u32 rcv_seq;
827 struct l2t_entry *l2t;
828 struct dst_entry *dst;
829 struct c4iw_mpa_attributes mpa_attr;
830 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
831 unsigned int mpa_pkt_len;
832 u32 ird;
833 u32 ord;
834 u32 tx_chan;
835 u32 mtu;
836 u16 mss;
837 u16 plen;
838 u16 rss_qid;
839 u16 txq_idx;
840 u16 ctrlq_idx;
841 u8 tos;
842 u8 retry_with_mpa_v1;
843 u8 tried_with_mpa_v1;
844 };
845
to_ep(struct iw_cm_id * cm_id)846 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
847 {
848 return cm_id->provider_data;
849 }
850
to_listen_ep(struct iw_cm_id * cm_id)851 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
852 {
853 return cm_id->provider_data;
854 }
855
compute_wscale(int win)856 static inline int compute_wscale(int win)
857 {
858 int wscale = 0;
859
860 while (wscale < 14 && (65535<<wscale) < win)
861 wscale++;
862 return wscale;
863 }
864
865 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
866 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
867 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
868 u32 reserved, u32 flags);
869 void c4iw_id_table_free(struct c4iw_id_table *alloc);
870
871 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct mbuf *m);
872
873 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
874 struct l2t_entry *l2t);
875 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
876 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
877 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_pdid);
878 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
879 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
880 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
881 void c4iw_destroy_resource(struct c4iw_resource *rscp);
882 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
883 int c4iw_register_device(struct c4iw_dev *dev);
884 void c4iw_unregister_device(struct c4iw_dev *dev);
885 int __init c4iw_cm_init(void);
886 void __exit c4iw_cm_term(void);
887 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
888 struct c4iw_dev_ucontext *uctx);
889 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
890 struct c4iw_dev_ucontext *uctx);
891 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
892 int c4iw_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
893 const struct ib_send_wr **bad_wr);
894 int c4iw_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
895 const struct ib_recv_wr **bad_wr);
896 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
897 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
898 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
899 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
900 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
901 void c4iw_qp_add_ref(struct ib_qp *qp);
902 void c4iw_qp_rem_ref(struct ib_qp *qp);
903 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
904 u32 max_num_sg, struct ib_udata *udata);
905 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
906 int sg_nents, unsigned int *sg_offset);
907 int c4iw_dealloc_mw(struct ib_mw *mw);
908 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
909 struct ib_udata *udata);
910 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, u64
911 virt, int acc, struct ib_udata *udata);
912 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
913 int c4iw_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata);
914 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey);
915 void c4iw_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
916 int c4iw_create_cq(struct ib_cq *ibcq,
917 const struct ib_cq_init_attr *attr,
918 struct ib_udata *udata);
919 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
920 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
921 int c4iw_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata);
922 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
923 struct ib_qp_init_attr *attrs,
924 struct ib_udata *udata);
925 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
926 int attr_mask, struct ib_udata *udata);
927 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
928 int attr_mask, struct ib_qp_init_attr *init_attr);
929 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
930 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
931 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
932 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
933 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
934 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct mbuf *m);
935 void c4iw_flush_hw_cq(struct c4iw_cq *cq, struct c4iw_qp *flush_qhp);
936 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
937 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
938 int __c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
939 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
940 int c4iw_flush_sq(struct c4iw_qp *qhp);
941 int c4iw_ev_handler(struct sge_iq *, const struct rsp_ctrl *);
942 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
943 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
944 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
945 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
946 struct c4iw_dev_ucontext *uctx);
947 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
948 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
949 struct c4iw_dev_ucontext *uctx);
950 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
951 struct c4iw_wr_wait *c4iw_alloc_wr_wait(gfp_t gfp);
952 void t4_dump_stag(struct adapter *sc, const u32 stag);
953 void t4_dump_all_stag(struct adapter *sc);
954 #endif
955