xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (revision 700637cbb5e582861067a11aaca4d053546871d2) 
1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the X86MCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/X86BaseInfo.h"
14 #include "MCTargetDesc/X86FixupKinds.h"
15 #include "MCTargetDesc/X86MCAsmInfo.h"
16 #include "MCTargetDesc/X86MCTargetDesc.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/BinaryFormat/ELF.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCFixup.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrDesc.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCSymbol.h"
29 #include "llvm/Support/Casting.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include <cassert>
32 #include <cstdint>
33 #include <cstdlib>
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "mccodeemitter"
38 
39 namespace {
40 
41 enum PrefixKind { None, REX, REX2, XOP, VEX2, VEX3, EVEX };
42 
emitByte(uint8_t C,SmallVectorImpl<char> & CB)43 static void emitByte(uint8_t C, SmallVectorImpl<char> &CB) { CB.push_back(C); }
44 
45 class X86OpcodePrefixHelper {
46   // REX (1 byte)
47   // +-----+ +------+
48   // | 40H | | WRXB |
49   // +-----+ +------+
50 
51   // REX2 (2 bytes)
52   // +-----+ +-------------------+
53   // | D5H | | M | R'X'B' | WRXB |
54   // +-----+ +-------------------+
55 
56   // XOP (3-byte)
57   // +-----+ +--------------+ +-------------------+
58   // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
59   // +-----+ +--------------+ +-------------------+
60 
61   // VEX2 (2 bytes)
62   // +-----+ +-------------------+
63   // | C5h | | R | vvvv | L | pp |
64   // +-----+ +-------------------+
65 
66   // VEX3 (3 bytes)
67   // +-----+ +--------------+ +-------------------+
68   // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
69   // +-----+ +--------------+ +-------------------+
70 
71   // VEX_R: opcode externsion equivalent to REX.R in
72   // 1's complement (inverted) form
73   //
74   //  1: Same as REX_R=0 (must be 1 in 32-bit mode)
75   //  0: Same as REX_R=1 (64 bit mode only)
76 
77   // VEX_X: equivalent to REX.X, only used when a
78   // register is used for index in SIB Byte.
79   //
80   //  1: Same as REX.X=0 (must be 1 in 32-bit mode)
81   //  0: Same as REX.X=1 (64-bit mode only)
82 
83   // VEX_B:
84   //  1: Same as REX_B=0 (ignored in 32-bit mode)
85   //  0: Same as REX_B=1 (64 bit mode only)
86 
87   // VEX_W: opcode specific (use like REX.W, or used for
88   // opcode extension, or ignored, depending on the opcode byte)
89 
90   // VEX_5M (VEX m-mmmmm field):
91   //
92   //  0b00000: Reserved for future use
93   //  0b00001: implied 0F leading opcode
94   //  0b00010: implied 0F 38 leading opcode bytes
95   //  0b00011: implied 0F 3A leading opcode bytes
96   //  0b00100: Reserved for future use
97   //  0b00101: VEX MAP5
98   //  0b00110: VEX MAP6
99   //  0b00111: VEX MAP7
100   //  0b00111-0b11111: Reserved for future use
101   //  0b01000: XOP map select - 08h instructions with imm byte
102   //  0b01001: XOP map select - 09h instructions with no imm byte
103   //  0b01010: XOP map select - 0Ah instructions with imm dword
104 
105   // VEX_4V (VEX vvvv field): a register specifier
106   // (in 1's complement form) or 1111 if unused.
107 
108   // VEX_PP: opcode extension providing equivalent
109   // functionality of a SIMD prefix
110   //  0b00: None
111   //  0b01: 66
112   //  0b10: F3
113   //  0b11: F2
114 
115   // EVEX (4 bytes)
116   // +-----+ +---------------+ +-------------------+ +------------------------+
117   // | 62h | | RXBR' | B'mmm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
118   // +-----+ +---------------+ +-------------------+ +------------------------+
119 
120   // EVEX_L2/VEX_L (Vector Length):
121   // L2 L
122   //  0 0: scalar or 128-bit vector
123   //  0 1: 256-bit vector
124   //  1 0: 512-bit vector
125 
126   // 32-Register Support in 64-bit Mode Using EVEX with Embedded REX/REX2 Bits:
127   //
128   // +----------+---------+--------+-----------+---------+--------------+
129   // |          |    4    |    3   |   [2:0]   | Type    | Common Usage |
130   // +----------+---------+--------+-----------+---------+--------------+
131   // | REG      | EVEX_R' | EVEX_R | modrm.reg | GPR, VR | Dest or Src  |
132   // | VVVV     | EVEX_v' |       EVEX.vvvv    | GPR, VR | Dest or Src  |
133   // | RM (VR)  | EVEX_X  | EVEX_B | modrm.r/m | VR      | Dest or Src  |
134   // | RM (GPR) | EVEX_B' | EVEX_B | modrm.r/m | GPR     | Dest or Src  |
135   // | BASE     | EVEX_B' | EVEX_B | modrm.r/m | GPR     | MA           |
136   // | INDEX    | EVEX_U  | EVEX_X | sib.index | GPR     | MA           |
137   // | VIDX     | EVEX_v' | EVEX_X | sib.index | VR      | VSIB MA      |
138   // +----------+---------+--------+-----------+---------+--------------+
139   //
140   // * GPR  - General-purpose register
141   // * VR   - Vector register
142   // * VIDX - Vector index
143   // * VSIB - Vector SIB
144   // * MA   - Memory addressing
145 
146 private:
147   unsigned W : 1;
148   unsigned R : 1;
149   unsigned X : 1;
150   unsigned B : 1;
151   unsigned M : 1;
152   unsigned R2 : 1;
153   unsigned X2 : 1;
154   unsigned B2 : 1;
155   unsigned VEX_4V : 4;
156   unsigned VEX_L : 1;
157   unsigned VEX_PP : 2;
158   unsigned VEX_5M : 5;
159   unsigned EVEX_z : 1;
160   unsigned EVEX_L2 : 1;
161   unsigned EVEX_b : 1;
162   unsigned EVEX_V2 : 1;
163   unsigned EVEX_aaa : 3;
164   PrefixKind Kind = None;
165   const MCRegisterInfo &MRI;
166 
getRegEncoding(const MCInst & MI,unsigned OpNum) const167   unsigned getRegEncoding(const MCInst &MI, unsigned OpNum) const {
168     return MRI.getEncodingValue(MI.getOperand(OpNum).getReg());
169   }
170 
setR(unsigned Encoding)171   void setR(unsigned Encoding) { R = Encoding >> 3 & 1; }
setR2(unsigned Encoding)172   void setR2(unsigned Encoding) {
173     R2 = Encoding >> 4 & 1;
174     assert((!R2 || (Kind <= REX2 || Kind == EVEX)) && "invalid setting");
175   }
setX(unsigned Encoding)176   void setX(unsigned Encoding) { X = Encoding >> 3 & 1; }
setX2(unsigned Encoding)177   void setX2(unsigned Encoding) {
178     assert((Kind <= REX2 || Kind == EVEX) && "invalid setting");
179     X2 = Encoding >> 4 & 1;
180   }
setB(unsigned Encoding)181   void setB(unsigned Encoding) { B = Encoding >> 3 & 1; }
setB2(unsigned Encoding)182   void setB2(unsigned Encoding) {
183     assert((Kind <= REX2 || Kind == EVEX) && "invalid setting");
184     B2 = Encoding >> 4 & 1;
185   }
set4V(unsigned Encoding)186   void set4V(unsigned Encoding) { VEX_4V = Encoding & 0xf; }
setV2(unsigned Encoding)187   void setV2(unsigned Encoding) { EVEX_V2 = Encoding >> 4 & 1; }
188 
189 public:
setW(bool V)190   void setW(bool V) { W = V; }
setR(const MCInst & MI,unsigned OpNum)191   void setR(const MCInst &MI, unsigned OpNum) {
192     setR(getRegEncoding(MI, OpNum));
193   }
setX(const MCInst & MI,unsigned OpNum,unsigned Shift=3)194   void setX(const MCInst &MI, unsigned OpNum, unsigned Shift = 3) {
195     MCRegister Reg = MI.getOperand(OpNum).getReg();
196     // X is used to extend vector register only when shift is not 3.
197     if (Shift != 3 && X86II::isApxExtendedReg(Reg))
198       return;
199     unsigned Encoding = MRI.getEncodingValue(Reg);
200     X = Encoding >> Shift & 1;
201   }
setB(const MCInst & MI,unsigned OpNum)202   void setB(const MCInst &MI, unsigned OpNum) {
203     B = getRegEncoding(MI, OpNum) >> 3 & 1;
204   }
set4V(const MCInst & MI,unsigned OpNum,bool IsImm=false)205   void set4V(const MCInst &MI, unsigned OpNum, bool IsImm = false) {
206     // OF, SF, ZF and CF reuse VEX_4V bits but are not reversed
207     if (IsImm)
208       set4V(~(MI.getOperand(OpNum).getImm()));
209     else
210       set4V(getRegEncoding(MI, OpNum));
211   }
setL(bool V)212   void setL(bool V) { VEX_L = V; }
setPP(unsigned V)213   void setPP(unsigned V) { VEX_PP = V; }
set5M(unsigned V)214   void set5M(unsigned V) { VEX_5M = V; }
setR2(const MCInst & MI,unsigned OpNum)215   void setR2(const MCInst &MI, unsigned OpNum) {
216     setR2(getRegEncoding(MI, OpNum));
217   }
setRR2(const MCInst & MI,unsigned OpNum)218   void setRR2(const MCInst &MI, unsigned OpNum) {
219     unsigned Encoding = getRegEncoding(MI, OpNum);
220     setR(Encoding);
221     setR2(Encoding);
222   }
setM(bool V)223   void setM(bool V) { M = V; }
setXX2(const MCInst & MI,unsigned OpNum)224   void setXX2(const MCInst &MI, unsigned OpNum) {
225     MCRegister Reg = MI.getOperand(OpNum).getReg();
226     unsigned Encoding = MRI.getEncodingValue(Reg);
227     setX(Encoding);
228     // Index can be a vector register while X2 is used to extend GPR only.
229     if (Kind <= REX2 || X86II::isApxExtendedReg(Reg))
230       setX2(Encoding);
231   }
setBB2(const MCInst & MI,unsigned OpNum)232   void setBB2(const MCInst &MI, unsigned OpNum) {
233     MCRegister Reg = MI.getOperand(OpNum).getReg();
234     unsigned Encoding = MRI.getEncodingValue(Reg);
235     setB(Encoding);
236     // Base can be a vector register while B2 is used to extend GPR only
237     if (Kind <= REX2 || X86II::isApxExtendedReg(Reg))
238       setB2(Encoding);
239   }
setZ(bool V)240   void setZ(bool V) { EVEX_z = V; }
setL2(bool V)241   void setL2(bool V) { EVEX_L2 = V; }
setEVEX_b(bool V)242   void setEVEX_b(bool V) { EVEX_b = V; }
setEVEX_U(bool V)243   void setEVEX_U(bool V) { X2 = V; }
setV2(const MCInst & MI,unsigned OpNum,bool HasVEX_4V)244   void setV2(const MCInst &MI, unsigned OpNum, bool HasVEX_4V) {
245     // Only needed with VSIB which don't use VVVV.
246     if (HasVEX_4V)
247       return;
248     MCRegister Reg = MI.getOperand(OpNum).getReg();
249     if (X86II::isApxExtendedReg(Reg))
250       return;
251     setV2(MRI.getEncodingValue(Reg));
252   }
set4VV2(const MCInst & MI,unsigned OpNum)253   void set4VV2(const MCInst &MI, unsigned OpNum) {
254     unsigned Encoding = getRegEncoding(MI, OpNum);
255     set4V(Encoding);
256     setV2(Encoding);
257   }
setAAA(const MCInst & MI,unsigned OpNum)258   void setAAA(const MCInst &MI, unsigned OpNum) {
259     EVEX_aaa = getRegEncoding(MI, OpNum);
260   }
setNF(bool V)261   void setNF(bool V) { EVEX_aaa |= V << 2; }
setSC(const MCInst & MI,unsigned OpNum)262   void setSC(const MCInst &MI, unsigned OpNum) {
263     unsigned Encoding = MI.getOperand(OpNum).getImm();
264     EVEX_V2 = ~(Encoding >> 3) & 0x1;
265     EVEX_aaa = Encoding & 0x7;
266   }
267 
X86OpcodePrefixHelper(const MCRegisterInfo & MRI)268   X86OpcodePrefixHelper(const MCRegisterInfo &MRI)
269       : W(0), R(0), X(0), B(0), M(0), R2(0), X2(0), B2(0), VEX_4V(0), VEX_L(0),
270         VEX_PP(0), VEX_5M(0), EVEX_z(0), EVEX_L2(0), EVEX_b(0), EVEX_V2(0),
271         EVEX_aaa(0), MRI(MRI) {}
272 
setLowerBound(PrefixKind K)273   void setLowerBound(PrefixKind K) { Kind = K; }
274 
determineOptimalKind()275   PrefixKind determineOptimalKind() {
276     switch (Kind) {
277     case None:
278       // Not M bit here by intention b/c
279       // 1. No guarantee that REX2 is supported by arch w/o explict EGPR
280       // 2. REX2 is longer than 0FH
281       Kind = (R2 | X2 | B2) ? REX2 : (W | R | X | B) ? REX : None;
282       break;
283     case REX:
284       Kind = (R2 | X2 | B2) ? REX2 : REX;
285       break;
286     case REX2:
287     case XOP:
288     case VEX3:
289     case EVEX:
290       break;
291     case VEX2:
292       Kind = (W | X | B | (VEX_5M != 1)) ? VEX3 : VEX2;
293       break;
294     }
295     return Kind;
296   }
297 
emit(SmallVectorImpl<char> & CB) const298   void emit(SmallVectorImpl<char> &CB) const {
299     uint8_t FirstPayload =
300         ((~R) & 0x1) << 7 | ((~X) & 0x1) << 6 | ((~B) & 0x1) << 5;
301     uint8_t LastPayload = ((~VEX_4V) & 0xf) << 3 | VEX_L << 2 | VEX_PP;
302     switch (Kind) {
303     case None:
304       return;
305     case REX:
306       emitByte(0x40 | W << 3 | R << 2 | X << 1 | B, CB);
307       return;
308     case REX2:
309       emitByte(0xD5, CB);
310       emitByte(M << 7 | R2 << 6 | X2 << 5 | B2 << 4 | W << 3 | R << 2 | X << 1 |
311                    B,
312                CB);
313       return;
314     case VEX2:
315       emitByte(0xC5, CB);
316       emitByte(((~R) & 1) << 7 | LastPayload, CB);
317       return;
318     case VEX3:
319     case XOP:
320       emitByte(Kind == VEX3 ? 0xC4 : 0x8F, CB);
321       emitByte(FirstPayload | VEX_5M, CB);
322       emitByte(W << 7 | LastPayload, CB);
323       return;
324     case EVEX:
325       assert(VEX_5M && !(VEX_5M & 0x8) && "invalid mmm fields for EVEX!");
326       emitByte(0x62, CB);
327       emitByte(FirstPayload | ((~R2) & 0x1) << 4 | B2 << 3 | VEX_5M, CB);
328       emitByte(W << 7 | ((~VEX_4V) & 0xf) << 3 | ((~X2) & 0x1) << 2 | VEX_PP,
329                CB);
330       emitByte(EVEX_z << 7 | EVEX_L2 << 6 | VEX_L << 5 | EVEX_b << 4 |
331                    ((~EVEX_V2) & 0x1) << 3 | EVEX_aaa,
332                CB);
333       return;
334     }
335   }
336 };
337 
338 class X86MCCodeEmitter : public MCCodeEmitter {
339   const MCInstrInfo &MCII;
340   MCContext &Ctx;
341 
342 public:
X86MCCodeEmitter(const MCInstrInfo & mcii,MCContext & ctx)343   X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
344       : MCII(mcii), Ctx(ctx) {}
345   X86MCCodeEmitter(const X86MCCodeEmitter &) = delete;
346   X86MCCodeEmitter &operator=(const X86MCCodeEmitter &) = delete;
347   ~X86MCCodeEmitter() override = default;
348 
349   void emitPrefix(const MCInst &MI, SmallVectorImpl<char> &CB,
350                   const MCSubtargetInfo &STI) const;
351 
352   void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
353                          SmallVectorImpl<MCFixup> &Fixups,
354                          const MCSubtargetInfo &STI) const override;
355 
356 private:
357   unsigned getX86RegNum(const MCOperand &MO) const;
358 
359   unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const;
360 
361   void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned FixupKind,
362                      bool IsPCRel, uint64_t StartByte,
363                      SmallVectorImpl<char> &CB,
364                      SmallVectorImpl<MCFixup> &Fixups, int ImmOffset = 0) const;
365 
366   void emitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
367                         SmallVectorImpl<char> &CB) const;
368 
369   void emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
370                    SmallVectorImpl<char> &CB) const;
371 
372   void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
373                         uint64_t TSFlags, PrefixKind Kind, uint64_t StartByte,
374                         SmallVectorImpl<char> &CB,
375                         SmallVectorImpl<MCFixup> &Fixups,
376                         const MCSubtargetInfo &STI,
377                         bool ForceSIB = false) const;
378 
379   PrefixKind emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
380                             const MCSubtargetInfo &STI,
381                             SmallVectorImpl<char> &CB) const;
382 
383   PrefixKind emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
384                                  const MCSubtargetInfo &STI,
385                                  SmallVectorImpl<char> &CB) const;
386 
387   void emitSegmentOverridePrefix(unsigned SegOperand, const MCInst &MI,
388                                  SmallVectorImpl<char> &CB) const;
389 
390   PrefixKind emitOpcodePrefix(int MemOperand, const MCInst &MI,
391                               const MCSubtargetInfo &STI,
392                               SmallVectorImpl<char> &CB) const;
393 
394   PrefixKind emitREXPrefix(int MemOperand, const MCInst &MI,
395                            const MCSubtargetInfo &STI,
396                            SmallVectorImpl<char> &CB) const;
397 };
398 
399 } // end anonymous namespace
400 
modRMByte(unsigned Mod,unsigned RegOpcode,unsigned RM)401 static uint8_t modRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM) {
402   assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
403   return RM | (RegOpcode << 3) | (Mod << 6);
404 }
405 
emitConstant(uint64_t Val,unsigned Size,SmallVectorImpl<char> & CB)406 static void emitConstant(uint64_t Val, unsigned Size,
407                          SmallVectorImpl<char> &CB) {
408   // Output the constant in little endian byte order.
409   for (unsigned i = 0; i != Size; ++i) {
410     emitByte(Val & 255, CB);
411     Val >>= 8;
412   }
413 }
414 
415 /// Determine if this immediate can fit in a disp8 or a compressed disp8 for
416 /// EVEX instructions. \p will be set to the value to pass to the ImmOffset
417 /// parameter of emitImmediate.
isDispOrCDisp8(uint64_t TSFlags,int Value,int & ImmOffset)418 static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) {
419   bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
420 
421   unsigned CD8_Scale =
422       (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift;
423   CD8_Scale = CD8_Scale ? 1U << (CD8_Scale - 1) : 0U;
424   if (!HasEVEX || !CD8_Scale)
425     return isInt<8>(Value);
426 
427   assert(isPowerOf2_32(CD8_Scale) && "Unexpected CD8 scale!");
428   if (Value & (CD8_Scale - 1)) // Unaligned offset
429     return false;
430 
431   int CDisp8 = Value / static_cast<int>(CD8_Scale);
432   if (!isInt<8>(CDisp8))
433     return false;
434 
435   // ImmOffset will be added to Value in emitImmediate leaving just CDisp8.
436   ImmOffset = CDisp8 - Value;
437   return true;
438 }
439 
440 /// \returns the appropriate fixup kind to use for an immediate in an
441 /// instruction with the specified TSFlags.
getImmFixupKind(uint64_t TSFlags)442 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
443   unsigned Size = X86II::getSizeOfImm(TSFlags);
444   if (X86II::isImmSigned(TSFlags)) {
445     switch (Size) {
446     default:
447       llvm_unreachable("Unsupported signed fixup size!");
448     case 4:
449       return X86::reloc_signed_4byte;
450     }
451   }
452   switch (Size) {
453   default:
454     llvm_unreachable("Invalid generic fixup size!");
455   case 1:
456     return FK_Data_1;
457   case 2:
458     return FK_Data_2;
459   case 4:
460     return FK_Data_4;
461   case 8:
462     return FK_Data_8;
463   }
464 }
465 
466 enum GlobalOffsetTableExprKind { GOT_None, GOT_Normal, GOT_SymDiff };
467 
468 /// Check if this expression starts with  _GLOBAL_OFFSET_TABLE_ and if it is
469 /// of the form _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on
470 /// ELF i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
471 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start of a
472 /// binary expression.
473 ///
474 /// TODO: Move this to X86AsmBackend.cpp at relocation decision phase so that we
475 /// don't have to mess with MCExpr.
476 static GlobalOffsetTableExprKind
startsWithGlobalOffsetTable(const MCExpr * Expr)477 startsWithGlobalOffsetTable(const MCExpr *Expr) {
478   const MCExpr *RHS = nullptr;
479   if (Expr->getKind() == MCExpr::Binary) {
480     const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
481     Expr = BE->getLHS();
482     RHS = BE->getRHS();
483   }
484 
485   if (Expr->getKind() != MCExpr::SymbolRef)
486     return GOT_None;
487 
488   const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
489   const MCSymbol &S = Ref->getSymbol();
490   if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
491     return GOT_None;
492   if (RHS && RHS->getKind() == MCExpr::SymbolRef)
493     return GOT_SymDiff;
494   return GOT_Normal;
495 }
496 
hasSecRelSymbolRef(const MCExpr * Expr)497 static bool hasSecRelSymbolRef(const MCExpr *Expr) {
498   if (Expr->getKind() == MCExpr::SymbolRef) {
499     auto *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
500     return Ref->getSpecifier() == X86::S_COFF_SECREL;
501   }
502   return false;
503 }
504 
isPCRel32Branch(const MCInst & MI,const MCInstrInfo & MCII)505 static bool isPCRel32Branch(const MCInst &MI, const MCInstrInfo &MCII) {
506   unsigned Opcode = MI.getOpcode();
507   const MCInstrDesc &Desc = MCII.get(Opcode);
508   if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4 &&
509        Opcode != X86::JCC_4) ||
510       !(getImmFixupKind(Desc.TSFlags) == FK_Data_4 &&
511         X86II::isImmPCRel(Desc.TSFlags)))
512     return false;
513 
514   unsigned CurOp = X86II::getOperandBias(Desc);
515   const MCOperand &Op = MI.getOperand(CurOp);
516   if (!Op.isExpr())
517     return false;
518 
519   auto *Ref = dyn_cast<MCSymbolRefExpr>(Op.getExpr());
520   return Ref && Ref->getSpecifier() == X86::S_None;
521 }
522 
getX86RegNum(const MCOperand & MO) const523 unsigned X86MCCodeEmitter::getX86RegNum(const MCOperand &MO) const {
524   return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
525 }
526 
getX86RegEncoding(const MCInst & MI,unsigned OpNum) const527 unsigned X86MCCodeEmitter::getX86RegEncoding(const MCInst &MI,
528                                              unsigned OpNum) const {
529   return Ctx.getRegisterInfo()->getEncodingValue(MI.getOperand(OpNum).getReg());
530 }
531 
emitImmediate(const MCOperand & DispOp,SMLoc Loc,unsigned FixupKind,bool PCRel,uint64_t StartByte,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,int ImmOffset) const532 void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
533                                      unsigned FixupKind, bool PCRel,
534                                      uint64_t StartByte,
535                                      SmallVectorImpl<char> &CB,
536                                      SmallVectorImpl<MCFixup> &Fixups,
537                                      int ImmOffset) const {
538   unsigned Size = 4;
539   switch (FixupKind) {
540   case FK_Data_1:
541     Size = 1;
542     break;
543   case FK_Data_2:
544     Size = 2;
545     break;
546   case FK_Data_8:
547     Size = 8;
548     break;
549   }
550   const MCExpr *Expr = nullptr;
551   if (DispOp.isImm()) {
552     // If this is a simple integer displacement that doesn't require a
553     // relocation, emit it now.
554     if (!(is_contained({FK_Data_1, FK_Data_2, FK_Data_4}, FixupKind) &&
555           PCRel)) {
556       emitConstant(DispOp.getImm() + ImmOffset, Size, CB);
557       return;
558     }
559     Expr = MCConstantExpr::create(DispOp.getImm(), Ctx);
560   } else {
561     Expr = DispOp.getExpr();
562   }
563 
564   // If we have an immoffset, add it to the expression.
565   if ((FixupKind == FK_Data_4 || FixupKind == FK_Data_8 ||
566        FixupKind == X86::reloc_signed_4byte)) {
567     GlobalOffsetTableExprKind Kind = startsWithGlobalOffsetTable(Expr);
568     if (Kind != GOT_None) {
569       assert(ImmOffset == 0);
570 
571       if (Size == 8) {
572         FixupKind = FirstLiteralRelocationKind + ELF::R_X86_64_GOTPC64;
573       } else {
574         assert(Size == 4);
575         FixupKind = X86::reloc_global_offset_table;
576       }
577 
578       if (Kind == GOT_Normal)
579         ImmOffset = static_cast<int>(CB.size() - StartByte);
580     } else if (Expr->getKind() == MCExpr::SymbolRef) {
581       if (hasSecRelSymbolRef(Expr)) {
582         FixupKind = FK_SecRel_4;
583       }
584     } else if (Expr->getKind() == MCExpr::Binary) {
585       const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr *>(Expr);
586       if (hasSecRelSymbolRef(Bin->getLHS()) ||
587           hasSecRelSymbolRef(Bin->getRHS())) {
588         FixupKind = FK_SecRel_4;
589       }
590     }
591   }
592 
593   if (ImmOffset)
594     Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx),
595                                    Ctx, Expr->getLoc());
596 
597   // Emit a symbolic constant as a fixup and a few zero bytes.
598   Fixups.push_back(MCFixup::create(static_cast<uint32_t>(CB.size() - StartByte),
599                                    Expr, FixupKind, PCRel));
600   emitConstant(0, Size, CB);
601 }
602 
emitRegModRMByte(const MCOperand & ModRMReg,unsigned RegOpcodeFld,SmallVectorImpl<char> & CB) const603 void X86MCCodeEmitter::emitRegModRMByte(const MCOperand &ModRMReg,
604                                         unsigned RegOpcodeFld,
605                                         SmallVectorImpl<char> &CB) const {
606   emitByte(modRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)), CB);
607 }
608 
emitSIBByte(unsigned SS,unsigned Index,unsigned Base,SmallVectorImpl<char> & CB) const609 void X86MCCodeEmitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
610                                    SmallVectorImpl<char> &CB) const {
611   // SIB byte is in the same format as the modRMByte.
612   emitByte(modRMByte(SS, Index, Base), CB);
613 }
614 
emitMemModRMByte(const MCInst & MI,unsigned Op,unsigned RegOpcodeField,uint64_t TSFlags,PrefixKind Kind,uint64_t StartByte,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI,bool ForceSIB) const615 void X86MCCodeEmitter::emitMemModRMByte(
616     const MCInst &MI, unsigned Op, unsigned RegOpcodeField, uint64_t TSFlags,
617     PrefixKind Kind, uint64_t StartByte, SmallVectorImpl<char> &CB,
618     SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI,
619     bool ForceSIB) const {
620   const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp);
621   const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
622   const MCOperand &Scale = MI.getOperand(Op + X86::AddrScaleAmt);
623   const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg);
624   MCRegister BaseReg = Base.getReg();
625 
626   // Handle %rip relative addressing.
627   if (BaseReg == X86::RIP ||
628       BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
629     assert(STI.hasFeature(X86::Is64Bit) &&
630            "Rip-relative addressing requires 64-bit mode");
631     assert(!IndexReg.getReg() && !ForceSIB && "Invalid rip-relative address");
632     emitByte(modRMByte(0, RegOpcodeField, 5), CB);
633 
634     unsigned Opcode = MI.getOpcode();
635     unsigned FixupKind = [&]() {
636       // Enable relaxed relocation only for a MCSymbolRefExpr.  We cannot use a
637       // relaxed relocation if an offset is present (e.g. x@GOTPCREL+4).
638       if (!(Disp.isExpr() && isa<MCSymbolRefExpr>(Disp.getExpr())))
639         return X86::reloc_riprel_4byte;
640 
641       // Certain loads for GOT references can be relocated against the symbol
642       // directly if the symbol ends up in the same linkage unit.
643       switch (Opcode) {
644       default:
645         return X86::reloc_riprel_4byte;
646       case X86::MOV64rm:
647         // movq loads is a subset of reloc_riprel_4byte_relax_rex/rex2. It is a
648         // special case because COFF and Mach-O don't support ELF's more
649         // flexible R_X86_64_REX_GOTPCRELX/R_X86_64_CODE_4_GOTPCRELX relaxation.
650         return Kind == REX2 ? X86::reloc_riprel_4byte_movq_load_rex2
651                             : X86::reloc_riprel_4byte_movq_load;
652       case X86::ADC32rm:
653       case X86::ADD32rm:
654       case X86::AND32rm:
655       case X86::CMP32rm:
656       case X86::MOV32rm:
657       case X86::OR32rm:
658       case X86::SBB32rm:
659       case X86::SUB32rm:
660       case X86::TEST32mr:
661       case X86::XOR32rm:
662       case X86::CALL64m:
663       case X86::JMP64m:
664       case X86::TAILJMPm64:
665       case X86::TEST64mr:
666       case X86::ADC64rm:
667       case X86::ADD64rm:
668       case X86::AND64rm:
669       case X86::CMP64rm:
670       case X86::OR64rm:
671       case X86::SBB64rm:
672       case X86::SUB64rm:
673       case X86::XOR64rm:
674       case X86::LEA64r:
675         return Kind == REX2  ? X86::reloc_riprel_4byte_relax_rex2
676                : Kind == REX ? X86::reloc_riprel_4byte_relax_rex
677                              : X86::reloc_riprel_4byte_relax;
678       case X86::ADD64rm_NF:
679       case X86::ADD64rm_ND:
680       case X86::ADD64mr_ND:
681       case X86::ADD64mr_NF_ND:
682       case X86::ADD64rm_NF_ND:
683         return X86::reloc_riprel_4byte_relax_evex;
684       }
685     }();
686 
687     // rip-relative addressing is actually relative to the *next* instruction.
688     // Since an immediate can follow the mod/rm byte for an instruction, this
689     // means that we need to bias the displacement field of the instruction with
690     // the size of the immediate field. If we have this case, add it into the
691     // expression to emit.
692     // Note: rip-relative addressing using immediate displacement values should
693     // not be adjusted, assuming it was the user's intent.
694     int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags)
695                       ? X86II::getSizeOfImm(TSFlags)
696                       : 0;
697 
698     emitImmediate(Disp, MI.getLoc(), FixupKind, true, StartByte, CB, Fixups,
699                   -ImmSize);
700     return;
701   }
702 
703   unsigned BaseRegNo = BaseReg ? getX86RegNum(Base) : -1U;
704 
705   bool IsAdSize16 = STI.hasFeature(X86::Is32Bit) &&
706                     (TSFlags & X86II::AdSizeMask) == X86II::AdSize16;
707 
708   // 16-bit addressing forms of the ModR/M byte have a different encoding for
709   // the R/M field and are far more limited in which registers can be used.
710   if (IsAdSize16 || X86_MC::is16BitMemOperand(MI, Op, STI)) {
711     if (BaseReg) {
712       // For 32-bit addressing, the row and column values in Table 2-2 are
713       // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
714       // some special cases. And getX86RegNum reflects that numbering.
715       // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
716       // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
717       // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
718       // while values 0-3 indicate the allowed combinations (base+index) of
719       // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
720       //
721       // R16Table[] is a lookup from the normal RegNo, to the row values from
722       // Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
723       static const unsigned R16Table[] = {0, 0, 0, 7, 0, 6, 4, 5};
724       unsigned RMfield = R16Table[BaseRegNo];
725 
726       assert(RMfield && "invalid 16-bit base register");
727 
728       if (IndexReg.getReg()) {
729         unsigned IndexReg16 = R16Table[getX86RegNum(IndexReg)];
730 
731         assert(IndexReg16 && "invalid 16-bit index register");
732         // We must have one of SI/DI (4,5), and one of BP/BX (6,7).
733         assert(((IndexReg16 ^ RMfield) & 2) &&
734                "invalid 16-bit base/index register combination");
735         assert(Scale.getImm() == 1 &&
736                "invalid scale for 16-bit memory reference");
737 
738         // Allow base/index to appear in either order (although GAS doesn't).
739         if (IndexReg16 & 2)
740           RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
741         else
742           RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
743       }
744 
745       if (Disp.isImm() && isInt<8>(Disp.getImm())) {
746         if (Disp.getImm() == 0 && RMfield != 6) {
747           // There is no displacement; just the register.
748           emitByte(modRMByte(0, RegOpcodeField, RMfield), CB);
749           return;
750         }
751         // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
752         emitByte(modRMByte(1, RegOpcodeField, RMfield), CB);
753         emitImmediate(Disp, MI.getLoc(), FK_Data_1, false, StartByte, CB,
754                       Fixups);
755         return;
756       }
757       // This is the [REG]+disp16 case.
758       emitByte(modRMByte(2, RegOpcodeField, RMfield), CB);
759     } else {
760       assert(!IndexReg.getReg() && "Unexpected index register!");
761       // There is no BaseReg; this is the plain [disp16] case.
762       emitByte(modRMByte(0, RegOpcodeField, 6), CB);
763     }
764 
765     // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
766     emitImmediate(Disp, MI.getLoc(), FK_Data_2, false, StartByte, CB, Fixups);
767     return;
768   }
769 
770   // Check for presence of {disp8} or {disp32} pseudo prefixes.
771   bool UseDisp8 = MI.getFlags() & X86::IP_USE_DISP8;
772   bool UseDisp32 = MI.getFlags() & X86::IP_USE_DISP32;
773 
774   // We only allow no displacement if no pseudo prefix is present.
775   bool AllowNoDisp = !UseDisp8 && !UseDisp32;
776   // Disp8 is allowed unless the {disp32} prefix is present.
777   bool AllowDisp8 = !UseDisp32;
778 
779   // Determine whether a SIB byte is needed.
780   if (!ForceSIB && !X86II::needSIB(BaseReg, IndexReg.getReg(),
781                                    STI.hasFeature(X86::Is64Bit))) {
782     if (!BaseReg) { // [disp32]     in X86-32 mode
783       emitByte(modRMByte(0, RegOpcodeField, 5), CB);
784       emitImmediate(Disp, MI.getLoc(), FK_Data_4, false, StartByte, CB, Fixups);
785       return;
786     }
787 
788     // If the base is not EBP/ESP/R12/R13/R20/R21/R28/R29 and there is no
789     // displacement, use simple indirect register encoding, this handles
790     // addresses like [EAX]. The encoding for [EBP], [R13], [R20], [R21], [R28]
791     // or [R29] with no displacement means [disp32] so we handle it by emitting
792     // a displacement of 0 later.
793     if (BaseRegNo != N86::EBP) {
794       if (Disp.isImm() && Disp.getImm() == 0 && AllowNoDisp) {
795         emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CB);
796         return;
797       }
798 
799       // If the displacement is @tlscall, treat it as a zero.
800       if (Disp.isExpr()) {
801         auto *Sym = dyn_cast<MCSymbolRefExpr>(Disp.getExpr());
802         if (Sym && Sym->getSpecifier() == X86::S_TLSCALL) {
803           // This is exclusively used by call *a@tlscall(base). The relocation
804           // (R_386_TLSCALL or R_X86_64_TLSCALL) applies to the beginning.
805           Fixups.push_back(MCFixup::create(0, Sym, FK_NONE));
806           emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CB);
807           return;
808         }
809       }
810     }
811 
812     // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
813     // Including a compressed disp8 for EVEX instructions that support it.
814     // This also handles the 0 displacement for [EBP], [R13], [R21] or [R29]. We
815     // can't use disp8 if the {disp32} pseudo prefix is present.
816     if (Disp.isImm() && AllowDisp8) {
817       int ImmOffset = 0;
818       if (isDispOrCDisp8(TSFlags, Disp.getImm(), ImmOffset)) {
819         emitByte(modRMByte(1, RegOpcodeField, BaseRegNo), CB);
820         emitImmediate(Disp, MI.getLoc(), FK_Data_1, false, StartByte, CB,
821                       Fixups, ImmOffset);
822         return;
823       }
824     }
825 
826     // Otherwise, emit the most general non-SIB encoding: [REG+disp32].
827     // Displacement may be 0 for [EBP], [R13], [R21], [R29] case if {disp32}
828     // pseudo prefix prevented using disp8 above.
829     emitByte(modRMByte(2, RegOpcodeField, BaseRegNo), CB);
830     unsigned Opcode = MI.getOpcode();
831     unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax
832                                                 : X86::reloc_signed_4byte;
833     emitImmediate(Disp, MI.getLoc(), MCFixupKind(FixupKind), false, StartByte,
834                   CB, Fixups);
835     return;
836   }
837 
838   // We need a SIB byte, so start by outputting the ModR/M byte first
839   assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP &&
840          "Cannot use ESP as index reg!");
841 
842   bool ForceDisp32 = false;
843   bool ForceDisp8 = false;
844   int ImmOffset = 0;
845   if (!BaseReg) {
846     // If there is no base register, we emit the special case SIB byte with
847     // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
848     BaseRegNo = 5;
849     emitByte(modRMByte(0, RegOpcodeField, 4), CB);
850     ForceDisp32 = true;
851   } else if (Disp.isImm() && Disp.getImm() == 0 && AllowNoDisp &&
852              // Base reg can't be EBP/RBP/R13/R21/R29 as that would end up with
853              // '5' as the base field, but that is the magic [*] nomenclature
854              // that indicates no base when mod=0. For these cases we'll emit a
855              // 0 displacement instead.
856              BaseRegNo != N86::EBP) {
857     // Emit no displacement ModR/M byte
858     emitByte(modRMByte(0, RegOpcodeField, 4), CB);
859   } else if (Disp.isImm() && AllowDisp8 &&
860              isDispOrCDisp8(TSFlags, Disp.getImm(), ImmOffset)) {
861     // Displacement fits in a byte or matches an EVEX compressed disp8, use
862     // disp8 encoding. This also handles EBP/R13/R21/R29 base with 0
863     // displacement unless {disp32} pseudo prefix was used.
864     emitByte(modRMByte(1, RegOpcodeField, 4), CB);
865     ForceDisp8 = true;
866   } else {
867     // Otherwise, emit the normal disp32 encoding.
868     emitByte(modRMByte(2, RegOpcodeField, 4), CB);
869     ForceDisp32 = true;
870   }
871 
872   // Calculate what the SS field value should be...
873   static const unsigned SSTable[] = {~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3};
874   unsigned SS = SSTable[Scale.getImm()];
875 
876   unsigned IndexRegNo = IndexReg.getReg() ? getX86RegNum(IndexReg) : 4;
877 
878   emitSIBByte(SS, IndexRegNo, BaseRegNo, CB);
879 
880   // Do we need to output a displacement?
881   if (ForceDisp8)
882     emitImmediate(Disp, MI.getLoc(), FK_Data_1, false, StartByte, CB, Fixups,
883                   ImmOffset);
884   else if (ForceDisp32)
885     emitImmediate(Disp, MI.getLoc(), X86::reloc_signed_4byte, false, StartByte,
886                   CB, Fixups);
887 }
888 
889 /// Emit all instruction prefixes.
890 ///
891 /// \returns one of the REX, XOP, VEX2, VEX3, EVEX if any of them is used,
892 /// otherwise returns None.
emitPrefixImpl(unsigned & CurOp,const MCInst & MI,const MCSubtargetInfo & STI,SmallVectorImpl<char> & CB) const893 PrefixKind X86MCCodeEmitter::emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
894                                             const MCSubtargetInfo &STI,
895                                             SmallVectorImpl<char> &CB) const {
896   uint64_t TSFlags = MCII.get(MI.getOpcode()).TSFlags;
897   // Determine where the memory operand starts, if present.
898   int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
899   // Emit segment override opcode prefix as needed.
900   if (MemoryOperand != -1) {
901     MemoryOperand += CurOp;
902     emitSegmentOverridePrefix(MemoryOperand + X86::AddrSegmentReg, MI, CB);
903   }
904 
905   // Emit the repeat opcode prefix as needed.
906   unsigned Flags = MI.getFlags();
907   if (TSFlags & X86II::REP || Flags & X86::IP_HAS_REPEAT)
908     emitByte(0xF3, CB);
909   if (Flags & X86::IP_HAS_REPEAT_NE)
910     emitByte(0xF2, CB);
911 
912   // Emit the address size opcode prefix as needed.
913   if (X86_MC::needsAddressSizeOverride(MI, STI, MemoryOperand, TSFlags) ||
914       Flags & X86::IP_HAS_AD_SIZE)
915     emitByte(0x67, CB);
916 
917   uint64_t Form = TSFlags & X86II::FormMask;
918   switch (Form) {
919   default:
920     break;
921   case X86II::RawFrmDstSrc: {
922     // Emit segment override opcode prefix as needed (not for %ds).
923     if (MI.getOperand(2).getReg() != X86::DS)
924       emitSegmentOverridePrefix(2, MI, CB);
925     CurOp += 3; // Consume operands.
926     break;
927   }
928   case X86II::RawFrmSrc: {
929     // Emit segment override opcode prefix as needed (not for %ds).
930     if (MI.getOperand(1).getReg() != X86::DS)
931       emitSegmentOverridePrefix(1, MI, CB);
932     CurOp += 2; // Consume operands.
933     break;
934   }
935   case X86II::RawFrmDst: {
936     ++CurOp; // Consume operand.
937     break;
938   }
939   case X86II::RawFrmMemOffs: {
940     // Emit segment override opcode prefix as needed.
941     emitSegmentOverridePrefix(1, MI, CB);
942     break;
943   }
944   }
945 
946   // REX prefix is optional, but if used must be immediately before the opcode
947   // Encoding type for this instruction.
948   return (TSFlags & X86II::EncodingMask)
949              ? emitVEXOpcodePrefix(MemoryOperand, MI, STI, CB)
950              : emitOpcodePrefix(MemoryOperand, MI, STI, CB);
951 }
952 
953 // AVX instructions are encoded using an encoding scheme that combines
954 // prefix bytes, opcode extension field, operand encoding fields, and vector
955 // length encoding capability into a new prefix, referred to as VEX.
956 
957 // The majority of the AVX-512 family of instructions (operating on
958 // 512/256/128-bit vector register operands) are encoded using a new prefix
959 // (called EVEX).
960 
961 // XOP is a revised subset of what was originally intended as SSE5. It was
962 // changed to be similar but not overlapping with AVX.
963 
964 /// Emit XOP, VEX2, VEX3 or EVEX prefix.
965 /// \returns the used prefix.
966 PrefixKind
emitVEXOpcodePrefix(int MemOperand,const MCInst & MI,const MCSubtargetInfo & STI,SmallVectorImpl<char> & CB) const967 X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
968                                       const MCSubtargetInfo &STI,
969                                       SmallVectorImpl<char> &CB) const {
970   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
971   uint64_t TSFlags = Desc.TSFlags;
972 
973   assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
974 
975 #ifndef NDEBUG
976   unsigned NumOps = MI.getNumOperands();
977   for (unsigned I = NumOps ? X86II::getOperandBias(Desc) : 0; I != NumOps;
978        ++I) {
979     const MCOperand &MO = MI.getOperand(I);
980     if (!MO.isReg())
981       continue;
982     MCRegister Reg = MO.getReg();
983     if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
984       report_fatal_error(
985           "Cannot encode high byte register in VEX/EVEX-prefixed instruction");
986   }
987 #endif
988 
989   X86OpcodePrefixHelper Prefix(*Ctx.getRegisterInfo());
990   switch (TSFlags & X86II::EncodingMask) {
991   default:
992     break;
993   case X86II::XOP:
994     Prefix.setLowerBound(XOP);
995     break;
996   case X86II::VEX:
997     // VEX can be 2 byte or 3 byte, not determined yet if not explicit
998     Prefix.setLowerBound((MI.getFlags() & X86::IP_USE_VEX3) ? VEX3 : VEX2);
999     break;
1000   case X86II::EVEX:
1001     Prefix.setLowerBound(EVEX);
1002     break;
1003   }
1004 
1005   Prefix.setW(TSFlags & X86II::REX_W);
1006   Prefix.setNF(TSFlags & X86II::EVEX_NF);
1007 
1008   bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1009   bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1010   bool IsND = X86II::hasNewDataDest(TSFlags); // IsND implies HasVEX_4V
1011   bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
1012 
1013   switch (TSFlags & X86II::OpMapMask) {
1014   default:
1015     llvm_unreachable("Invalid prefix!");
1016   case X86II::TB:
1017     Prefix.set5M(0x1); // 0F
1018     break;
1019   case X86II::T8:
1020     Prefix.set5M(0x2); // 0F 38
1021     break;
1022   case X86II::TA:
1023     Prefix.set5M(0x3); // 0F 3A
1024     break;
1025   case X86II::XOP8:
1026     Prefix.set5M(0x8);
1027     break;
1028   case X86II::XOP9:
1029     Prefix.set5M(0x9);
1030     break;
1031   case X86II::XOPA:
1032     Prefix.set5M(0xA);
1033     break;
1034   case X86II::T_MAP4:
1035     Prefix.set5M(0x4);
1036     break;
1037   case X86II::T_MAP5:
1038     Prefix.set5M(0x5);
1039     break;
1040   case X86II::T_MAP6:
1041     Prefix.set5M(0x6);
1042     break;
1043   case X86II::T_MAP7:
1044     Prefix.set5M(0x7);
1045     break;
1046   }
1047 
1048   Prefix.setL(TSFlags & X86II::VEX_L);
1049   Prefix.setL2(TSFlags & X86II::EVEX_L2);
1050   if ((TSFlags & X86II::EVEX_L2) && STI.hasFeature(X86::FeatureAVX512) &&
1051       !STI.hasFeature(X86::FeatureEVEX512))
1052     report_fatal_error("ZMM registers are not supported without EVEX512");
1053   switch (TSFlags & X86II::OpPrefixMask) {
1054   case X86II::PD:
1055     Prefix.setPP(0x1); // 66
1056     break;
1057   case X86II::XS:
1058     Prefix.setPP(0x2); // F3
1059     break;
1060   case X86II::XD:
1061     Prefix.setPP(0x3); // F2
1062     break;
1063   }
1064 
1065   Prefix.setZ(HasEVEX_K && (TSFlags & X86II::EVEX_Z));
1066   Prefix.setEVEX_b(TSFlags & X86II::EVEX_B);
1067   Prefix.setEVEX_U(TSFlags & X86II::EVEX_U);
1068 
1069   bool EncodeRC = false;
1070   uint8_t EVEX_rc = 0;
1071 
1072   unsigned CurOp = X86II::getOperandBias(Desc);
1073   bool HasTwoConditionalOps = TSFlags & X86II::TwoConditionalOps;
1074 
1075   switch (TSFlags & X86II::FormMask) {
1076   default:
1077     llvm_unreachable("Unexpected form in emitVEXOpcodePrefix!");
1078   case X86II::MRMDestMem4VOp3CC: {
1079     //  src1(ModR/M), MemAddr, src2(VEX_4V)
1080     Prefix.setRR2(MI, CurOp++);
1081     Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1082     Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1083     CurOp += X86::AddrNumOperands;
1084     Prefix.set4VV2(MI, CurOp++);
1085     break;
1086   }
1087   case X86II::MRM_C0:
1088   case X86II::RawFrm:
1089     break;
1090   case X86II::MRMDestMemCC:
1091   case X86II::MRMDestMemFSIB:
1092   case X86II::MRMDestMem: {
1093     // MRMDestMem instructions forms:
1094     //  MemAddr, src1(ModR/M)
1095     //  MemAddr, src1(VEX_4V), src2(ModR/M)
1096     //  MemAddr, src1(ModR/M), imm8
1097     //
1098     // NDD:
1099     //  dst(VEX_4V), MemAddr, src1(ModR/M)
1100     Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1101     Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1102     Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V);
1103 
1104     if (IsND)
1105       Prefix.set4VV2(MI, CurOp++);
1106 
1107     CurOp += X86::AddrNumOperands;
1108 
1109     if (HasEVEX_K)
1110       Prefix.setAAA(MI, CurOp++);
1111 
1112     if (!IsND && HasVEX_4V)
1113       Prefix.set4VV2(MI, CurOp++);
1114 
1115     Prefix.setRR2(MI, CurOp++);
1116     if (HasTwoConditionalOps) {
1117       Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1118       Prefix.setSC(MI, CurOp++);
1119     }
1120     break;
1121   }
1122   case X86II::MRMSrcMemCC:
1123   case X86II::MRMSrcMemFSIB:
1124   case X86II::MRMSrcMem: {
1125     // MRMSrcMem instructions forms:
1126     //  src1(ModR/M), MemAddr
1127     //  src1(ModR/M), src2(VEX_4V), MemAddr
1128     //  src1(ModR/M), MemAddr, imm8
1129     //  src1(ModR/M), MemAddr, src2(Imm[7:4])
1130     //
1131     //  FMA4:
1132     //  dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
1133     //
1134     //  NDD:
1135     //  dst(VEX_4V), src1(ModR/M), MemAddr
1136     if (IsND)
1137       Prefix.set4VV2(MI, CurOp++);
1138 
1139     Prefix.setRR2(MI, CurOp++);
1140 
1141     if (HasEVEX_K)
1142       Prefix.setAAA(MI, CurOp++);
1143 
1144     if (!IsND && HasVEX_4V)
1145       Prefix.set4VV2(MI, CurOp++);
1146 
1147     Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1148     Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1149     Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V);
1150     CurOp += X86::AddrNumOperands;
1151     if (HasTwoConditionalOps) {
1152       Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1153       Prefix.setSC(MI, CurOp++);
1154     }
1155     break;
1156   }
1157   case X86II::MRMSrcMem4VOp3: {
1158     // Instruction format for 4VOp3:
1159     //   src1(ModR/M), MemAddr, src3(VEX_4V)
1160     Prefix.setRR2(MI, CurOp++);
1161     Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1162     Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1163     Prefix.set4VV2(MI, CurOp + X86::AddrNumOperands);
1164     break;
1165   }
1166   case X86II::MRMSrcMemOp4: {
1167     //  dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
1168     Prefix.setR(MI, CurOp++);
1169     Prefix.set4V(MI, CurOp++);
1170     Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1171     Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1172     break;
1173   }
1174   case X86II::MRMXmCC:
1175   case X86II::MRM0m:
1176   case X86II::MRM1m:
1177   case X86II::MRM2m:
1178   case X86II::MRM3m:
1179   case X86II::MRM4m:
1180   case X86II::MRM5m:
1181   case X86II::MRM6m:
1182   case X86II::MRM7m: {
1183     // MRM[0-9]m instructions forms:
1184     //  MemAddr
1185     //  src1(VEX_4V), MemAddr
1186     if (HasVEX_4V)
1187       Prefix.set4VV2(MI, CurOp++);
1188 
1189     if (HasEVEX_K)
1190       Prefix.setAAA(MI, CurOp++);
1191 
1192     Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1193     Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1194     Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V);
1195     CurOp += X86::AddrNumOperands + 1; // Skip first imm.
1196     if (HasTwoConditionalOps) {
1197       Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1198       Prefix.setSC(MI, CurOp++);
1199     }
1200     break;
1201   }
1202   case X86II::MRMSrcRegCC:
1203   case X86II::MRMSrcReg: {
1204     // MRMSrcReg instructions forms:
1205     //  dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
1206     //  dst(ModR/M), src1(ModR/M)
1207     //  dst(ModR/M), src1(ModR/M), imm8
1208     //
1209     //  FMA4:
1210     //  dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
1211     //
1212     //  NDD:
1213     //  dst(VEX_4V), src1(ModR/M.reg), src2(ModR/M)
1214     if (IsND)
1215       Prefix.set4VV2(MI, CurOp++);
1216     Prefix.setRR2(MI, CurOp++);
1217 
1218     if (HasEVEX_K)
1219       Prefix.setAAA(MI, CurOp++);
1220 
1221     if (!IsND && HasVEX_4V)
1222       Prefix.set4VV2(MI, CurOp++);
1223 
1224     Prefix.setBB2(MI, CurOp);
1225     Prefix.setX(MI, CurOp, 4);
1226     ++CurOp;
1227 
1228     if (HasTwoConditionalOps) {
1229       Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1230       Prefix.setSC(MI, CurOp++);
1231     }
1232 
1233     if (TSFlags & X86II::EVEX_B) {
1234       if (HasEVEX_RC) {
1235         unsigned NumOps = Desc.getNumOperands();
1236         unsigned RcOperand = NumOps - 1;
1237         assert(RcOperand >= CurOp);
1238         EVEX_rc = MI.getOperand(RcOperand).getImm();
1239         assert(EVEX_rc <= 3 && "Invalid rounding control!");
1240       }
1241       EncodeRC = true;
1242     }
1243     break;
1244   }
1245   case X86II::MRMSrcReg4VOp3: {
1246     // Instruction format for 4VOp3:
1247     //   src1(ModR/M), src2(ModR/M), src3(VEX_4V)
1248     Prefix.setRR2(MI, CurOp++);
1249     Prefix.setBB2(MI, CurOp++);
1250     Prefix.set4VV2(MI, CurOp++);
1251     break;
1252   }
1253   case X86II::MRMSrcRegOp4: {
1254     //  dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
1255     Prefix.setR(MI, CurOp++);
1256     Prefix.set4V(MI, CurOp++);
1257     // Skip second register source (encoded in Imm[7:4])
1258     ++CurOp;
1259 
1260     Prefix.setB(MI, CurOp);
1261     Prefix.setX(MI, CurOp, 4);
1262     ++CurOp;
1263     break;
1264   }
1265   case X86II::MRMDestRegCC:
1266   case X86II::MRMDestReg: {
1267     // MRMDestReg instructions forms:
1268     //  dst(ModR/M), src(ModR/M)
1269     //  dst(ModR/M), src(ModR/M), imm8
1270     //  dst(ModR/M), src1(VEX_4V), src2(ModR/M)
1271     //
1272     // NDD:
1273     // dst(VEX_4V), src1(ModR/M), src2(ModR/M)
1274     if (IsND)
1275       Prefix.set4VV2(MI, CurOp++);
1276     Prefix.setBB2(MI, CurOp);
1277     Prefix.setX(MI, CurOp, 4);
1278     ++CurOp;
1279 
1280     if (HasEVEX_K)
1281       Prefix.setAAA(MI, CurOp++);
1282 
1283     if (!IsND && HasVEX_4V)
1284       Prefix.set4VV2(MI, CurOp++);
1285 
1286     Prefix.setRR2(MI, CurOp++);
1287     if (HasTwoConditionalOps) {
1288       Prefix.set4V(MI, CurOp++, /*IsImm=*/true);
1289       Prefix.setSC(MI, CurOp++);
1290     }
1291     if (TSFlags & X86II::EVEX_B)
1292       EncodeRC = true;
1293     break;
1294   }
1295   case X86II::MRMr0: {
1296     // MRMr0 instructions forms:
1297     //  11:rrr:000
1298     //  dst(ModR/M)
1299     Prefix.setRR2(MI, CurOp++);
1300     break;
1301   }
1302   case X86II::MRMXrCC:
1303   case X86II::MRM0r:
1304   case X86II::MRM1r:
1305   case X86II::MRM2r:
1306   case X86II::MRM3r:
1307   case X86II::MRM4r:
1308   case X86II::MRM5r:
1309   case X86II::MRM6r:
1310   case X86II::MRM7r: {
1311     // MRM0r-MRM7r instructions forms:
1312     //  dst(VEX_4V), src(ModR/M), imm8
1313     if (HasVEX_4V)
1314       Prefix.set4VV2(MI, CurOp++);
1315 
1316     if (HasEVEX_K)
1317       Prefix.setAAA(MI, CurOp++);
1318 
1319     Prefix.setBB2(MI, CurOp);
1320     Prefix.setX(MI, CurOp, 4);
1321     ++CurOp;
1322     if (HasTwoConditionalOps) {
1323       Prefix.set4V(MI, ++CurOp, /*IsImm=*/true);
1324       Prefix.setSC(MI, ++CurOp);
1325     }
1326     break;
1327   }
1328   }
1329   if (EncodeRC) {
1330     Prefix.setL(EVEX_rc & 0x1);
1331     Prefix.setL2(EVEX_rc & 0x2);
1332   }
1333   PrefixKind Kind = Prefix.determineOptimalKind();
1334   Prefix.emit(CB);
1335   return Kind;
1336 }
1337 
1338 /// Emit REX prefix which specifies
1339 ///   1) 64-bit instructions,
1340 ///   2) non-default operand size, and
1341 ///   3) use of X86-64 extended registers.
1342 ///
1343 /// \returns the used prefix (REX or None).
emitREXPrefix(int MemOperand,const MCInst & MI,const MCSubtargetInfo & STI,SmallVectorImpl<char> & CB) const1344 PrefixKind X86MCCodeEmitter::emitREXPrefix(int MemOperand, const MCInst &MI,
1345                                            const MCSubtargetInfo &STI,
1346                                            SmallVectorImpl<char> &CB) const {
1347   if (!STI.hasFeature(X86::Is64Bit))
1348     return None;
1349   X86OpcodePrefixHelper Prefix(*Ctx.getRegisterInfo());
1350   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1351   uint64_t TSFlags = Desc.TSFlags;
1352   Prefix.setW(TSFlags & X86II::REX_W);
1353   unsigned NumOps = MI.getNumOperands();
1354   bool UsesHighByteReg = false;
1355 #ifndef NDEBUG
1356   bool HasRegOp = false;
1357 #endif
1358   unsigned CurOp = NumOps ? X86II::getOperandBias(Desc) : 0;
1359   for (unsigned i = CurOp; i != NumOps; ++i) {
1360     const MCOperand &MO = MI.getOperand(i);
1361     if (MO.isReg()) {
1362 #ifndef NDEBUG
1363       HasRegOp = true;
1364 #endif
1365       MCRegister Reg = MO.getReg();
1366       if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
1367         UsesHighByteReg = true;
1368       // If it accesses SPL, BPL, SIL, or DIL, then it requires a REX prefix.
1369       if (X86II::isX86_64NonExtLowByteReg(Reg))
1370         Prefix.setLowerBound(REX);
1371     } else if (MO.isExpr() && STI.getTargetTriple().isX32()) {
1372       // GOTTPOFF and TLSDESC relocations require a REX prefix to allow
1373       // linker optimizations: even if the instructions we see may not require
1374       // any prefix, they may be replaced by instructions that do. This is
1375       // handled as a special case here so that it also works for hand-written
1376       // assembly without the user needing to write REX, as with GNU as.
1377       const auto *Ref = dyn_cast<MCSymbolRefExpr>(MO.getExpr());
1378       if (Ref && (Ref->getSpecifier() == X86::S_GOTTPOFF ||
1379                   Ref->getSpecifier() == X86::S_TLSDESC)) {
1380         Prefix.setLowerBound(REX);
1381       }
1382     }
1383   }
1384   if (MI.getFlags() & X86::IP_USE_REX)
1385     Prefix.setLowerBound(REX);
1386   if ((TSFlags & X86II::ExplicitOpPrefixMask) == X86II::ExplicitREX2Prefix ||
1387       MI.getFlags() & X86::IP_USE_REX2)
1388     Prefix.setLowerBound(REX2);
1389   switch (TSFlags & X86II::FormMask) {
1390   default:
1391     assert(!HasRegOp && "Unexpected form in emitREXPrefix!");
1392     break;
1393   case X86II::RawFrm:
1394   case X86II::RawFrmMemOffs:
1395   case X86II::RawFrmSrc:
1396   case X86II::RawFrmDst:
1397   case X86II::RawFrmDstSrc:
1398     break;
1399   case X86II::AddRegFrm:
1400     Prefix.setBB2(MI, CurOp++);
1401     break;
1402   case X86II::MRMSrcReg:
1403   case X86II::MRMSrcRegCC:
1404     Prefix.setRR2(MI, CurOp++);
1405     Prefix.setBB2(MI, CurOp++);
1406     break;
1407   case X86II::MRMSrcMem:
1408   case X86II::MRMSrcMemCC:
1409     Prefix.setRR2(MI, CurOp++);
1410     Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1411     Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1412     CurOp += X86::AddrNumOperands;
1413     break;
1414   case X86II::MRMDestReg:
1415     Prefix.setBB2(MI, CurOp++);
1416     Prefix.setRR2(MI, CurOp++);
1417     break;
1418   case X86II::MRMDestMem:
1419     Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1420     Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1421     CurOp += X86::AddrNumOperands;
1422     Prefix.setRR2(MI, CurOp++);
1423     break;
1424   case X86II::MRMXmCC:
1425   case X86II::MRMXm:
1426   case X86II::MRM0m:
1427   case X86II::MRM1m:
1428   case X86II::MRM2m:
1429   case X86II::MRM3m:
1430   case X86II::MRM4m:
1431   case X86II::MRM5m:
1432   case X86II::MRM6m:
1433   case X86II::MRM7m:
1434     Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg);
1435     Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
1436     break;
1437   case X86II::MRMXrCC:
1438   case X86II::MRMXr:
1439   case X86II::MRM0r:
1440   case X86II::MRM1r:
1441   case X86II::MRM2r:
1442   case X86II::MRM3r:
1443   case X86II::MRM4r:
1444   case X86II::MRM5r:
1445   case X86II::MRM6r:
1446   case X86II::MRM7r:
1447     Prefix.setBB2(MI, CurOp++);
1448     break;
1449   }
1450   Prefix.setM((TSFlags & X86II::OpMapMask) == X86II::TB);
1451   PrefixKind Kind = Prefix.determineOptimalKind();
1452   if (Kind && UsesHighByteReg)
1453     report_fatal_error(
1454         "Cannot encode high byte register in REX-prefixed instruction");
1455   Prefix.emit(CB);
1456   return Kind;
1457 }
1458 
1459 /// Emit segment override opcode prefix as needed.
emitSegmentOverridePrefix(unsigned SegOperand,const MCInst & MI,SmallVectorImpl<char> & CB) const1460 void X86MCCodeEmitter::emitSegmentOverridePrefix(
1461     unsigned SegOperand, const MCInst &MI, SmallVectorImpl<char> &CB) const {
1462   // Check for explicit segment override on memory operand.
1463   if (MCRegister Reg = MI.getOperand(SegOperand).getReg())
1464     emitByte(X86::getSegmentOverridePrefixForReg(Reg), CB);
1465 }
1466 
1467 /// Emit all instruction prefixes prior to the opcode.
1468 ///
1469 /// \param MemOperand the operand # of the start of a memory operand if present.
1470 /// If not present, it is -1.
1471 ///
1472 /// \returns the used prefix (REX or None).
emitOpcodePrefix(int MemOperand,const MCInst & MI,const MCSubtargetInfo & STI,SmallVectorImpl<char> & CB) const1473 PrefixKind X86MCCodeEmitter::emitOpcodePrefix(int MemOperand, const MCInst &MI,
1474                                               const MCSubtargetInfo &STI,
1475                                               SmallVectorImpl<char> &CB) const {
1476   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1477   uint64_t TSFlags = Desc.TSFlags;
1478 
1479   // Emit the operand size opcode prefix as needed.
1480   if ((TSFlags & X86II::OpSizeMask) ==
1481       (STI.hasFeature(X86::Is16Bit) ? X86II::OpSize32 : X86II::OpSize16))
1482     emitByte(0x66, CB);
1483 
1484   // Emit the LOCK opcode prefix.
1485   if (TSFlags & X86II::LOCK || MI.getFlags() & X86::IP_HAS_LOCK)
1486     emitByte(0xF0, CB);
1487 
1488   // Emit the NOTRACK opcode prefix.
1489   if (TSFlags & X86II::NOTRACK || MI.getFlags() & X86::IP_HAS_NOTRACK)
1490     emitByte(0x3E, CB);
1491 
1492   switch (TSFlags & X86II::OpPrefixMask) {
1493   case X86II::PD: // 66
1494     emitByte(0x66, CB);
1495     break;
1496   case X86II::XS: // F3
1497     emitByte(0xF3, CB);
1498     break;
1499   case X86II::XD: // F2
1500     emitByte(0xF2, CB);
1501     break;
1502   }
1503 
1504   // Handle REX prefix.
1505   assert((STI.hasFeature(X86::Is64Bit) || !(TSFlags & X86II::REX_W)) &&
1506          "REX.W requires 64bit mode.");
1507   PrefixKind Kind = emitREXPrefix(MemOperand, MI, STI, CB);
1508 
1509   // 0x0F escape code must be emitted just before the opcode.
1510   switch (TSFlags & X86II::OpMapMask) {
1511   case X86II::TB:        // Two-byte opcode map
1512     // Encoded by M bit in REX2
1513     if (Kind == REX2)
1514       break;
1515     [[fallthrough]];
1516   case X86II::T8:        // 0F 38
1517   case X86II::TA:        // 0F 3A
1518   case X86II::ThreeDNow: // 0F 0F, second 0F emitted by caller.
1519     emitByte(0x0F, CB);
1520     break;
1521   }
1522 
1523   switch (TSFlags & X86II::OpMapMask) {
1524   case X86II::T8: // 0F 38
1525     emitByte(0x38, CB);
1526     break;
1527   case X86II::TA: // 0F 3A
1528     emitByte(0x3A, CB);
1529     break;
1530   }
1531 
1532   return Kind;
1533 }
1534 
emitPrefix(const MCInst & MI,SmallVectorImpl<char> & CB,const MCSubtargetInfo & STI) const1535 void X86MCCodeEmitter::emitPrefix(const MCInst &MI, SmallVectorImpl<char> &CB,
1536                                   const MCSubtargetInfo &STI) const {
1537   unsigned Opcode = MI.getOpcode();
1538   const MCInstrDesc &Desc = MCII.get(Opcode);
1539   uint64_t TSFlags = Desc.TSFlags;
1540 
1541   // Pseudo instructions don't get encoded.
1542   if (X86II::isPseudo(TSFlags))
1543     return;
1544 
1545   unsigned CurOp = X86II::getOperandBias(Desc);
1546 
1547   emitPrefixImpl(CurOp, MI, STI, CB);
1548 }
1549 
emitPrefix(MCCodeEmitter & MCE,const MCInst & MI,SmallVectorImpl<char> & CB,const MCSubtargetInfo & STI)1550 void X86_MC::emitPrefix(MCCodeEmitter &MCE, const MCInst &MI,
1551                         SmallVectorImpl<char> &CB, const MCSubtargetInfo &STI) {
1552   static_cast<X86MCCodeEmitter &>(MCE).emitPrefix(MI, CB, STI);
1553 }
1554 
encodeInstruction(const MCInst & MI,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const1555 void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
1556                                          SmallVectorImpl<char> &CB,
1557                                          SmallVectorImpl<MCFixup> &Fixups,
1558                                          const MCSubtargetInfo &STI) const {
1559   unsigned Opcode = MI.getOpcode();
1560   const MCInstrDesc &Desc = MCII.get(Opcode);
1561   uint64_t TSFlags = Desc.TSFlags;
1562 
1563   // Pseudo instructions don't get encoded.
1564   if (X86II::isPseudo(TSFlags))
1565     return;
1566 
1567   unsigned NumOps = Desc.getNumOperands();
1568   unsigned CurOp = X86II::getOperandBias(Desc);
1569 
1570   uint64_t StartByte = CB.size();
1571 
1572   PrefixKind Kind = emitPrefixImpl(CurOp, MI, STI, CB);
1573 
1574   // It uses the VEX.VVVV field?
1575   bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1576   bool HasVEX_I8Reg = (TSFlags & X86II::ImmMask) == X86II::Imm8Reg;
1577 
1578   // It uses the EVEX.aaa field?
1579   bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1580   bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
1581 
1582   // Used if a register is encoded in 7:4 of immediate.
1583   unsigned I8RegNum = 0;
1584 
1585   uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1586 
1587   if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
1588     BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1589 
1590   unsigned OpcodeOffset = 0;
1591 
1592   bool IsND = X86II::hasNewDataDest(TSFlags);
1593   bool HasTwoConditionalOps = TSFlags & X86II::TwoConditionalOps;
1594 
1595   uint64_t Form = TSFlags & X86II::FormMask;
1596   switch (Form) {
1597   default:
1598     errs() << "FORM: " << Form << "\n";
1599     llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1600   case X86II::Pseudo:
1601     llvm_unreachable("Pseudo instruction shouldn't be emitted");
1602   case X86II::RawFrmDstSrc:
1603   case X86II::RawFrmSrc:
1604   case X86II::RawFrmDst:
1605   case X86II::PrefixByte:
1606     emitByte(BaseOpcode, CB);
1607     break;
1608   case X86II::AddCCFrm: {
1609     // This will be added to the opcode in the fallthrough.
1610     OpcodeOffset = MI.getOperand(NumOps - 1).getImm();
1611     assert(OpcodeOffset < 16 && "Unexpected opcode offset!");
1612     --NumOps; // Drop the operand from the end.
1613     [[fallthrough]];
1614   case X86II::RawFrm:
1615     emitByte(BaseOpcode + OpcodeOffset, CB);
1616 
1617     if (!STI.hasFeature(X86::Is64Bit) || !isPCRel32Branch(MI, MCII))
1618       break;
1619 
1620     const MCOperand &Op = MI.getOperand(CurOp++);
1621     emitImmediate(Op, MI.getLoc(), X86::reloc_branch_4byte_pcrel, true,
1622                   StartByte, CB, Fixups);
1623     break;
1624   }
1625   case X86II::RawFrmMemOffs:
1626     emitByte(BaseOpcode, CB);
1627     emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), getImmFixupKind(TSFlags),
1628                   X86II::isImmPCRel(TSFlags), StartByte, CB, Fixups);
1629     ++CurOp; // skip segment operand
1630     break;
1631   case X86II::RawFrmImm8:
1632     emitByte(BaseOpcode, CB);
1633     emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), getImmFixupKind(TSFlags),
1634                   X86II::isImmPCRel(TSFlags), StartByte, CB, Fixups);
1635     emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), FK_Data_1, false,
1636                   StartByte, CB, Fixups);
1637     break;
1638   case X86II::RawFrmImm16:
1639     emitByte(BaseOpcode, CB);
1640     emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), getImmFixupKind(TSFlags),
1641                   X86II::isImmPCRel(TSFlags), StartByte, CB, Fixups);
1642     emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), FK_Data_2, false,
1643                   StartByte, CB, Fixups);
1644     break;
1645 
1646   case X86II::AddRegFrm:
1647     emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), CB);
1648     break;
1649 
1650   case X86II::MRMDestReg: {
1651     emitByte(BaseOpcode, CB);
1652     unsigned SrcRegNum = CurOp + 1;
1653 
1654     if (HasEVEX_K) // Skip writemask
1655       ++SrcRegNum;
1656 
1657     if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1658       ++SrcRegNum;
1659     if (IsND) // Skip the NDD operand encoded in EVEX_VVVV
1660       ++CurOp;
1661 
1662     emitRegModRMByte(MI.getOperand(CurOp),
1663                      getX86RegNum(MI.getOperand(SrcRegNum)), CB);
1664     CurOp = SrcRegNum + 1;
1665     break;
1666   }
1667   case X86II::MRMDestRegCC: {
1668     unsigned FirstOp = CurOp++;
1669     unsigned SecondOp = CurOp++;
1670     unsigned CC = MI.getOperand(CurOp++).getImm();
1671     emitByte(BaseOpcode + CC, CB);
1672     emitRegModRMByte(MI.getOperand(FirstOp),
1673                      getX86RegNum(MI.getOperand(SecondOp)), CB);
1674     break;
1675   }
1676   case X86II::MRMDestMem4VOp3CC: {
1677     unsigned CC = MI.getOperand(8).getImm();
1678     emitByte(BaseOpcode + CC, CB);
1679     unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
1680     emitMemModRMByte(MI, CurOp + 1, getX86RegNum(MI.getOperand(0)), TSFlags,
1681                      Kind, StartByte, CB, Fixups, STI, false);
1682     CurOp = SrcRegNum + 3; // skip reg, VEX_V4 and CC
1683     break;
1684   }
1685   case X86II::MRMDestMemFSIB:
1686   case X86II::MRMDestMem: {
1687     emitByte(BaseOpcode, CB);
1688     unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
1689 
1690     if (HasEVEX_K) // Skip writemask
1691       ++SrcRegNum;
1692 
1693     if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1694       ++SrcRegNum;
1695 
1696     if (IsND) // Skip new data destination
1697       ++CurOp;
1698 
1699     bool ForceSIB = (Form == X86II::MRMDestMemFSIB);
1700     emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(SrcRegNum)), TSFlags,
1701                      Kind, StartByte, CB, Fixups, STI, ForceSIB);
1702     CurOp = SrcRegNum + 1;
1703     break;
1704   }
1705   case X86II::MRMDestMemCC: {
1706     unsigned MemOp = CurOp;
1707     CurOp = MemOp + X86::AddrNumOperands;
1708     unsigned RegOp = CurOp++;
1709     unsigned CC = MI.getOperand(CurOp++).getImm();
1710     emitByte(BaseOpcode + CC, CB);
1711     emitMemModRMByte(MI, MemOp, getX86RegNum(MI.getOperand(RegOp)), TSFlags,
1712                      Kind, StartByte, CB, Fixups, STI);
1713     break;
1714   }
1715   case X86II::MRMSrcReg: {
1716     emitByte(BaseOpcode, CB);
1717     unsigned SrcRegNum = CurOp + 1;
1718 
1719     if (HasEVEX_K) // Skip writemask
1720       ++SrcRegNum;
1721 
1722     if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1723       ++SrcRegNum;
1724 
1725     if (IsND) // Skip new data destination
1726       ++CurOp;
1727 
1728     emitRegModRMByte(MI.getOperand(SrcRegNum),
1729                      getX86RegNum(MI.getOperand(CurOp)), CB);
1730     CurOp = SrcRegNum + 1;
1731     if (HasVEX_I8Reg)
1732       I8RegNum = getX86RegEncoding(MI, CurOp++);
1733     // do not count the rounding control operand
1734     if (HasEVEX_RC)
1735       --NumOps;
1736     break;
1737   }
1738   case X86II::MRMSrcReg4VOp3: {
1739     emitByte(BaseOpcode, CB);
1740     unsigned SrcRegNum = CurOp + 1;
1741 
1742     emitRegModRMByte(MI.getOperand(SrcRegNum),
1743                      getX86RegNum(MI.getOperand(CurOp)), CB);
1744     CurOp = SrcRegNum + 1;
1745     ++CurOp; // Encoded in VEX.VVVV
1746     break;
1747   }
1748   case X86II::MRMSrcRegOp4: {
1749     emitByte(BaseOpcode, CB);
1750     unsigned SrcRegNum = CurOp + 1;
1751 
1752     // Skip 1st src (which is encoded in VEX_VVVV)
1753     ++SrcRegNum;
1754 
1755     // Capture 2nd src (which is encoded in Imm[7:4])
1756     assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
1757     I8RegNum = getX86RegEncoding(MI, SrcRegNum++);
1758 
1759     emitRegModRMByte(MI.getOperand(SrcRegNum),
1760                      getX86RegNum(MI.getOperand(CurOp)), CB);
1761     CurOp = SrcRegNum + 1;
1762     break;
1763   }
1764   case X86II::MRMSrcRegCC: {
1765     if (IsND) // Skip new data destination
1766       ++CurOp;
1767     unsigned FirstOp = CurOp++;
1768     unsigned SecondOp = CurOp++;
1769 
1770     unsigned CC = MI.getOperand(CurOp++).getImm();
1771     emitByte(BaseOpcode + CC, CB);
1772 
1773     emitRegModRMByte(MI.getOperand(SecondOp),
1774                      getX86RegNum(MI.getOperand(FirstOp)), CB);
1775     break;
1776   }
1777   case X86II::MRMSrcMemFSIB:
1778   case X86II::MRMSrcMem: {
1779     unsigned FirstMemOp = CurOp + 1;
1780 
1781     if (IsND) // Skip new data destination
1782       CurOp++;
1783 
1784     if (HasEVEX_K) // Skip writemask
1785       ++FirstMemOp;
1786 
1787     if (HasVEX_4V)
1788       ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1789 
1790     emitByte(BaseOpcode, CB);
1791 
1792     bool ForceSIB = (Form == X86II::MRMSrcMemFSIB);
1793     emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
1794                      TSFlags, Kind, StartByte, CB, Fixups, STI, ForceSIB);
1795     CurOp = FirstMemOp + X86::AddrNumOperands;
1796     if (HasVEX_I8Reg)
1797       I8RegNum = getX86RegEncoding(MI, CurOp++);
1798     break;
1799   }
1800   case X86II::MRMSrcMem4VOp3: {
1801     unsigned FirstMemOp = CurOp + 1;
1802 
1803     emitByte(BaseOpcode, CB);
1804 
1805     emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
1806                      TSFlags, Kind, StartByte, CB, Fixups, STI);
1807     CurOp = FirstMemOp + X86::AddrNumOperands;
1808     ++CurOp; // Encoded in VEX.VVVV.
1809     break;
1810   }
1811   case X86II::MRMSrcMemOp4: {
1812     unsigned FirstMemOp = CurOp + 1;
1813 
1814     ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1815 
1816     // Capture second register source (encoded in Imm[7:4])
1817     assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
1818     I8RegNum = getX86RegEncoding(MI, FirstMemOp++);
1819 
1820     emitByte(BaseOpcode, CB);
1821 
1822     emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
1823                      TSFlags, Kind, StartByte, CB, Fixups, STI);
1824     CurOp = FirstMemOp + X86::AddrNumOperands;
1825     break;
1826   }
1827   case X86II::MRMSrcMemCC: {
1828     if (IsND) // Skip new data destination
1829       ++CurOp;
1830     unsigned RegOp = CurOp++;
1831     unsigned FirstMemOp = CurOp;
1832     CurOp = FirstMemOp + X86::AddrNumOperands;
1833 
1834     unsigned CC = MI.getOperand(CurOp++).getImm();
1835     emitByte(BaseOpcode + CC, CB);
1836 
1837     emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)),
1838                      TSFlags, Kind, StartByte, CB, Fixups, STI);
1839     break;
1840   }
1841 
1842   case X86II::MRMXrCC: {
1843     unsigned RegOp = CurOp++;
1844 
1845     unsigned CC = MI.getOperand(CurOp++).getImm();
1846     emitByte(BaseOpcode + CC, CB);
1847     emitRegModRMByte(MI.getOperand(RegOp), 0, CB);
1848     break;
1849   }
1850 
1851   case X86II::MRMXr:
1852   case X86II::MRM0r:
1853   case X86II::MRM1r:
1854   case X86II::MRM2r:
1855   case X86II::MRM3r:
1856   case X86II::MRM4r:
1857   case X86II::MRM5r:
1858   case X86II::MRM6r:
1859   case X86II::MRM7r:
1860     if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1861       ++CurOp;
1862     if (HasEVEX_K) // Skip writemask
1863       ++CurOp;
1864     emitByte(BaseOpcode, CB);
1865     emitRegModRMByte(MI.getOperand(CurOp++),
1866                      (Form == X86II::MRMXr) ? 0 : Form - X86II::MRM0r, CB);
1867     break;
1868   case X86II::MRMr0:
1869     emitByte(BaseOpcode, CB);
1870     emitByte(modRMByte(3, getX86RegNum(MI.getOperand(CurOp++)), 0), CB);
1871     break;
1872 
1873   case X86II::MRMXmCC: {
1874     unsigned FirstMemOp = CurOp;
1875     CurOp = FirstMemOp + X86::AddrNumOperands;
1876 
1877     unsigned CC = MI.getOperand(CurOp++).getImm();
1878     emitByte(BaseOpcode + CC, CB);
1879 
1880     emitMemModRMByte(MI, FirstMemOp, 0, TSFlags, Kind, StartByte, CB, Fixups,
1881                      STI);
1882     break;
1883   }
1884 
1885   case X86II::MRMXm:
1886   case X86II::MRM0m:
1887   case X86II::MRM1m:
1888   case X86II::MRM2m:
1889   case X86II::MRM3m:
1890   case X86II::MRM4m:
1891   case X86II::MRM5m:
1892   case X86II::MRM6m:
1893   case X86II::MRM7m:
1894     if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1895       ++CurOp;
1896     if (HasEVEX_K) // Skip writemask
1897       ++CurOp;
1898     emitByte(BaseOpcode, CB);
1899     emitMemModRMByte(MI, CurOp,
1900                      (Form == X86II::MRMXm) ? 0 : Form - X86II::MRM0m, TSFlags,
1901                      Kind, StartByte, CB, Fixups, STI);
1902     CurOp += X86::AddrNumOperands;
1903     break;
1904 
1905   case X86II::MRM0X:
1906   case X86II::MRM1X:
1907   case X86II::MRM2X:
1908   case X86II::MRM3X:
1909   case X86II::MRM4X:
1910   case X86II::MRM5X:
1911   case X86II::MRM6X:
1912   case X86II::MRM7X:
1913     emitByte(BaseOpcode, CB);
1914     emitByte(0xC0 + ((Form - X86II::MRM0X) << 3), CB);
1915     break;
1916 
1917   case X86II::MRM_C0:
1918   case X86II::MRM_C1:
1919   case X86II::MRM_C2:
1920   case X86II::MRM_C3:
1921   case X86II::MRM_C4:
1922   case X86II::MRM_C5:
1923   case X86II::MRM_C6:
1924   case X86II::MRM_C7:
1925   case X86II::MRM_C8:
1926   case X86II::MRM_C9:
1927   case X86II::MRM_CA:
1928   case X86II::MRM_CB:
1929   case X86II::MRM_CC:
1930   case X86II::MRM_CD:
1931   case X86II::MRM_CE:
1932   case X86II::MRM_CF:
1933   case X86II::MRM_D0:
1934   case X86II::MRM_D1:
1935   case X86II::MRM_D2:
1936   case X86II::MRM_D3:
1937   case X86II::MRM_D4:
1938   case X86II::MRM_D5:
1939   case X86II::MRM_D6:
1940   case X86II::MRM_D7:
1941   case X86II::MRM_D8:
1942   case X86II::MRM_D9:
1943   case X86II::MRM_DA:
1944   case X86II::MRM_DB:
1945   case X86II::MRM_DC:
1946   case X86II::MRM_DD:
1947   case X86II::MRM_DE:
1948   case X86II::MRM_DF:
1949   case X86II::MRM_E0:
1950   case X86II::MRM_E1:
1951   case X86II::MRM_E2:
1952   case X86II::MRM_E3:
1953   case X86II::MRM_E4:
1954   case X86II::MRM_E5:
1955   case X86II::MRM_E6:
1956   case X86II::MRM_E7:
1957   case X86II::MRM_E8:
1958   case X86II::MRM_E9:
1959   case X86II::MRM_EA:
1960   case X86II::MRM_EB:
1961   case X86II::MRM_EC:
1962   case X86II::MRM_ED:
1963   case X86II::MRM_EE:
1964   case X86II::MRM_EF:
1965   case X86II::MRM_F0:
1966   case X86II::MRM_F1:
1967   case X86II::MRM_F2:
1968   case X86II::MRM_F3:
1969   case X86II::MRM_F4:
1970   case X86II::MRM_F5:
1971   case X86II::MRM_F6:
1972   case X86II::MRM_F7:
1973   case X86II::MRM_F8:
1974   case X86II::MRM_F9:
1975   case X86II::MRM_FA:
1976   case X86II::MRM_FB:
1977   case X86II::MRM_FC:
1978   case X86II::MRM_FD:
1979   case X86II::MRM_FE:
1980   case X86II::MRM_FF:
1981     emitByte(BaseOpcode, CB);
1982     emitByte(0xC0 + Form - X86II::MRM_C0, CB);
1983     break;
1984   }
1985 
1986   if (HasVEX_I8Reg) {
1987     // The last source register of a 4 operand instruction in AVX is encoded
1988     // in bits[7:4] of a immediate byte.
1989     assert(I8RegNum < 16 && "Register encoding out of range");
1990     I8RegNum <<= 4;
1991     if (CurOp != NumOps) {
1992       unsigned Val = MI.getOperand(CurOp++).getImm();
1993       assert(Val < 16 && "Immediate operand value out of range");
1994       I8RegNum |= Val;
1995     }
1996     emitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), FK_Data_1, false,
1997                   StartByte, CB, Fixups);
1998   } else {
1999     // If there is a remaining operand, it must be a trailing immediate. Emit it
2000     // according to the right size for the instruction. Some instructions
2001     // (SSE4a extrq and insertq) have two trailing immediates.
2002 
2003     // Skip two trainling conditional operands encoded in EVEX prefix
2004     unsigned RemainingOps = NumOps - CurOp - 2 * HasTwoConditionalOps;
2005     while (RemainingOps) {
2006       emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
2007                     getImmFixupKind(Desc.TSFlags),
2008                     X86II::isImmPCRel(Desc.TSFlags), StartByte, CB, Fixups);
2009       --RemainingOps;
2010     }
2011     CurOp += 2 * HasTwoConditionalOps;
2012   }
2013 
2014   if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
2015     emitByte(X86II::getBaseOpcodeFor(TSFlags), CB);
2016 
2017   if (CB.size() - StartByte > 15)
2018     Ctx.reportError(MI.getLoc(), "instruction length exceeds the limit of 15");
2019 #ifndef NDEBUG
2020   // FIXME: Verify.
2021   if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
2022     errs() << "Cannot encode all operands of: ";
2023     MI.dump();
2024     errs() << '\n';
2025     abort();
2026   }
2027 #endif
2028 }
2029 
createX86MCCodeEmitter(const MCInstrInfo & MCII,MCContext & Ctx)2030 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
2031                                             MCContext &Ctx) {
2032   return new X86MCCodeEmitter(MCII, Ctx);
2033 }
2034