1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /* A10/A20 EMAC driver */
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/bus.h>
36 #include <sys/lock.h>
37 #include <sys/mbuf.h>
38 #include <sys/mutex.h>
39 #include <sys/rman.h>
40 #include <sys/socket.h>
41 #include <sys/sockio.h>
42 #include <sys/sysctl.h>
43 #include <sys/gpio.h>
44
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #include <machine/intr.h>
48
49 #include <net/if.h>
50 #include <net/if_var.h>
51 #include <net/if_arp.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
55 #include <net/if_mib.h>
56 #include <net/ethernet.h>
57 #include <net/if_vlan_var.h>
58
59 #ifdef INET
60 #include <netinet/in.h>
61 #include <netinet/in_systm.h>
62 #include <netinet/in_var.h>
63 #include <netinet/ip.h>
64 #endif
65
66 #include <net/bpf.h>
67 #include <net/bpfdesc.h>
68
69 #include <dev/ofw/ofw_bus.h>
70 #include <dev/ofw/ofw_bus_subr.h>
71
72 #include <dev/mii/mii.h>
73 #include <dev/mii/miivar.h>
74
75 #include <arm/allwinner/if_emacreg.h>
76 #include <arm/allwinner/aw_sid.h>
77
78 #include <dev/clk/clk.h>
79
80 #include "miibus_if.h"
81
82 #include "gpio_if.h"
83
84 #include "a10_sramc.h"
85
86 struct emac_softc {
87 if_t emac_ifp;
88 device_t emac_dev;
89 device_t emac_miibus;
90 bus_space_handle_t emac_handle;
91 bus_space_tag_t emac_tag;
92 struct resource *emac_res;
93 struct resource *emac_irq;
94 void *emac_intrhand;
95 clk_t emac_clk;
96 int emac_if_flags;
97 struct mtx emac_mtx;
98 struct callout emac_tick_ch;
99 int emac_watchdog_timer;
100 int emac_rx_process_limit;
101 int emac_link;
102 uint32_t emac_fifo_mask;
103 };
104
105 static int emac_probe(device_t);
106 static int emac_attach(device_t);
107 static int emac_detach(device_t);
108 static int emac_shutdown(device_t);
109 static int emac_suspend(device_t);
110 static int emac_resume(device_t);
111
112 static int emac_sys_setup(struct emac_softc *);
113 static void emac_reset(struct emac_softc *);
114
115 static void emac_init_locked(struct emac_softc *);
116 static void emac_start_locked(if_t);
117 static void emac_init(void *);
118 static void emac_stop_locked(struct emac_softc *);
119 static void emac_intr(void *);
120 static int emac_ioctl(if_t, u_long, caddr_t);
121
122 static void emac_rxeof(struct emac_softc *, int);
123 static void emac_txeof(struct emac_softc *, uint32_t);
124
125 static int emac_miibus_readreg(device_t, int, int);
126 static int emac_miibus_writereg(device_t, int, int, int);
127 static void emac_miibus_statchg(device_t);
128
129 static int emac_ifmedia_upd(if_t);
130 static void emac_ifmedia_sts(if_t, struct ifmediareq *);
131
132 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
133 static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS);
134
135 #define EMAC_READ_REG(sc, reg) \
136 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg)
137 #define EMAC_WRITE_REG(sc, reg, val) \
138 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val)
139
140 static int
emac_sys_setup(struct emac_softc * sc)141 emac_sys_setup(struct emac_softc *sc)
142 {
143 int error;
144
145 /* Activate EMAC clock. */
146 error = clk_get_by_ofw_index(sc->emac_dev, 0, 0, &sc->emac_clk);
147 if (error != 0) {
148 device_printf(sc->emac_dev, "cannot get clock\n");
149 return (error);
150 }
151 error = clk_enable(sc->emac_clk);
152 if (error != 0) {
153 device_printf(sc->emac_dev, "cannot enable clock\n");
154 return (error);
155 }
156
157 /* Map sram. */
158 a10_map_to_emac();
159
160 return (0);
161 }
162
163 static void
emac_get_hwaddr(struct emac_softc * sc,uint8_t * hwaddr)164 emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr)
165 {
166 uint32_t val0, val1, rnd;
167 u_char rootkey[16];
168 size_t rootkey_size;
169
170 /*
171 * Try to get MAC address from running hardware.
172 * If there is something non-zero there just use it.
173 *
174 * Otherwise set the address to a convenient locally assigned address,
175 * using the SID rootkey.
176 * This is was uboot does so we end up with the same mac as if uboot
177 * did set it.
178 * If we can't get the root key, generate a random one,
179 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
180 * assigned bit set, and the broadcast/multicast bit clear.
181 */
182 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0);
183 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1);
184 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) {
185 hwaddr[0] = (val1 >> 16) & 0xff;
186 hwaddr[1] = (val1 >> 8) & 0xff;
187 hwaddr[2] = (val1 >> 0) & 0xff;
188 hwaddr[3] = (val0 >> 16) & 0xff;
189 hwaddr[4] = (val0 >> 8) & 0xff;
190 hwaddr[5] = (val0 >> 0) & 0xff;
191 } else {
192 rootkey_size = sizeof(rootkey);
193 if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey,
194 &rootkey_size) == 0) {
195 hwaddr[0] = 0x2;
196 hwaddr[1] = rootkey[3];
197 hwaddr[2] = rootkey[12];
198 hwaddr[3] = rootkey[13];
199 hwaddr[4] = rootkey[14];
200 hwaddr[5] = rootkey[15];
201 }
202 else {
203 rnd = arc4random() & 0x00ffffff;
204 hwaddr[0] = 'b';
205 hwaddr[1] = 's';
206 hwaddr[2] = 'd';
207 hwaddr[3] = (rnd >> 16) & 0xff;
208 hwaddr[4] = (rnd >> 8) & 0xff;
209 hwaddr[5] = (rnd >> 0) & 0xff;
210 }
211 }
212 if (bootverbose)
213 printf("MAC address: %s\n", ether_sprintf(hwaddr));
214 }
215
216 static u_int
emac_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)217 emac_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
218 {
219 uint32_t h, *hashes = arg;
220
221 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
222 hashes[h >> 5] |= 1 << (h & 0x1f);
223
224 return (1);
225 }
226
227 static void
emac_set_rx_mode(struct emac_softc * sc)228 emac_set_rx_mode(struct emac_softc *sc)
229 {
230 if_t ifp;
231 uint32_t hashes[2];
232 uint32_t rcr = 0;
233
234 EMAC_ASSERT_LOCKED(sc);
235
236 ifp = sc->emac_ifp;
237
238 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL);
239
240 /* Unicast packet and DA filtering */
241 rcr |= EMAC_RX_UCAD;
242 rcr |= EMAC_RX_DAF;
243
244 hashes[0] = 0;
245 hashes[1] = 0;
246 if (if_getflags(ifp) & IFF_ALLMULTI) {
247 hashes[0] = 0xffffffff;
248 hashes[1] = 0xffffffff;
249 } else
250 if_foreach_llmaddr(ifp, emac_hash_maddr, hashes);
251 rcr |= EMAC_RX_MCO;
252 rcr |= EMAC_RX_MHF;
253 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]);
254 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]);
255
256 if (if_getflags(ifp) & IFF_BROADCAST) {
257 rcr |= EMAC_RX_BCO;
258 rcr |= EMAC_RX_MCO;
259 }
260
261 if (if_getflags(ifp) & IFF_PROMISC)
262 rcr |= EMAC_RX_PA;
263 else
264 rcr |= EMAC_RX_UCAD;
265
266 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr);
267 }
268
269 static void
emac_reset(struct emac_softc * sc)270 emac_reset(struct emac_softc *sc)
271 {
272
273 EMAC_WRITE_REG(sc, EMAC_CTL, 0);
274 DELAY(200);
275 EMAC_WRITE_REG(sc, EMAC_CTL, 1);
276 DELAY(200);
277 }
278
279 static void
emac_drain_rxfifo(struct emac_softc * sc)280 emac_drain_rxfifo(struct emac_softc *sc)
281 {
282
283 while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0)
284 (void)EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
285 }
286
287 static void
emac_txeof(struct emac_softc * sc,uint32_t status)288 emac_txeof(struct emac_softc *sc, uint32_t status)
289 {
290 if_t ifp;
291
292 EMAC_ASSERT_LOCKED(sc);
293
294 ifp = sc->emac_ifp;
295 status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1);
296 sc->emac_fifo_mask &= ~status;
297 if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
298 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2);
299 else
300 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
301 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
302
303 /* Unarm watchdog timer if no TX */
304 sc->emac_watchdog_timer = 0;
305 }
306
307 static void
emac_rxeof(struct emac_softc * sc,int count)308 emac_rxeof(struct emac_softc *sc, int count)
309 {
310 if_t ifp;
311 struct mbuf *m, *m0;
312 uint32_t reg_val, rxcount;
313 int16_t len;
314 uint16_t status;
315 int i;
316
317 ifp = sc->emac_ifp;
318 for (; count > 0 &&
319 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; count--) {
320 /*
321 * Race warning: The first packet might arrive with
322 * the interrupts disabled, but the second will fix
323 */
324 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC);
325 if (!rxcount) {
326 /* Had one stuck? */
327 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC);
328 if (!rxcount)
329 return;
330 }
331 /* Check packet header */
332 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
333 if (reg_val != EMAC_PACKET_HEADER) {
334 /* Packet header is wrong */
335 if (bootverbose)
336 if_printf(ifp, "wrong packet header\n");
337 /* Disable RX */
338 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
339 reg_val &= ~EMAC_CTL_RX_EN;
340 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
341
342 /* Flush RX FIFO */
343 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
344 reg_val |= EMAC_RX_FLUSH_FIFO;
345 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
346 for (i = 100; i > 0; i--) {
347 DELAY(100);
348 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) &
349 EMAC_RX_FLUSH_FIFO) == 0)
350 break;
351 }
352 if (i == 0) {
353 device_printf(sc->emac_dev,
354 "flush FIFO timeout\n");
355 /* Reinitialize controller */
356 emac_init_locked(sc);
357 return;
358 }
359 /* Enable RX */
360 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
361 reg_val |= EMAC_CTL_RX_EN;
362 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
363
364 return;
365 }
366
367 /* Get packet size and status */
368 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
369 len = reg_val & 0xffff;
370 status = (reg_val >> 16) & 0xffff;
371
372 if (len < 64 || (status & EMAC_PKT_OK) == 0) {
373 if (bootverbose)
374 if_printf(ifp,
375 "bad packet: len = %i status = %i\n",
376 len, status);
377 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
378 emac_drain_rxfifo(sc);
379 continue;
380 }
381 #if 0
382 if (status & (EMAC_CRCERR | EMAC_LENERR)) {
383 good_packet = 0;
384 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
385 if (status & EMAC_CRCERR)
386 if_printf(ifp, "crc error\n");
387 if (status & EMAC_LENERR)
388 if_printf(ifp, "length error\n");
389 }
390 #endif
391 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
392 if (m == NULL) {
393 emac_drain_rxfifo(sc);
394 return;
395 }
396 m->m_len = m->m_pkthdr.len = MCLBYTES;
397
398 /* Copy entire frame to mbuf first. */
399 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle,
400 EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4);
401
402 m->m_pkthdr.rcvif = ifp;
403 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN;
404
405 /*
406 * Emac controller needs strict alignment, so to avoid
407 * copying over an entire frame to align, we allocate
408 * a new mbuf and copy ethernet header + IP header to
409 * the new mbuf. The new mbuf is prepended into the
410 * existing mbuf chain.
411 */
412 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) {
413 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
414 m->m_data += ETHER_HDR_LEN;
415 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) &&
416 m->m_len > (MHLEN - ETHER_HDR_LEN)) {
417 MGETHDR(m0, M_NOWAIT, MT_DATA);
418 if (m0 != NULL) {
419 len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen;
420 bcopy(m->m_data, m0->m_data, len);
421 m->m_data += len;
422 m->m_len -= len;
423 m0->m_len = len;
424 M_MOVE_PKTHDR(m0, m);
425 m0->m_next = m;
426 m = m0;
427 } else {
428 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
429 m_freem(m);
430 m = NULL;
431 continue;
432 }
433 } else if (m->m_len > EMAC_MAC_MAXF) {
434 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
435 m_freem(m);
436 m = NULL;
437 continue;
438 }
439 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
440 EMAC_UNLOCK(sc);
441 if_input(ifp, m);
442 EMAC_LOCK(sc);
443 }
444 }
445
446 static void
emac_watchdog(struct emac_softc * sc)447 emac_watchdog(struct emac_softc *sc)
448 {
449 if_t ifp;
450
451 EMAC_ASSERT_LOCKED(sc);
452
453 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer)
454 return;
455
456 ifp = sc->emac_ifp;
457
458 if (sc->emac_link == 0) {
459 if (bootverbose)
460 if_printf(sc->emac_ifp, "watchdog timeout "
461 "(missed link)\n");
462 } else
463 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n");
464
465 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
466 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
467 emac_init_locked(sc);
468 if (!if_sendq_empty(ifp))
469 emac_start_locked(ifp);
470 }
471
472 static void
emac_tick(void * arg)473 emac_tick(void *arg)
474 {
475 struct emac_softc *sc;
476 struct mii_data *mii;
477
478 sc = (struct emac_softc *)arg;
479 mii = device_get_softc(sc->emac_miibus);
480 mii_tick(mii);
481
482 emac_watchdog(sc);
483 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
484 }
485
486 static void
emac_init(void * xcs)487 emac_init(void *xcs)
488 {
489 struct emac_softc *sc;
490
491 sc = (struct emac_softc *)xcs;
492 EMAC_LOCK(sc);
493 emac_init_locked(sc);
494 EMAC_UNLOCK(sc);
495 }
496
497 static void
emac_init_locked(struct emac_softc * sc)498 emac_init_locked(struct emac_softc *sc)
499 {
500 if_t ifp;
501 struct mii_data *mii;
502 uint32_t reg_val;
503 uint8_t *eaddr;
504
505 EMAC_ASSERT_LOCKED(sc);
506
507 ifp = sc->emac_ifp;
508 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
509 return;
510
511 /* Flush RX FIFO */
512 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
513 reg_val |= EMAC_RX_FLUSH_FIFO;
514 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
515 DELAY(1);
516
517 /* Soft reset MAC */
518 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
519 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST);
520 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
521
522 /* Set MII clock */
523 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG);
524 reg_val &= (~(0xf << 2));
525 reg_val |= (0xd << 2);
526 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val);
527
528 /* Clear RX counter */
529 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0);
530
531 /* Disable all interrupt and clear interrupt status */
532 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
533 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
534 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
535 DELAY(1);
536
537 /* Set up TX */
538 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE);
539 reg_val |= EMAC_TX_AB_M;
540 reg_val &= EMAC_TX_TM;
541 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val);
542
543 /* Set up RX */
544 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
545 reg_val |= EMAC_RX_SETUP;
546 reg_val &= EMAC_RX_TM;
547 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
548
549 /* Set up MAC CTL0. */
550 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
551 reg_val |= EMAC_MAC_CTL0_SETUP;
552 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
553
554 /* Set up MAC CTL1. */
555 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1);
556 reg_val |= EMAC_MAC_CTL1_SETUP;
557 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val);
558
559 /* Set up IPGT */
560 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD);
561
562 /* Set up IPGR */
563 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 |
564 (EMAC_MAC_NBTB_IPG1 << 8));
565
566 /* Set up Collison window */
567 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8));
568
569 /* Set up Max Frame Length */
570 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL);
571
572 /* Setup ethernet address */
573 eaddr = if_getlladdr(ifp);
574 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 |
575 eaddr[1] << 8 | eaddr[2]);
576 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 |
577 eaddr[4] << 8 | eaddr[5]);
578
579 /* Setup rx filter */
580 emac_set_rx_mode(sc);
581
582 /* Enable RX/TX0/RX Hlevel interrupt */
583 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
584 reg_val |= EMAC_INT_EN;
585 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
586
587 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
588 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
589
590 sc->emac_link = 0;
591
592 /* Switch to the current media. */
593 mii = device_get_softc(sc->emac_miibus);
594 mii_mediachg(mii);
595
596 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
597 }
598
599 static void
emac_start(if_t ifp)600 emac_start(if_t ifp)
601 {
602 struct emac_softc *sc;
603
604 sc = if_getsoftc(ifp);
605 EMAC_LOCK(sc);
606 emac_start_locked(ifp);
607 EMAC_UNLOCK(sc);
608 }
609
610 static void
emac_start_locked(if_t ifp)611 emac_start_locked(if_t ifp)
612 {
613 struct emac_softc *sc;
614 struct mbuf *m, *m0;
615 uint32_t fifo, reg;
616
617 sc = if_getsoftc(ifp);
618 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
619 return;
620 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
621 return;
622 if (sc->emac_link == 0)
623 return;
624 m = if_dequeue(ifp);
625 if (m == NULL)
626 return;
627
628 /* Select channel */
629 if (sc->emac_fifo_mask & EMAC_TX_FIFO0)
630 fifo = 1;
631 else
632 fifo = 0;
633 sc->emac_fifo_mask |= (1 << fifo);
634 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
635 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
636 EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo);
637
638 /*
639 * Emac controller wants 4 byte aligned TX buffers.
640 * We have to copy pretty much all the time.
641 */
642 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) {
643 m0 = m_defrag(m, M_NOWAIT);
644 if (m0 == NULL) {
645 m_freem(m);
646 m = NULL;
647 return;
648 }
649 m = m0;
650 }
651 /* Write data */
652 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle,
653 EMAC_TX_IO_DATA, mtod(m, uint32_t *),
654 roundup2(m->m_len, 4) / 4);
655
656 /* Send the data lengh. */
657 reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1;
658 EMAC_WRITE_REG(sc, reg, m->m_len);
659
660 /* Start translate from fifo to phy. */
661 reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1;
662 EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1);
663
664 /* Set timeout */
665 sc->emac_watchdog_timer = 5;
666
667 /* Data have been sent to hardware, it is okay to free the mbuf now. */
668 BPF_MTAP(ifp, m);
669 m_freem(m);
670 }
671
672 static void
emac_stop_locked(struct emac_softc * sc)673 emac_stop_locked(struct emac_softc *sc)
674 {
675 if_t ifp;
676 uint32_t reg_val;
677
678 EMAC_ASSERT_LOCKED(sc);
679
680 ifp = sc->emac_ifp;
681 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
682 sc->emac_link = 0;
683
684 /* Disable all interrupt and clear interrupt status */
685 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
686 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
687 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
688
689 /* Disable RX/TX */
690 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
691 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
692 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
693
694 callout_stop(&sc->emac_tick_ch);
695 }
696
697 static void
emac_intr(void * arg)698 emac_intr(void *arg)
699 {
700 struct emac_softc *sc;
701 if_t ifp;
702 uint32_t reg_val;
703
704 sc = (struct emac_softc *)arg;
705 EMAC_LOCK(sc);
706
707 /* Disable all interrupts */
708 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
709 /* Get EMAC interrupt status */
710 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
711 /* Clear ISR status */
712 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
713
714 /* Received incoming packet */
715 if (reg_val & EMAC_INT_STA_RX)
716 emac_rxeof(sc, sc->emac_rx_process_limit);
717
718 /* Transmit Interrupt check */
719 if (reg_val & EMAC_INT_STA_TX) {
720 emac_txeof(sc, reg_val);
721 ifp = sc->emac_ifp;
722 if (!if_sendq_empty(ifp))
723 emac_start_locked(ifp);
724 }
725
726 /* Re-enable interrupt mask */
727 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
728 reg_val |= EMAC_INT_EN;
729 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
730 EMAC_UNLOCK(sc);
731 }
732
733 static int
emac_ioctl(if_t ifp,u_long command,caddr_t data)734 emac_ioctl(if_t ifp, u_long command, caddr_t data)
735 {
736 struct emac_softc *sc;
737 struct mii_data *mii;
738 struct ifreq *ifr;
739 int error = 0;
740
741 sc = if_getsoftc(ifp);
742 ifr = (struct ifreq *)data;
743
744 switch (command) {
745 case SIOCSIFFLAGS:
746 EMAC_LOCK(sc);
747 if (if_getflags(ifp) & IFF_UP) {
748 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
749 if ((if_getflags(ifp) ^ sc->emac_if_flags) &
750 (IFF_PROMISC | IFF_ALLMULTI))
751 emac_set_rx_mode(sc);
752 } else
753 emac_init_locked(sc);
754 } else {
755 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
756 emac_stop_locked(sc);
757 }
758 sc->emac_if_flags = if_getflags(ifp);
759 EMAC_UNLOCK(sc);
760 break;
761 case SIOCADDMULTI:
762 case SIOCDELMULTI:
763 EMAC_LOCK(sc);
764 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
765 emac_set_rx_mode(sc);
766 }
767 EMAC_UNLOCK(sc);
768 break;
769 case SIOCGIFMEDIA:
770 case SIOCSIFMEDIA:
771 mii = device_get_softc(sc->emac_miibus);
772 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
773 break;
774 default:
775 error = ether_ioctl(ifp, command, data);
776 break;
777 }
778 return (error);
779 }
780
781 static int
emac_probe(device_t dev)782 emac_probe(device_t dev)
783 {
784
785 if (!ofw_bus_status_okay(dev))
786 return (ENXIO);
787
788 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-emac"))
789 return (ENXIO);
790
791 device_set_desc(dev, "A10/A20 EMAC ethernet controller");
792 return (BUS_PROBE_DEFAULT);
793 }
794
795 static int
emac_detach(device_t dev)796 emac_detach(device_t dev)
797 {
798 struct emac_softc *sc;
799
800 sc = device_get_softc(dev);
801 if_setdrvflagbits(sc->emac_ifp, 0, IFF_DRV_RUNNING);
802 if (device_is_attached(dev)) {
803 ether_ifdetach(sc->emac_ifp);
804 EMAC_LOCK(sc);
805 emac_stop_locked(sc);
806 EMAC_UNLOCK(sc);
807 callout_drain(&sc->emac_tick_ch);
808 }
809
810 if (sc->emac_intrhand != NULL)
811 bus_teardown_intr(sc->emac_dev, sc->emac_irq,
812 sc->emac_intrhand);
813
814 if (sc->emac_miibus != NULL) {
815 device_delete_child(sc->emac_dev, sc->emac_miibus);
816 bus_generic_detach(sc->emac_dev);
817 }
818
819 if (sc->emac_clk != NULL)
820 clk_disable(sc->emac_clk);
821
822 if (sc->emac_res != NULL)
823 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res);
824
825 if (sc->emac_irq != NULL)
826 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq);
827
828 if (sc->emac_ifp != NULL)
829 if_free(sc->emac_ifp);
830
831 if (mtx_initialized(&sc->emac_mtx))
832 mtx_destroy(&sc->emac_mtx);
833
834 return (0);
835 }
836
837 static int
emac_shutdown(device_t dev)838 emac_shutdown(device_t dev)
839 {
840
841 return (emac_suspend(dev));
842 }
843
844 static int
emac_suspend(device_t dev)845 emac_suspend(device_t dev)
846 {
847 struct emac_softc *sc;
848 if_t ifp;
849
850 sc = device_get_softc(dev);
851
852 EMAC_LOCK(sc);
853 ifp = sc->emac_ifp;
854 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
855 emac_stop_locked(sc);
856 EMAC_UNLOCK(sc);
857
858 return (0);
859 }
860
861 static int
emac_resume(device_t dev)862 emac_resume(device_t dev)
863 {
864 struct emac_softc *sc;
865 if_t ifp;
866
867 sc = device_get_softc(dev);
868
869 EMAC_LOCK(sc);
870 ifp = sc->emac_ifp;
871 if ((if_getflags(ifp) & IFF_UP) != 0) {
872 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
873 emac_init_locked(sc);
874 }
875 EMAC_UNLOCK(sc);
876
877 return (0);
878 }
879
880 static int
emac_attach(device_t dev)881 emac_attach(device_t dev)
882 {
883 struct emac_softc *sc;
884 if_t ifp;
885 int error, rid;
886 uint8_t eaddr[ETHER_ADDR_LEN];
887
888 sc = device_get_softc(dev);
889 sc->emac_dev = dev;
890
891 error = 0;
892 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
893 MTX_DEF);
894 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0);
895
896 rid = 0;
897 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
898 RF_ACTIVE);
899 if (sc->emac_res == NULL) {
900 device_printf(dev, "unable to map memory\n");
901 error = ENXIO;
902 goto fail;
903 }
904
905 sc->emac_tag = rman_get_bustag(sc->emac_res);
906 sc->emac_handle = rman_get_bushandle(sc->emac_res);
907
908 rid = 0;
909 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
910 RF_SHAREABLE | RF_ACTIVE);
911 if (sc->emac_irq == NULL) {
912 device_printf(dev, "cannot allocate IRQ resources.\n");
913 error = ENXIO;
914 goto fail;
915 }
916 /* Create device sysctl node. */
917 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
918 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
919 OID_AUTO, "process_limit",
920 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
921 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I",
922 "max number of Rx events to process");
923
924 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT;
925 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
926 "process_limit", &sc->emac_rx_process_limit);
927 if (error == 0) {
928 if (sc->emac_rx_process_limit < EMAC_PROC_MIN ||
929 sc->emac_rx_process_limit > EMAC_PROC_MAX) {
930 device_printf(dev, "process_limit value out of range; "
931 "using default: %d\n", EMAC_PROC_DEFAULT);
932 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT;
933 }
934 }
935 /* Setup EMAC */
936 error = emac_sys_setup(sc);
937 if (error != 0)
938 goto fail;
939
940 emac_reset(sc);
941
942 ifp = sc->emac_ifp = if_alloc(IFT_ETHER);
943 if_setsoftc(ifp, sc);
944
945 /* Setup MII */
946 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd,
947 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
948 if (error != 0) {
949 device_printf(dev, "PHY probe failed\n");
950 goto fail;
951 }
952
953 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
954 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
955 if_setstartfn(ifp, emac_start);
956 if_setioctlfn(ifp, emac_ioctl);
957 if_setinitfn(ifp, emac_init);
958 if_setsendqlen(ifp, IFQ_MAXLEN);
959
960 /* Get MAC address */
961 emac_get_hwaddr(sc, eaddr);
962 ether_ifattach(ifp, eaddr);
963
964 /* VLAN capability setup. */
965 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
966 if_setcapenable(ifp, if_getcapabilities(ifp));
967 /* Tell the upper layer we support VLAN over-sized frames. */
968 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
969
970 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE,
971 NULL, emac_intr, sc, &sc->emac_intrhand);
972 if (error != 0) {
973 device_printf(dev, "could not set up interrupt handler.\n");
974 ether_ifdetach(ifp);
975 goto fail;
976 }
977
978 fail:
979 if (error != 0)
980 emac_detach(dev);
981 return (error);
982 }
983
984 static bool
emac_miibus_iowait(struct emac_softc * sc)985 emac_miibus_iowait(struct emac_softc *sc)
986 {
987 uint32_t timeout;
988
989 for (timeout = 100; timeout != 0; --timeout) {
990 DELAY(100);
991 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0)
992 return (true);
993 }
994
995 return (false);
996 }
997
998 /*
999 * The MII bus interface
1000 */
1001 static int
emac_miibus_readreg(device_t dev,int phy,int reg)1002 emac_miibus_readreg(device_t dev, int phy, int reg)
1003 {
1004 struct emac_softc *sc;
1005 int rval;
1006
1007 sc = device_get_softc(dev);
1008
1009 /* Issue phy address and reg */
1010 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1011 /* Pull up the phy io line */
1012 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
1013 if (!emac_miibus_iowait(sc)) {
1014 device_printf(dev, "timeout waiting for mii read\n");
1015 return (0);
1016 }
1017 /* Push down the phy io line */
1018 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
1019 /* Read data */
1020 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD);
1021
1022 return (rval);
1023 }
1024
1025 static int
emac_miibus_writereg(device_t dev,int phy,int reg,int data)1026 emac_miibus_writereg(device_t dev, int phy, int reg, int data)
1027 {
1028 struct emac_softc *sc;
1029
1030 sc = device_get_softc(dev);
1031
1032 /* Issue phy address and reg */
1033 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1034 /* Write data */
1035 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data);
1036 /* Pull up the phy io line */
1037 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
1038 if (!emac_miibus_iowait(sc)) {
1039 device_printf(dev, "timeout waiting for mii write\n");
1040 return (0);
1041 }
1042 /* Push down the phy io line */
1043 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
1044
1045 return (0);
1046 }
1047
1048 static void
emac_miibus_statchg(device_t dev)1049 emac_miibus_statchg(device_t dev)
1050 {
1051 struct emac_softc *sc;
1052 struct mii_data *mii;
1053 if_t ifp;
1054 uint32_t reg_val;
1055
1056 sc = device_get_softc(dev);
1057
1058 mii = device_get_softc(sc->emac_miibus);
1059 ifp = sc->emac_ifp;
1060 if (mii == NULL || ifp == NULL ||
1061 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1062 return;
1063
1064 sc->emac_link = 0;
1065 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1066 (IFM_ACTIVE | IFM_AVALID)) {
1067 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1068 case IFM_10_T:
1069 case IFM_100_TX:
1070 sc->emac_link = 1;
1071 break;
1072 default:
1073 break;
1074 }
1075 }
1076 /* Program MACs with resolved speed/duplex. */
1077 if (sc->emac_link != 0) {
1078 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT);
1079 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1080 reg_val &= ~EMAC_MAC_IPGT_HD;
1081 reg_val |= EMAC_MAC_IPGT_FD;
1082 } else {
1083 reg_val &= ~EMAC_MAC_IPGT_FD;
1084 reg_val |= EMAC_MAC_IPGT_HD;
1085 }
1086 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val);
1087 /* Enable RX/TX */
1088 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
1089 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN;
1090 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
1091 } else {
1092 /* Disable RX/TX */
1093 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
1094 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
1095 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
1096 }
1097 }
1098
1099 static int
emac_ifmedia_upd(if_t ifp)1100 emac_ifmedia_upd(if_t ifp)
1101 {
1102 struct emac_softc *sc;
1103 struct mii_data *mii;
1104 struct mii_softc *miisc;
1105 int error;
1106
1107 sc = if_getsoftc(ifp);
1108 mii = device_get_softc(sc->emac_miibus);
1109 EMAC_LOCK(sc);
1110 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1111 PHY_RESET(miisc);
1112 error = mii_mediachg(mii);
1113 EMAC_UNLOCK(sc);
1114
1115 return (error);
1116 }
1117
1118 static void
emac_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1119 emac_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1120 {
1121 struct emac_softc *sc;
1122 struct mii_data *mii;
1123
1124 sc = if_getsoftc(ifp);
1125 mii = device_get_softc(sc->emac_miibus);
1126
1127 EMAC_LOCK(sc);
1128 mii_pollstat(mii);
1129 ifmr->ifm_active = mii->mii_media_active;
1130 ifmr->ifm_status = mii->mii_media_status;
1131 EMAC_UNLOCK(sc);
1132 }
1133
1134 static device_method_t emac_methods[] = {
1135 /* Device interface */
1136 DEVMETHOD(device_probe, emac_probe),
1137 DEVMETHOD(device_attach, emac_attach),
1138 DEVMETHOD(device_detach, emac_detach),
1139 DEVMETHOD(device_shutdown, emac_shutdown),
1140 DEVMETHOD(device_suspend, emac_suspend),
1141 DEVMETHOD(device_resume, emac_resume),
1142
1143 /* bus interface, for miibus */
1144 DEVMETHOD(bus_print_child, bus_generic_print_child),
1145 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1146
1147 /* MII interface */
1148 DEVMETHOD(miibus_readreg, emac_miibus_readreg),
1149 DEVMETHOD(miibus_writereg, emac_miibus_writereg),
1150 DEVMETHOD(miibus_statchg, emac_miibus_statchg),
1151
1152 DEVMETHOD_END
1153 };
1154
1155 static driver_t emac_driver = {
1156 "emac",
1157 emac_methods,
1158 sizeof(struct emac_softc)
1159 };
1160
1161 DRIVER_MODULE(emac, simplebus, emac_driver, 0, 0);
1162 DRIVER_MODULE(miibus, emac, miibus_driver, 0, 0);
1163 MODULE_DEPEND(emac, miibus, 1, 1, 1);
1164 MODULE_DEPEND(emac, ether, 1, 1, 1);
1165
1166 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)1167 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
1168 {
1169 int error, value;
1170
1171 if (arg1 == NULL)
1172 return (EINVAL);
1173 value = *(int *)arg1;
1174 error = sysctl_handle_int(oidp, &value, 0, req);
1175 if (error || req->newptr == NULL)
1176 return (error);
1177 if (value < low || value > high)
1178 return (EINVAL);
1179 *(int *)arg1 = value;
1180
1181 return (0);
1182 }
1183
1184 static int
sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS)1185 sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS)
1186 {
1187
1188 return (sysctl_int_range(oidp, arg1, arg2, req,
1189 EMAC_PROC_MIN, EMAC_PROC_MAX));
1190 }
1191