1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2010 Google, Inc. 4 */ 5 6 #ifndef __TEGRA_USB_PHY_H 7 #define __TEGRA_USB_PHY_H 8 9 #include <linux/clk.h> 10 #include <linux/regmap.h> 11 #include <linux/reset.h> 12 #include <linux/usb/otg.h> 13 14 struct gpio_desc; 15 16 /* 17 * utmi_pll_config_in_car_module: true if the UTMI PLL configuration registers 18 * should be set up by clk-tegra, false if by the PHY code 19 * has_hostpc: true if the USB controller has the HOSTPC extension, which 20 * changes the location of the PHCD and PTS fields 21 * requires_usbmode_setup: true if the USBMODE register needs to be set to 22 * enter host mode 23 * requires_extra_tuning_parameters: true if xcvr_hsslew, hssquelch_level 24 * and hsdiscon_level should be set for adequate signal quality 25 * requires_pmc_ao_power_up: true if USB AO is powered down by default 26 * uhsic_registers_offset: for Tegra30+ where HSIC registers were offset 27 * comparing to Tegra20 by 0x400, since Tegra20 has no UTMIP on PHY2 28 * uhsic_tx_rtune: fine tuned 50 Ohm termination resistor for NMOS/PMOS driver 29 * uhsic_pts_value: parallel transceiver select enumeration value 30 * portsc1_offset: register offset of PORTSC1 31 */ 32 33 struct tegra_phy_soc_config { 34 bool utmi_pll_config_in_car_module; 35 bool has_hostpc; 36 bool requires_usbmode_setup; 37 bool requires_extra_tuning_parameters; 38 bool requires_pmc_ao_power_up; 39 u32 uhsic_registers_offset; 40 u32 uhsic_tx_rtune; 41 u32 uhsic_pts_value; 42 u32 portsc1_offset; 43 }; 44 45 struct tegra_utmip_config { 46 u8 hssync_start_delay; 47 u8 elastic_limit; 48 u8 idle_wait_delay; 49 u8 term_range_adj; 50 bool xcvr_setup_use_fuses; 51 u8 xcvr_setup; 52 u8 xcvr_lsfslew; 53 u8 xcvr_lsrslew; 54 u8 xcvr_hsslew; 55 u8 hssquelch_level; 56 u8 hsdiscon_level; 57 }; 58 59 enum tegra_usb_phy_port_speed { 60 TEGRA_USB_PHY_PORT_SPEED_FULL = 0, 61 TEGRA_USB_PHY_PORT_SPEED_LOW, 62 TEGRA_USB_PHY_PORT_SPEED_HIGH, 63 }; 64 65 struct tegra_xtal_freq; 66 67 struct tegra_usb_phy { 68 int irq; 69 int instance; 70 const struct tegra_xtal_freq *freq; 71 void __iomem *regs; 72 void __iomem *pad_regs; 73 struct clk *clk; 74 struct clk *pll_u; 75 struct clk *pad_clk; 76 struct regulator *vbus; 77 struct regmap *pmc_regmap; 78 enum usb_dr_mode mode; 79 void *config; 80 const struct tegra_phy_soc_config *soc_config; 81 struct usb_phy *ulpi; 82 struct usb_phy u_phy; 83 bool is_legacy_phy; 84 enum usb_phy_interface phy_type; 85 struct gpio_desc *reset_gpio; 86 struct reset_control *pad_rst; 87 bool wakeup_enabled; 88 bool pad_wakeup; 89 bool powered_on; 90 }; 91 92 #endif /* __TEGRA_USB_PHY_H */ 93