1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 #ifndef _SYS_USB_EHCID_H 26 #define _SYS_USB_EHCID_H 27 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * Enchanced Host Controller Driver (EHCI) 35 * 36 * The EHCI driver is a software driver which interfaces to the Universal 37 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 38 * the Host Controller is defined by the EHCI Host Controller Interface. 39 * 40 * This header file describes the data structures and function prototypes 41 * required for the EHCI Driver to maintain state of Host Controller (HC), 42 * to perform different USB transfers and for the bandwidth allocations. 43 */ 44 45 #include <sys/usb/hcd/ehci/ehci.h> 46 #include <sys/usb/hcd/ehci/ehci_hub.h> 47 48 49 /* 50 * EHCI Bandwidth Maintainence Structure. 51 * 52 * The ehci_bandwidth array keeps track of allocated bandwidth for ehci 53 * host controller. There are 32 bandwidth lists corresponding to 32 ms 54 * periodic frame lists. Each bandwidth list inturn will contain eight 55 * micro frame bandwidth lists. 56 */ 57 #define EHCI_MAX_UFRAMES 8 /* Max uframes 125us per frame */ 58 59 typedef struct ehci_frame_bandwidth { 60 uint_t ehci_allocated_frame_bandwidth; 61 uint_t ehci_micro_frame_bandwidth[EHCI_MAX_UFRAMES]; 62 } ehci_frame_bandwidth_t; 63 64 65 /* 66 * EHCI Host Controller state structure 67 * 68 * The Host Controller Driver (HCD) maintains the state of Host Controller 69 * (HC). There is an ehci_state structure per instance of the EHCI 70 * host controller. 71 */ 72 typedef struct ehci_state { 73 dev_info_t *ehci_dip; /* Dip of HC */ 74 uint_t ehci_instance; 75 usba_hcdi_ops_t *ehci_hcdi_ops; /* HCDI structure */ 76 uint_t ehci_flags; /* Used for cleanup */ 77 uint16_t ehci_vendor_id; /* chip vendor */ 78 uint16_t ehci_device_id; /* chip device */ 79 uint8_t ehci_rev_id; /* chip revison */ 80 81 ddi_acc_handle_t ehci_caps_handle; /* Caps Reg Handle */ 82 ehci_caps_t *ehci_capsp; /* Capability Regs */ 83 ehci_regs_t *ehci_regsp; /* Operational Regs */ 84 85 ddi_acc_handle_t ehci_config_handle; /* Config space hndle */ 86 uint_t ehci_frame_interval; /* Frme inter reg */ 87 ddi_dma_attr_t ehci_dma_attr; /* DMA attributes */ 88 89 ddi_intr_handle_t *ehci_htable; /* intr handle */ 90 int ehci_intr_type; /* intr type used */ 91 int ehci_intr_cnt; /* # of intrs inuse */ 92 uint_t ehci_intr_pri; /* intr priority */ 93 int ehci_intr_cap; /* intr capabilities */ 94 boolean_t ehci_msi_enabled; /* default to true */ 95 kmutex_t ehci_int_mutex; /* Global EHCI mutex */ 96 97 /* Periodic Frame List area */ 98 ehci_periodic_frame_list_t *ehci_periodic_frame_list_tablep; 99 /* Virtual Periodic Frame List ptr */ 100 ddi_dma_cookie_t ehci_pflt_cookie; /* DMA cookie */ 101 ddi_dma_handle_t ehci_pflt_dma_handle; /* DMA handle */ 102 ddi_acc_handle_t ehci_pflt_mem_handle; /* Memory handle */ 103 104 /* 105 * There are two pools of memory. One pool contains the memory for 106 * the transfer descriptors and other pool contains the memory for 107 * the endpoint descriptors. The advantage of the pools is that it's 108 * easy to go back and forth between the iommu and the cpu addresses. 109 * 110 * The pools are protected by the ehci_int_mutex because the memory 111 * in the pools may be accessed by either the host controller or the 112 * host controller driver. 113 */ 114 115 /* Endpoint descriptor pool */ 116 ehci_qh_t *ehci_qh_pool_addr; /* Start of the pool */ 117 ddi_dma_cookie_t ehci_qh_pool_cookie; /* DMA cookie */ 118 ddi_dma_handle_t ehci_qh_pool_dma_handle; /* DMA handle */ 119 ddi_acc_handle_t ehci_qh_pool_mem_handle; /* Mem handle */ 120 uint_t ehci_dma_addr_bind_flag; /* DMA flag */ 121 122 /* General transfer descriptor pool */ 123 ehci_qtd_t *ehci_qtd_pool_addr; /* Start of the pool */ 124 ddi_dma_cookie_t ehci_qtd_pool_cookie; /* DMA cookie */ 125 ddi_dma_handle_t ehci_qtd_pool_dma_handle; /* DMA hndle */ 126 ddi_acc_handle_t ehci_qtd_pool_mem_handle; /* Mem hndle */ 127 128 /* Isochronous transfer descriptor pool */ 129 ehci_itd_t *ehci_itd_pool_addr; /* Start of the pool */ 130 ddi_dma_cookie_t ehci_itd_pool_cookie; /* DMA cookie */ 131 ddi_dma_handle_t ehci_itd_pool_dma_handle; /* DMA hndle */ 132 ddi_acc_handle_t ehci_itd_pool_mem_handle; /* Mem hndle */ 133 134 /* Condition variable for advance on Asynchronous Schedule */ 135 kcondvar_t ehci_async_schedule_advance_cv; 136 137 /* Head of Asynchronous Schedule List */ 138 ehci_qh_t *ehci_head_of_async_sched_list; 139 140 /* 141 * List of QTD inserted either into Asynchronous or Periodic 142 * Schedule lists. 143 */ 144 ehci_qtd_t *ehci_active_qtd_list; 145 /* 146 * List of ITD active itd list. 147 */ 148 ehci_itd_t *ehci_active_itd_list; 149 150 /* 151 * Bandwidth fields 152 * 153 * The ehci_bandwidth array keeps track of allocated bandwidth for 154 * ehci host controller. There are 32 bandwidth lists corresponding 155 * to 32 ms periodic frame lists. Each bandwidth list in turn will 156 * contain eight micro frame bandwidth lists. 157 * 158 * ehci_min_frame_bandwidth field indicates least allocated milli 159 * second bandwidth list. 160 */ 161 ehci_frame_bandwidth_t ehci_frame_bandwidth[EHCI_NUM_INTR_QH_LISTS]; 162 163 /* No. of open pipes, async qh, and periodic qh */ 164 uint_t ehci_open_pipe_count; 165 uint_t ehci_open_async_count; 166 uint_t ehci_open_periodic_count; 167 168 /* No. of async and periodic requests */ 169 uint_t ehci_async_req_count; 170 uint_t ehci_periodic_req_count; 171 172 /* 173 * Endpoint Reclamation List 174 * 175 * The interrupt list processing cannot be stopped when a periodic 176 * endpoint is removed from the list. The endpoints are detached 177 * from the interrupt lattice tree and put on to the reclaimation 178 * list. On next SOF interrupt all those endpoints, which are on 179 * the reclaimation list will be deallocated. 180 */ 181 ehci_qh_t *ehci_reclaim_list; /* Reclaimation list */ 182 183 ehci_root_hub_t ehci_root_hub; /* Root hub info */ 184 185 /* Frame number overflow information */ 186 usb_frame_number_t ehci_fno; 187 188 /* For host controller error counter */ 189 uint_t ehci_hc_error; 190 191 /* 192 * ehci_missed_intr_sts is used to save the normal mode interrupt 193 * status information if an interrupt is pending for normal mode 194 * when polled code is entered. 195 */ 196 uint_t ehci_missed_intr_sts; 197 198 /* 199 * Saved copy of the ehci registers of the normal mode & change 200 * required ehci registers values for the polled mode operation. 201 * Before returning from the polled mode to normal mode replace 202 * the required current registers with this saved ehci registers 203 * copy. 204 */ 205 ehci_regs_t ehci_polled_save_regs; 206 207 /* 208 * Saved copy of the interrupt table used in normal ehci mode and 209 * replace this table by another interrupt table that used in the 210 * POLLED mode. 211 */ 212 ehci_qh_t *ehci_polled_frame_list_table[EHCI_NUM_PERIODIC_FRAME_LISTS]; 213 214 /* ehci polled mode enter counter */ 215 uint_t ehci_polled_enter_count; 216 217 /* 218 * counter for polled mode and used in suspend mode to see if 219 * there is a keyboard connected. 220 */ 221 uint_t ehci_polled_kbd_count; 222 223 /* counter for polled read and use it to clean the interrupt status */ 224 uint_t ehci_polled_read_count; 225 226 #if defined(__x86) 227 /* counter for polled root hub status */ 228 uint_t ehci_polled_root_hub_count; 229 #endif /* __x86 */ 230 231 /* EHCI Host Controller Software State information */ 232 uint_t ehci_hc_soft_state; 233 234 /* Log handle for debug, console, log messages */ 235 usb_log_handle_t ehci_log_hdl; 236 237 /* Kstat structures */ 238 kstat_t *ehci_intrs_stats; 239 kstat_t *ehci_total_stats; 240 kstat_t *ehci_count_stats[USB_N_COUNT_KSTATS]; 241 } ehci_state_t; 242 243 typedef struct ehci_intrs_stats { 244 struct kstat_named ehci_sts_async_sched_status; 245 struct kstat_named ehci_sts_periodic_sched_status; 246 struct kstat_named ehci_sts_empty_async_schedule; 247 struct kstat_named ehci_sts_host_ctrl_halted; 248 struct kstat_named ehci_sts_async_advance_intr; 249 struct kstat_named ehci_sts_host_system_error_intr; 250 struct kstat_named ehci_sts_frm_list_rollover_intr; 251 struct kstat_named ehci_sts_rh_port_change_intr; 252 struct kstat_named ehci_sts_usb_error_intr; 253 struct kstat_named ehci_sts_usb_intr; 254 struct kstat_named ehci_sts_not_claimed; 255 struct kstat_named ehci_sts_total; 256 } ehci_intrs_stats_t; 257 258 /* 259 * ehci kstat defines 260 */ 261 #define EHCI_INTRS_STATS(ehci) ((ehci)->ehci_intrs_stats) 262 #define EHCI_INTRS_STATS_DATA(ehci) \ 263 ((ehci_intrs_stats_t *)EHCI_INTRS_STATS((ehci))->ks_data) 264 265 #define EHCI_TOTAL_STATS(ehci) ((ehci)->ehci_total_stats) 266 #define EHCI_TOTAL_STATS_DATA(ehci) (KSTAT_IO_PTR((ehci)->ehci_total_stats)) 267 #define EHCI_CTRL_STATS(ehci) \ 268 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_CONTROL])) 269 #define EHCI_BULK_STATS(ehci) \ 270 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_BULK])) 271 #define EHCI_INTR_STATS(ehci) \ 272 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_INTR])) 273 #define EHCI_ISOC_STATS(ehci) \ 274 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_ISOCH])) 275 276 /* warlock directives, stable data */ 277 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_state_t)) 278 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_intr_pri)) 279 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dip)) 280 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_regsp)) 281 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_instance)) 282 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_vendor_id)) 283 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_device_id)) 284 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_rev_id)) 285 286 /* this may not be stable data in the future */ 287 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_addr)) 288 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_mem_handle)) 289 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_cookie)) 290 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_addr)) 291 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_mem_handle)) 292 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_cookie)) 293 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_addr)) 294 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_mem_handle)) 295 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_cookie)) 296 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dma_addr_bind_flag)) 297 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_log_hdl)) 298 299 _NOTE(LOCK_ORDER(ehci_state::ehci_int_mutex \ 300 usba_pipe_handle_data::p_mutex \ 301 usba_device::usb_mutex \ 302 usba_ph_impl::usba_ph_mutex)) 303 304 /* 305 * Host Contoller Software States 306 * 307 * EHCI_CTLR_INIT_STATE: 308 * The host controller soft state will be set to this during the 309 * ehci_attach. 310 * 311 * EHCI_CTLR_SUSPEND_STATE: 312 * The host controller soft state will be set to this during the 313 * ehci_cpr_suspend. 314 * 315 * EHCI_CTLR_OPERATIONAL_STATE: 316 * The host controller soft state will be set to this after moving 317 * host controller to operational state and host controller start 318 * generating SOF successfully. 319 * 320 * EHCI_CTLR_ERROR_STATE: 321 * The host controller soft state will be set to this during the 322 * no SOF or UE error conditions. 323 * 324 * Under this state or condition, only pipe stop polling, pipe reset 325 * and pipe close are allowed. But all other entry points like pipe 326 * open, get/set pipe policy, cotrol send/receive, bulk send/receive 327 * isoch send/receive, start polling etc. will fail. 328 * 329 * State Diagram for the host controller software state 330 * 331 * 332 * ehci_attach->[INIT_STATE] 333 * | 334 * | -------->----[ERROR_STATE]--<-----------<--- 335 * | | Failure (UE/no SOF condition) | 336 * | ^ ^ 337 * V | Success | 338 * ehci_init_ctlr--->--------[OPERATIONAL_STATE]------>-ehci_send/recv/polling 339 * ^ | 340 * | | 341 * | V 342 * -<-ehci_cpr_resume--[SUSPEND_STATE]-<-ehci_cpr_suspend 343 */ 344 #define EHCI_CTLR_INIT_STATE 0 /* Initilization state */ 345 #define EHCI_CTLR_SUSPEND_STATE 1 /* Suspend state */ 346 #define EHCI_CTLR_OPERATIONAL_STATE 2 /* Operational state */ 347 #define EHCI_CTLR_ERROR_STATE 3 /* Ue error or no sof state */ 348 349 /* 350 * Flags for initializatoin of host controller 351 */ 352 #define EHCI_NORMAL_INITIALIZATION 0 /* Normal initialization */ 353 #define EHCI_REINITIALIZATION 1 /* Re-initialization */ 354 355 /* 356 * Periodic and non-periodic macros 357 */ 358 #define EHCI_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 359 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\ 360 ((endpoint->bmAttributes &\ 361 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 362 363 #define EHCI_NON_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 364 USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\ 365 ((endpoint->bmAttributes &\ 366 USB_EP_ATTR_MASK) == USB_EP_ATTR_BULK)) 367 368 #define EHCI_ISOC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 369 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 370 371 #define EHCI_INTR_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 372 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR)) 373 374 375 /* 376 * EHCI QH and QTD Pool sizes. 377 */ 378 #define EHCI_QH_POOL_SIZE 1000 379 #define EHCI_QTD_POOL_SIZE 200 380 #define EHCI_ITD_POOL_SIZE 200 381 382 /* 383 * ehci_dma_addr_bind_flag values 384 * 385 * This flag indicates if the various DMA addresses allocated by the EHCI 386 * have been bound to their respective handles. This is needed to recover 387 * without errors from ehci_cleanup when it calls ddi_dma_unbind_handle() 388 */ 389 #define EHCI_QTD_POOL_BOUND 0x01 /* For QTD pools */ 390 #define EHCI_QH_POOL_BOUND 0x02 /* For QH pools */ 391 #define EHCI_PFLT_DMA_BOUND 0x04 /* For Periodic Frame List area */ 392 #define EHCI_ITD_POOL_BOUND 0x08 /* For QTD pools */ 393 394 /* 395 * Maximum SOF wait count 396 */ 397 #define MAX_SOF_WAIT_COUNT 2 /* Wait for maximum SOF frames */ 398 399 /* 400 * One uFrame 125 micro seconds 401 * One Frame 1 milli second or 8 uFrames 402 */ 403 #define EHCI_uFRAMES_PER_USB_FRAME 8 404 #define EHCI_uFRAMES_PER_USB_FRAME_SHIFT 3 405 406 407 /* 408 * Pipe private structure 409 * 410 * There is an instance of this structure per pipe. This structure holds 411 * HCD specific pipe information. A pointer to this structure is kept in 412 * the USBA pipe handle (usba_pipe_handle_data_t). 413 */ 414 typedef struct ehci_pipe_private { 415 usba_pipe_handle_data_t *pp_pipe_handle; /* Back ptr to handle */ 416 ehci_qh_t *pp_qh; /* Pipe's qh */ 417 418 /* State of the pipe */ 419 uint_t pp_state; /* See below */ 420 421 /* Local copy of the pipe policy */ 422 usb_pipe_policy_t pp_policy; 423 424 /* For Periodic Pipes Only */ 425 uint_t pp_pnode; /* periodic node */ 426 uchar_t pp_smask; /* Start split mask */ 427 uchar_t pp_cmask; /* Comp split mask */ 428 uint_t pp_cur_periodic_req_cnt; /* Curr req count */ 429 uint_t pp_max_periodic_req_cnt; /* Max req count */ 430 431 /* For Isochronous pipes only */ 432 usb_frame_number_t pp_next_frame_number; /* Next frame no */ 433 434 /* 435 * Each pipe may have multiple transfer wrappers. Each transfer 436 * wrapper represents a USB transfer on the bus. A transfer is 437 * made up of one or more transactions. 438 */ 439 struct ehci_trans_wrapper *pp_tw_head; /* Head of the list */ 440 struct ehci_trans_wrapper *pp_tw_tail; /* Tail of the list */ 441 442 struct ehci_isoc_xwrapper *pp_itw_head; /* Head of the list */ 443 struct ehci_isoc_xwrapper *pp_itw_tail; /* Tail of the list */ 444 445 /* 446 * Pipe's transfer timeout handling & this transfer timeout handling 447 * will be per pipe. 448 */ 449 struct ehci_trans_wrapper *pp_timeout_list; /* Timeout list */ 450 timeout_id_t pp_timer_id; /* Timer id */ 451 452 /* Done td count */ 453 uint_t pp_count_done_qtds; /* Done td count */ 454 455 /* Errors */ 456 usb_cr_t pp_error; /* Pipe error */ 457 458 /* Condition variable for transfers completion event */ 459 kcondvar_t pp_xfer_cmpl_cv; /* Xfer completion */ 460 461 /* Pipe flag */ 462 uint_t pp_flag; /* For polled mode */ 463 464 /* Halting States */ 465 uint_t pp_halt_state; /* Is it halting */ 466 467 /* Condition variable for halt completion event */ 468 kcondvar_t pp_halt_cmpl_cv; /* Xfer completion */ 469 470 /* 471 * HCD gets Interrupt/Isochronous IN polling request only once and 472 * it has to insert next polling requests after completion of first 473 * request until either stop polling/pipe close is called. So HCD 474 * has to take copy of the original Interrupt/Isochronous IN request. 475 */ 476 usb_opaque_t pp_client_periodic_in_reqp; 477 } ehci_pipe_private_t; 478 479 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_pipe_private_t)) 480 481 /* 482 * Pipe states 483 * 484 * ehci pipe states will be similar to usba. Refer usbai.h. 485 */ 486 #define EHCI_PIPE_STATE_IDLE 1 /* Pipe is in ready state */ 487 #define EHCI_PIPE_STATE_ACTIVE 2 /* Pipe is in busy state */ 488 #define EHCI_PIPE_STATE_ERROR 3 /* Pipe is in error state */ 489 490 /* Additional ehci pipe states for the ehci_pipe_cleanup */ 491 #define EHCI_PIPE_STATE_CLOSE 4 /* Pipe close */ 492 #define EHCI_PIPE_STATE_RESET 5 /* Pipe reset */ 493 #define EHCI_PIPE_STATE_STOP_POLLING 6 /* Pipe stop polling */ 494 495 /* 496 * Pipe flag 497 * 498 * Interrupt or polled mode. 499 */ 500 #define EHCI_INTERRUPT_MODE_FLAG 0 /* Interrupt mode flag */ 501 #define EHCI_POLLED_MODE_FLAG 1 /* Polled mode flag */ 502 503 /* Pipe specific flags */ 504 #define EHCI_ISOC_XFER_CONTINUE 1 /* For isoc transfers */ 505 506 /* 507 * Halting States 508 * prevent halting from interleaving. 509 */ 510 #define EHCI_HALT_STATE_FREE 0 /* Pipe free to accept reqs */ 511 #define EHCI_HALT_STATE_HALTING 1 /* Currently Halting */ 512 513 /* 514 * Request values for Clear_TT_Buffer 515 */ 516 #define EHCI_CLEAR_TT_BUFFER_REQTYPE (USB_DEV_REQ_TYPE_CLASS | \ 517 USB_DEV_REQ_RCPT_OTHER) 518 #define EHCI_CLEAR_TT_BUFFER_BREQ 8 519 520 /* 521 * USB frame offset 522 * 523 * Add appropriate frame offset to the current usb frame number and use it 524 * as a starting frame number for a given usb isochronous request. 525 */ 526 #define EHCI_FRAME_OFFSET 2 /* Frame offset */ 527 528 /* 529 * Different interrupt polling intervals supported for high speed 530 * devices and its range must be from 1 to 16 units. This value is 531 * used as th exponent for a 2 ^ (bInterval - 1). Ex: a Binterval 532 * of 4 means a period of 8us (2 ^ (4-1)). 533 * 534 * The following values are defined after above convertion in terms 535 * 125us units. 536 */ 537 #define EHCI_INTR_1US_POLL 1 /* 1us poll interval */ 538 #define EHCI_INTR_2US_POLL 2 /* 2us poll interval */ 539 #define EHCI_INTR_4US_POLL 4 /* 4us poll interval */ 540 #define EHCI_INTR_XUS_POLL 8 /* 8us and above */ 541 542 /* 543 * The following indecies are are used to calculate Start and complete 544 * masks as per the polling interval. 545 */ 546 #define EHCI_1US_MASK_INDEX 14 /* 1us mask index */ 547 #define EHCI_2US_MASK_INDEX 12 /* 2us mask index */ 548 #define EHCI_4US_MASK_INDEX 8 /* 4us mask index */ 549 #define EHCI_XUS_MASK_INDEX 0 /* 8us and above */ 550 551 /* 552 * Different interrupt polling intervals supported for low/full/high 553 * speed devices. For high speed devices, the following values are 554 * applicable after convertion. 555 */ 556 #define EHCI_INTR_1MS_POLL 1 /* 1ms poll interval */ 557 #define EHCI_INTR_2MS_POLL 2 /* 2ms poll interval */ 558 #define EHCI_INTR_4MS_POLL 4 /* 4ms poll interval */ 559 #define EHCI_INTR_8MS_POLL 8 /* 8ms poll interval */ 560 #define EHCI_INTR_16MS_POLL 16 /* 16ms poll interval */ 561 #define EHCI_INTR_32MS_POLL 32 /* 32ms poll interval */ 562 563 /* 564 * Number of interrupt transfer requests that should be maintained on 565 * the interrupt endpoint corresponding to different polling intervals 566 * supported. 567 */ 568 #define EHCI_INTR_1MS_REQS 4 /* 1ms polling interval */ 569 #define EHCI_INTR_2MS_REQS 2 /* 2ms polling interval */ 570 #define EHCI_INTR_XMS_REQS 1 /* Between 4ms and 32ms */ 571 572 /* Function prototype */ 573 typedef void (*ehci_handler_function_t)( 574 ehci_state_t *ehcip, 575 ehci_pipe_private_t *pp, 576 struct ehci_trans_wrapper *tw, 577 ehci_qtd_t *qtd, 578 void *ehci_handle_callback_value); 579 580 581 /* 582 * Transfer wrapper 583 * 584 * The transfer wrapper represents a USB transfer on the bus and there 585 * is one instance per USB transfer. A transfer is made up of one or 586 * more transactions. EHCI uses one QTD for one transaction. So one 587 * transfer wrapper may have one or more QTDs associated. 588 * 589 * The data to be transferred are contained in the TW buffer which is 590 * virtually contiguous but physically discontiguous. When preparing 591 * the QTDs for a USB transfer, the DMA cookies corresponding to the 592 * TW buffer need to be walked through to retrieve the DMA addresses. 593 * 594 * Control and bulk pipes will have one transfer wrapper per transfer 595 * and where as Isochronous and Interrupt pipes will only have one 596 * transfer wrapper. The transfers wrapper are continually reused for 597 * the Interrupt and Isochronous pipes as those pipes are polled. 598 */ 599 typedef struct ehci_trans_wrapper { 600 struct ehci_trans_wrapper *tw_next; /* Next wrapper */ 601 ehci_pipe_private_t *tw_pipe_private; /* Back ptr */ 602 ddi_dma_handle_t tw_dmahandle; /* DMA handle */ 603 ddi_acc_handle_t tw_accesshandle; /* Acc hndle */ 604 ddi_dma_cookie_t tw_cookie; /* DMA cookie */ 605 uint_t tw_ncookies; /* DMA cookie count */ 606 uint_t tw_cookie_idx; /* DMA cookie index */ 607 size_t tw_dma_offs; /* DMA buffer offset */ 608 uint32_t tw_id; /* 32bit ID */ 609 size_t tw_length; /* Txfer length */ 610 char *tw_buf; /* Buffer for Xfer */ 611 usb_flags_t tw_flags; /* Flags */ 612 uint_t tw_num_qtds; /* Number of QTDs */ 613 ehci_qtd_t *tw_qtd_head; /* Head QTD */ 614 ehci_qtd_t *tw_qtd_tail; /* Tail QTD */ 615 uint_t tw_direction; /* Direction of QTD */ 616 617 /* Current transfer request pointer */ 618 usb_opaque_t tw_curr_xfer_reqp; 619 620 /* Transfer timeout information */ 621 int tw_timeout; /* Timeout value */ 622 struct ehci_trans_wrapper *tw_timeout_next; /* Xfer Timeout Q */ 623 624 /* 625 * This is the function to call when this td is done. This way 626 * we don't have to look in the td to figure out what kind it is. 627 */ 628 ehci_handler_function_t tw_handle_qtd; 629 630 /* 631 * This is the callback value used when processing a done td. 632 */ 633 usb_opaque_t tw_handle_callback_value; 634 635 /* We preallocate all the td's for each tw and place them here */ 636 ehci_qtd_t *tw_qtd_free_list; 637 ehci_qtd_t *tw_alt_qtd; 638 } ehci_trans_wrapper_t; 639 640 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_trans_wrapper)) 641 642 /* 643 * Isochronous Transfer Wrapper 644 * 645 * This transfer wrapper is built specifically for the LOW/FULL/HIGH speed 646 * isochronous transfers. A transfer wrapper consists of one or more 647 * transactionsl, but there is one one instance per USB transfer request. 648 * 649 * The isochrnous transfer wrapper are continiously reused because these 650 * pipes are polled. 651 */ 652 typedef struct ehci_isoc_xwrapper { 653 struct ehci_isoc_xwrapper *itw_next; /* Next wrapper in pp */ 654 ehci_pipe_private_t *itw_pipe_private; 655 656 /* DMA and memory pointers */ 657 ddi_dma_handle_t itw_dmahandle; /* DMA handle ETT */ 658 ddi_acc_handle_t itw_accesshandle; /* Acc hndle */ 659 ddi_dma_cookie_t itw_cookie; /* DMA cookie */ 660 661 /* Transfer information */ 662 char *itw_buf; /* Buffer for Xfer */ 663 size_t itw_length; /* Txfer length */ 664 usb_flags_t itw_flags; /* Flags */ 665 usb_port_status_t itw_port_status; /* Port Speed */ 666 uint_t itw_direction; /* Direction of ITD */ 667 668 /* ITD information */ 669 uint_t itw_num_itds; /* Number of ITDs */ 670 ehci_itd_t *itw_itd_head; /* Head ITD */ 671 ehci_itd_t *itw_itd_tail; /* Tail ITD */ 672 usb_isoc_req_t *itw_curr_xfer_reqp; 673 usb_isoc_pkt_descr_t *itw_curr_isoc_pktp; 674 675 /* We preallocate all the td's for each tw and place them here */ 676 ehci_itd_t *itw_itd_free_list; 677 678 /* Device and hub information needed by every iTD */ 679 uint_t itw_hub_addr; 680 uint_t itw_hub_port; 681 uint_t itw_endpoint_num; 682 uint_t itw_device_addr; 683 684 /* 685 * Callback handling function and arguement. Called when an iTD is 686 * is done. 687 */ 688 usb_opaque_t itw_handle_callback_value; 689 690 /* 32bit ID */ 691 uint32_t itw_id; 692 } ehci_isoc_xwrapper_t; 693 694 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_isoc_xwrapper_t)) 695 696 /* 697 * Time waits for the different EHCI specific operations. 698 * These timeout values are specified in terms of microseconds. 699 */ 700 #define EHCI_RESET_TIMEWAIT 10000 /* HC reset waiting time */ 701 #define EHCI_TIMEWAIT 10000 /* HC any other waiting time */ 702 #define EHCI_SOF_TIMEWAIT 20000 /* SOF Wait time */ 703 #define EHCI_TAKEOVER_DELAY 10000 /* HC take over waiting time */ 704 #define EHCI_TAKEOVER_WAIT_COUNT 25 /* HC take over waiting count */ 705 706 /* These timeout values are specified in seconds */ 707 #define EHCI_DEFAULT_XFER_TIMEOUT 5 /* Default transfer timeout */ 708 #define EHCI_XFER_CMPL_TIMEWAIT 3 /* Xfers completion timewait */ 709 710 /* EHCI flags for general use */ 711 #define EHCI_FLAGS_NOSLEEP 0x000 /* Don't wait for SOF */ 712 #define EHCI_FLAGS_SLEEP 0x100 /* Wait for SOF */ 713 #define EHCI_FLAGS_DMA_SYNC 0x200 /* Call ddi_dma_sync */ 714 715 /* 716 * Maximum allowable data transfer size per transaction as supported 717 * by EHCI is 20k. (See EHCI Host Controller Interface Spec Rev 0.96) 718 * 719 * Also within QTD, there will be five buffer pointers abd each buffer 720 * pointer can transfer upto 4k bytes of data. 721 */ 722 #define EHCI_MAX_QTD_XFER_SIZE 0x5000 /* Maxmum data per transaction */ 723 #define EHCI_MAX_QTD_BUF_SIZE 0x1000 /* Maxmum data per buffer */ 724 725 /* 726 * The maximum allowable bulk data transfer size. It can be different 727 * from EHCI_MAX_QTD_XFER_SIZE and if it is more then ehci driver will 728 * take care of breaking a bulk data request into multiples of ehci 729 * EHCI_MAX_QTD_XFER_SIZE until request is satisfied. Currently this 730 * value is set to 640k bytes. 731 */ 732 #define EHCI_MAX_BULK_XFER_SIZE 0xA0000 /* Maximum bulk transfer size */ 733 734 /* 735 * Timeout flags 736 * 737 * These flags will be used to stop the timer before timeout handler 738 * gets executed. 739 */ 740 #define EHCI_REMOVE_XFER_IFLAST 1 /* Stop the timer if it is last QTD */ 741 #define EHCI_REMOVE_XFER_ALWAYS 2 /* Stop the timer without condition */ 742 743 744 /* 745 * High speed bandwidth allocation 746 * 747 * The following definitions are used during bandwidth calculations 748 * for a given high speed endpoint or high speed split transactions. 749 */ 750 #define HS_BUS_BANDWIDTH 7500 /* Up to 7500 bytes per 125us */ 751 #define HS_MAX_POLL_INTERVAL 16 /* Max high speed polling interval */ 752 #define HS_MIN_POLL_INTERVAL 1 /* Min high speed polling interval */ 753 #define HS_SOF 12 /* Length in bytes of High speed SOF */ 754 #define HS_EOF 70 /* Length in bytes of High speed EOF */ 755 #define TREE_HEIGHT 5 /* Log base 2 of 32 */ 756 757 /* 758 * As per USB 2.0 specification section 5.5.4, 20% of bus time is reserved 759 * for the non-periodic high-speed transfers. Where as peridoic high-speed 760 * transfers will get 80% of the bus time. In one micro-frame or 125us, we 761 * can transfer 7500 bytes or 60,000 bits. 762 */ 763 #define HS_NON_PERIODIC_BANDWIDTH 1500 764 #define HS_PERIODIC_BANDWIDTH (HS_BUS_BANDWIDTH - HS_SOF - \ 765 HS_EOF - HS_NON_PERIODIC_BANDWIDTH) 766 767 /* 768 * High speed periodic frame bandwidth will be eight times the micro frame 769 * high speed periodic bandwidth. 770 */ 771 #define HS_PERIODIC_FRAME_BANDWIDTH HS_PERIODIC_BANDWIDTH * EHCI_MAX_UFRAMES 772 773 /* 774 * The following are the protocol overheads in terms of Bytes for the 775 * different transfer types. All these protocol overhead values are 776 * derived from the 5.11.3 section of USB 2.0 Specification. 777 */ 778 #define HS_NON_ISOC_PROTO_OVERHEAD 55 779 #define HS_ISOC_PROTO_OVERHEAD 38 780 781 /* 782 * The following are THE protocol overheads in terms of Bytes for the 783 * start and complete split transactions tokens overheads. All these 784 * protocol overhead values are derived from the 8.4.2.2 and 8.4.2.3 785 * of USB2.0 Specification. 786 */ 787 #define START_SPLIT_OVERHEAD 04 788 #define COMPLETE_SPLIT_OVERHEAD 04 789 790 /* 791 * The Host Controller (HC) delays are the USB host controller specific 792 * delays. The value shown below is the host controller delay for the 793 * given EHCI host controller. 794 */ 795 #define EHCI_HOST_CONTROLLER_DELAY 18 796 797 /* 798 * Low/Full speed bandwidth allocation 799 * 800 * The following definitions are used during bandwidth calculations for 801 * a given high speed hub or a transaction translator (TT) and for a 802 * given low/full speed device connected to high speed hub or TT using 803 * split transactions 804 */ 805 #define FS_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per 1ms */ 806 #define FS_MAX_POLL_INTERVAL 255 /* Max full speed poll interval */ 807 #define FS_MIN_POLL_INTERVAL 1 /* Min full speed polling interval */ 808 #define FS_SOF 6 /* Length in bytes of Full speed SOF */ 809 #define FS_EOF 4 /* Length in bytes of Full speed EOF */ 810 811 /* 812 * Minimum polling interval for low speed endpoint 813 * 814 * According USB 2.0 Specification, a full-speed endpoint can specify 815 * a desired polling interval 1ms to 255ms and a low speed endpoints 816 * are limited to specifying only 10ms to 255ms. But some old keyboards 817 * and mice uses polling interval of 8ms. For compatibility purpose, 818 * we are using polling interval between 8ms and 255ms for low speed 819 * endpoints. The ehci driver will use 8ms polling interval if a low 820 * speed device reports a polling interval that is less than 8ms. 821 */ 822 #define LS_MAX_POLL_INTERVAL 255 /* Max low speed poll interval */ 823 #define LS_MIN_POLL_INTERVAL 8 /* Min low speed polling interval */ 824 825 /* 826 * For non-periodic transfers, reserve atleast for one low-speed device 827 * transaction. According to USB Bandwidth Analysis white paper and also 828 * as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed 829 * transaction takes 0x628h full speed bits (197 bytes), which comes to 830 * around 13% of USB frame time. 831 * 832 * The periodic transfers will get around 87% of USB frame time. 833 */ 834 #define FS_NON_PERIODIC_BANDWIDTH 197 835 #define FS_PERIODIC_BANDWIDTH (FS_BUS_BANDWIDTH - FS_SOF - \ 836 FS_EOF - FS_NON_PERIODIC_BANDWIDTH) 837 838 /* 839 * The following are the protocol overheads in terms of Bytes for the 840 * different transfer types. All these protocol overhead values are 841 * derived from the 5.11.3 section of USB Specification and with the 842 * help of Bandwidth Analysis white paper which is posted on the USB 843 * developer forum. 844 */ 845 #define FS_NON_ISOC_PROTO_OVERHEAD 14 846 #define FS_ISOC_INPUT_PROTO_OVERHEAD 11 847 #define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10 848 #define LOW_SPEED_PROTO_OVERHEAD 97 849 #define HUB_LOW_SPEED_PROTO_OVERHEAD 01 850 851 /* The maximum amount of isoch data that can be transferred in one uFrame */ 852 #define MAX_UFRAME_SITD_XFER 188 853 854 /* 855 * The low speed clock below represents that to transmit one low-speed 856 * bit takes eight times more than one full speed bit time. 857 */ 858 #define LOW_SPEED_CLOCK 8 859 860 /* 861 * The Transaction Translator (TT) delay is the additional time needed 862 * to execute low/full speed transaction from high speed split transaction 863 * for the low/full device connected to the high speed extrenal hub. 864 */ 865 #define TT_DELAY 18 866 867 868 /* 869 * Macros for setting/getting information 870 */ 871 #define Get_QH(addr) ddi_get32(ehcip->ehci_qh_pool_mem_handle, \ 872 (uint32_t *)&addr) 873 874 #define Set_QH(addr, val) ddi_put32(ehcip->ehci_qh_pool_mem_handle, \ 875 ((uint32_t *)&addr), \ 876 ((int32_t)(val))) 877 878 #define Get_QTD(addr) ddi_get32(ehcip->ehci_qtd_pool_mem_handle, \ 879 (uint32_t *)&addr) 880 881 #define Set_QTD(addr, val) ddi_put32(ehcip->ehci_qtd_pool_mem_handle, \ 882 ((uint32_t *)&addr), \ 883 ((int32_t)(val))) 884 885 #define Get_ITD(addr) ddi_get32(ehcip->ehci_itd_pool_mem_handle, \ 886 (uint32_t *)&addr) 887 888 #define Set_ITD(addr, val) ddi_put32(ehcip->ehci_itd_pool_mem_handle, \ 889 ((uint32_t *)&addr), \ 890 ((int32_t)(val))) 891 892 #define Get_ITD_BODY(ptr, addr) ddi_get32( \ 893 ehcip->ehci_itd_pool_mem_handle, \ 894 (uint32_t *)&ptr->itd_body[addr]) 895 896 #define Set_ITD_BODY(ptr, addr, val) ddi_put32( \ 897 ehcip->ehci_itd_pool_mem_handle, \ 898 ((uint32_t *)&ptr->itd_body[addr]),\ 899 ((int32_t)(val))) 900 901 #define Get_ITD_INDEX(ptr, pos) ddi_get32( \ 902 ehcip->ehci_itd_pool_mem_handle, \ 903 (uint32_t *)&ptr->itd_index[pos]) 904 905 #define Set_ITD_INDEX(ptr, pos, val) ddi_put32( \ 906 ehcip->ehci_itd_pool_mem_handle, \ 907 ((uint32_t *)&ptr->itd_index[pos]),\ 908 ((uint32_t)(val))) 909 910 #define Get_ITD_FRAME(addr) ddi_get64( \ 911 ehcip->ehci_itd_pool_mem_handle, \ 912 (uint64_t *)&addr) 913 914 #define Set_ITD_FRAME(addr, val) ddi_put64( \ 915 ehcip->ehci_itd_pool_mem_handle, \ 916 ((uint64_t *)&addr), \ 917 (val)) 918 919 #define Get_PFLT(addr) ddi_get32(ehcip->ehci_pflt_mem_handle, \ 920 (uint32_t *)&addr) 921 922 #define Set_PFLT(addr, val) ddi_put32(ehcip->ehci_pflt_mem_handle, \ 923 ((uint32_t *)&addr), \ 924 ((int32_t)(uintptr_t)(val))) 925 926 #define Get_8Cap(addr) ddi_get8(ehcip->ehci_caps_handle, \ 927 (uint8_t *)&ehcip->ehci_capsp->addr) 928 929 #define Get_16Cap(addr) ddi_get16(ehcip->ehci_caps_handle, \ 930 (uint16_t *)&ehcip->ehci_capsp->addr) 931 932 #define Get_Cap(addr) ddi_get32(ehcip->ehci_caps_handle, \ 933 (uint32_t *)&ehcip->ehci_capsp->addr) 934 935 #define Get_OpReg(addr) ddi_get32(ehcip->ehci_caps_handle, \ 936 (uint32_t *)&ehcip->ehci_regsp->addr) 937 938 #define Set_OpReg(addr, val) ddi_put32(ehcip->ehci_caps_handle, \ 939 ((uint32_t *)&ehcip->ehci_regsp->addr), \ 940 ((int32_t)(val))) 941 942 #define CalculateITDMultiField(pkgSize) (1 + (((pkgSize)>>11) & 0x03)) 943 944 #define EHCI_MAX_RETRY 10 945 946 #define Set_OpRegRetry(addr, val, r) \ 947 while (Get_OpReg(addr) != val) { \ 948 if (r >= EHCI_MAX_RETRY) \ 949 break; \ 950 r++; \ 951 Set_OpReg(addr, val); \ 952 } 953 954 #define Sync_QH_QTD_Pool(ehcip) (void) ddi_dma_sync( \ 955 ehcip->ehci_qh_pool_dma_handle, \ 956 0, EHCI_QH_POOL_SIZE * sizeof (ehci_qh_t), \ 957 DDI_DMA_SYNC_FORCPU); \ 958 (void) ddi_dma_sync( \ 959 ehcip->ehci_qtd_pool_dma_handle, \ 960 0, EHCI_QTD_POOL_SIZE * sizeof (ehci_qtd_t), \ 961 DDI_DMA_SYNC_FORCPU); 962 963 #define Sync_ITD_Pool(ehcip) (void) ddi_dma_sync( \ 964 ehcip->ehci_itd_pool_dma_handle, \ 965 0, EHCI_ITD_POOL_SIZE * sizeof (ehci_itd_t), \ 966 DDI_DMA_SYNC_FORCPU); 967 968 #define Sync_IO_Buffer(dma_handle, length) \ 969 (void) ddi_dma_sync(dma_handle, \ 970 0, length, DDI_DMA_SYNC_FORCPU); 971 972 #define Sync_IO_Buffer_for_device(dma_handle, length) \ 973 (void) ddi_dma_sync(dma_handle, \ 974 0, length, DDI_DMA_SYNC_FORDEV); 975 976 /* 977 * Macros to speed handling of 32bit IDs 978 */ 979 #define EHCI_GET_ID(x) id32_alloc((void *)(x), KM_SLEEP) 980 #define EHCI_LOOKUP_ID(x) id32_lookup((x)) 981 #define EHCI_FREE_ID(x) id32_free((x)) 982 983 984 /* 985 * Miscellaneous definitions. 986 */ 987 988 /* Data toggle bits */ 989 #define DATA0 0 990 #define DATA1 1 991 992 /* Halt bit actions */ 993 #define CLEAR_HALT 0 994 #define SET_HALT 1 995 996 typedef uint_t halt_bit_t; 997 998 /* 999 * Setup Packet 1000 */ 1001 typedef struct setup_pkt { 1002 uchar_t bmRequestType; 1003 uchar_t bRequest; 1004 ushort_t wValue; 1005 ushort_t wIndex; 1006 ushort_t wLength; 1007 }setup_pkt_t; 1008 1009 #define SETUP_SIZE 8 /* Setup packet is always 8 bytes */ 1010 1011 #define REQUEST_TYPE_OFFSET 0 1012 #define REQUEST_OFFSET 1 1013 #define VALUE_OFFSET 2 1014 #define INDEX_OFFSET 4 1015 #define LENGTH_OFFSET 6 1016 1017 #define TYPE_DEV_TO_HOST 0x80000000 1018 #define DEVICE 0x00000001 1019 #define CONFIGURATION 0x00000002 1020 1021 /* 1022 * The following are used in attach to indicate 1023 * what has been succesfully allocated, so detach 1024 * can remove them. 1025 */ 1026 #define EHCI_ATTACH 0x01 /* ehci driver initilization */ 1027 #define EHCI_ZALLOC 0x02 /* Memory for ehci state structure */ 1028 #define EHCI_INTR 0x04 /* Interrupt handler registered */ 1029 #define EHCI_USBAREG 0x08 /* USBA registered */ 1030 #define EHCI_RHREG 0x10 /* Root hub driver loaded */ 1031 1032 /* 1033 * This variable is used in the EHCI_FLAGS to tell the ISR to broadcase 1034 * the ehci_async_schedule_advance_cv when an intr occurs. It is used to 1035 * make sure that EHCI is receiving interrupts. 1036 */ 1037 #define EHCI_CV_INTR 0x20 /* Ask INTR to broadcast cv */ 1038 1039 #define EHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB) 1040 1041 /* 1042 * Debug printing 1043 * Masks 1044 */ 1045 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */ 1046 #define PRINT_MASK_LISTS 0x00000002 /* List management */ 1047 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */ 1048 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */ 1049 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */ 1050 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */ 1051 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */ 1052 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */ 1053 #define PRINT_MASK_DUMPING 0x00000100 /* Dump ehci info */ 1054 #define PRINT_MASK_ALL 0xFFFFFFFF 1055 1056 #define PCI_VENDOR_NVIDIA 0x10de /* PCI Vendor-id NVIDIA */ 1057 #define PCI_DEVICE_NVIDIA_CK804 0x5b 1058 #define PCI_DEVICE_NVIDIA_MCP04 0x3c 1059 /* 1060 * workaround for ALI chips 1061 */ 1062 #define PCI_VENDOR_ALI 0x10b9 /* PCI Vendor-id Acer */ 1063 1064 /* 1065 * NEC on COMBO and Uli M1575 can support PM 1066 */ 1067 #define PCI_VENDOR_NEC_COMBO 0x1033 1068 #define PCI_DEVICE_NEC_COMBO 0xe0 1069 #define PCI_VENDOR_ULi_M1575 0x10b9 1070 #define PCI_DEVICE_ULi_M1575 0x5239 1071 1072 /* 1073 * VIA chips have some problems, the workaround can ensure those chips 1074 * work reliably. Revisions >= 0x80 are part of a southbridge and appear 1075 * to be reliable. 1076 */ 1077 #define PCI_VENDOR_VIA 0x1106 /* PCI Vendor-id VIA */ 1078 #define PCI_VIA_REVISION_6212 0x80 /* VIA 6212 revision ID */ 1079 1080 #define EHCI_VIA_LOST_INTERRUPTS 0x01 1081 #define EHCI_VIA_ASYNC_SCHEDULE 0x02 1082 #define EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE 0x04 1083 1084 #define EHCI_VIA_WORKAROUNDS \ 1085 (EHCI_VIA_LOST_INTERRUPTS | \ 1086 EHCI_VIA_ASYNC_SCHEDULE | \ 1087 EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE) 1088 1089 #define EHCI_VIA_MAX_BULK_XFER_SIZE 0x8000 /* Maximum bulk transfer size */ 1090 1091 1092 /* 1093 * EHCI HCDI entry points 1094 * 1095 * The Host Controller Driver Interfaces (HCDI) are the software interfaces 1096 * between the Universal Serial Bus Driver (USBA) and the Host Controller 1097 * Driver (HCD). The HCDI interfaces or entry points are subject to change. 1098 */ 1099 int ehci_hcdi_pipe_open( 1100 usba_pipe_handle_data_t *ph, 1101 usb_flags_t usb_flags); 1102 int ehci_hcdi_pipe_close( 1103 usba_pipe_handle_data_t *ph, 1104 usb_flags_t usb_flags); 1105 int ehci_hcdi_pipe_reset( 1106 usba_pipe_handle_data_t *ph, 1107 usb_flags_t usb_flags); 1108 void ehci_hcdi_pipe_reset_data_toggle( 1109 usba_pipe_handle_data_t *ph); 1110 int ehci_hcdi_pipe_ctrl_xfer( 1111 usba_pipe_handle_data_t *ph, 1112 usb_ctrl_req_t *ctrl_reqp, 1113 usb_flags_t usb_flags); 1114 int ehci_hcdi_bulk_transfer_size( 1115 usba_device_t *usba_device, 1116 size_t *size); 1117 int ehci_hcdi_pipe_bulk_xfer( 1118 usba_pipe_handle_data_t *ph, 1119 usb_bulk_req_t *bulk_reqp, 1120 usb_flags_t usb_flags); 1121 int ehci_hcdi_pipe_intr_xfer( 1122 usba_pipe_handle_data_t *ph, 1123 usb_intr_req_t *intr_req, 1124 usb_flags_t usb_flags); 1125 int ehci_hcdi_pipe_stop_intr_polling( 1126 usba_pipe_handle_data_t *ph, 1127 usb_flags_t usb_flags); 1128 int ehci_hcdi_get_current_frame_number( 1129 usba_device_t *usba_device, 1130 usb_frame_number_t *frame_number); 1131 int ehci_hcdi_get_max_isoc_pkts( 1132 usba_device_t *usba_device, 1133 uint_t *max_isoc_pkts_per_request); 1134 int ehci_hcdi_pipe_isoc_xfer( 1135 usba_pipe_handle_data_t *ph, 1136 usb_isoc_req_t *isoc_reqp, 1137 usb_flags_t usb_flags); 1138 int ehci_hcdi_pipe_stop_isoc_polling( 1139 usba_pipe_handle_data_t *ph, 1140 usb_flags_t usb_flags); 1141 1142 /* 1143 * EHCI Polled entry points function prototypes. 1144 */ 1145 int ehci_hcdi_polled_input_init( 1146 usba_pipe_handle_data_t *ph, 1147 uchar_t **polled_buf, 1148 usb_console_info_impl_t *info); 1149 int ehci_hcdi_polled_input_enter( 1150 usb_console_info_impl_t *info); 1151 int ehci_hcdi_polled_read( 1152 usb_console_info_impl_t *info, 1153 uint_t *num_characters); 1154 int ehci_hcdi_polled_input_exit( 1155 usb_console_info_impl_t *info); 1156 int ehci_hcdi_polled_input_fini( 1157 usb_console_info_impl_t *info); 1158 int ehci_hcdi_polled_output_init( 1159 usba_pipe_handle_data_t *ph, 1160 usb_console_info_impl_t *console_output_info); 1161 int ehci_hcdi_polled_output_enter( 1162 usb_console_info_impl_t *info); 1163 int ehci_hcdi_polled_write( 1164 usb_console_info_impl_t *info, 1165 uchar_t *buf, 1166 uint_t num_characters, 1167 uint_t *num_characters_written); 1168 int ehci_hcdi_polled_output_exit( 1169 usb_console_info_impl_t *info); 1170 int ehci_hcdi_polled_output_fini( 1171 usb_console_info_impl_t *info); 1172 /* 1173 * EHCI Root Hub entry points function prototypes. 1174 */ 1175 int ehci_init_root_hub( 1176 ehci_state_t *ehcip); 1177 int ehci_load_root_hub_driver( 1178 ehci_state_t *ehcip); 1179 int ehci_unload_root_hub_driver( 1180 ehci_state_t *ehcip); 1181 int ehci_handle_root_hub_pipe_open( 1182 usba_pipe_handle_data_t *ph, 1183 usb_flags_t flags); 1184 int ehci_handle_root_hub_pipe_close( 1185 usba_pipe_handle_data_t *ph); 1186 int ehci_handle_root_hub_pipe_reset( 1187 usba_pipe_handle_data_t *ph, 1188 usb_flags_t flags); 1189 int ehci_handle_root_hub_request( 1190 ehci_state_t *ehcip, 1191 usba_pipe_handle_data_t *ph, 1192 usb_ctrl_req_t *ctrl_reqp); 1193 int ehci_handle_root_hub_pipe_start_intr_polling( 1194 usba_pipe_handle_data_t *ph, 1195 usb_intr_req_t *intr_reqp, 1196 usb_flags_t flags); 1197 void ehci_handle_root_hub_pipe_stop_intr_polling( 1198 usba_pipe_handle_data_t *ph, 1199 usb_flags_t flags); 1200 1201 /* 1202 * EHCI Interrupt Handler entry point. 1203 */ 1204 uint_t ehci_intr(caddr_t arg1, 1205 caddr_t arg2); 1206 1207 #ifdef __cplusplus 1208 } 1209 #endif 1210 1211 #endif /* _SYS_USB_EHCID_H */ 1212