1 /*
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org>
5 * Copyright (c) 2015 Peter Grehan <grehan@freebsd.org>
6 * Copyright (c) 2013 Jeremiah Lott, Avere Systems
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer
14 * in this position and unchanged.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 #include <sys/types.h>
33 #ifndef WITHOUT_CAPSICUM
34 #include <sys/capsicum.h>
35 #endif
36 #include <sys/limits.h>
37 #include <sys/ioctl.h>
38 #include <sys/uio.h>
39 #include <net/ethernet.h>
40 #include <netinet/in.h>
41 #include <netinet/tcp.h>
42
43 #ifndef WITHOUT_CAPSICUM
44 #include <capsicum_helpers.h>
45 #endif
46
47 #include <err.h>
48 #include <errno.h>
49 #include <fcntl.h>
50 #include <md5.h>
51 #include <stdio.h>
52 #include <stdlib.h>
53 #include <string.h>
54 #include <sysexits.h>
55 #include <unistd.h>
56 #include <pthread.h>
57 #include <pthread_np.h>
58
59 #include "e1000_regs.h"
60 #include "e1000_defines.h"
61 #include "mii.h"
62
63 #include "bhyverun.h"
64 #include "config.h"
65 #include "debug.h"
66 #include "pci_emul.h"
67 #ifdef BHYVE_SNAPSHOT
68 #include "snapshot.h"
69 #endif
70 #include "mevent.h"
71 #include "net_utils.h"
72 #include "net_backends.h"
73
74 /* Hardware/register definitions XXX: move some to common code. */
75 #define E82545_VENDOR_ID_INTEL 0x8086
76 #define E82545_DEV_ID_82545EM_COPPER 0x100F
77 #define E82545_SUBDEV_ID 0x1008
78
79 #define E82545_REVISION_4 4
80
81 #define E82545_MDIC_DATA_MASK 0x0000FFFF
82 #define E82545_MDIC_OP_MASK 0x0c000000
83 #define E82545_MDIC_IE 0x20000000
84
85 #define E82545_EECD_FWE_DIS 0x00000010 /* Flash writes disabled */
86 #define E82545_EECD_FWE_EN 0x00000020 /* Flash writes enabled */
87 #define E82545_EECD_FWE_MASK 0x00000030 /* Flash writes mask */
88
89 #define E82545_BAR_REGISTER 0
90 #define E82545_BAR_REGISTER_LEN (128*1024)
91 #define E82545_BAR_FLASH 1
92 #define E82545_BAR_FLASH_LEN (64*1024)
93 #define E82545_BAR_IO 2
94 #define E82545_BAR_IO_LEN 8
95
96 #define E82545_IOADDR 0x00000000
97 #define E82545_IODATA 0x00000004
98 #define E82545_IO_REGISTER_MAX 0x0001FFFF
99 #define E82545_IO_FLASH_BASE 0x00080000
100 #define E82545_IO_FLASH_MAX 0x000FFFFF
101
102 #define E82545_ARRAY_ENTRY(reg, offset) (reg + (offset<<2))
103 #define E82545_RAR_MAX 15
104 #define E82545_MTA_MAX 127
105 #define E82545_VFTA_MAX 127
106
107 /* Slightly modified from the driver versions, hardcoded for 3 opcode bits,
108 * followed by 6 address bits.
109 * TODO: make opcode bits and addr bits configurable?
110 * NVM Commands - Microwire */
111 #define E82545_NVM_OPCODE_BITS 3
112 #define E82545_NVM_ADDR_BITS 6
113 #define E82545_NVM_DATA_BITS 16
114 #define E82545_NVM_OPADDR_BITS (E82545_NVM_OPCODE_BITS + E82545_NVM_ADDR_BITS)
115 #define E82545_NVM_ADDR_MASK ((1 << E82545_NVM_ADDR_BITS)-1)
116 #define E82545_NVM_OPCODE_MASK \
117 (((1 << E82545_NVM_OPCODE_BITS) - 1) << E82545_NVM_ADDR_BITS)
118 #define E82545_NVM_OPCODE_READ (0x6 << E82545_NVM_ADDR_BITS) /* read */
119 #define E82545_NVM_OPCODE_WRITE (0x5 << E82545_NVM_ADDR_BITS) /* write */
120 #define E82545_NVM_OPCODE_ERASE (0x7 << E82545_NVM_ADDR_BITS) /* erase */
121 #define E82545_NVM_OPCODE_EWEN (0x4 << E82545_NVM_ADDR_BITS) /* wr-enable */
122
123 #define E82545_NVM_EEPROM_SIZE 64 /* 64 * 16-bit values == 128K */
124
125 #define E1000_ICR_SRPD 0x00010000
126
127 /* This is an arbitrary number. There is no hard limit on the chip. */
128 #define I82545_MAX_TXSEGS 64
129
130 /* Legacy receive descriptor */
131 struct e1000_rx_desc {
132 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
133 uint16_t length; /* Length of data DMAed into data buffer */
134 uint16_t csum; /* Packet checksum */
135 uint8_t status; /* Descriptor status */
136 uint8_t errors; /* Descriptor Errors */
137 uint16_t special;
138 };
139
140 /* Transmit descriptor types */
141 #define E1000_TXD_MASK (E1000_TXD_CMD_DEXT | 0x00F00000)
142 #define E1000_TXD_TYP_L (0)
143 #define E1000_TXD_TYP_C (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C)
144 #define E1000_TXD_TYP_D (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)
145
146 /* Legacy transmit descriptor */
147 struct e1000_tx_desc {
148 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
149 union {
150 uint32_t data;
151 struct {
152 uint16_t length; /* Data buffer length */
153 uint8_t cso; /* Checksum offset */
154 uint8_t cmd; /* Descriptor control */
155 } flags;
156 } lower;
157 union {
158 uint32_t data;
159 struct {
160 uint8_t status; /* Descriptor status */
161 uint8_t css; /* Checksum start */
162 uint16_t special;
163 } fields;
164 } upper;
165 };
166
167 /* Context descriptor */
168 struct e1000_context_desc {
169 union {
170 uint32_t ip_config;
171 struct {
172 uint8_t ipcss; /* IP checksum start */
173 uint8_t ipcso; /* IP checksum offset */
174 uint16_t ipcse; /* IP checksum end */
175 } ip_fields;
176 } lower_setup;
177 union {
178 uint32_t tcp_config;
179 struct {
180 uint8_t tucss; /* TCP checksum start */
181 uint8_t tucso; /* TCP checksum offset */
182 uint16_t tucse; /* TCP checksum end */
183 } tcp_fields;
184 } upper_setup;
185 uint32_t cmd_and_length;
186 union {
187 uint32_t data;
188 struct {
189 uint8_t status; /* Descriptor status */
190 uint8_t hdr_len; /* Header length */
191 uint16_t mss; /* Maximum segment size */
192 } fields;
193 } tcp_seg_setup;
194 };
195
196 /* Data descriptor */
197 struct e1000_data_desc {
198 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
199 union {
200 uint32_t data;
201 struct {
202 uint16_t length; /* Data buffer length */
203 uint8_t typ_len_ext;
204 uint8_t cmd;
205 } flags;
206 } lower;
207 union {
208 uint32_t data;
209 struct {
210 uint8_t status; /* Descriptor status */
211 uint8_t popts; /* Packet Options */
212 uint16_t special;
213 } fields;
214 } upper;
215 };
216
217 union e1000_tx_udesc {
218 struct e1000_tx_desc td;
219 struct e1000_context_desc cd;
220 struct e1000_data_desc dd;
221 };
222
223 /* Tx checksum info for a packet. */
224 struct ck_info {
225 int ck_valid; /* ck_info is valid */
226 uint8_t ck_start; /* start byte of cksum calcuation */
227 uint8_t ck_off; /* offset of cksum insertion */
228 uint16_t ck_len; /* length of cksum calc: 0 is to packet-end */
229 };
230
231 /*
232 * Debug printf
233 */
234 static int e82545_debug = 0;
235 #define WPRINTF(msg,params...) PRINTLN("e82545: " msg, ##params)
236 #define DPRINTF(msg,params...) if (e82545_debug) WPRINTF(msg, params)
237
238 #define MIN(a,b) (((a)<(b))?(a):(b))
239 #define MAX(a,b) (((a)>(b))?(a):(b))
240
241 /* s/w representation of the RAL/RAH regs */
242 struct eth_uni {
243 int eu_valid;
244 int eu_addrsel;
245 struct ether_addr eu_eth;
246 };
247
248
249 struct e82545_softc {
250 struct pci_devinst *esc_pi;
251 struct vmctx *esc_ctx;
252 struct mevent *esc_mevpitr;
253 pthread_mutex_t esc_mtx;
254 struct ether_addr esc_mac;
255 net_backend_t *esc_be;
256
257 /* General */
258 uint32_t esc_CTRL; /* x0000 device ctl */
259 uint32_t esc_FCAL; /* x0028 flow ctl addr lo */
260 uint32_t esc_FCAH; /* x002C flow ctl addr hi */
261 uint32_t esc_FCT; /* x0030 flow ctl type */
262 uint32_t esc_VET; /* x0038 VLAN eth type */
263 uint32_t esc_FCTTV; /* x0170 flow ctl tx timer */
264 uint32_t esc_LEDCTL; /* x0E00 LED control */
265 uint32_t esc_PBA; /* x1000 pkt buffer allocation */
266
267 /* Interrupt control */
268 int esc_irq_asserted;
269 uint32_t esc_ICR; /* x00C0 cause read/clear */
270 uint32_t esc_ITR; /* x00C4 intr throttling */
271 uint32_t esc_ICS; /* x00C8 cause set */
272 uint32_t esc_IMS; /* x00D0 mask set/read */
273 uint32_t esc_IMC; /* x00D8 mask clear */
274
275 /* Transmit */
276 union e1000_tx_udesc *esc_txdesc;
277 struct e1000_context_desc esc_txctx;
278 pthread_t esc_tx_tid;
279 pthread_cond_t esc_tx_cond;
280 int esc_tx_enabled;
281 int esc_tx_active;
282 uint32_t esc_TXCW; /* x0178 transmit config */
283 uint32_t esc_TCTL; /* x0400 transmit ctl */
284 uint32_t esc_TIPG; /* x0410 inter-packet gap */
285 uint16_t esc_AIT; /* x0458 Adaptive Interframe Throttle */
286 uint64_t esc_tdba; /* verified 64-bit desc table addr */
287 uint32_t esc_TDBAL; /* x3800 desc table addr, low bits */
288 uint32_t esc_TDBAH; /* x3804 desc table addr, hi 32-bits */
289 uint32_t esc_TDLEN; /* x3808 # descriptors in bytes */
290 uint16_t esc_TDH; /* x3810 desc table head idx */
291 uint16_t esc_TDHr; /* internal read version of TDH */
292 uint16_t esc_TDT; /* x3818 desc table tail idx */
293 uint32_t esc_TIDV; /* x3820 intr delay */
294 uint32_t esc_TXDCTL; /* x3828 desc control */
295 uint32_t esc_TADV; /* x382C intr absolute delay */
296
297 /* L2 frame acceptance */
298 struct eth_uni esc_uni[16]; /* 16 x unicast MAC addresses */
299 uint32_t esc_fmcast[128]; /* Multicast filter bit-match */
300 uint32_t esc_fvlan[128]; /* VLAN 4096-bit filter */
301
302 /* Receive */
303 struct e1000_rx_desc *esc_rxdesc;
304 pthread_cond_t esc_rx_cond;
305 int esc_rx_enabled;
306 int esc_rx_active;
307 int esc_rx_loopback;
308 uint32_t esc_RCTL; /* x0100 receive ctl */
309 uint32_t esc_FCRTL; /* x2160 flow cntl thresh, low */
310 uint32_t esc_FCRTH; /* x2168 flow cntl thresh, hi */
311 uint64_t esc_rdba; /* verified 64-bit desc table addr */
312 uint32_t esc_RDBAL; /* x2800 desc table addr, low bits */
313 uint32_t esc_RDBAH; /* x2804 desc table addr, hi 32-bits*/
314 uint32_t esc_RDLEN; /* x2808 #descriptors */
315 uint16_t esc_RDH; /* x2810 desc table head idx */
316 uint16_t esc_RDT; /* x2818 desc table tail idx */
317 uint32_t esc_RDTR; /* x2820 intr delay */
318 uint32_t esc_RXDCTL; /* x2828 desc control */
319 uint32_t esc_RADV; /* x282C intr absolute delay */
320 uint32_t esc_RSRPD; /* x2C00 recv small packet detect */
321 uint32_t esc_RXCSUM; /* x5000 receive cksum ctl */
322
323 /* IO Port register access */
324 uint32_t io_addr;
325
326 /* Shadow copy of MDIC */
327 uint32_t mdi_control;
328 /* Shadow copy of EECD */
329 uint32_t eeprom_control;
330 /* Latest NVM in/out */
331 uint16_t nvm_data;
332 uint16_t nvm_opaddr;
333 /* stats */
334 uint32_t missed_pkt_count; /* dropped for no room in rx queue */
335 uint32_t pkt_rx_by_size[6];
336 uint32_t pkt_tx_by_size[6];
337 uint32_t good_pkt_rx_count;
338 uint32_t bcast_pkt_rx_count;
339 uint32_t mcast_pkt_rx_count;
340 uint32_t good_pkt_tx_count;
341 uint32_t bcast_pkt_tx_count;
342 uint32_t mcast_pkt_tx_count;
343 uint32_t oversize_rx_count;
344 uint32_t tso_tx_count;
345 uint64_t good_octets_rx;
346 uint64_t good_octets_tx;
347 uint64_t missed_octets; /* counts missed and oversized */
348
349 uint8_t nvm_bits:6; /* number of bits remaining in/out */
350 uint8_t nvm_mode:2;
351 #define E82545_NVM_MODE_OPADDR 0x0
352 #define E82545_NVM_MODE_DATAIN 0x1
353 #define E82545_NVM_MODE_DATAOUT 0x2
354 /* EEPROM data */
355 uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE];
356 };
357
358 static void e82545_reset(struct e82545_softc *sc, int dev);
359 static void e82545_rx_enable(struct e82545_softc *sc);
360 static void e82545_rx_disable(struct e82545_softc *sc);
361 static void e82545_rx_callback(int fd, enum ev_type type, void *param);
362 static void e82545_tx_start(struct e82545_softc *sc);
363 static void e82545_tx_enable(struct e82545_softc *sc);
364 static void e82545_tx_disable(struct e82545_softc *sc);
365
366 static inline int __unused
e82545_size_stat_index(uint32_t size)367 e82545_size_stat_index(uint32_t size)
368 {
369 if (size <= 64) {
370 return 0;
371 } else if (size >= 1024) {
372 return 5;
373 } else {
374 /* should be 1-4 */
375 return (ffs(size) - 6);
376 }
377 }
378
379 static void
e82545_init_eeprom(struct e82545_softc * sc)380 e82545_init_eeprom(struct e82545_softc *sc)
381 {
382 uint16_t checksum, i;
383
384 /* mac addr */
385 sc->eeprom_data[NVM_MAC_ADDR] = ((uint16_t)sc->esc_mac.octet[0]) |
386 (((uint16_t)sc->esc_mac.octet[1]) << 8);
387 sc->eeprom_data[NVM_MAC_ADDR+1] = ((uint16_t)sc->esc_mac.octet[2]) |
388 (((uint16_t)sc->esc_mac.octet[3]) << 8);
389 sc->eeprom_data[NVM_MAC_ADDR+2] = ((uint16_t)sc->esc_mac.octet[4]) |
390 (((uint16_t)sc->esc_mac.octet[5]) << 8);
391
392 /* pci ids */
393 sc->eeprom_data[NVM_SUB_DEV_ID] = E82545_SUBDEV_ID;
394 sc->eeprom_data[NVM_SUB_VEN_ID] = E82545_VENDOR_ID_INTEL;
395 sc->eeprom_data[NVM_DEV_ID] = E82545_DEV_ID_82545EM_COPPER;
396 sc->eeprom_data[NVM_VEN_ID] = E82545_VENDOR_ID_INTEL;
397
398 /* fill in the checksum */
399 checksum = 0;
400 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
401 checksum += sc->eeprom_data[i];
402 }
403 checksum = NVM_SUM - checksum;
404 sc->eeprom_data[NVM_CHECKSUM_REG] = checksum;
405 DPRINTF("eeprom checksum: 0x%x", checksum);
406 }
407
408 static void
e82545_write_mdi(struct e82545_softc * sc __unused,uint8_t reg_addr,uint8_t phy_addr,uint32_t data)409 e82545_write_mdi(struct e82545_softc *sc __unused, uint8_t reg_addr,
410 uint8_t phy_addr, uint32_t data)
411 {
412 DPRINTF("Write mdi reg:0x%x phy:0x%x data: 0x%x", reg_addr, phy_addr, data);
413 }
414
415 static uint32_t
e82545_read_mdi(struct e82545_softc * sc __unused,uint8_t reg_addr,uint8_t phy_addr)416 e82545_read_mdi(struct e82545_softc *sc __unused, uint8_t reg_addr,
417 uint8_t phy_addr)
418 {
419 //DPRINTF("Read mdi reg:0x%x phy:0x%x", reg_addr, phy_addr);
420 switch (reg_addr) {
421 case PHY_STATUS:
422 return (MII_SR_LINK_STATUS | MII_SR_AUTONEG_CAPS |
423 MII_SR_AUTONEG_COMPLETE);
424 case PHY_AUTONEG_ADV:
425 return NWAY_AR_SELECTOR_FIELD;
426 case PHY_LP_ABILITY:
427 return 0;
428 case PHY_1000T_STATUS:
429 return (SR_1000T_LP_FD_CAPS | SR_1000T_REMOTE_RX_STATUS |
430 SR_1000T_LOCAL_RX_STATUS);
431 case PHY_ID1:
432 return (M88E1011_I_PHY_ID >> 16) & 0xFFFF;
433 case PHY_ID2:
434 return (M88E1011_I_PHY_ID | E82545_REVISION_4) & 0xFFFF;
435 default:
436 DPRINTF("Unknown mdi read reg:0x%x phy:0x%x", reg_addr, phy_addr);
437 return 0;
438 }
439 /* not reached */
440 }
441
442 static void
e82545_eecd_strobe(struct e82545_softc * sc)443 e82545_eecd_strobe(struct e82545_softc *sc)
444 {
445 /* Microwire state machine */
446 /*
447 DPRINTF("eeprom state machine srtobe "
448 "0x%x 0x%x 0x%x 0x%x",
449 sc->nvm_mode, sc->nvm_bits,
450 sc->nvm_opaddr, sc->nvm_data);*/
451
452 if (sc->nvm_bits == 0) {
453 DPRINTF("eeprom state machine not expecting data! "
454 "0x%x 0x%x 0x%x 0x%x",
455 sc->nvm_mode, sc->nvm_bits,
456 sc->nvm_opaddr, sc->nvm_data);
457 return;
458 }
459 sc->nvm_bits--;
460 if (sc->nvm_mode == E82545_NVM_MODE_DATAOUT) {
461 /* shifting out */
462 if (sc->nvm_data & 0x8000) {
463 sc->eeprom_control |= E1000_EECD_DO;
464 } else {
465 sc->eeprom_control &= ~E1000_EECD_DO;
466 }
467 sc->nvm_data <<= 1;
468 if (sc->nvm_bits == 0) {
469 /* read done, back to opcode mode. */
470 sc->nvm_opaddr = 0;
471 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
472 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
473 }
474 } else if (sc->nvm_mode == E82545_NVM_MODE_DATAIN) {
475 /* shifting in */
476 sc->nvm_data <<= 1;
477 if (sc->eeprom_control & E1000_EECD_DI) {
478 sc->nvm_data |= 1;
479 }
480 if (sc->nvm_bits == 0) {
481 /* eeprom write */
482 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK;
483 uint16_t addr = sc->nvm_opaddr & E82545_NVM_ADDR_MASK;
484 if (op != E82545_NVM_OPCODE_WRITE) {
485 DPRINTF("Illegal eeprom write op 0x%x",
486 sc->nvm_opaddr);
487 } else if (addr >= E82545_NVM_EEPROM_SIZE) {
488 DPRINTF("Illegal eeprom write addr 0x%x",
489 sc->nvm_opaddr);
490 } else {
491 DPRINTF("eeprom write eeprom[0x%x] = 0x%x",
492 addr, sc->nvm_data);
493 sc->eeprom_data[addr] = sc->nvm_data;
494 }
495 /* back to opcode mode */
496 sc->nvm_opaddr = 0;
497 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
498 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
499 }
500 } else if (sc->nvm_mode == E82545_NVM_MODE_OPADDR) {
501 sc->nvm_opaddr <<= 1;
502 if (sc->eeprom_control & E1000_EECD_DI) {
503 sc->nvm_opaddr |= 1;
504 }
505 if (sc->nvm_bits == 0) {
506 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK;
507 switch (op) {
508 case E82545_NVM_OPCODE_EWEN:
509 DPRINTF("eeprom write enable: 0x%x",
510 sc->nvm_opaddr);
511 /* back to opcode mode */
512 sc->nvm_opaddr = 0;
513 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
514 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
515 break;
516 case E82545_NVM_OPCODE_READ:
517 {
518 uint16_t addr = sc->nvm_opaddr &
519 E82545_NVM_ADDR_MASK;
520 sc->nvm_mode = E82545_NVM_MODE_DATAOUT;
521 sc->nvm_bits = E82545_NVM_DATA_BITS;
522 if (addr < E82545_NVM_EEPROM_SIZE) {
523 sc->nvm_data = sc->eeprom_data[addr];
524 DPRINTF("eeprom read: eeprom[0x%x] = 0x%x",
525 addr, sc->nvm_data);
526 } else {
527 DPRINTF("eeprom illegal read: 0x%x",
528 sc->nvm_opaddr);
529 sc->nvm_data = 0;
530 }
531 break;
532 }
533 case E82545_NVM_OPCODE_WRITE:
534 sc->nvm_mode = E82545_NVM_MODE_DATAIN;
535 sc->nvm_bits = E82545_NVM_DATA_BITS;
536 sc->nvm_data = 0;
537 break;
538 default:
539 DPRINTF("eeprom unknown op: 0x%x",
540 sc->nvm_opaddr);
541 /* back to opcode mode */
542 sc->nvm_opaddr = 0;
543 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
544 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
545 }
546 }
547 } else {
548 DPRINTF("eeprom state machine wrong state! "
549 "0x%x 0x%x 0x%x 0x%x",
550 sc->nvm_mode, sc->nvm_bits,
551 sc->nvm_opaddr, sc->nvm_data);
552 }
553 }
554
555 static void
e82545_itr_callback(int fd __unused,enum ev_type type __unused,void * param)556 e82545_itr_callback(int fd __unused, enum ev_type type __unused, void *param)
557 {
558 uint32_t new;
559 struct e82545_softc *sc = param;
560
561 pthread_mutex_lock(&sc->esc_mtx);
562 new = sc->esc_ICR & sc->esc_IMS;
563 if (new && !sc->esc_irq_asserted) {
564 DPRINTF("itr callback: lintr assert %x", new);
565 sc->esc_irq_asserted = 1;
566 pci_lintr_assert(sc->esc_pi);
567 } else {
568 mevent_delete(sc->esc_mevpitr);
569 sc->esc_mevpitr = NULL;
570 }
571 pthread_mutex_unlock(&sc->esc_mtx);
572 }
573
574 static void
e82545_icr_assert(struct e82545_softc * sc,uint32_t bits)575 e82545_icr_assert(struct e82545_softc *sc, uint32_t bits)
576 {
577 uint32_t new;
578
579 DPRINTF("icr assert: 0x%x", bits);
580
581 /*
582 * An interrupt is only generated if bits are set that
583 * aren't already in the ICR, these bits are unmasked,
584 * and there isn't an interrupt already pending.
585 */
586 new = bits & ~sc->esc_ICR & sc->esc_IMS;
587 sc->esc_ICR |= bits;
588
589 if (new == 0) {
590 DPRINTF("icr assert: masked %x, ims %x", new, sc->esc_IMS);
591 } else if (sc->esc_mevpitr != NULL) {
592 DPRINTF("icr assert: throttled %x, ims %x", new, sc->esc_IMS);
593 } else if (!sc->esc_irq_asserted) {
594 DPRINTF("icr assert: lintr assert %x", new);
595 sc->esc_irq_asserted = 1;
596 pci_lintr_assert(sc->esc_pi);
597 if (sc->esc_ITR != 0) {
598 sc->esc_mevpitr = mevent_add(
599 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */
600 EVF_TIMER, e82545_itr_callback, sc);
601 }
602 }
603 }
604
605 static void
e82545_ims_change(struct e82545_softc * sc,uint32_t bits)606 e82545_ims_change(struct e82545_softc *sc, uint32_t bits)
607 {
608 uint32_t new;
609
610 /*
611 * Changing the mask may allow previously asserted
612 * but masked interrupt requests to generate an interrupt.
613 */
614 new = bits & sc->esc_ICR & ~sc->esc_IMS;
615 sc->esc_IMS |= bits;
616
617 if (new == 0) {
618 DPRINTF("ims change: masked %x, ims %x", new, sc->esc_IMS);
619 } else if (sc->esc_mevpitr != NULL) {
620 DPRINTF("ims change: throttled %x, ims %x", new, sc->esc_IMS);
621 } else if (!sc->esc_irq_asserted) {
622 DPRINTF("ims change: lintr assert %x", new);
623 sc->esc_irq_asserted = 1;
624 pci_lintr_assert(sc->esc_pi);
625 if (sc->esc_ITR != 0) {
626 sc->esc_mevpitr = mevent_add(
627 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */
628 EVF_TIMER, e82545_itr_callback, sc);
629 }
630 }
631 }
632
633 static void
e82545_icr_deassert(struct e82545_softc * sc,uint32_t bits)634 e82545_icr_deassert(struct e82545_softc *sc, uint32_t bits)
635 {
636
637 DPRINTF("icr deassert: 0x%x", bits);
638 sc->esc_ICR &= ~bits;
639
640 /*
641 * If there are no longer any interrupt sources and there
642 * was an asserted interrupt, clear it
643 */
644 if (sc->esc_irq_asserted && !(sc->esc_ICR & sc->esc_IMS)) {
645 DPRINTF("icr deassert: lintr deassert %x", bits);
646 pci_lintr_deassert(sc->esc_pi);
647 sc->esc_irq_asserted = 0;
648 }
649 }
650
651 static void
e82545_intr_write(struct e82545_softc * sc,uint32_t offset,uint32_t value)652 e82545_intr_write(struct e82545_softc *sc, uint32_t offset, uint32_t value)
653 {
654
655 DPRINTF("intr_write: off %x, val %x", offset, value);
656
657 switch (offset) {
658 case E1000_ICR:
659 e82545_icr_deassert(sc, value);
660 break;
661 case E1000_ITR:
662 sc->esc_ITR = value;
663 break;
664 case E1000_ICS:
665 sc->esc_ICS = value; /* not used: store for debug */
666 e82545_icr_assert(sc, value);
667 break;
668 case E1000_IMS:
669 e82545_ims_change(sc, value);
670 break;
671 case E1000_IMC:
672 sc->esc_IMC = value; /* for debug */
673 sc->esc_IMS &= ~value;
674 // XXX clear interrupts if all ICR bits now masked
675 // and interrupt was pending ?
676 break;
677 default:
678 break;
679 }
680 }
681
682 static uint32_t
e82545_intr_read(struct e82545_softc * sc,uint32_t offset)683 e82545_intr_read(struct e82545_softc *sc, uint32_t offset)
684 {
685 uint32_t retval;
686
687 retval = 0;
688
689 DPRINTF("intr_read: off %x", offset);
690
691 switch (offset) {
692 case E1000_ICR:
693 retval = sc->esc_ICR;
694 sc->esc_ICR = 0;
695 e82545_icr_deassert(sc, ~0);
696 break;
697 case E1000_ITR:
698 retval = sc->esc_ITR;
699 break;
700 case E1000_ICS:
701 /* write-only register */
702 break;
703 case E1000_IMS:
704 retval = sc->esc_IMS;
705 break;
706 case E1000_IMC:
707 /* write-only register */
708 break;
709 default:
710 break;
711 }
712
713 return (retval);
714 }
715
716 static void
e82545_devctl(struct e82545_softc * sc,uint32_t val)717 e82545_devctl(struct e82545_softc *sc, uint32_t val)
718 {
719
720 sc->esc_CTRL = val & ~E1000_CTRL_RST;
721
722 if (val & E1000_CTRL_RST) {
723 DPRINTF("e1k: s/w reset, ctl %x", val);
724 e82545_reset(sc, 1);
725 }
726 /* XXX check for phy reset ? */
727 }
728
729 static void
e82545_rx_update_rdba(struct e82545_softc * sc)730 e82545_rx_update_rdba(struct e82545_softc *sc)
731 {
732
733 /* XXX verify desc base/len within phys mem range */
734 sc->esc_rdba = (uint64_t)sc->esc_RDBAH << 32 |
735 sc->esc_RDBAL;
736
737 /* Cache host mapping of guest descriptor array */
738 sc->esc_rxdesc = paddr_guest2host(sc->esc_ctx,
739 sc->esc_rdba, sc->esc_RDLEN);
740 }
741
742 static void
e82545_rx_ctl(struct e82545_softc * sc,uint32_t val)743 e82545_rx_ctl(struct e82545_softc *sc, uint32_t val)
744 {
745 int on;
746
747 on = ((val & E1000_RCTL_EN) == E1000_RCTL_EN);
748
749 /* Save RCTL after stripping reserved bits 31:27,24,21,14,11:10,0 */
750 sc->esc_RCTL = val & ~0xF9204c01;
751
752 DPRINTF("rx_ctl - %s RCTL %x, val %x",
753 on ? "on" : "off", sc->esc_RCTL, val);
754
755 /* state change requested */
756 if (on != sc->esc_rx_enabled) {
757 if (on) {
758 /* Catch disallowed/unimplemented settings */
759 //assert(!(val & E1000_RCTL_LBM_TCVR));
760
761 if (sc->esc_RCTL & E1000_RCTL_LBM_TCVR) {
762 sc->esc_rx_loopback = 1;
763 } else {
764 sc->esc_rx_loopback = 0;
765 }
766
767 e82545_rx_update_rdba(sc);
768 e82545_rx_enable(sc);
769 } else {
770 e82545_rx_disable(sc);
771 sc->esc_rx_loopback = 0;
772 sc->esc_rdba = 0;
773 sc->esc_rxdesc = NULL;
774 }
775 }
776 }
777
778 static void
e82545_tx_update_tdba(struct e82545_softc * sc)779 e82545_tx_update_tdba(struct e82545_softc *sc)
780 {
781
782 /* XXX verify desc base/len within phys mem range */
783 sc->esc_tdba = (uint64_t)sc->esc_TDBAH << 32 | sc->esc_TDBAL;
784
785 /* Cache host mapping of guest descriptor array */
786 sc->esc_txdesc = paddr_guest2host(sc->esc_ctx, sc->esc_tdba,
787 sc->esc_TDLEN);
788 }
789
790 static void
e82545_tx_ctl(struct e82545_softc * sc,uint32_t val)791 e82545_tx_ctl(struct e82545_softc *sc, uint32_t val)
792 {
793 int on;
794
795 on = ((val & E1000_TCTL_EN) == E1000_TCTL_EN);
796
797 /* ignore TCTL_EN settings that don't change state */
798 if (on == sc->esc_tx_enabled)
799 return;
800
801 if (on) {
802 e82545_tx_update_tdba(sc);
803 e82545_tx_enable(sc);
804 } else {
805 e82545_tx_disable(sc);
806 sc->esc_tdba = 0;
807 sc->esc_txdesc = NULL;
808 }
809
810 /* Save TCTL value after stripping reserved bits 31:25,23,2,0 */
811 sc->esc_TCTL = val & ~0xFE800005;
812 }
813
814 static int
e82545_bufsz(uint32_t rctl)815 e82545_bufsz(uint32_t rctl)
816 {
817
818 switch (rctl & (E1000_RCTL_BSEX | E1000_RCTL_SZ_256)) {
819 case (E1000_RCTL_SZ_2048): return (2048);
820 case (E1000_RCTL_SZ_1024): return (1024);
821 case (E1000_RCTL_SZ_512): return (512);
822 case (E1000_RCTL_SZ_256): return (256);
823 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_16384): return (16384);
824 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_8192): return (8192);
825 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_4096): return (4096);
826 }
827 return (256); /* Forbidden value. */
828 }
829
830 /* XXX one packet at a time until this is debugged */
831 static void
e82545_rx_callback(int fd __unused,enum ev_type type __unused,void * param)832 e82545_rx_callback(int fd __unused, enum ev_type type __unused, void *param)
833 {
834 struct e82545_softc *sc = param;
835 struct e1000_rx_desc *rxd;
836 struct iovec vec[64];
837 ssize_t len;
838 int left, lim, maxpktsz, maxpktdesc, bufsz, i, n, size;
839 uint32_t cause = 0;
840 uint16_t *tp, tag, head;
841
842 pthread_mutex_lock(&sc->esc_mtx);
843 DPRINTF("rx_run: head %x, tail %x", sc->esc_RDH, sc->esc_RDT);
844
845 if (!sc->esc_rx_enabled || sc->esc_rx_loopback) {
846 DPRINTF("rx disabled (!%d || %d) -- packet(s) dropped",
847 sc->esc_rx_enabled, sc->esc_rx_loopback);
848 while (netbe_rx_discard(sc->esc_be) > 0) {
849 }
850 goto done1;
851 }
852 bufsz = e82545_bufsz(sc->esc_RCTL);
853 maxpktsz = (sc->esc_RCTL & E1000_RCTL_LPE) ? 16384 : 1522;
854 maxpktdesc = (maxpktsz + bufsz - 1) / bufsz;
855 size = sc->esc_RDLEN / 16;
856 head = sc->esc_RDH;
857 left = (size + sc->esc_RDT - head) % size;
858 if (left < maxpktdesc) {
859 DPRINTF("rx overflow (%d < %d) -- packet(s) dropped",
860 left, maxpktdesc);
861 while (netbe_rx_discard(sc->esc_be) > 0) {
862 }
863 goto done1;
864 }
865
866 sc->esc_rx_active = 1;
867 pthread_mutex_unlock(&sc->esc_mtx);
868
869 for (lim = size / 4; lim > 0 && left >= maxpktdesc; lim -= n) {
870
871 /* Grab rx descriptor pointed to by the head pointer */
872 for (i = 0; i < maxpktdesc; i++) {
873 rxd = &sc->esc_rxdesc[(head + i) % size];
874 vec[i].iov_base = paddr_guest2host(sc->esc_ctx,
875 rxd->buffer_addr, bufsz);
876 vec[i].iov_len = bufsz;
877 }
878 len = netbe_recv(sc->esc_be, vec, maxpktdesc);
879 if (len <= 0) {
880 DPRINTF("netbe_recv() returned %zd", len);
881 goto done;
882 }
883
884 /*
885 * Adjust the packet length based on whether the CRC needs
886 * to be stripped or if the packet is less than the minimum
887 * eth packet size.
888 */
889 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
890 len = ETHER_MIN_LEN - ETHER_CRC_LEN;
891 if (!(sc->esc_RCTL & E1000_RCTL_SECRC))
892 len += ETHER_CRC_LEN;
893 n = (len + bufsz - 1) / bufsz;
894
895 DPRINTF("packet read %zd bytes, %d segs, head %d",
896 len, n, head);
897
898 /* Apply VLAN filter. */
899 tp = (uint16_t *)vec[0].iov_base + 6;
900 if ((sc->esc_RCTL & E1000_RCTL_VFE) &&
901 (ntohs(tp[0]) == sc->esc_VET)) {
902 tag = ntohs(tp[1]) & 0x0fff;
903 if ((sc->esc_fvlan[tag >> 5] &
904 (1 << (tag & 0x1f))) != 0) {
905 DPRINTF("known VLAN %d", tag);
906 } else {
907 DPRINTF("unknown VLAN %d", tag);
908 n = 0;
909 continue;
910 }
911 }
912
913 /* Update all consumed descriptors. */
914 for (i = 0; i < n - 1; i++) {
915 rxd = &sc->esc_rxdesc[(head + i) % size];
916 rxd->length = bufsz;
917 rxd->csum = 0;
918 rxd->errors = 0;
919 rxd->special = 0;
920 rxd->status = E1000_RXD_STAT_DD;
921 }
922 rxd = &sc->esc_rxdesc[(head + i) % size];
923 rxd->length = len % bufsz;
924 rxd->csum = 0;
925 rxd->errors = 0;
926 rxd->special = 0;
927 /* XXX signal no checksum for now */
928 rxd->status = E1000_RXD_STAT_PIF | E1000_RXD_STAT_IXSM |
929 E1000_RXD_STAT_EOP | E1000_RXD_STAT_DD;
930
931 /* Schedule receive interrupts. */
932 if ((uint32_t)len <= sc->esc_RSRPD) {
933 cause |= E1000_ICR_SRPD | E1000_ICR_RXT0;
934 } else {
935 /* XXX: RDRT and RADV timers should be here. */
936 cause |= E1000_ICR_RXT0;
937 }
938
939 head = (head + n) % size;
940 left -= n;
941 }
942
943 done:
944 pthread_mutex_lock(&sc->esc_mtx);
945 sc->esc_rx_active = 0;
946 if (sc->esc_rx_enabled == 0)
947 pthread_cond_signal(&sc->esc_rx_cond);
948
949 sc->esc_RDH = head;
950 /* Respect E1000_RCTL_RDMTS */
951 left = (size + sc->esc_RDT - head) % size;
952 if (left < (size >> (((sc->esc_RCTL >> 8) & 3) + 1)))
953 cause |= E1000_ICR_RXDMT0;
954 /* Assert all accumulated interrupts. */
955 if (cause != 0)
956 e82545_icr_assert(sc, cause);
957 done1:
958 DPRINTF("rx_run done: head %x, tail %x", sc->esc_RDH, sc->esc_RDT);
959 pthread_mutex_unlock(&sc->esc_mtx);
960 }
961
962 static uint16_t
e82545_carry(uint32_t sum)963 e82545_carry(uint32_t sum)
964 {
965
966 sum = (sum & 0xFFFF) + (sum >> 16);
967 if (sum > 0xFFFF)
968 sum -= 0xFFFF;
969 return (sum);
970 }
971
972 static uint16_t
e82545_buf_checksum(uint8_t * buf,int len)973 e82545_buf_checksum(uint8_t *buf, int len)
974 {
975 int i;
976 uint32_t sum = 0;
977
978 /* Checksum all the pairs of bytes first... */
979 for (i = 0; i < (len & ~1); i += 2)
980 sum += *((u_int16_t *)(buf + i));
981
982 /*
983 * If there's a single byte left over, checksum it, too.
984 * Network byte order is big-endian, so the remaining byte is
985 * the high byte.
986 */
987 if (i < len)
988 sum += htons(buf[i] << 8);
989
990 return (e82545_carry(sum));
991 }
992
993 static uint16_t
e82545_iov_checksum(struct iovec * iov,int iovcnt,unsigned int off,unsigned int len)994 e82545_iov_checksum(struct iovec *iov, int iovcnt, unsigned int off,
995 unsigned int len)
996 {
997 unsigned int now, odd;
998 uint32_t sum = 0, s;
999
1000 /* Skip completely unneeded vectors. */
1001 while (iovcnt > 0 && iov->iov_len <= off && off > 0) {
1002 off -= iov->iov_len;
1003 iov++;
1004 iovcnt--;
1005 }
1006
1007 /* Calculate checksum of requested range. */
1008 odd = 0;
1009 while (len > 0 && iovcnt > 0) {
1010 now = MIN(len, iov->iov_len - off);
1011 s = e82545_buf_checksum((uint8_t *)iov->iov_base + off, now);
1012 sum += odd ? (s << 8) : s;
1013 odd ^= (now & 1);
1014 len -= now;
1015 off = 0;
1016 iov++;
1017 iovcnt--;
1018 }
1019
1020 return (e82545_carry(sum));
1021 }
1022
1023 /*
1024 * Return the transmit descriptor type.
1025 */
1026 static int
e82545_txdesc_type(uint32_t lower)1027 e82545_txdesc_type(uint32_t lower)
1028 {
1029 int type;
1030
1031 type = 0;
1032
1033 if (lower & E1000_TXD_CMD_DEXT)
1034 type = lower & E1000_TXD_MASK;
1035
1036 return (type);
1037 }
1038
1039 static void
e82545_transmit_checksum(struct iovec * iov,int iovcnt,struct ck_info * ck)1040 e82545_transmit_checksum(struct iovec *iov, int iovcnt, struct ck_info *ck)
1041 {
1042 uint16_t cksum;
1043 unsigned int cklen;
1044
1045 DPRINTF("tx cksum: iovcnt/s/off/len %d/%d/%d/%d",
1046 iovcnt, ck->ck_start, ck->ck_off, ck->ck_len);
1047 cklen = ck->ck_len ? ck->ck_len - ck->ck_start + 1U : UINT_MAX;
1048 cksum = e82545_iov_checksum(iov, iovcnt, ck->ck_start, cklen);
1049 *(uint16_t *)((uint8_t *)iov[0].iov_base + ck->ck_off) = ~cksum;
1050 }
1051
1052 static void
e82545_transmit_backend(struct e82545_softc * sc,struct iovec * iov,int iovcnt)1053 e82545_transmit_backend(struct e82545_softc *sc, struct iovec *iov, int iovcnt)
1054 {
1055
1056 if (sc->esc_be == NULL)
1057 return;
1058
1059 (void) netbe_send(sc->esc_be, iov, iovcnt);
1060 }
1061
1062 static void
e82545_transmit_done(struct e82545_softc * sc,uint16_t head,uint16_t tail,uint16_t dsize,int * tdwb)1063 e82545_transmit_done(struct e82545_softc *sc, uint16_t head, uint16_t tail,
1064 uint16_t dsize, int *tdwb)
1065 {
1066 union e1000_tx_udesc *dsc;
1067
1068 for ( ; head != tail; head = (head + 1) % dsize) {
1069 dsc = &sc->esc_txdesc[head];
1070 if (dsc->td.lower.data & E1000_TXD_CMD_RS) {
1071 dsc->td.upper.data |= E1000_TXD_STAT_DD;
1072 *tdwb = 1;
1073 }
1074 }
1075 }
1076
1077 static int
e82545_transmit(struct e82545_softc * sc,uint16_t head,uint16_t tail,uint16_t dsize,uint16_t * rhead,int * tdwb)1078 e82545_transmit(struct e82545_softc *sc, uint16_t head, uint16_t tail,
1079 uint16_t dsize, uint16_t *rhead, int *tdwb)
1080 {
1081 uint8_t *hdr, *hdrp;
1082 struct iovec iovb[I82545_MAX_TXSEGS + 2];
1083 struct iovec tiov[I82545_MAX_TXSEGS + 2];
1084 struct e1000_context_desc *cd;
1085 struct ck_info ckinfo[2];
1086 struct iovec *iov;
1087 union e1000_tx_udesc *dsc;
1088 int desc, dtype, ntype, iovcnt, tcp, tso, paylen, seg, tiovcnt, pv;
1089 unsigned hdrlen, vlen, pktlen, len, left, mss, now, nnow, nleft, pvoff;
1090 uint32_t tcpsum, tcpseq;
1091 uint16_t ipcs, tcpcs, ipid, ohead;
1092 bool invalid;
1093
1094 ckinfo[0].ck_valid = ckinfo[1].ck_valid = 0;
1095 iovcnt = 0;
1096 ntype = 0;
1097 tso = 0;
1098 pktlen = 0;
1099 ohead = head;
1100 invalid = false;
1101
1102 /* iovb[0/1] may be used for writable copy of headers. */
1103 iov = &iovb[2];
1104
1105 for (desc = 0; ; desc++, head = (head + 1) % dsize) {
1106 if (head == tail) {
1107 *rhead = head;
1108 return (0);
1109 }
1110 dsc = &sc->esc_txdesc[head];
1111 dtype = e82545_txdesc_type(dsc->td.lower.data);
1112
1113 if (desc == 0) {
1114 switch (dtype) {
1115 case E1000_TXD_TYP_C:
1116 DPRINTF("tx ctxt desc idx %d: %016jx "
1117 "%08x%08x",
1118 head, dsc->td.buffer_addr,
1119 dsc->td.upper.data, dsc->td.lower.data);
1120 /* Save context and return */
1121 sc->esc_txctx = dsc->cd;
1122 goto done;
1123 case E1000_TXD_TYP_L:
1124 DPRINTF("tx legacy desc idx %d: %08x%08x",
1125 head, dsc->td.upper.data, dsc->td.lower.data);
1126 /*
1127 * legacy cksum start valid in first descriptor
1128 */
1129 ntype = dtype;
1130 ckinfo[0].ck_start = dsc->td.upper.fields.css;
1131 break;
1132 case E1000_TXD_TYP_D:
1133 DPRINTF("tx data desc idx %d: %08x%08x",
1134 head, dsc->td.upper.data, dsc->td.lower.data);
1135 ntype = dtype;
1136 break;
1137 default:
1138 break;
1139 }
1140 } else {
1141 /* Descriptor type must be consistent */
1142 assert(dtype == ntype);
1143 DPRINTF("tx next desc idx %d: %08x%08x",
1144 head, dsc->td.upper.data, dsc->td.lower.data);
1145 }
1146
1147 len = (dtype == E1000_TXD_TYP_L) ? dsc->td.lower.flags.length :
1148 dsc->dd.lower.data & 0xFFFFF;
1149
1150 /* Strip checksum supplied by guest. */
1151 if ((dsc->td.lower.data & E1000_TXD_CMD_EOP) != 0 &&
1152 (dsc->td.lower.data & E1000_TXD_CMD_IFCS) == 0) {
1153 if (len <= 2) {
1154 WPRINTF("final descriptor too short (%d) -- dropped",
1155 len);
1156 invalid = true;
1157 } else
1158 len -= 2;
1159 }
1160
1161 if (len > 0 && iovcnt < I82545_MAX_TXSEGS) {
1162 iov[iovcnt].iov_base = paddr_guest2host(sc->esc_ctx,
1163 dsc->td.buffer_addr, len);
1164 iov[iovcnt].iov_len = len;
1165 iovcnt++;
1166 pktlen += len;
1167 }
1168
1169 /*
1170 * Pull out info that is valid in the final descriptor
1171 * and exit descriptor loop.
1172 */
1173 if (dsc->td.lower.data & E1000_TXD_CMD_EOP) {
1174 if (dtype == E1000_TXD_TYP_L) {
1175 if (dsc->td.lower.data & E1000_TXD_CMD_IC) {
1176 ckinfo[0].ck_valid = 1;
1177 ckinfo[0].ck_off =
1178 dsc->td.lower.flags.cso;
1179 ckinfo[0].ck_len = 0;
1180 }
1181 } else {
1182 cd = &sc->esc_txctx;
1183 if (dsc->dd.lower.data & E1000_TXD_CMD_TSE)
1184 tso = 1;
1185 if (dsc->dd.upper.fields.popts &
1186 E1000_TXD_POPTS_IXSM)
1187 ckinfo[0].ck_valid = 1;
1188 if (dsc->dd.upper.fields.popts &
1189 E1000_TXD_POPTS_IXSM || tso) {
1190 ckinfo[0].ck_start =
1191 cd->lower_setup.ip_fields.ipcss;
1192 ckinfo[0].ck_off =
1193 cd->lower_setup.ip_fields.ipcso;
1194 ckinfo[0].ck_len =
1195 cd->lower_setup.ip_fields.ipcse;
1196 }
1197 if (dsc->dd.upper.fields.popts &
1198 E1000_TXD_POPTS_TXSM)
1199 ckinfo[1].ck_valid = 1;
1200 if (dsc->dd.upper.fields.popts &
1201 E1000_TXD_POPTS_TXSM || tso) {
1202 ckinfo[1].ck_start =
1203 cd->upper_setup.tcp_fields.tucss;
1204 ckinfo[1].ck_off =
1205 cd->upper_setup.tcp_fields.tucso;
1206 ckinfo[1].ck_len =
1207 cd->upper_setup.tcp_fields.tucse;
1208 }
1209 }
1210 break;
1211 }
1212 }
1213
1214 if (invalid)
1215 goto done;
1216
1217 if (iovcnt > I82545_MAX_TXSEGS) {
1218 WPRINTF("tx too many descriptors (%d > %d) -- dropped",
1219 iovcnt, I82545_MAX_TXSEGS);
1220 goto done;
1221 }
1222
1223 hdrlen = vlen = 0;
1224 /* Estimate writable space for VLAN header insertion. */
1225 if ((sc->esc_CTRL & E1000_CTRL_VME) &&
1226 (dsc->td.lower.data & E1000_TXD_CMD_VLE)) {
1227 hdrlen = ETHER_ADDR_LEN*2;
1228 vlen = ETHER_VLAN_ENCAP_LEN;
1229 }
1230 if (!tso) {
1231 /* Estimate required writable space for checksums. */
1232 if (ckinfo[0].ck_valid)
1233 hdrlen = MAX(hdrlen, ckinfo[0].ck_off + 2U);
1234 if (ckinfo[1].ck_valid)
1235 hdrlen = MAX(hdrlen, ckinfo[1].ck_off + 2U);
1236 /* Round up writable space to the first vector. */
1237 if (hdrlen != 0 && iov[0].iov_len > hdrlen &&
1238 iov[0].iov_len < hdrlen + 100)
1239 hdrlen = iov[0].iov_len;
1240 } else {
1241 /* In case of TSO header length provided by software. */
1242 hdrlen = sc->esc_txctx.tcp_seg_setup.fields.hdr_len;
1243
1244 /*
1245 * Cap the header length at 240 based on 7.2.4.5 of
1246 * the Intel 82576EB (Rev 2.63) datasheet.
1247 */
1248 if (hdrlen > 240) {
1249 WPRINTF("TSO hdrlen too large: %d", hdrlen);
1250 goto done;
1251 }
1252
1253 /*
1254 * If VLAN insertion is requested, ensure the header
1255 * at least holds the amount of data copied during
1256 * VLAN insertion below.
1257 *
1258 * XXX: Realistic packets will include a full Ethernet
1259 * header before the IP header at ckinfo[0].ck_start,
1260 * but this check is sufficient to prevent
1261 * out-of-bounds access below.
1262 */
1263 if (vlen != 0 && hdrlen < ETHER_ADDR_LEN*2) {
1264 WPRINTF("TSO hdrlen too small for vlan insertion "
1265 "(%d vs %d) -- dropped", hdrlen,
1266 ETHER_ADDR_LEN*2);
1267 goto done;
1268 }
1269
1270 /*
1271 * Ensure that the header length covers the used fields
1272 * in the IP and TCP headers as well as the IP and TCP
1273 * checksums. The following fields are accessed below:
1274 *
1275 * Header | Field | Offset | Length
1276 * -------+-------+--------+-------
1277 * IPv4 | len | 2 | 2
1278 * IPv4 | ID | 4 | 2
1279 * IPv6 | len | 4 | 2
1280 * TCP | seq # | 4 | 4
1281 * TCP | flags | 13 | 1
1282 * UDP | len | 4 | 4
1283 */
1284 if (hdrlen < ckinfo[0].ck_start + 6U ||
1285 hdrlen < ckinfo[0].ck_off + 2U) {
1286 WPRINTF("TSO hdrlen too small for IP fields (%d) "
1287 "-- dropped", hdrlen);
1288 goto done;
1289 }
1290 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) {
1291 if (hdrlen < ckinfo[1].ck_start + 14U) {
1292 WPRINTF("TSO hdrlen too small for TCP fields "
1293 "(%d) -- dropped", hdrlen);
1294 goto done;
1295 }
1296 } else {
1297 if (hdrlen < ckinfo[1].ck_start + 8U) {
1298 WPRINTF("TSO hdrlen too small for UDP fields "
1299 "(%d) -- dropped", hdrlen);
1300 goto done;
1301 }
1302 }
1303 if (ckinfo[1].ck_valid && hdrlen < ckinfo[1].ck_off + 2U) {
1304 WPRINTF("TSO hdrlen too small for TCP/UDP fields "
1305 "(%d) -- dropped", hdrlen);
1306 goto done;
1307 }
1308 }
1309
1310 if (pktlen < hdrlen + vlen) {
1311 WPRINTF("packet too small for writable header");
1312 goto done;
1313 }
1314
1315 /* Allocate, fill and prepend writable header vector. */
1316 if (hdrlen + vlen != 0) {
1317 hdr = __builtin_alloca(hdrlen + vlen);
1318 hdr += vlen;
1319 for (left = hdrlen, hdrp = hdr; left > 0;
1320 left -= now, hdrp += now) {
1321 now = MIN(left, iov->iov_len);
1322 memcpy(hdrp, iov->iov_base, now);
1323 iov->iov_base = (uint8_t *)iov->iov_base + now;
1324 iov->iov_len -= now;
1325 if (iov->iov_len == 0) {
1326 iov++;
1327 iovcnt--;
1328 }
1329 }
1330 iov--;
1331 iovcnt++;
1332 iov->iov_base = hdr;
1333 iov->iov_len = hdrlen;
1334 } else
1335 hdr = NULL;
1336
1337 /* Insert VLAN tag. */
1338 if (vlen != 0) {
1339 hdr -= ETHER_VLAN_ENCAP_LEN;
1340 memmove(hdr, hdr + ETHER_VLAN_ENCAP_LEN, ETHER_ADDR_LEN*2);
1341 hdrlen += ETHER_VLAN_ENCAP_LEN;
1342 hdr[ETHER_ADDR_LEN*2 + 0] = sc->esc_VET >> 8;
1343 hdr[ETHER_ADDR_LEN*2 + 1] = sc->esc_VET & 0xff;
1344 hdr[ETHER_ADDR_LEN*2 + 2] = dsc->td.upper.fields.special >> 8;
1345 hdr[ETHER_ADDR_LEN*2 + 3] = dsc->td.upper.fields.special & 0xff;
1346 iov->iov_base = hdr;
1347 iov->iov_len += ETHER_VLAN_ENCAP_LEN;
1348 /* Correct checksum offsets after VLAN tag insertion. */
1349 ckinfo[0].ck_start += ETHER_VLAN_ENCAP_LEN;
1350 ckinfo[0].ck_off += ETHER_VLAN_ENCAP_LEN;
1351 if (ckinfo[0].ck_len != 0)
1352 ckinfo[0].ck_len += ETHER_VLAN_ENCAP_LEN;
1353 ckinfo[1].ck_start += ETHER_VLAN_ENCAP_LEN;
1354 ckinfo[1].ck_off += ETHER_VLAN_ENCAP_LEN;
1355 if (ckinfo[1].ck_len != 0)
1356 ckinfo[1].ck_len += ETHER_VLAN_ENCAP_LEN;
1357 }
1358
1359 /* Simple non-TSO case. */
1360 if (!tso) {
1361 /* Calculate checksums and transmit. */
1362 if (ckinfo[0].ck_valid)
1363 e82545_transmit_checksum(iov, iovcnt, &ckinfo[0]);
1364 if (ckinfo[1].ck_valid)
1365 e82545_transmit_checksum(iov, iovcnt, &ckinfo[1]);
1366 e82545_transmit_backend(sc, iov, iovcnt);
1367 goto done;
1368 }
1369
1370 /* Doing TSO. */
1371 tcp = (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) != 0;
1372 mss = sc->esc_txctx.tcp_seg_setup.fields.mss;
1373 paylen = (sc->esc_txctx.cmd_and_length & 0x000fffff);
1374 DPRINTF("tx %s segmentation offload %d+%d/%u bytes %d iovs",
1375 tcp ? "TCP" : "UDP", hdrlen, paylen, mss, iovcnt);
1376 ipid = ntohs(*(uint16_t *)&hdr[ckinfo[0].ck_start + 4]);
1377 tcpseq = 0;
1378 if (tcp)
1379 tcpseq = ntohl(*(uint32_t *)&hdr[ckinfo[1].ck_start + 4]);
1380 ipcs = *(uint16_t *)&hdr[ckinfo[0].ck_off];
1381 tcpcs = 0;
1382 if (ckinfo[1].ck_valid) /* Save partial pseudo-header checksum. */
1383 tcpcs = *(uint16_t *)&hdr[ckinfo[1].ck_off];
1384 pv = 1;
1385 pvoff = 0;
1386 for (seg = 0, left = paylen; left > 0; seg++, left -= now) {
1387 now = MIN(left, mss);
1388
1389 /* Construct IOVs for the segment. */
1390 /* Include whole original header. */
1391 tiov[0].iov_base = hdr;
1392 tiov[0].iov_len = hdrlen;
1393 tiovcnt = 1;
1394 /* Include respective part of payload IOV. */
1395 for (nleft = now; pv < iovcnt && nleft > 0; nleft -= nnow) {
1396 nnow = MIN(nleft, iov[pv].iov_len - pvoff);
1397 tiov[tiovcnt].iov_base = (uint8_t *)iov[pv].iov_base +
1398 pvoff;
1399 tiov[tiovcnt++].iov_len = nnow;
1400 if (pvoff + nnow == iov[pv].iov_len) {
1401 pv++;
1402 pvoff = 0;
1403 } else
1404 pvoff += nnow;
1405 }
1406 DPRINTF("tx segment %d %d+%d bytes %d iovs",
1407 seg, hdrlen, now, tiovcnt);
1408
1409 /* Update IP header. */
1410 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_IP) {
1411 /* IPv4 -- set length and ID */
1412 *(uint16_t *)&hdr[ckinfo[0].ck_start + 2] =
1413 htons(hdrlen - ckinfo[0].ck_start + now);
1414 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] =
1415 htons(ipid + seg);
1416 } else {
1417 /* IPv6 -- set length */
1418 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] =
1419 htons(hdrlen - ckinfo[0].ck_start - 40 +
1420 now);
1421 }
1422
1423 /* Update pseudo-header checksum. */
1424 tcpsum = tcpcs;
1425 tcpsum += htons(hdrlen - ckinfo[1].ck_start + now);
1426
1427 /* Update TCP/UDP headers. */
1428 if (tcp) {
1429 /* Update sequence number and FIN/PUSH flags. */
1430 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] =
1431 htonl(tcpseq + paylen - left);
1432 if (now < left) {
1433 hdr[ckinfo[1].ck_start + 13] &=
1434 ~(TH_FIN | TH_PUSH);
1435 }
1436 } else {
1437 /* Update payload length. */
1438 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] =
1439 hdrlen - ckinfo[1].ck_start + now;
1440 }
1441
1442 /* Calculate checksums and transmit. */
1443 if (ckinfo[0].ck_valid) {
1444 *(uint16_t *)&hdr[ckinfo[0].ck_off] = ipcs;
1445 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[0]);
1446 }
1447 if (ckinfo[1].ck_valid) {
1448 *(uint16_t *)&hdr[ckinfo[1].ck_off] =
1449 e82545_carry(tcpsum);
1450 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[1]);
1451 }
1452 e82545_transmit_backend(sc, tiov, tiovcnt);
1453 }
1454
1455 done:
1456 head = (head + 1) % dsize;
1457 e82545_transmit_done(sc, ohead, head, dsize, tdwb);
1458
1459 *rhead = head;
1460 return (desc + 1);
1461 }
1462
1463 static void
e82545_tx_run(struct e82545_softc * sc)1464 e82545_tx_run(struct e82545_softc *sc)
1465 {
1466 uint32_t cause;
1467 uint16_t head, rhead, tail, size;
1468 int lim, tdwb, sent;
1469
1470 size = sc->esc_TDLEN / 16;
1471 if (size == 0)
1472 return;
1473
1474 head = sc->esc_TDH % size;
1475 tail = sc->esc_TDT % size;
1476 DPRINTF("tx_run: head %x, rhead %x, tail %x",
1477 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT);
1478
1479 pthread_mutex_unlock(&sc->esc_mtx);
1480 rhead = head;
1481 tdwb = 0;
1482 for (lim = size / 4; sc->esc_tx_enabled && lim > 0; lim -= sent) {
1483 sent = e82545_transmit(sc, head, tail, size, &rhead, &tdwb);
1484 if (sent == 0)
1485 break;
1486 head = rhead;
1487 }
1488 pthread_mutex_lock(&sc->esc_mtx);
1489
1490 sc->esc_TDH = head;
1491 sc->esc_TDHr = rhead;
1492 cause = 0;
1493 if (tdwb)
1494 cause |= E1000_ICR_TXDW;
1495 if (lim != size / 4 && sc->esc_TDH == sc->esc_TDT)
1496 cause |= E1000_ICR_TXQE;
1497 if (cause)
1498 e82545_icr_assert(sc, cause);
1499
1500 DPRINTF("tx_run done: head %x, rhead %x, tail %x",
1501 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT);
1502 }
1503
1504 static _Noreturn void *
e82545_tx_thread(void * param)1505 e82545_tx_thread(void *param)
1506 {
1507 struct e82545_softc *sc = param;
1508
1509 pthread_mutex_lock(&sc->esc_mtx);
1510 for (;;) {
1511 while (!sc->esc_tx_enabled || sc->esc_TDHr == sc->esc_TDT) {
1512 if (sc->esc_tx_enabled && sc->esc_TDHr != sc->esc_TDT)
1513 break;
1514 sc->esc_tx_active = 0;
1515 if (sc->esc_tx_enabled == 0)
1516 pthread_cond_signal(&sc->esc_tx_cond);
1517 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx);
1518 }
1519 sc->esc_tx_active = 1;
1520
1521 /* Process some tx descriptors. Lock dropped inside. */
1522 e82545_tx_run(sc);
1523 }
1524 }
1525
1526 static void
e82545_tx_start(struct e82545_softc * sc)1527 e82545_tx_start(struct e82545_softc *sc)
1528 {
1529
1530 if (sc->esc_tx_active == 0)
1531 pthread_cond_signal(&sc->esc_tx_cond);
1532 }
1533
1534 static void
e82545_tx_enable(struct e82545_softc * sc)1535 e82545_tx_enable(struct e82545_softc *sc)
1536 {
1537
1538 sc->esc_tx_enabled = 1;
1539 }
1540
1541 static void
e82545_tx_disable(struct e82545_softc * sc)1542 e82545_tx_disable(struct e82545_softc *sc)
1543 {
1544
1545 sc->esc_tx_enabled = 0;
1546 while (sc->esc_tx_active)
1547 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx);
1548 }
1549
1550 static void
e82545_rx_enable(struct e82545_softc * sc)1551 e82545_rx_enable(struct e82545_softc *sc)
1552 {
1553
1554 sc->esc_rx_enabled = 1;
1555 }
1556
1557 static void
e82545_rx_disable(struct e82545_softc * sc)1558 e82545_rx_disable(struct e82545_softc *sc)
1559 {
1560
1561 sc->esc_rx_enabled = 0;
1562 while (sc->esc_rx_active)
1563 pthread_cond_wait(&sc->esc_rx_cond, &sc->esc_mtx);
1564 }
1565
1566 static void
e82545_write_ra(struct e82545_softc * sc,int reg,uint32_t wval)1567 e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval)
1568 {
1569 struct eth_uni *eu;
1570 int idx;
1571
1572 idx = reg >> 1;
1573 assert(idx < 15);
1574
1575 eu = &sc->esc_uni[idx];
1576
1577 if (reg & 0x1) {
1578 /* RAH */
1579 eu->eu_valid = ((wval & E1000_RAH_AV) == E1000_RAH_AV);
1580 eu->eu_addrsel = (wval >> 16) & 0x3;
1581 eu->eu_eth.octet[5] = wval >> 8;
1582 eu->eu_eth.octet[4] = wval;
1583 } else {
1584 /* RAL */
1585 eu->eu_eth.octet[3] = wval >> 24;
1586 eu->eu_eth.octet[2] = wval >> 16;
1587 eu->eu_eth.octet[1] = wval >> 8;
1588 eu->eu_eth.octet[0] = wval;
1589 }
1590 }
1591
1592 static uint32_t
e82545_read_ra(struct e82545_softc * sc,int reg)1593 e82545_read_ra(struct e82545_softc *sc, int reg)
1594 {
1595 struct eth_uni *eu;
1596 uint32_t retval;
1597 int idx;
1598
1599 idx = reg >> 1;
1600 assert(idx < 15);
1601
1602 eu = &sc->esc_uni[idx];
1603
1604 if (reg & 0x1) {
1605 /* RAH */
1606 retval = (eu->eu_valid << 31) |
1607 (eu->eu_addrsel << 16) |
1608 (eu->eu_eth.octet[5] << 8) |
1609 eu->eu_eth.octet[4];
1610 } else {
1611 /* RAL */
1612 retval = (eu->eu_eth.octet[3] << 24) |
1613 (eu->eu_eth.octet[2] << 16) |
1614 (eu->eu_eth.octet[1] << 8) |
1615 eu->eu_eth.octet[0];
1616 }
1617
1618 return (retval);
1619 }
1620
1621 static void
e82545_write_register(struct e82545_softc * sc,uint32_t offset,uint32_t value)1622 e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value)
1623 {
1624 int ridx;
1625
1626 if (offset & 0x3) {
1627 DPRINTF("Unaligned register write offset:0x%x value:0x%x", offset, value);
1628 return;
1629 }
1630 DPRINTF("Register write: 0x%x value: 0x%x", offset, value);
1631
1632 switch (offset) {
1633 case E1000_CTRL:
1634 case E1000_CTRL_DUP:
1635 e82545_devctl(sc, value);
1636 break;
1637 case E1000_FCAL:
1638 sc->esc_FCAL = value;
1639 break;
1640 case E1000_FCAH:
1641 sc->esc_FCAH = value & ~0xFFFF0000;
1642 break;
1643 case E1000_FCT:
1644 sc->esc_FCT = value & ~0xFFFF0000;
1645 break;
1646 case E1000_VET:
1647 sc->esc_VET = value & ~0xFFFF0000;
1648 break;
1649 case E1000_FCTTV:
1650 sc->esc_FCTTV = value & ~0xFFFF0000;
1651 break;
1652 case E1000_LEDCTL:
1653 sc->esc_LEDCTL = value & ~0x30303000;
1654 break;
1655 case E1000_PBA:
1656 sc->esc_PBA = value & 0x0000FF80;
1657 break;
1658 case E1000_ICR:
1659 case E1000_ITR:
1660 case E1000_ICS:
1661 case E1000_IMS:
1662 case E1000_IMC:
1663 e82545_intr_write(sc, offset, value);
1664 break;
1665 case E1000_RCTL:
1666 e82545_rx_ctl(sc, value);
1667 break;
1668 case E1000_FCRTL:
1669 sc->esc_FCRTL = value & ~0xFFFF0007;
1670 break;
1671 case E1000_FCRTH:
1672 sc->esc_FCRTH = value & ~0xFFFF0007;
1673 break;
1674 case E1000_RDBAL(0):
1675 sc->esc_RDBAL = value & ~0xF;
1676 if (sc->esc_rx_enabled) {
1677 /* Apparently legal: update cached address */
1678 e82545_rx_update_rdba(sc);
1679 }
1680 break;
1681 case E1000_RDBAH(0):
1682 assert(!sc->esc_rx_enabled);
1683 sc->esc_RDBAH = value;
1684 break;
1685 case E1000_RDLEN(0):
1686 assert(!sc->esc_rx_enabled);
1687 sc->esc_RDLEN = value & ~0xFFF0007F;
1688 break;
1689 case E1000_RDH(0):
1690 /* XXX should only ever be zero ? Range check ? */
1691 sc->esc_RDH = value;
1692 break;
1693 case E1000_RDT(0):
1694 /* XXX if this opens up the rx ring, do something ? */
1695 sc->esc_RDT = value;
1696 break;
1697 case E1000_RDTR:
1698 /* ignore FPD bit 31 */
1699 sc->esc_RDTR = value & ~0xFFFF0000;
1700 break;
1701 case E1000_RXDCTL(0):
1702 sc->esc_RXDCTL = value & ~0xFEC0C0C0;
1703 break;
1704 case E1000_RADV:
1705 sc->esc_RADV = value & ~0xFFFF0000;
1706 break;
1707 case E1000_RSRPD:
1708 sc->esc_RSRPD = value & ~0xFFFFF000;
1709 break;
1710 case E1000_RXCSUM:
1711 sc->esc_RXCSUM = value & ~0xFFFFF800;
1712 break;
1713 case E1000_TXCW:
1714 sc->esc_TXCW = value & ~0x3FFF0000;
1715 break;
1716 case E1000_TCTL:
1717 e82545_tx_ctl(sc, value);
1718 break;
1719 case E1000_TIPG:
1720 sc->esc_TIPG = value;
1721 break;
1722 case E1000_AIT:
1723 sc->esc_AIT = value;
1724 break;
1725 case E1000_TDBAL(0):
1726 sc->esc_TDBAL = value & ~0xF;
1727 if (sc->esc_tx_enabled)
1728 e82545_tx_update_tdba(sc);
1729 break;
1730 case E1000_TDBAH(0):
1731 sc->esc_TDBAH = value;
1732 if (sc->esc_tx_enabled)
1733 e82545_tx_update_tdba(sc);
1734 break;
1735 case E1000_TDLEN(0):
1736 sc->esc_TDLEN = value & ~0xFFF0007F;
1737 if (sc->esc_tx_enabled)
1738 e82545_tx_update_tdba(sc);
1739 break;
1740 case E1000_TDH(0):
1741 if (sc->esc_tx_enabled) {
1742 WPRINTF("ignoring write to TDH while transmit enabled");
1743 break;
1744 }
1745 if (value != 0) {
1746 WPRINTF("ignoring non-zero value written to TDH");
1747 break;
1748 }
1749 sc->esc_TDHr = sc->esc_TDH = value;
1750 break;
1751 case E1000_TDT(0):
1752 sc->esc_TDT = value;
1753 if (sc->esc_tx_enabled)
1754 e82545_tx_start(sc);
1755 break;
1756 case E1000_TIDV:
1757 sc->esc_TIDV = value & ~0xFFFF0000;
1758 break;
1759 case E1000_TXDCTL(0):
1760 //assert(!sc->esc_tx_enabled);
1761 sc->esc_TXDCTL = value & ~0xC0C0C0;
1762 break;
1763 case E1000_TADV:
1764 sc->esc_TADV = value & ~0xFFFF0000;
1765 break;
1766 case E1000_RAL(0) ... E1000_RAH(15):
1767 /* convert to u32 offset */
1768 ridx = (offset - E1000_RAL(0)) >> 2;
1769 e82545_write_ra(sc, ridx, value);
1770 break;
1771 case E1000_MTA ... (E1000_MTA + (127*4)):
1772 sc->esc_fmcast[(offset - E1000_MTA) >> 2] = value;
1773 break;
1774 case E1000_VFTA ... (E1000_VFTA + (127*4)):
1775 sc->esc_fvlan[(offset - E1000_VFTA) >> 2] = value;
1776 break;
1777 case E1000_EECD:
1778 {
1779 //DPRINTF("EECD write 0x%x -> 0x%x", sc->eeprom_control, value);
1780 /* edge triggered low->high */
1781 uint32_t eecd_strobe = ((sc->eeprom_control & E1000_EECD_SK) ?
1782 0 : (value & E1000_EECD_SK));
1783 uint32_t eecd_mask = (E1000_EECD_SK|E1000_EECD_CS|
1784 E1000_EECD_DI|E1000_EECD_REQ);
1785 sc->eeprom_control &= ~eecd_mask;
1786 sc->eeprom_control |= (value & eecd_mask);
1787 /* grant/revoke immediately */
1788 if (value & E1000_EECD_REQ) {
1789 sc->eeprom_control |= E1000_EECD_GNT;
1790 } else {
1791 sc->eeprom_control &= ~E1000_EECD_GNT;
1792 }
1793 if (eecd_strobe && (sc->eeprom_control & E1000_EECD_CS)) {
1794 e82545_eecd_strobe(sc);
1795 }
1796 return;
1797 }
1798 case E1000_MDIC:
1799 {
1800 uint8_t reg_addr = (uint8_t)((value & E1000_MDIC_REG_MASK) >>
1801 E1000_MDIC_REG_SHIFT);
1802 uint8_t phy_addr = (uint8_t)((value & E1000_MDIC_PHY_MASK) >>
1803 E1000_MDIC_PHY_SHIFT);
1804 sc->mdi_control =
1805 (value & ~(E1000_MDIC_ERROR|E1000_MDIC_DEST));
1806 if ((value & E1000_MDIC_READY) != 0) {
1807 DPRINTF("Incorrect MDIC ready bit: 0x%x", value);
1808 return;
1809 }
1810 switch (value & E82545_MDIC_OP_MASK) {
1811 case E1000_MDIC_OP_READ:
1812 sc->mdi_control &= ~E82545_MDIC_DATA_MASK;
1813 sc->mdi_control |= e82545_read_mdi(sc, reg_addr, phy_addr);
1814 break;
1815 case E1000_MDIC_OP_WRITE:
1816 e82545_write_mdi(sc, reg_addr, phy_addr,
1817 value & E82545_MDIC_DATA_MASK);
1818 break;
1819 default:
1820 DPRINTF("Unknown MDIC op: 0x%x", value);
1821 return;
1822 }
1823 /* TODO: barrier? */
1824 sc->mdi_control |= E1000_MDIC_READY;
1825 if (value & E82545_MDIC_IE) {
1826 // TODO: generate interrupt
1827 }
1828 return;
1829 }
1830 case E1000_MANC:
1831 case E1000_STATUS:
1832 return;
1833 default:
1834 DPRINTF("Unknown write register: 0x%x value:%x", offset, value);
1835 return;
1836 }
1837 }
1838
1839 static uint32_t
e82545_read_register(struct e82545_softc * sc,uint32_t offset)1840 e82545_read_register(struct e82545_softc *sc, uint32_t offset)
1841 {
1842 uint32_t retval;
1843 int ridx;
1844
1845 if (offset & 0x3) {
1846 DPRINTF("Unaligned register read offset:0x%x", offset);
1847 return 0;
1848 }
1849
1850 DPRINTF("Register read: 0x%x", offset);
1851
1852 switch (offset) {
1853 case E1000_CTRL:
1854 retval = sc->esc_CTRL;
1855 break;
1856 case E1000_STATUS:
1857 retval = E1000_STATUS_FD | E1000_STATUS_LU |
1858 E1000_STATUS_SPEED_1000;
1859 break;
1860 case E1000_FCAL:
1861 retval = sc->esc_FCAL;
1862 break;
1863 case E1000_FCAH:
1864 retval = sc->esc_FCAH;
1865 break;
1866 case E1000_FCT:
1867 retval = sc->esc_FCT;
1868 break;
1869 case E1000_VET:
1870 retval = sc->esc_VET;
1871 break;
1872 case E1000_FCTTV:
1873 retval = sc->esc_FCTTV;
1874 break;
1875 case E1000_LEDCTL:
1876 retval = sc->esc_LEDCTL;
1877 break;
1878 case E1000_PBA:
1879 retval = sc->esc_PBA;
1880 break;
1881 case E1000_ICR:
1882 case E1000_ITR:
1883 case E1000_ICS:
1884 case E1000_IMS:
1885 case E1000_IMC:
1886 retval = e82545_intr_read(sc, offset);
1887 break;
1888 case E1000_RCTL:
1889 retval = sc->esc_RCTL;
1890 break;
1891 case E1000_FCRTL:
1892 retval = sc->esc_FCRTL;
1893 break;
1894 case E1000_FCRTH:
1895 retval = sc->esc_FCRTH;
1896 break;
1897 case E1000_RDBAL(0):
1898 retval = sc->esc_RDBAL;
1899 break;
1900 case E1000_RDBAH(0):
1901 retval = sc->esc_RDBAH;
1902 break;
1903 case E1000_RDLEN(0):
1904 retval = sc->esc_RDLEN;
1905 break;
1906 case E1000_RDH(0):
1907 retval = sc->esc_RDH;
1908 break;
1909 case E1000_RDT(0):
1910 retval = sc->esc_RDT;
1911 break;
1912 case E1000_RDTR:
1913 retval = sc->esc_RDTR;
1914 break;
1915 case E1000_RXDCTL(0):
1916 retval = sc->esc_RXDCTL;
1917 break;
1918 case E1000_RADV:
1919 retval = sc->esc_RADV;
1920 break;
1921 case E1000_RSRPD:
1922 retval = sc->esc_RSRPD;
1923 break;
1924 case E1000_RXCSUM:
1925 retval = sc->esc_RXCSUM;
1926 break;
1927 case E1000_TXCW:
1928 retval = sc->esc_TXCW;
1929 break;
1930 case E1000_TCTL:
1931 retval = sc->esc_TCTL;
1932 break;
1933 case E1000_TIPG:
1934 retval = sc->esc_TIPG;
1935 break;
1936 case E1000_AIT:
1937 retval = sc->esc_AIT;
1938 break;
1939 case E1000_TDBAL(0):
1940 retval = sc->esc_TDBAL;
1941 break;
1942 case E1000_TDBAH(0):
1943 retval = sc->esc_TDBAH;
1944 break;
1945 case E1000_TDLEN(0):
1946 retval = sc->esc_TDLEN;
1947 break;
1948 case E1000_TDH(0):
1949 retval = sc->esc_TDH;
1950 break;
1951 case E1000_TDT(0):
1952 retval = sc->esc_TDT;
1953 break;
1954 case E1000_TIDV:
1955 retval = sc->esc_TIDV;
1956 break;
1957 case E1000_TXDCTL(0):
1958 retval = sc->esc_TXDCTL;
1959 break;
1960 case E1000_TADV:
1961 retval = sc->esc_TADV;
1962 break;
1963 case E1000_RAL(0) ... E1000_RAH(15):
1964 /* convert to u32 offset */
1965 ridx = (offset - E1000_RAL(0)) >> 2;
1966 retval = e82545_read_ra(sc, ridx);
1967 break;
1968 case E1000_MTA ... (E1000_MTA + (127*4)):
1969 retval = sc->esc_fmcast[(offset - E1000_MTA) >> 2];
1970 break;
1971 case E1000_VFTA ... (E1000_VFTA + (127*4)):
1972 retval = sc->esc_fvlan[(offset - E1000_VFTA) >> 2];
1973 break;
1974 case E1000_EECD:
1975 //DPRINTF("EECD read %x", sc->eeprom_control);
1976 retval = sc->eeprom_control;
1977 break;
1978 case E1000_MDIC:
1979 retval = sc->mdi_control;
1980 break;
1981 case E1000_MANC:
1982 retval = 0;
1983 break;
1984 /* stats that we emulate. */
1985 case E1000_MPC:
1986 retval = sc->missed_pkt_count;
1987 break;
1988 case E1000_PRC64:
1989 retval = sc->pkt_rx_by_size[0];
1990 break;
1991 case E1000_PRC127:
1992 retval = sc->pkt_rx_by_size[1];
1993 break;
1994 case E1000_PRC255:
1995 retval = sc->pkt_rx_by_size[2];
1996 break;
1997 case E1000_PRC511:
1998 retval = sc->pkt_rx_by_size[3];
1999 break;
2000 case E1000_PRC1023:
2001 retval = sc->pkt_rx_by_size[4];
2002 break;
2003 case E1000_PRC1522:
2004 retval = sc->pkt_rx_by_size[5];
2005 break;
2006 case E1000_GPRC:
2007 retval = sc->good_pkt_rx_count;
2008 break;
2009 case E1000_BPRC:
2010 retval = sc->bcast_pkt_rx_count;
2011 break;
2012 case E1000_MPRC:
2013 retval = sc->mcast_pkt_rx_count;
2014 break;
2015 case E1000_GPTC:
2016 case E1000_TPT:
2017 retval = sc->good_pkt_tx_count;
2018 break;
2019 case E1000_GORCL:
2020 retval = (uint32_t)sc->good_octets_rx;
2021 break;
2022 case E1000_GORCH:
2023 retval = (uint32_t)(sc->good_octets_rx >> 32);
2024 break;
2025 case E1000_TOTL:
2026 case E1000_GOTCL:
2027 retval = (uint32_t)sc->good_octets_tx;
2028 break;
2029 case E1000_TOTH:
2030 case E1000_GOTCH:
2031 retval = (uint32_t)(sc->good_octets_tx >> 32);
2032 break;
2033 case E1000_ROC:
2034 retval = sc->oversize_rx_count;
2035 break;
2036 case E1000_TORL:
2037 retval = (uint32_t)(sc->good_octets_rx + sc->missed_octets);
2038 break;
2039 case E1000_TORH:
2040 retval = (uint32_t)((sc->good_octets_rx +
2041 sc->missed_octets) >> 32);
2042 break;
2043 case E1000_TPR:
2044 retval = sc->good_pkt_rx_count + sc->missed_pkt_count +
2045 sc->oversize_rx_count;
2046 break;
2047 case E1000_PTC64:
2048 retval = sc->pkt_tx_by_size[0];
2049 break;
2050 case E1000_PTC127:
2051 retval = sc->pkt_tx_by_size[1];
2052 break;
2053 case E1000_PTC255:
2054 retval = sc->pkt_tx_by_size[2];
2055 break;
2056 case E1000_PTC511:
2057 retval = sc->pkt_tx_by_size[3];
2058 break;
2059 case E1000_PTC1023:
2060 retval = sc->pkt_tx_by_size[4];
2061 break;
2062 case E1000_PTC1522:
2063 retval = sc->pkt_tx_by_size[5];
2064 break;
2065 case E1000_MPTC:
2066 retval = sc->mcast_pkt_tx_count;
2067 break;
2068 case E1000_BPTC:
2069 retval = sc->bcast_pkt_tx_count;
2070 break;
2071 case E1000_TSCTC:
2072 retval = sc->tso_tx_count;
2073 break;
2074 /* stats that are always 0. */
2075 case E1000_CRCERRS:
2076 case E1000_ALGNERRC:
2077 case E1000_SYMERRS:
2078 case E1000_RXERRC:
2079 case E1000_SCC:
2080 case E1000_ECOL:
2081 case E1000_MCC:
2082 case E1000_LATECOL:
2083 case E1000_COLC:
2084 case E1000_DC:
2085 case E1000_TNCRS:
2086 case E1000_SEC:
2087 case E1000_CEXTERR:
2088 case E1000_RLEC:
2089 case E1000_XONRXC:
2090 case E1000_XONTXC:
2091 case E1000_XOFFRXC:
2092 case E1000_XOFFTXC:
2093 case E1000_FCRUC:
2094 case E1000_RNBC:
2095 case E1000_RUC:
2096 case E1000_RFC:
2097 case E1000_RJC:
2098 case E1000_MGTPRC:
2099 case E1000_MGTPDC:
2100 case E1000_MGTPTC:
2101 case E1000_TSCTFC:
2102 retval = 0;
2103 break;
2104 default:
2105 DPRINTF("Unknown read register: 0x%x", offset);
2106 retval = 0;
2107 break;
2108 }
2109
2110 return (retval);
2111 }
2112
2113 static void
e82545_write(struct pci_devinst * pi,int baridx,uint64_t offset,int size,uint64_t value)2114 e82545_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
2115 uint64_t value)
2116 {
2117 struct e82545_softc *sc;
2118
2119 //DPRINTF("Write bar:%d offset:0x%lx value:0x%lx size:%d", baridx, offset, value, size);
2120
2121 sc = pi->pi_arg;
2122
2123 pthread_mutex_lock(&sc->esc_mtx);
2124
2125 switch (baridx) {
2126 case E82545_BAR_IO:
2127 switch (offset) {
2128 case E82545_IOADDR:
2129 if (size != 4) {
2130 DPRINTF("Wrong io addr write sz:%d value:0x%lx", size, value);
2131 } else
2132 sc->io_addr = (uint32_t)value;
2133 break;
2134 case E82545_IODATA:
2135 if (size != 4) {
2136 DPRINTF("Wrong io data write size:%d value:0x%lx", size, value);
2137 } else if (sc->io_addr > E82545_IO_REGISTER_MAX) {
2138 DPRINTF("Non-register io write addr:0x%x value:0x%lx", sc->io_addr, value);
2139 } else
2140 e82545_write_register(sc, sc->io_addr,
2141 (uint32_t)value);
2142 break;
2143 default:
2144 DPRINTF("Unknown io bar write offset:0x%lx value:0x%lx size:%d", offset, value, size);
2145 break;
2146 }
2147 break;
2148 case E82545_BAR_REGISTER:
2149 if (size != 4) {
2150 DPRINTF("Wrong register write size:%d offset:0x%lx value:0x%lx", size, offset, value);
2151 } else
2152 e82545_write_register(sc, (uint32_t)offset,
2153 (uint32_t)value);
2154 break;
2155 default:
2156 DPRINTF("Unknown write bar:%d off:0x%lx val:0x%lx size:%d",
2157 baridx, offset, value, size);
2158 }
2159
2160 pthread_mutex_unlock(&sc->esc_mtx);
2161 }
2162
2163 static uint64_t
e82545_read(struct pci_devinst * pi,int baridx,uint64_t offset,int size)2164 e82545_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
2165 {
2166 struct e82545_softc *sc;
2167 uint64_t retval;
2168
2169 //DPRINTF("Read bar:%d offset:0x%lx size:%d", baridx, offset, size);
2170 sc = pi->pi_arg;
2171 retval = 0;
2172
2173 pthread_mutex_lock(&sc->esc_mtx);
2174
2175 switch (baridx) {
2176 case E82545_BAR_IO:
2177 switch (offset) {
2178 case E82545_IOADDR:
2179 if (size != 4) {
2180 DPRINTF("Wrong io addr read sz:%d", size);
2181 } else
2182 retval = sc->io_addr;
2183 break;
2184 case E82545_IODATA:
2185 if (size != 4) {
2186 DPRINTF("Wrong io data read sz:%d", size);
2187 }
2188 if (sc->io_addr > E82545_IO_REGISTER_MAX) {
2189 DPRINTF("Non-register io read addr:0x%x",
2190 sc->io_addr);
2191 } else
2192 retval = e82545_read_register(sc, sc->io_addr);
2193 break;
2194 default:
2195 DPRINTF("Unknown io bar read offset:0x%lx size:%d",
2196 offset, size);
2197 break;
2198 }
2199 break;
2200 case E82545_BAR_REGISTER:
2201 if (size != 4) {
2202 DPRINTF("Wrong register read size:%d offset:0x%lx",
2203 size, offset);
2204 } else
2205 retval = e82545_read_register(sc, (uint32_t)offset);
2206 break;
2207 default:
2208 DPRINTF("Unknown read bar:%d offset:0x%lx size:%d",
2209 baridx, offset, size);
2210 break;
2211 }
2212
2213 pthread_mutex_unlock(&sc->esc_mtx);
2214
2215 return (retval);
2216 }
2217
2218 static void
e82545_reset(struct e82545_softc * sc,int drvr)2219 e82545_reset(struct e82545_softc *sc, int drvr)
2220 {
2221 int i;
2222
2223 e82545_rx_disable(sc);
2224 e82545_tx_disable(sc);
2225
2226 /* clear outstanding interrupts */
2227 if (sc->esc_irq_asserted)
2228 pci_lintr_deassert(sc->esc_pi);
2229
2230 /* misc */
2231 if (!drvr) {
2232 sc->esc_FCAL = 0;
2233 sc->esc_FCAH = 0;
2234 sc->esc_FCT = 0;
2235 sc->esc_VET = 0;
2236 sc->esc_FCTTV = 0;
2237 }
2238 sc->esc_LEDCTL = 0x07061302;
2239 sc->esc_PBA = 0x00100030;
2240
2241 /* start nvm in opcode mode. */
2242 sc->nvm_opaddr = 0;
2243 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
2244 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
2245 sc->eeprom_control = E1000_EECD_PRES | E82545_EECD_FWE_EN;
2246 e82545_init_eeprom(sc);
2247
2248 /* interrupt */
2249 sc->esc_ICR = 0;
2250 sc->esc_ITR = 250;
2251 sc->esc_ICS = 0;
2252 sc->esc_IMS = 0;
2253 sc->esc_IMC = 0;
2254
2255 /* L2 filters */
2256 if (!drvr) {
2257 memset(sc->esc_fvlan, 0, sizeof(sc->esc_fvlan));
2258 memset(sc->esc_fmcast, 0, sizeof(sc->esc_fmcast));
2259 memset(sc->esc_uni, 0, sizeof(sc->esc_uni));
2260
2261 /* XXX not necessary on 82545 ?? */
2262 sc->esc_uni[0].eu_valid = 1;
2263 memcpy(sc->esc_uni[0].eu_eth.octet, sc->esc_mac.octet,
2264 ETHER_ADDR_LEN);
2265 } else {
2266 /* Clear RAH valid bits */
2267 for (i = 0; i < 16; i++)
2268 sc->esc_uni[i].eu_valid = 0;
2269 }
2270
2271 /* receive */
2272 if (!drvr) {
2273 sc->esc_RDBAL = 0;
2274 sc->esc_RDBAH = 0;
2275 }
2276 sc->esc_RCTL = 0;
2277 sc->esc_FCRTL = 0;
2278 sc->esc_FCRTH = 0;
2279 sc->esc_RDLEN = 0;
2280 sc->esc_RDH = 0;
2281 sc->esc_RDT = 0;
2282 sc->esc_RDTR = 0;
2283 sc->esc_RXDCTL = (1 << 24) | (1 << 16); /* default GRAN/WTHRESH */
2284 sc->esc_RADV = 0;
2285 sc->esc_RXCSUM = 0;
2286
2287 /* transmit */
2288 if (!drvr) {
2289 sc->esc_TDBAL = 0;
2290 sc->esc_TDBAH = 0;
2291 sc->esc_TIPG = 0;
2292 sc->esc_AIT = 0;
2293 sc->esc_TIDV = 0;
2294 sc->esc_TADV = 0;
2295 }
2296 sc->esc_tdba = 0;
2297 sc->esc_txdesc = NULL;
2298 sc->esc_TXCW = 0;
2299 sc->esc_TCTL = 0;
2300 sc->esc_TDLEN = 0;
2301 sc->esc_TDT = 0;
2302 sc->esc_TDHr = sc->esc_TDH = 0;
2303 sc->esc_TXDCTL = 0;
2304 }
2305
2306 static int
e82545_init(struct pci_devinst * pi,nvlist_t * nvl)2307 e82545_init(struct pci_devinst *pi, nvlist_t *nvl)
2308 {
2309 char nstr[80];
2310 struct e82545_softc *sc;
2311 const char *mac;
2312 int err;
2313
2314 /* Setup our softc */
2315 sc = calloc(1, sizeof(*sc));
2316
2317 pi->pi_arg = sc;
2318 sc->esc_pi = pi;
2319 sc->esc_ctx = pi->pi_vmctx;
2320
2321 pthread_mutex_init(&sc->esc_mtx, NULL);
2322 pthread_cond_init(&sc->esc_rx_cond, NULL);
2323 pthread_cond_init(&sc->esc_tx_cond, NULL);
2324 pthread_create(&sc->esc_tx_tid, NULL, e82545_tx_thread, sc);
2325 snprintf(nstr, sizeof(nstr), "e82545-%d:%d tx", pi->pi_slot,
2326 pi->pi_func);
2327 pthread_set_name_np(sc->esc_tx_tid, nstr);
2328
2329 pci_set_cfgdata16(pi, PCIR_DEVICE, E82545_DEV_ID_82545EM_COPPER);
2330 pci_set_cfgdata16(pi, PCIR_VENDOR, E82545_VENDOR_ID_INTEL);
2331 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_NETWORK);
2332 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_NETWORK_ETHERNET);
2333 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, E82545_SUBDEV_ID);
2334 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, E82545_VENDOR_ID_INTEL);
2335
2336 pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL);
2337 pci_set_cfgdata8(pi, PCIR_INTPIN, 0x1);
2338
2339 /* TODO: this card also supports msi, but the freebsd driver for it
2340 * does not, so I have not implemented it. */
2341 pci_lintr_request(pi);
2342
2343 pci_emul_alloc_bar(pi, E82545_BAR_REGISTER, PCIBAR_MEM32,
2344 E82545_BAR_REGISTER_LEN);
2345 pci_emul_alloc_bar(pi, E82545_BAR_FLASH, PCIBAR_MEM32,
2346 E82545_BAR_FLASH_LEN);
2347 pci_emul_alloc_bar(pi, E82545_BAR_IO, PCIBAR_IO,
2348 E82545_BAR_IO_LEN);
2349
2350 mac = get_config_value_node(nvl, "mac");
2351 if (mac != NULL) {
2352 err = net_parsemac(mac, sc->esc_mac.octet);
2353 if (err) {
2354 free(sc);
2355 return (err);
2356 }
2357 } else
2358 net_genmac(pi, sc->esc_mac.octet);
2359
2360 err = netbe_init(&sc->esc_be, nvl, e82545_rx_callback, sc);
2361 if (err) {
2362 free(sc);
2363 return (err);
2364 }
2365
2366 netbe_rx_enable(sc->esc_be);
2367
2368 /* H/w initiated reset */
2369 e82545_reset(sc, 0);
2370
2371 return (0);
2372 }
2373
2374 #ifdef BHYVE_SNAPSHOT
2375 static int
e82545_snapshot(struct vm_snapshot_meta * meta)2376 e82545_snapshot(struct vm_snapshot_meta *meta)
2377 {
2378 int i;
2379 int ret;
2380 struct e82545_softc *sc;
2381 struct pci_devinst *pi;
2382 uint64_t bitmap_value;
2383
2384 pi = meta->dev_data;
2385 sc = pi->pi_arg;
2386
2387 /* esc_mevp and esc_mevpitr should be reinitiated at init. */
2388 SNAPSHOT_VAR_OR_LEAVE(sc->esc_mac, meta, ret, done);
2389
2390 /* General */
2391 SNAPSHOT_VAR_OR_LEAVE(sc->esc_CTRL, meta, ret, done);
2392 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCAL, meta, ret, done);
2393 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCAH, meta, ret, done);
2394 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCT, meta, ret, done);
2395 SNAPSHOT_VAR_OR_LEAVE(sc->esc_VET, meta, ret, done);
2396 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCTTV, meta, ret, done);
2397 SNAPSHOT_VAR_OR_LEAVE(sc->esc_LEDCTL, meta, ret, done);
2398 SNAPSHOT_VAR_OR_LEAVE(sc->esc_PBA, meta, ret, done);
2399
2400 /* Interrupt control */
2401 SNAPSHOT_VAR_OR_LEAVE(sc->esc_irq_asserted, meta, ret, done);
2402 SNAPSHOT_VAR_OR_LEAVE(sc->esc_ICR, meta, ret, done);
2403 SNAPSHOT_VAR_OR_LEAVE(sc->esc_ITR, meta, ret, done);
2404 SNAPSHOT_VAR_OR_LEAVE(sc->esc_ICS, meta, ret, done);
2405 SNAPSHOT_VAR_OR_LEAVE(sc->esc_IMS, meta, ret, done);
2406 SNAPSHOT_VAR_OR_LEAVE(sc->esc_IMC, meta, ret, done);
2407
2408 /*
2409 * Transmit
2410 *
2411 * The fields in the unions are in superposition to access certain
2412 * bytes in the larger uint variables.
2413 * e.g., ip_config = [ipcss|ipcso|ipcse0|ipcse1]
2414 */
2415 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.lower_setup.ip_config, meta, ret, done);
2416 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.upper_setup.tcp_config, meta, ret, done);
2417 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.cmd_and_length, meta, ret, done);
2418 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.tcp_seg_setup.data, meta, ret, done);
2419
2420 SNAPSHOT_VAR_OR_LEAVE(sc->esc_tx_enabled, meta, ret, done);
2421 SNAPSHOT_VAR_OR_LEAVE(sc->esc_tx_active, meta, ret, done);
2422 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TXCW, meta, ret, done);
2423 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TCTL, meta, ret, done);
2424 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TIPG, meta, ret, done);
2425 SNAPSHOT_VAR_OR_LEAVE(sc->esc_AIT, meta, ret, done);
2426 SNAPSHOT_VAR_OR_LEAVE(sc->esc_tdba, meta, ret, done);
2427 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDBAL, meta, ret, done);
2428 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDBAH, meta, ret, done);
2429 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDLEN, meta, ret, done);
2430 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDH, meta, ret, done);
2431 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDHr, meta, ret, done);
2432 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDT, meta, ret, done);
2433 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TIDV, meta, ret, done);
2434 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TXDCTL, meta, ret, done);
2435 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TADV, meta, ret, done);
2436
2437 /* Has dependency on esc_TDLEN; reoreder of fields from struct. */
2438 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, sc->esc_txdesc,
2439 sc->esc_TDLEN, true, meta, ret, done);
2440
2441 /* L2 frame acceptance */
2442 for (i = 0; i < (int)nitems(sc->esc_uni); i++) {
2443 SNAPSHOT_VAR_OR_LEAVE(sc->esc_uni[i].eu_valid, meta, ret, done);
2444 SNAPSHOT_VAR_OR_LEAVE(sc->esc_uni[i].eu_addrsel, meta, ret, done);
2445 SNAPSHOT_VAR_OR_LEAVE(sc->esc_uni[i].eu_eth, meta, ret, done);
2446 }
2447
2448 SNAPSHOT_BUF_OR_LEAVE(sc->esc_fmcast, sizeof(sc->esc_fmcast),
2449 meta, ret, done);
2450 SNAPSHOT_BUF_OR_LEAVE(sc->esc_fvlan, sizeof(sc->esc_fvlan),
2451 meta, ret, done);
2452
2453 /* Receive */
2454 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rx_enabled, meta, ret, done);
2455 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rx_active, meta, ret, done);
2456 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rx_loopback, meta, ret, done);
2457 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RCTL, meta, ret, done);
2458 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCRTL, meta, ret, done);
2459 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCRTH, meta, ret, done);
2460 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rdba, meta, ret, done);
2461 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDBAL, meta, ret, done);
2462 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDBAH, meta, ret, done);
2463 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDLEN, meta, ret, done);
2464 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDH, meta, ret, done);
2465 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDT, meta, ret, done);
2466 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDTR, meta, ret, done);
2467 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RXDCTL, meta, ret, done);
2468 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RADV, meta, ret, done);
2469 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RSRPD, meta, ret, done);
2470 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RXCSUM, meta, ret, done);
2471
2472 /* Has dependency on esc_RDLEN; reoreder of fields from struct. */
2473 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, sc->esc_rxdesc,
2474 sc->esc_TDLEN, true, meta, ret, done);
2475
2476 /* IO Port register access */
2477 SNAPSHOT_VAR_OR_LEAVE(sc->io_addr, meta, ret, done);
2478
2479 /* Shadow copy of MDIC */
2480 SNAPSHOT_VAR_OR_LEAVE(sc->mdi_control, meta, ret, done);
2481
2482 /* Shadow copy of EECD */
2483 SNAPSHOT_VAR_OR_LEAVE(sc->eeprom_control, meta, ret, done);
2484
2485 /* Latest NVM in/out */
2486 SNAPSHOT_VAR_OR_LEAVE(sc->nvm_data, meta, ret, done);
2487 SNAPSHOT_VAR_OR_LEAVE(sc->nvm_opaddr, meta, ret, done);
2488
2489 /* Stats */
2490 SNAPSHOT_VAR_OR_LEAVE(sc->missed_pkt_count, meta, ret, done);
2491 SNAPSHOT_BUF_OR_LEAVE(sc->pkt_rx_by_size, sizeof(sc->pkt_rx_by_size),
2492 meta, ret, done);
2493 SNAPSHOT_BUF_OR_LEAVE(sc->pkt_tx_by_size, sizeof(sc->pkt_tx_by_size),
2494 meta, ret, done);
2495 SNAPSHOT_VAR_OR_LEAVE(sc->good_pkt_rx_count, meta, ret, done);
2496 SNAPSHOT_VAR_OR_LEAVE(sc->bcast_pkt_rx_count, meta, ret, done);
2497 SNAPSHOT_VAR_OR_LEAVE(sc->mcast_pkt_rx_count, meta, ret, done);
2498 SNAPSHOT_VAR_OR_LEAVE(sc->good_pkt_tx_count, meta, ret, done);
2499 SNAPSHOT_VAR_OR_LEAVE(sc->bcast_pkt_tx_count, meta, ret, done);
2500 SNAPSHOT_VAR_OR_LEAVE(sc->mcast_pkt_tx_count, meta, ret, done);
2501 SNAPSHOT_VAR_OR_LEAVE(sc->oversize_rx_count, meta, ret, done);
2502 SNAPSHOT_VAR_OR_LEAVE(sc->tso_tx_count, meta, ret, done);
2503 SNAPSHOT_VAR_OR_LEAVE(sc->good_octets_rx, meta, ret, done);
2504 SNAPSHOT_VAR_OR_LEAVE(sc->good_octets_tx, meta, ret, done);
2505 SNAPSHOT_VAR_OR_LEAVE(sc->missed_octets, meta, ret, done);
2506
2507 if (meta->op == VM_SNAPSHOT_SAVE)
2508 bitmap_value = sc->nvm_bits;
2509 SNAPSHOT_VAR_OR_LEAVE(bitmap_value, meta, ret, done);
2510 if (meta->op == VM_SNAPSHOT_RESTORE)
2511 sc->nvm_bits = bitmap_value;
2512
2513 if (meta->op == VM_SNAPSHOT_SAVE)
2514 bitmap_value = sc->nvm_bits;
2515 SNAPSHOT_VAR_OR_LEAVE(bitmap_value, meta, ret, done);
2516 if (meta->op == VM_SNAPSHOT_RESTORE)
2517 sc->nvm_bits = bitmap_value;
2518
2519 /* EEPROM data */
2520 SNAPSHOT_BUF_OR_LEAVE(sc->eeprom_data, sizeof(sc->eeprom_data),
2521 meta, ret, done);
2522
2523 done:
2524 return (ret);
2525 }
2526 #endif
2527
2528 static const struct pci_devemu pci_de_e82545 = {
2529 .pe_emu = "e1000",
2530 .pe_init = e82545_init,
2531 .pe_legacy_config = netbe_legacy_config,
2532 .pe_barwrite = e82545_write,
2533 .pe_barread = e82545_read,
2534 #ifdef BHYVE_SNAPSHOT
2535 .pe_snapshot = e82545_snapshot,
2536 #endif
2537 };
2538 PCI_EMUL_SET(pci_de_e82545);
2539