1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #ifndef ECORE_INIT_OPS_H
31 #define ECORE_INIT_OPS_H
32
33
34
35
36
37
38
39
40
41
42 static int ecore_gunzip(struct bxe_softc *sc, const uint8_t *zbuf, int len);
43 static void ecore_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, uint32_t val);
44 static void ecore_write_dmae_phys_len(struct bxe_softc *sc,
45 ecore_dma_addr_t phys_addr, uint32_t addr,
46 uint32_t len);
47
ecore_init_str_wr(struct bxe_softc * sc,uint32_t addr,const uint32_t * data,uint32_t len)48 static void ecore_init_str_wr(struct bxe_softc *sc, uint32_t addr,
49 const uint32_t *data, uint32_t len)
50 {
51 uint32_t i;
52
53 for (i = 0; i < len; i++)
54 REG_WR(sc, addr + i*4, data[i]);
55 }
56
ecore_init_ind_wr(struct bxe_softc * sc,uint32_t addr,const uint32_t * data,uint32_t len)57 static void ecore_init_ind_wr(struct bxe_softc *sc, uint32_t addr,
58 const uint32_t *data, uint32_t len)
59 {
60 uint32_t i;
61
62 for (i = 0; i < len; i++)
63 ecore_reg_wr_ind(sc, addr + i*4, data[i]);
64 }
65
ecore_write_big_buf(struct bxe_softc * sc,uint32_t addr,uint32_t len,uint8_t wb)66 static void ecore_write_big_buf(struct bxe_softc *sc, uint32_t addr, uint32_t len,
67 uint8_t wb)
68 {
69 if (DMAE_READY(sc))
70 ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
71
72 /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
73 else if (wb && CHIP_IS_E1(sc))
74 ecore_init_ind_wr(sc, addr, GUNZIP_BUF(sc), len);
75
76 /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
77 else
78 ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
79 }
80
ecore_init_fill(struct bxe_softc * sc,uint32_t addr,int fill,uint32_t len,uint8_t wb)81 static void ecore_init_fill(struct bxe_softc *sc, uint32_t addr, int fill,
82 uint32_t len, uint8_t wb)
83 {
84 uint32_t buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
85 uint32_t buf_len32 = buf_len/4;
86 uint32_t i;
87
88 ECORE_MEMSET(GUNZIP_BUF(sc), (uint8_t)fill, buf_len);
89
90 for (i = 0; i < len; i += buf_len32) {
91 uint32_t cur_len = min(buf_len32, len - i);
92
93 ecore_write_big_buf(sc, addr + i*4, cur_len, wb);
94 }
95 }
96
ecore_write_big_buf_wb(struct bxe_softc * sc,uint32_t addr,uint32_t len)97 static void ecore_write_big_buf_wb(struct bxe_softc *sc, uint32_t addr, uint32_t len)
98 {
99 if (DMAE_READY(sc))
100 ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
101
102 /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
103 else if (CHIP_IS_E1(sc))
104 ecore_init_ind_wr(sc, addr, GUNZIP_BUF(sc), len);
105
106 /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
107 else
108 ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
109 }
110
ecore_init_wr_64(struct bxe_softc * sc,uint32_t addr,const uint32_t * data,uint32_t len64)111 static void ecore_init_wr_64(struct bxe_softc *sc, uint32_t addr,
112 const uint32_t *data, uint32_t len64)
113 {
114 uint32_t buf_len32 = FW_BUF_SIZE/4;
115 uint32_t len = len64*2;
116 uint64_t data64 = 0;
117 uint32_t i;
118
119 /* 64 bit value is in a blob: first low DWORD, then high DWORD */
120 data64 = HILO_U64((*(data + 1)), (*data));
121
122 len64 = min((uint32_t)(FW_BUF_SIZE/8), len64);
123 for (i = 0; i < len64; i++) {
124 uint64_t *pdata = ((uint64_t *)(GUNZIP_BUF(sc))) + i;
125
126 *pdata = data64;
127 }
128
129 for (i = 0; i < len; i += buf_len32) {
130 uint32_t cur_len = min(buf_len32, len - i);
131
132 ecore_write_big_buf_wb(sc, addr + i*4, cur_len);
133 }
134 }
135
136 /*********************************************************
137 There are different blobs for each PRAM section.
138 In addition, each blob write operation is divided into a few operations
139 in order to decrease the amount of phys. contiguous buffer needed.
140 Thus, when we select a blob the address may be with some offset
141 from the beginning of PRAM section.
142 The same holds for the INT_TABLE sections.
143 **********************************************************/
144 #define IF_IS_INT_TABLE_ADDR(base, addr) \
145 if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
146
147 #define IF_IS_PRAM_ADDR(base, addr) \
148 if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
149
ecore_sel_blob(struct bxe_softc * sc,uint32_t addr,const uint8_t * data)150 static const uint8_t *ecore_sel_blob(struct bxe_softc *sc, uint32_t addr,
151 const uint8_t *data)
152 {
153 IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
154 data = INIT_TSEM_INT_TABLE_DATA(sc);
155 else
156 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
157 data = INIT_CSEM_INT_TABLE_DATA(sc);
158 else
159 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
160 data = INIT_USEM_INT_TABLE_DATA(sc);
161 else
162 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
163 data = INIT_XSEM_INT_TABLE_DATA(sc);
164 else
165 IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
166 data = INIT_TSEM_PRAM_DATA(sc);
167 else
168 IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
169 data = INIT_CSEM_PRAM_DATA(sc);
170 else
171 IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
172 data = INIT_USEM_PRAM_DATA(sc);
173 else
174 IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
175 data = INIT_XSEM_PRAM_DATA(sc);
176
177 return data;
178 }
179
ecore_init_wr_wb(struct bxe_softc * sc,uint32_t addr,const uint32_t * data,uint32_t len)180 static void ecore_init_wr_wb(struct bxe_softc *sc, uint32_t addr,
181 const uint32_t *data, uint32_t len)
182 {
183 if (DMAE_READY(sc))
184 VIRT_WR_DMAE_LEN(sc, data, addr, len, 0);
185
186 /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
187 else if (CHIP_IS_E1(sc))
188 ecore_init_ind_wr(sc, addr, data, len);
189
190 /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
191 else
192 ecore_init_str_wr(sc, addr, data, len);
193 }
194
195 #ifndef FW_ZIP_SUPPORT
ecore_init_fw(struct bxe_softc * sc,uint32_t addr,uint32_t len)196 static void ecore_init_fw(struct bxe_softc *sc, uint32_t addr, uint32_t len)
197 {
198 const uint8_t *data = NULL;
199
200 data = ecore_sel_blob(sc, addr, (const uint8_t *)data);
201
202 if (DMAE_READY(sc))
203 VIRT_WR_DMAE_LEN(sc, data, addr, len, 1);
204
205 /* in E1 BIOS initiated ZLR may interrupt widebus writes */
206 else if (CHIP_IS_E1(sc))
207 ecore_init_ind_wr(sc, addr, (const uint32_t *)data, len);
208
209 /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
210 else
211 ecore_init_str_wr(sc, addr, (const uint32_t *)data, len);
212 }
213
214 #endif
215
ecore_wr_64(struct bxe_softc * sc,uint32_t reg,uint32_t val_lo,uint32_t val_hi)216 static void ecore_wr_64(struct bxe_softc *sc, uint32_t reg, uint32_t val_lo,
217 uint32_t val_hi)
218 {
219 uint32_t wb_write[2];
220
221 wb_write[0] = val_lo;
222 wb_write[1] = val_hi;
223 REG_WR_DMAE_LEN(sc, reg, wb_write, 2);
224 }
225
ecore_init_wr_zp(struct bxe_softc * sc,uint32_t addr,uint32_t len,uint32_t blob_off)226 static void ecore_init_wr_zp(struct bxe_softc *sc, uint32_t addr, uint32_t len,
227 uint32_t blob_off)
228 {
229 const uint8_t *data = NULL;
230 int rc;
231 uint32_t i;
232
233 data = ecore_sel_blob(sc, addr, data) + blob_off*4;
234
235 rc = ecore_gunzip(sc, data, len);
236 if (rc)
237 return;
238
239 /* gunzip_outlen is in dwords */
240 len = GUNZIP_OUTLEN(sc);
241 for (i = 0; i < len; i++)
242 ((uint32_t *)GUNZIP_BUF(sc))[i] = (uint32_t)
243 ECORE_CPU_TO_LE32(((uint32_t *)GUNZIP_BUF(sc))[i]);
244
245 ecore_write_big_buf_wb(sc, addr, len);
246 }
247
ecore_init_block(struct bxe_softc * sc,uint32_t block,uint32_t stage)248 static void ecore_init_block(struct bxe_softc *sc, uint32_t block, uint32_t stage)
249 {
250 uint16_t op_start =
251 INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage,
252 STAGE_START)];
253 uint16_t op_end =
254 INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage,
255 STAGE_END)];
256 const union init_op *op;
257 uint32_t op_idx, op_type, addr, len;
258 const uint32_t *data, *data_base;
259
260 /* If empty block */
261 if (op_start == op_end)
262 return;
263
264 data_base = INIT_DATA(sc);
265
266 for (op_idx = op_start; op_idx < op_end; op_idx++) {
267
268 op = (const union init_op *)&(INIT_OPS(sc)[op_idx]);
269 /* Get generic data */
270 op_type = op->raw.op;
271 addr = op->raw.offset;
272 /* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and
273 * OP_WR64 (we assume that op_arr_write and op_write have the
274 * same structure).
275 */
276 len = op->arr_wr.data_len;
277 data = data_base + op->arr_wr.data_off;
278
279 switch (op_type) {
280 case OP_RD:
281 REG_RD(sc, addr);
282 break;
283 case OP_WR:
284 REG_WR(sc, addr, op->write.val);
285 break;
286 case OP_SW:
287 ecore_init_str_wr(sc, addr, data, len);
288 break;
289 case OP_WB:
290 ecore_init_wr_wb(sc, addr, data, len);
291 break;
292 #ifndef FW_ZIP_SUPPORT
293 case OP_FW:
294 ecore_init_fw(sc, addr, len);
295 break;
296 #endif
297 case OP_ZR:
298 ecore_init_fill(sc, addr, 0, op->zero.len, 0);
299 break;
300 case OP_WB_ZR:
301 ecore_init_fill(sc, addr, 0, op->zero.len, 1);
302 break;
303 case OP_ZP:
304 ecore_init_wr_zp(sc, addr, len,
305 op->arr_wr.data_off);
306 break;
307 case OP_WR_64:
308 ecore_init_wr_64(sc, addr, data, len);
309 break;
310 case OP_IF_MODE_AND:
311 /* if any of the flags doesn't match, skip the
312 * conditional block.
313 */
314 if ((INIT_MODE_FLAGS(sc) &
315 op->if_mode.mode_bit_map) !=
316 op->if_mode.mode_bit_map)
317 op_idx += op->if_mode.cmd_offset;
318 break;
319 case OP_IF_MODE_OR:
320 /* if all the flags don't match, skip the conditional
321 * block.
322 */
323 if ((INIT_MODE_FLAGS(sc) &
324 op->if_mode.mode_bit_map) == 0)
325 op_idx += op->if_mode.cmd_offset;
326 break;
327 /* the following opcodes are unused at the moment. */
328 case OP_IF_PHASE:
329 case OP_RT:
330 case OP_DELAY:
331 case OP_VERIFY:
332 default:
333 /* Should never get here! */
334
335 break;
336 }
337 }
338 }
339
340
341 /****************************************************************************
342 * PXP Arbiter
343 ****************************************************************************/
344 /*
345 * This code configures the PCI read/write arbiter
346 * which implements a weighted round robin
347 * between the virtual queues in the chip.
348 *
349 * The values were derived for each PCI max payload and max request size.
350 * since max payload and max request size are only known at run time,
351 * this is done as a separate init stage.
352 */
353
354 #define NUM_WR_Q 13
355 #define NUM_RD_Q 29
356 #define MAX_RD_ORD 3
357 #define MAX_WR_ORD 2
358
359 /* configuration for one arbiter queue */
360 struct arb_line {
361 int l;
362 int add;
363 int ubound;
364 };
365
366 /* derived configuration for each read queue for each max request size */
367 static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
368 /* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
369 { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
370 { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
371 { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
372 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
373 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
374 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
375 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
376 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
377 /* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
378 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
379 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
380 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
381 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
382 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
383 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
384 { {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
385 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
386 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
387 /* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
388 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
389 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
390 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
391 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
392 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
393 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
394 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
395 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
396 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
397 };
398
399 /* derived configuration for each write queue for each max request size */
400 static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
401 /* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
402 { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
403 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
404 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
405 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
406 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
407 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
408 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
409 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
410 /* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
411 { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
412 { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
413 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
414 };
415
416 /* register addresses for read queues */
417 static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
418 /* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
419 PXP2_REG_RQ_BW_RD_UBOUND0},
420 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
421 PXP2_REG_PSWRQ_BW_UB1},
422 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
423 PXP2_REG_PSWRQ_BW_UB2},
424 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
425 PXP2_REG_PSWRQ_BW_UB3},
426 {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
427 PXP2_REG_RQ_BW_RD_UBOUND4},
428 {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
429 PXP2_REG_RQ_BW_RD_UBOUND5},
430 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
431 PXP2_REG_PSWRQ_BW_UB6},
432 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
433 PXP2_REG_PSWRQ_BW_UB7},
434 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
435 PXP2_REG_PSWRQ_BW_UB8},
436 /* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
437 PXP2_REG_PSWRQ_BW_UB9},
438 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
439 PXP2_REG_PSWRQ_BW_UB10},
440 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
441 PXP2_REG_PSWRQ_BW_UB11},
442 {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
443 PXP2_REG_RQ_BW_RD_UBOUND12},
444 {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
445 PXP2_REG_RQ_BW_RD_UBOUND13},
446 {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
447 PXP2_REG_RQ_BW_RD_UBOUND14},
448 {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
449 PXP2_REG_RQ_BW_RD_UBOUND15},
450 {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
451 PXP2_REG_RQ_BW_RD_UBOUND16},
452 {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
453 PXP2_REG_RQ_BW_RD_UBOUND17},
454 {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
455 PXP2_REG_RQ_BW_RD_UBOUND18},
456 /* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
457 PXP2_REG_RQ_BW_RD_UBOUND19},
458 {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
459 PXP2_REG_RQ_BW_RD_UBOUND20},
460 {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
461 PXP2_REG_RQ_BW_RD_UBOUND22},
462 {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
463 PXP2_REG_RQ_BW_RD_UBOUND23},
464 {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
465 PXP2_REG_RQ_BW_RD_UBOUND24},
466 {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
467 PXP2_REG_RQ_BW_RD_UBOUND25},
468 {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
469 PXP2_REG_RQ_BW_RD_UBOUND26},
470 {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
471 PXP2_REG_RQ_BW_RD_UBOUND27},
472 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
473 PXP2_REG_PSWRQ_BW_UB28}
474 };
475
476 /* register addresses for write queues */
477 static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
478 /* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
479 PXP2_REG_PSWRQ_BW_UB1},
480 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
481 PXP2_REG_PSWRQ_BW_UB2},
482 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
483 PXP2_REG_PSWRQ_BW_UB3},
484 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
485 PXP2_REG_PSWRQ_BW_UB6},
486 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
487 PXP2_REG_PSWRQ_BW_UB7},
488 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
489 PXP2_REG_PSWRQ_BW_UB8},
490 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
491 PXP2_REG_PSWRQ_BW_UB9},
492 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
493 PXP2_REG_PSWRQ_BW_UB10},
494 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
495 PXP2_REG_PSWRQ_BW_UB11},
496 /* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
497 PXP2_REG_PSWRQ_BW_UB28},
498 {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
499 PXP2_REG_RQ_BW_WR_UBOUND29},
500 {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
501 PXP2_REG_RQ_BW_WR_UBOUND30}
502 };
503
ecore_init_pxp_arb(struct bxe_softc * sc,int r_order,int w_order)504 static void ecore_init_pxp_arb(struct bxe_softc *sc, int r_order,
505 int w_order)
506 {
507 uint32_t val, i;
508
509 if (r_order > MAX_RD_ORD) {
510 ECORE_MSG(sc, "read order of %d order adjusted to %d\n",
511 r_order, MAX_RD_ORD);
512 r_order = MAX_RD_ORD;
513 }
514 if (w_order > MAX_WR_ORD) {
515 ECORE_MSG(sc, "write order of %d order adjusted to %d\n",
516 w_order, MAX_WR_ORD);
517 w_order = MAX_WR_ORD;
518 }
519 if (CHIP_REV_IS_FPGA(sc)) {
520 ECORE_MSG(sc, "write order adjusted to 1 for FPGA\n");
521 w_order = 0;
522 }
523 ECORE_MSG(sc, "read order %d write order %d\n", r_order, w_order);
524
525 for (i = 0; i < NUM_RD_Q-1; i++) {
526 REG_WR(sc, read_arb_addr[i].l, read_arb_data[i][r_order].l);
527 REG_WR(sc, read_arb_addr[i].add,
528 read_arb_data[i][r_order].add);
529 REG_WR(sc, read_arb_addr[i].ubound,
530 read_arb_data[i][r_order].ubound);
531 }
532
533 for (i = 0; i < NUM_WR_Q-1; i++) {
534 if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
535 (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
536
537 REG_WR(sc, write_arb_addr[i].l,
538 write_arb_data[i][w_order].l);
539
540 REG_WR(sc, write_arb_addr[i].add,
541 write_arb_data[i][w_order].add);
542
543 REG_WR(sc, write_arb_addr[i].ubound,
544 write_arb_data[i][w_order].ubound);
545 } else {
546
547 val = REG_RD(sc, write_arb_addr[i].l);
548 REG_WR(sc, write_arb_addr[i].l,
549 val | (write_arb_data[i][w_order].l << 10));
550
551 val = REG_RD(sc, write_arb_addr[i].add);
552 REG_WR(sc, write_arb_addr[i].add,
553 val | (write_arb_data[i][w_order].add << 10));
554
555 val = REG_RD(sc, write_arb_addr[i].ubound);
556 REG_WR(sc, write_arb_addr[i].ubound,
557 val | (write_arb_data[i][w_order].ubound << 7));
558 }
559 }
560
561 val = write_arb_data[NUM_WR_Q-1][w_order].add;
562 val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
563 val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
564 REG_WR(sc, PXP2_REG_PSWRQ_BW_RD, val);
565
566 val = read_arb_data[NUM_RD_Q-1][r_order].add;
567 val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
568 val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
569 REG_WR(sc, PXP2_REG_PSWRQ_BW_WR, val);
570
571 REG_WR(sc, PXP2_REG_RQ_WR_MBS0, w_order);
572 REG_WR(sc, PXP2_REG_RQ_WR_MBS1, w_order);
573 REG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order);
574 REG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order);
575
576 if ((CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) && (r_order == MAX_RD_ORD))
577 REG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
578
579 if (CHIP_IS_E3(sc))
580 REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order));
581 else if (CHIP_IS_E2(sc))
582 REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order));
583 else
584 REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
585
586 if (!CHIP_IS_E1(sc)) {
587 /* MPS w_order optimal TH presently TH
588 * 128 0 0 2
589 * 256 1 1 3
590 * >=512 2 2 3
591 */
592 /* DMAE is special */
593 if (!CHIP_IS_E1H(sc)) {
594 /* E2 can use optimal TH */
595 val = w_order;
596 REG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);
597 } else {
598 val = ((w_order == 0) ? 2 : 3);
599 REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);
600 }
601
602 REG_WR(sc, PXP2_REG_WR_HC_MPS, val);
603 REG_WR(sc, PXP2_REG_WR_USDM_MPS, val);
604 REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);
605 REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);
606 REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);
607 REG_WR(sc, PXP2_REG_WR_QM_MPS, val);
608 REG_WR(sc, PXP2_REG_WR_TM_MPS, val);
609 REG_WR(sc, PXP2_REG_WR_SRC_MPS, val);
610 REG_WR(sc, PXP2_REG_WR_DBG_MPS, val);
611 REG_WR(sc, PXP2_REG_WR_CDU_MPS, val);
612 }
613
614 /* Validate number of tags suppoted by device */
615 #define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980
616 val = REG_RD(sc, PCIE_REG_PCIER_TL_HDR_FC_ST);
617 val &= 0xFF;
618 if (val <= 0x20)
619 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x20);
620 }
621
622 /****************************************************************************
623 * ILT management
624 ****************************************************************************/
625 /*
626 * This codes hides the low level HW interaction for ILT management and
627 * configuration. The API consists of a shadow ILT table which is set by the
628 * driver and a set of routines to use it to configure the HW.
629 *
630 */
631
632 /* ILT HW init operations */
633
634 /* ILT memory management operations */
635 #define ILT_MEMOP_ALLOC 0
636 #define ILT_MEMOP_FREE 1
637
638 /* the phys address is shifted right 12 bits and has an added
639 * 1=valid bit added to the 53rd bit
640 * then since this is a wide register(TM)
641 * we split it into two 32 bit writes
642 */
643 #define ILT_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
644 #define ILT_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
645 #define ILT_RANGE(f, l) (((l) << 10) | f)
646
ecore_ilt_line_mem_op(struct bxe_softc * sc,struct ilt_line * line,uint32_t size,uint8_t memop)647 static int ecore_ilt_line_mem_op(struct bxe_softc *sc,
648 struct ilt_line *line, uint32_t size, uint8_t memop)
649 {
650 if (memop == ILT_MEMOP_FREE) {
651 ECORE_ILT_FREE(line->page, line->page_mapping, line->size);
652 return 0;
653 }
654 ECORE_ILT_ZALLOC(line->page, &line->page_mapping, size);
655 if (!line->page)
656 return -1;
657 line->size = size;
658 return 0;
659 }
660
661
ecore_ilt_client_mem_op(struct bxe_softc * sc,int cli_num,uint8_t memop)662 static int ecore_ilt_client_mem_op(struct bxe_softc *sc, int cli_num,
663 uint8_t memop)
664 {
665 int i, rc;
666 struct ecore_ilt *ilt = SC_ILT(sc);
667 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
668
669 if (!ilt || !ilt->lines)
670 return -1;
671
672 if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
673 return 0;
674
675 for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
676 rc = ecore_ilt_line_mem_op(sc, &ilt->lines[i],
677 ilt_cli->page_size, memop);
678 }
679 return rc;
680 }
681
ecore_ilt_mem_op_cnic(struct bxe_softc * sc,uint8_t memop)682 static inline int ecore_ilt_mem_op_cnic(struct bxe_softc *sc, uint8_t memop)
683 {
684 int rc = 0;
685
686 if (CONFIGURE_NIC_MODE(sc))
687 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);
688 if (!rc)
689 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_TM, memop);
690
691 return rc;
692 }
693
ecore_ilt_mem_op(struct bxe_softc * sc,uint8_t memop)694 static int ecore_ilt_mem_op(struct bxe_softc *sc, uint8_t memop)
695 {
696 int rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_CDU, memop);
697 if (!rc)
698 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_QM, memop);
699 if (!rc && CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc))
700 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);
701
702 return rc;
703 }
704
ecore_ilt_line_wr(struct bxe_softc * sc,int abs_idx,ecore_dma_addr_t page_mapping)705 static void ecore_ilt_line_wr(struct bxe_softc *sc, int abs_idx,
706 ecore_dma_addr_t page_mapping)
707 {
708 uint32_t reg;
709
710 if (CHIP_IS_E1(sc))
711 reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8;
712 else
713 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
714
715 ecore_wr_64(sc, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
716 }
717
ecore_ilt_line_init_op(struct bxe_softc * sc,struct ecore_ilt * ilt,int idx,uint8_t initop)718 static void ecore_ilt_line_init_op(struct bxe_softc *sc,
719 struct ecore_ilt *ilt, int idx, uint8_t initop)
720 {
721 ecore_dma_addr_t null_mapping;
722 int abs_idx = ilt->start_line + idx;
723
724
725 switch (initop) {
726 case INITOP_INIT:
727 /* set in the init-value array */
728 case INITOP_SET:
729 ecore_ilt_line_wr(sc, abs_idx, ilt->lines[idx].page_mapping);
730 break;
731 case INITOP_CLEAR:
732 null_mapping = 0;
733 ecore_ilt_line_wr(sc, abs_idx, null_mapping);
734 break;
735 }
736 }
737
ecore_ilt_boundry_init_op(struct bxe_softc * sc,struct ilt_client_info * ilt_cli,uint32_t ilt_start,uint8_t initop)738 static void ecore_ilt_boundry_init_op(struct bxe_softc *sc,
739 struct ilt_client_info *ilt_cli,
740 uint32_t ilt_start, uint8_t initop)
741 {
742 uint32_t start_reg = 0;
743 uint32_t end_reg = 0;
744
745 /* The boundary is either SET or INIT,
746 CLEAR => SET and for now SET ~~ INIT */
747
748 /* find the appropriate regs */
749 if (CHIP_IS_E1(sc)) {
750 switch (ilt_cli->client_num) {
751 case ILT_CLIENT_CDU:
752 start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
753 break;
754 case ILT_CLIENT_QM:
755 start_reg = PXP2_REG_PSWRQ_QM0_L2P;
756 break;
757 case ILT_CLIENT_SRC:
758 start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
759 break;
760 case ILT_CLIENT_TM:
761 start_reg = PXP2_REG_PSWRQ_TM0_L2P;
762 break;
763 }
764 REG_WR(sc, start_reg + SC_FUNC(sc)*4,
765 ILT_RANGE((ilt_start + ilt_cli->start),
766 (ilt_start + ilt_cli->end)));
767 } else {
768 switch (ilt_cli->client_num) {
769 case ILT_CLIENT_CDU:
770 start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
771 end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
772 break;
773 case ILT_CLIENT_QM:
774 start_reg = PXP2_REG_RQ_QM_FIRST_ILT;
775 end_reg = PXP2_REG_RQ_QM_LAST_ILT;
776 break;
777 case ILT_CLIENT_SRC:
778 start_reg = PXP2_REG_RQ_SRC_FIRST_ILT;
779 end_reg = PXP2_REG_RQ_SRC_LAST_ILT;
780 break;
781 case ILT_CLIENT_TM:
782 start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
783 end_reg = PXP2_REG_RQ_TM_LAST_ILT;
784 break;
785 }
786 REG_WR(sc, start_reg, (ilt_start + ilt_cli->start));
787 REG_WR(sc, end_reg, (ilt_start + ilt_cli->end));
788 }
789 }
790
ecore_ilt_client_init_op_ilt(struct bxe_softc * sc,struct ecore_ilt * ilt,struct ilt_client_info * ilt_cli,uint8_t initop)791 static void ecore_ilt_client_init_op_ilt(struct bxe_softc *sc,
792 struct ecore_ilt *ilt,
793 struct ilt_client_info *ilt_cli,
794 uint8_t initop)
795 {
796 int i;
797
798 if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
799 return;
800
801 for (i = ilt_cli->start; i <= ilt_cli->end; i++)
802 ecore_ilt_line_init_op(sc, ilt, i, initop);
803
804 /* init/clear the ILT boundries */
805 ecore_ilt_boundry_init_op(sc, ilt_cli, ilt->start_line, initop);
806 }
807
ecore_ilt_client_init_op(struct bxe_softc * sc,struct ilt_client_info * ilt_cli,uint8_t initop)808 static void ecore_ilt_client_init_op(struct bxe_softc *sc,
809 struct ilt_client_info *ilt_cli, uint8_t initop)
810 {
811 struct ecore_ilt *ilt = SC_ILT(sc);
812
813 ecore_ilt_client_init_op_ilt(sc, ilt, ilt_cli, initop);
814 }
815
ecore_ilt_client_id_init_op(struct bxe_softc * sc,int cli_num,uint8_t initop)816 static void ecore_ilt_client_id_init_op(struct bxe_softc *sc,
817 int cli_num, uint8_t initop)
818 {
819 struct ecore_ilt *ilt = SC_ILT(sc);
820 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
821
822 ecore_ilt_client_init_op(sc, ilt_cli, initop);
823 }
824
ecore_ilt_init_op_cnic(struct bxe_softc * sc,uint8_t initop)825 static inline void ecore_ilt_init_op_cnic(struct bxe_softc *sc, uint8_t initop)
826 {
827 if (CONFIGURE_NIC_MODE(sc))
828 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);
829 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_TM, initop);
830 }
831
ecore_ilt_init_op(struct bxe_softc * sc,uint8_t initop)832 static void ecore_ilt_init_op(struct bxe_softc *sc, uint8_t initop)
833 {
834 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_CDU, initop);
835 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_QM, initop);
836 if (CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc))
837 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);
838 }
839
ecore_ilt_init_client_psz(struct bxe_softc * sc,int cli_num,uint32_t psz_reg,uint8_t initop)840 static void ecore_ilt_init_client_psz(struct bxe_softc *sc, int cli_num,
841 uint32_t psz_reg, uint8_t initop)
842 {
843 struct ecore_ilt *ilt = SC_ILT(sc);
844 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
845
846 if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
847 return;
848
849 switch (initop) {
850 case INITOP_INIT:
851 /* set in the init-value array */
852 case INITOP_SET:
853 REG_WR(sc, psz_reg, ILOG2(ilt_cli->page_size >> 12));
854 break;
855 case INITOP_CLEAR:
856 break;
857 }
858 }
859
860 /*
861 * called during init common stage, ilt clients should be initialized
862 * prioir to calling this function
863 */
ecore_ilt_init_page_size(struct bxe_softc * sc,uint8_t initop)864 static void ecore_ilt_init_page_size(struct bxe_softc *sc, uint8_t initop)
865 {
866 ecore_ilt_init_client_psz(sc, ILT_CLIENT_CDU,
867 PXP2_REG_RQ_CDU_P_SIZE, initop);
868 ecore_ilt_init_client_psz(sc, ILT_CLIENT_QM,
869 PXP2_REG_RQ_QM_P_SIZE, initop);
870 ecore_ilt_init_client_psz(sc, ILT_CLIENT_SRC,
871 PXP2_REG_RQ_SRC_P_SIZE, initop);
872 ecore_ilt_init_client_psz(sc, ILT_CLIENT_TM,
873 PXP2_REG_RQ_TM_P_SIZE, initop);
874 }
875
876 /****************************************************************************
877 * QM initializations
878 ****************************************************************************/
879 #define QM_QUEUES_PER_FUNC 16 /* E1 has 32, but only 16 are used */
880 #define QM_INIT_MIN_CID_COUNT 31
881 #define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT)
882
883 /* called during init port stage */
ecore_qm_init_cid_count(struct bxe_softc * sc,int qm_cid_count,uint8_t initop)884 static void ecore_qm_init_cid_count(struct bxe_softc *sc, int qm_cid_count,
885 uint8_t initop)
886 {
887 int port = SC_PORT(sc);
888
889 if (QM_INIT(qm_cid_count)) {
890 switch (initop) {
891 case INITOP_INIT:
892 /* set in the init-value array */
893 case INITOP_SET:
894 REG_WR(sc, QM_REG_CONNNUM_0 + port*4,
895 qm_cid_count/16 - 1);
896 break;
897 case INITOP_CLEAR:
898 break;
899 }
900 }
901 }
902
ecore_qm_set_ptr_table(struct bxe_softc * sc,int qm_cid_count,uint32_t base_reg,uint32_t reg)903 static void ecore_qm_set_ptr_table(struct bxe_softc *sc, int qm_cid_count,
904 uint32_t base_reg, uint32_t reg)
905 {
906 int i;
907 uint32_t wb_data[2] = {0, 0};
908 for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) {
909 REG_WR(sc, base_reg + i*4,
910 qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));
911 ecore_init_wr_wb(sc, reg + i*8,
912 wb_data, 2);
913 }
914 }
915
916 /* called during init common stage */
ecore_qm_init_ptr_table(struct bxe_softc * sc,int qm_cid_count,uint8_t initop)917 static void ecore_qm_init_ptr_table(struct bxe_softc *sc, int qm_cid_count,
918 uint8_t initop)
919 {
920 if (!QM_INIT(qm_cid_count))
921 return;
922
923 switch (initop) {
924 case INITOP_INIT:
925 /* set in the init-value array */
926 case INITOP_SET:
927 ecore_qm_set_ptr_table(sc, qm_cid_count,
928 QM_REG_BASEADDR, QM_REG_PTRTBL);
929 if (CHIP_IS_E1H(sc))
930 ecore_qm_set_ptr_table(sc, qm_cid_count,
931 QM_REG_BASEADDR_EXT_A,
932 QM_REG_PTRTBL_EXT_A);
933 break;
934 case INITOP_CLEAR:
935 break;
936 }
937 }
938
939 /****************************************************************************
940 * SRC initializations
941 ****************************************************************************/
942 #ifdef ECORE_L5
943 /* called during init func stage */
ecore_src_init_t2(struct bxe_softc * sc,struct src_ent * t2,ecore_dma_addr_t t2_mapping,int src_cid_count)944 static void ecore_src_init_t2(struct bxe_softc *sc, struct src_ent *t2,
945 ecore_dma_addr_t t2_mapping, int src_cid_count)
946 {
947 int i;
948 int port = SC_PORT(sc);
949
950 /* Initialize T2 */
951 for (i = 0; i < src_cid_count-1; i++)
952 t2[i].next = (uint64_t)(t2_mapping +
953 (i+1)*sizeof(struct src_ent));
954
955 /* tell the searcher where the T2 table is */
956 REG_WR(sc, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
957
958 ecore_wr_64(sc, SRC_REG_FIRSTFREE0 + port*16,
959 U64_LO(t2_mapping), U64_HI(t2_mapping));
960
961 ecore_wr_64(sc, SRC_REG_LASTFREE0 + port*16,
962 U64_LO((uint64_t)t2_mapping +
963 (src_cid_count-1) * sizeof(struct src_ent)),
964 U64_HI((uint64_t)t2_mapping +
965 (src_cid_count-1) * sizeof(struct src_ent)));
966 }
967 #endif
968 #endif /* ECORE_INIT_OPS_H */
969