1 #ifndef ECORE_INIT_OPS_H 2 #define ECORE_INIT_OPS_H 3 4 5 #ifndef PDEV_ILT 6 #define PDEV_ILT(bp) NULL 7 #endif 8 9 #ifndef PDEV_FUNC 10 #define PDEV_FUNC(bp) 0 11 #endif 12 13 #ifndef PDEV_PORT 14 #define PDEV_PORT(bp) 0 15 #endif 16 17 #ifndef ECORE_ILT_FREE 18 #define ECORE_ILT_FREE(x, y, sz) 19 #endif 20 21 #ifndef ECORE_ILT_ZALLOC 22 #define ECORE_ILT_ZALLOC(x, y, sz) 23 #endif 24 25 #ifndef ILOG2 26 #define ILOG2(x) x 27 #endif 28 29 #define FORCE32 (u32) 30 31 static int ecore_gunzip(struct _lm_device_t *pdev, const u8 *zbuf, int len); 32 static void ecore_reg_wr_ind(struct _lm_device_t *pdev, u32 addr, u32 val); 33 static void ecore_write_dmae_phys_len(struct _lm_device_t *pdev, 34 lm_address_t phys_addr, u32 addr, 35 u32 len); 36 37 static void ecore_init_str_wr(struct _lm_device_t *pdev, u32 addr, 38 const u32 *data, u32 len) 39 { 40 u32 i; 41 42 for (i = 0; i < len; i++) 43 REG_WR(pdev, addr + i*4, data[i]); 44 } 45 46 static void ecore_init_ind_wr(struct _lm_device_t *pdev, u32 addr, 47 const u32 *data, u32 len) 48 { 49 u32 i; 50 51 for (i = 0; i < len; i++) 52 ecore_reg_wr_ind(pdev, addr + i*4, data[i]); 53 } 54 55 static void ecore_write_big_buf(struct _lm_device_t *pdev, u32 addr, u32 len, 56 u8 wb) 57 { 58 if (DMAE_READY(pdev)) 59 ecore_write_dmae_phys_len(pdev, GUNZIP_PHYS(pdev), addr, len); 60 61 /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */ 62 else if (wb && CHIP_IS_E1(pdev)) 63 ecore_init_ind_wr(pdev, addr, GUNZIP_BUF(pdev), len); 64 65 /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */ 66 else 67 ecore_init_str_wr(pdev, addr, GUNZIP_BUF(pdev), len); 68 } 69 70 static void ecore_init_fill(struct _lm_device_t *pdev, u32 addr, int fill, 71 u32 len, u8 wb) 72 { 73 u32 buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4)); 74 u32 buf_len32 = buf_len/4; 75 u32 i; 76 77 mm_memset(GUNZIP_BUF(pdev), (u8)fill, buf_len); 78 79 for (i = 0; i < len; i += buf_len32) { 80 u32 cur_len = min(buf_len32, len - i); 81 82 ecore_write_big_buf(pdev, addr + i*4, cur_len, wb); 83 } 84 } 85 86 static void ecore_write_big_buf_wb(struct _lm_device_t *pdev, u32 addr, u32 len) 87 { 88 if (DMAE_READY(pdev)) 89 ecore_write_dmae_phys_len(pdev, GUNZIP_PHYS(pdev), addr, len); 90 91 /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */ 92 else if (CHIP_IS_E1(pdev)) 93 ecore_init_ind_wr(pdev, addr, GUNZIP_BUF(pdev), len); 94 95 /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */ 96 else 97 ecore_init_str_wr(pdev, addr, GUNZIP_BUF(pdev), len); 98 } 99 100 static void ecore_init_wr_64(struct _lm_device_t *pdev, u32 addr, 101 const u32 *data, u32 len64) 102 { 103 u32 buf_len32 = FW_BUF_SIZE/4; 104 u32 len = len64*2; 105 u64 data64 = 0; 106 u32 i; 107 108 /* 64 bit value is in a blob: first low DWORD, then high DWORD */ 109 data64 = HILO_U64((*(data + 1)), (*data)); 110 111 len64 = min((u32)(FW_BUF_SIZE/8), len64); 112 for (i = 0; i < len64; i++) { 113 u64 *pdata = ((u64 *)(GUNZIP_BUF(pdev))) + i; 114 115 *pdata = data64; 116 } 117 118 for (i = 0; i < len; i += buf_len32) { 119 u32 cur_len = min(buf_len32, len - i); 120 121 ecore_write_big_buf_wb(pdev, addr + i*4, cur_len); 122 } 123 } 124 125 /********************************************************* 126 There are different blobs for each PRAM section. 127 In addition, each blob write operation is divided into a few operations 128 in order to decrease the amount of phys. contiguous buffer needed. 129 Thus, when we select a blob the address may be with some offset 130 from the beginning of PRAM section. 131 The same holds for the INT_TABLE sections. 132 **********************************************************/ 133 #define IF_IS_INT_TABLE_ADDR(base, addr) \ 134 if (((base) <= (addr)) && ((base) + 0x400 >= (addr))) 135 136 #define IF_IS_PRAM_ADDR(base, addr) \ 137 if (((base) <= (addr)) && ((base) + 0x40000 >= (addr))) 138 139 static const u8 *ecore_sel_blob(struct _lm_device_t *pdev, u32 addr, 140 const u8 *data) 141 { 142 IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr) 143 data = INIT_TSEM_INT_TABLE_DATA(pdev); 144 else 145 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr) 146 data = INIT_CSEM_INT_TABLE_DATA(pdev); 147 else 148 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr) 149 data = INIT_USEM_INT_TABLE_DATA(pdev); 150 else 151 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr) 152 data = INIT_XSEM_INT_TABLE_DATA(pdev); 153 else 154 IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr) 155 data = INIT_TSEM_PRAM_DATA(pdev); 156 else 157 IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr) 158 data = INIT_CSEM_PRAM_DATA(pdev); 159 else 160 IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr) 161 data = INIT_USEM_PRAM_DATA(pdev); 162 else 163 IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr) 164 data = INIT_XSEM_PRAM_DATA(pdev); 165 166 return data; 167 } 168 169 static void ecore_init_wr_wb(struct _lm_device_t *pdev, u32 addr, 170 const u32 *data, u32 len) 171 { 172 if (DMAE_READY(pdev)) 173 VIRT_WR_DMAE_LEN(pdev, data, addr, len, 0); 174 175 /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */ 176 else if (CHIP_IS_E1(pdev)) 177 ecore_init_ind_wr(pdev, addr, data, len); 178 179 /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */ 180 else 181 ecore_init_str_wr(pdev, addr, data, len); 182 } 183 184 #ifndef FW_ZIP_SUPPORT /* ! BNX2X_UPSTREAM */ 185 static void ecore_init_fw(struct _lm_device_t *pdev, u32 addr, u32 len) 186 { 187 const u8 *data = NULL; 188 189 data = ecore_sel_blob(pdev, addr, (const u8 *)data); 190 191 if (DMAE_READY(pdev)) 192 VIRT_WR_DMAE_LEN(pdev, data, addr, len, 1); 193 194 /* in E1 BIOS initiated ZLR may interrupt widebus writes */ 195 else if (CHIP_IS_E1(pdev)) 196 ecore_init_ind_wr(pdev, addr, (const u32 *)data, len); 197 198 /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */ 199 else 200 ecore_init_str_wr(pdev, addr, (const u32 *)data, len); 201 } 202 203 #endif 204 205 #ifdef ECORE_UPSTREAM /* ECORE_UPSTREAM */ 206 static void ecore_wr_64(struct _lm_device_t *pdev, u32 reg, u32 val_lo, 207 u32 val_hi) 208 { 209 u32 wb_write[2]; 210 211 wb_write[0] = val_lo; 212 wb_write[1] = val_hi; 213 REG_WR_DMAE_LEN(pdev, reg, wb_write, 2); 214 } 215 #endif 216 217 static void ecore_init_wr_zp(struct _lm_device_t *pdev, u32 addr, u32 len, 218 u32 blob_off) 219 { 220 const u8 *data = NULL; 221 int rc; 222 u32 i; 223 224 data = ecore_sel_blob(pdev, addr, data) + blob_off*4; 225 226 rc = ecore_gunzip(pdev, data, len); 227 if (rc) 228 return; 229 230 /* gunzip_outlen is in dwords */ 231 len = GUNZIP_OUTLEN(pdev); 232 for (i = 0; i < len; i++) 233 ((u32 *)GUNZIP_BUF(pdev))[i] = FORCE32 234 mm_cpu_to_le32(((u32 *)GUNZIP_BUF(pdev))[i]); 235 236 ecore_write_big_buf_wb(pdev, addr, len); 237 } 238 239 static void ecore_init_block(struct _lm_device_t *pdev, u32 block, u32 stage) 240 { 241 u16 op_start = 242 INIT_OPS_OFFSETS(pdev)[BLOCK_OPS_IDX(block, stage, 243 STAGE_START)]; 244 u16 op_end = 245 INIT_OPS_OFFSETS(pdev)[BLOCK_OPS_IDX(block, stage, 246 STAGE_END)]; 247 const union init_op *op; 248 u32 op_idx, op_type, addr, len; 249 const u32 *data, *data_base; 250 251 /* If empty block */ 252 if (op_start == op_end) 253 return; 254 255 data_base = INIT_DATA(pdev); 256 257 for (op_idx = op_start; op_idx < op_end; op_idx++) { 258 259 op = (const union init_op *)&(INIT_OPS(pdev)[op_idx]); 260 /* Get generic data */ 261 op_type = op->raw.op; 262 addr = op->raw.offset; 263 /* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and 264 * OP_WR64 (we assume that op_arr_write and op_write have the 265 * same structure). 266 */ 267 len = op->arr_wr.data_len; 268 data = data_base + op->arr_wr.data_off; 269 270 switch (op_type) { 271 case OP_RD: 272 REG_RD(pdev, addr); 273 break; 274 case OP_WR: 275 REG_WR(pdev, addr, op->write.val); 276 break; 277 case OP_SW: 278 ecore_init_str_wr(pdev, addr, data, len); 279 break; 280 case OP_WB: 281 ecore_init_wr_wb(pdev, addr, data, len); 282 break; 283 #ifndef FW_ZIP_SUPPORT /* ! BNX2X_UPSTREAM */ 284 case OP_FW: 285 ecore_init_fw(pdev, addr, len); 286 break; 287 #endif 288 case OP_ZR: 289 ecore_init_fill(pdev, addr, 0, op->zero.len, 0); 290 break; 291 case OP_WB_ZR: 292 ecore_init_fill(pdev, addr, 0, op->zero.len, 1); 293 break; 294 case OP_ZP: 295 ecore_init_wr_zp(pdev, addr, len, 296 op->arr_wr.data_off); 297 break; 298 case OP_WR_64: 299 ecore_init_wr_64(pdev, addr, data, len); 300 break; 301 case OP_IF_MODE_AND: 302 /* if any of the flags doesn't match, skip the 303 * conditional block. 304 */ 305 if ((INIT_MODE_FLAGS(pdev) & 306 op->if_mode.mode_bit_map) != 307 op->if_mode.mode_bit_map) 308 op_idx += op->if_mode.cmd_offset; 309 break; 310 case OP_IF_MODE_OR: 311 /* if all the flags don't match, skip the conditional 312 * block. 313 */ 314 if ((INIT_MODE_FLAGS(pdev) & 315 op->if_mode.mode_bit_map) == 0) 316 op_idx += op->if_mode.cmd_offset; 317 break; 318 #ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ 319 /* the following opcodes are unused at the moment. */ 320 case OP_IF_PHASE: 321 case OP_RT: 322 case OP_DELAY: 323 case OP_VERIFY: 324 #endif 325 default: 326 /* Should never get here! */ 327 DbgBreakIf(TRUE); 328 break; 329 } 330 } 331 } 332 333 334 /**************************************************************************** 335 * PXP Arbiter 336 ****************************************************************************/ 337 /* 338 * This code configures the PCI read/write arbiter 339 * which implements a weighted round robin 340 * between the virtual queues in the chip. 341 * 342 * The values were derived for each PCI max payload and max request size. 343 * since max payload and max request size are only known at run time, 344 * this is done as a separate init stage. 345 */ 346 347 #define NUM_WR_Q 13 348 #define NUM_RD_Q 29 349 #define MAX_RD_ORD 3 350 #define MAX_WR_ORD 2 351 352 /* configuration for one arbiter queue */ 353 struct arb_line { 354 int l; 355 int add; 356 int ubound; 357 }; 358 359 /* derived configuration for each read queue for each max request size */ 360 static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = { 361 /* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} }, 362 { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} }, 363 { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} }, 364 { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} }, 365 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} }, 366 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, 367 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, 368 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, 369 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, 370 /* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 371 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 372 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 373 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 374 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 375 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 376 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 377 { {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} }, 378 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 379 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 380 /* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 381 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 382 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 383 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 384 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 385 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 386 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 387 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 388 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 389 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} } 390 }; 391 392 /* derived configuration for each write queue for each max request size */ 393 static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = { 394 /* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} }, 395 { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} }, 396 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, 397 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, 398 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, 399 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, 400 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} }, 401 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, 402 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, 403 /* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} }, 404 { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} }, 405 { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} }, 406 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} } 407 }; 408 409 /* register addresses for read queues */ 410 static const struct arb_line read_arb_addr[NUM_RD_Q-1] = { 411 /* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0, 412 PXP2_REG_RQ_BW_RD_UBOUND0}, 413 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, 414 PXP2_REG_PSWRQ_BW_UB1}, 415 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, 416 PXP2_REG_PSWRQ_BW_UB2}, 417 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, 418 PXP2_REG_PSWRQ_BW_UB3}, 419 {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4, 420 PXP2_REG_RQ_BW_RD_UBOUND4}, 421 {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5, 422 PXP2_REG_RQ_BW_RD_UBOUND5}, 423 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, 424 PXP2_REG_PSWRQ_BW_UB6}, 425 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, 426 PXP2_REG_PSWRQ_BW_UB7}, 427 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, 428 PXP2_REG_PSWRQ_BW_UB8}, 429 /* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, 430 PXP2_REG_PSWRQ_BW_UB9}, 431 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, 432 PXP2_REG_PSWRQ_BW_UB10}, 433 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, 434 PXP2_REG_PSWRQ_BW_UB11}, 435 {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12, 436 PXP2_REG_RQ_BW_RD_UBOUND12}, 437 {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13, 438 PXP2_REG_RQ_BW_RD_UBOUND13}, 439 {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14, 440 PXP2_REG_RQ_BW_RD_UBOUND14}, 441 {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15, 442 PXP2_REG_RQ_BW_RD_UBOUND15}, 443 {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16, 444 PXP2_REG_RQ_BW_RD_UBOUND16}, 445 {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17, 446 PXP2_REG_RQ_BW_RD_UBOUND17}, 447 {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18, 448 PXP2_REG_RQ_BW_RD_UBOUND18}, 449 /* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19, 450 PXP2_REG_RQ_BW_RD_UBOUND19}, 451 {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20, 452 PXP2_REG_RQ_BW_RD_UBOUND20}, 453 {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22, 454 PXP2_REG_RQ_BW_RD_UBOUND22}, 455 {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23, 456 PXP2_REG_RQ_BW_RD_UBOUND23}, 457 {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24, 458 PXP2_REG_RQ_BW_RD_UBOUND24}, 459 {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25, 460 PXP2_REG_RQ_BW_RD_UBOUND25}, 461 {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26, 462 PXP2_REG_RQ_BW_RD_UBOUND26}, 463 {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27, 464 PXP2_REG_RQ_BW_RD_UBOUND27}, 465 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, 466 PXP2_REG_PSWRQ_BW_UB28} 467 }; 468 469 /* register addresses for write queues */ 470 static const struct arb_line write_arb_addr[NUM_WR_Q-1] = { 471 /* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, 472 PXP2_REG_PSWRQ_BW_UB1}, 473 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, 474 PXP2_REG_PSWRQ_BW_UB2}, 475 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, 476 PXP2_REG_PSWRQ_BW_UB3}, 477 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, 478 PXP2_REG_PSWRQ_BW_UB6}, 479 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, 480 PXP2_REG_PSWRQ_BW_UB7}, 481 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, 482 PXP2_REG_PSWRQ_BW_UB8}, 483 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, 484 PXP2_REG_PSWRQ_BW_UB9}, 485 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, 486 PXP2_REG_PSWRQ_BW_UB10}, 487 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, 488 PXP2_REG_PSWRQ_BW_UB11}, 489 /* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, 490 PXP2_REG_PSWRQ_BW_UB28}, 491 {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29, 492 PXP2_REG_RQ_BW_WR_UBOUND29}, 493 {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30, 494 PXP2_REG_RQ_BW_WR_UBOUND30} 495 }; 496 497 static void ecore_init_pxp_arb(struct _lm_device_t *pdev, int r_order, 498 int w_order) 499 { 500 u32 val, i; 501 502 if (r_order > MAX_RD_ORD) { 503 DbgMessage(pdev, WARNi, "read order of %d order adjusted to %d\n", 504 r_order, MAX_RD_ORD); 505 r_order = MAX_RD_ORD; 506 } 507 if (w_order > MAX_WR_ORD) { 508 DbgMessage(pdev, WARNi, "write order of %d order adjusted to %d\n", 509 w_order, MAX_WR_ORD); 510 w_order = MAX_WR_ORD; 511 } 512 if (CHIP_REV_IS_FPGA(pdev)) { 513 DbgMessage(pdev, WARNi, "write order adjusted to 1 for FPGA\n"); 514 w_order = 0; 515 } 516 DbgMessage(pdev, INFORMi, "read order %d write order %d\n", r_order, w_order); 517 518 for (i = 0; i < NUM_RD_Q-1; i++) { 519 REG_WR(pdev, read_arb_addr[i].l, read_arb_data[i][r_order].l); 520 REG_WR(pdev, read_arb_addr[i].add, 521 read_arb_data[i][r_order].add); 522 REG_WR(pdev, read_arb_addr[i].ubound, 523 read_arb_data[i][r_order].ubound); 524 } 525 526 for (i = 0; i < NUM_WR_Q-1; i++) { 527 if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) || 528 (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) { 529 530 REG_WR(pdev, write_arb_addr[i].l, 531 write_arb_data[i][w_order].l); 532 533 REG_WR(pdev, write_arb_addr[i].add, 534 write_arb_data[i][w_order].add); 535 536 REG_WR(pdev, write_arb_addr[i].ubound, 537 write_arb_data[i][w_order].ubound); 538 } else { 539 540 val = REG_RD(pdev, write_arb_addr[i].l); 541 REG_WR(pdev, write_arb_addr[i].l, 542 val | (write_arb_data[i][w_order].l << 10)); 543 544 val = REG_RD(pdev, write_arb_addr[i].add); 545 REG_WR(pdev, write_arb_addr[i].add, 546 val | (write_arb_data[i][w_order].add << 10)); 547 548 val = REG_RD(pdev, write_arb_addr[i].ubound); 549 REG_WR(pdev, write_arb_addr[i].ubound, 550 val | (write_arb_data[i][w_order].ubound << 7)); 551 } 552 } 553 554 val = write_arb_data[NUM_WR_Q-1][w_order].add; 555 val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10; 556 val += write_arb_data[NUM_WR_Q-1][w_order].l << 17; 557 REG_WR(pdev, PXP2_REG_PSWRQ_BW_RD, val); 558 559 val = read_arb_data[NUM_RD_Q-1][r_order].add; 560 val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10; 561 val += read_arb_data[NUM_RD_Q-1][r_order].l << 17; 562 REG_WR(pdev, PXP2_REG_PSWRQ_BW_WR, val); 563 564 REG_WR(pdev, PXP2_REG_RQ_WR_MBS0, w_order); 565 REG_WR(pdev, PXP2_REG_RQ_WR_MBS1, w_order); 566 REG_WR(pdev, PXP2_REG_RQ_RD_MBS0, r_order); 567 REG_WR(pdev, PXP2_REG_RQ_RD_MBS1, r_order); 568 569 if ((CHIP_IS_E1(pdev) || CHIP_IS_E1H(pdev)) && (r_order == MAX_RD_ORD)) 570 REG_WR(pdev, PXP2_REG_RQ_PDR_LIMIT, 0xe00); 571 572 if (CHIP_IS_E3(pdev)) 573 REG_WR(pdev, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order)); 574 else if (CHIP_IS_E2(pdev)) 575 REG_WR(pdev, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order)); 576 else 577 REG_WR(pdev, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); 578 579 if (!CHIP_IS_E1(pdev)) { 580 /* MPS w_order optimal TH presently TH 581 * 128 0 0 2 582 * 256 1 1 3 583 * >=512 2 2 3 584 */ 585 /* DMAE is special */ 586 if (!CHIP_IS_E1H(pdev)) { 587 /* E2 can use optimal TH */ 588 val = w_order; 589 REG_WR(pdev, PXP2_REG_WR_DMAE_MPS, val); 590 } else { 591 val = ((w_order == 0) ? 2 : 3); 592 REG_WR(pdev, PXP2_REG_WR_DMAE_MPS, 2); 593 } 594 595 REG_WR(pdev, PXP2_REG_WR_HC_MPS, val); 596 REG_WR(pdev, PXP2_REG_WR_USDM_MPS, val); 597 REG_WR(pdev, PXP2_REG_WR_CSDM_MPS, val); 598 REG_WR(pdev, PXP2_REG_WR_TSDM_MPS, val); 599 REG_WR(pdev, PXP2_REG_WR_XSDM_MPS, val); 600 REG_WR(pdev, PXP2_REG_WR_QM_MPS, val); 601 REG_WR(pdev, PXP2_REG_WR_TM_MPS, val); 602 REG_WR(pdev, PXP2_REG_WR_SRC_MPS, val); 603 REG_WR(pdev, PXP2_REG_WR_DBG_MPS, val); 604 REG_WR(pdev, PXP2_REG_WR_CDU_MPS, val); 605 } 606 607 /* Validate number of tags suppoted by device */ 608 #define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980 609 val = REG_RD(pdev, PCIE_REG_PCIER_TL_HDR_FC_ST); 610 val &= 0xFF; 611 if (val <= 0x20) 612 REG_WR(pdev, PXP2_REG_PGL_TAGS_LIMIT, 0x20); 613 } 614 615 #ifdef ECORE_UPSTREAM /* ECORE_UPSTREAM */ 616 /**************************************************************************** 617 * ILT management 618 ****************************************************************************/ 619 /* 620 * This codes hides the low level HW interaction for ILT management and 621 * configuration. The API consists of a shadow ILT table which is set by the 622 * driver and a set of routines to use it to configure the HW. 623 * 624 */ 625 626 /* ILT HW init operations */ 627 628 /* ILT memory management operations */ 629 #define ILT_MEMOP_ALLOC 0 630 #define ILT_MEMOP_FREE 1 631 632 /* the phys address is shifted right 12 bits and has an added 633 * 1=valid bit added to the 53rd bit 634 * then since this is a wide register(TM) 635 * we split it into two 32 bit writes 636 */ 637 #define ILT_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 638 #define ILT_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 639 #define ILT_RANGE(f, l) (((l) << 10) | f) 640 641 static int ecore_ilt_line_mem_op(struct _lm_device_t *pdev, 642 struct ilt_line *line, u32 size, u8 memop) 643 { 644 if (memop == ILT_MEMOP_FREE) { 645 ECORE_ILT_FREE(line->page, line->page_mapping, line->size); 646 return 0; 647 } 648 ECORE_ILT_ZALLOC(line->page, &line->page_mapping, size); 649 if (!line->page) 650 return -1; 651 line->size = size; 652 return 0; 653 } 654 655 656 static int ecore_ilt_client_mem_op(struct _lm_device_t *pdev, int cli_num, 657 u8 memop) 658 { 659 int i, rc; 660 struct ecore_ilt *ilt = PDEV_ILT(pdev); 661 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num]; 662 663 if (!ilt || !ilt->lines) 664 return -1; 665 666 if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM)) 667 return 0; 668 669 for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) { 670 rc = ecore_ilt_line_mem_op(pdev, &ilt->lines[i], 671 ilt_cli->page_size, memop); 672 } 673 return rc; 674 } 675 676 static int ecore_ilt_mem_op_cnic(struct _lm_device_t *pdev, u8 memop) 677 { 678 int rc = 0; 679 680 if (CONFIGURE_NIC_MODE(pdev)) 681 rc = ecore_ilt_client_mem_op(pdev, ILT_CLIENT_SRC, memop); 682 if (!rc) 683 rc = ecore_ilt_client_mem_op(pdev, ILT_CLIENT_TM, memop); 684 685 return rc; 686 } 687 688 static int ecore_ilt_mem_op(struct _lm_device_t *pdev, u8 memop) 689 { 690 int rc = ecore_ilt_client_mem_op(pdev, ILT_CLIENT_CDU, memop); 691 if (!rc) 692 rc = ecore_ilt_client_mem_op(pdev, ILT_CLIENT_QM, memop); 693 if (!rc && CNIC_SUPPORT(pdev) && !CONFIGURE_NIC_MODE(pdev)) 694 rc = ecore_ilt_client_mem_op(pdev, ILT_CLIENT_SRC, memop); 695 696 return rc; 697 } 698 699 static void ecore_ilt_line_wr(struct _lm_device_t *pdev, int abs_idx, 700 lm_address_t page_mapping) 701 { 702 u32 reg; 703 704 if (CHIP_IS_E1(pdev)) 705 reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8; 706 else 707 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8; 708 709 ecore_wr_64(pdev, reg, ILT_ADDR1(page_mapping.as_u64), ILT_ADDR2(page_mapping.as_u64)); 710 } 711 712 static void ecore_ilt_line_init_op(struct _lm_device_t *pdev, 713 struct ecore_ilt *ilt, int idx, u8 initop) 714 { 715 lm_address_t null_mapping; 716 int abs_idx = ilt->start_line + idx; 717 718 719 switch (initop) { 720 case INITOP_INIT: 721 /* set in the init-value array */ 722 case INITOP_SET: 723 ecore_ilt_line_wr(pdev, abs_idx, ilt->lines[idx].page_mapping); 724 break; 725 case INITOP_CLEAR: 726 null_mapping.as_u64 = 0; 727 ecore_ilt_line_wr(pdev, abs_idx, null_mapping); 728 break; 729 } 730 } 731 732 static void ecore_ilt_boundry_init_op(struct _lm_device_t *pdev, 733 struct ilt_client_info *ilt_cli, 734 u32 ilt_start, u8 initop) 735 { 736 u32 start_reg = 0; 737 u32 end_reg = 0; 738 739 /* The boundary is either SET or INIT, 740 CLEAR => SET and for now SET ~~ INIT */ 741 742 /* find the appropriate regs */ 743 if (CHIP_IS_E1(pdev)) { 744 switch (ilt_cli->client_num) { 745 case ILT_CLIENT_CDU: 746 start_reg = PXP2_REG_PSWRQ_CDU0_L2P; 747 break; 748 case ILT_CLIENT_QM: 749 start_reg = PXP2_REG_PSWRQ_QM0_L2P; 750 break; 751 case ILT_CLIENT_SRC: 752 start_reg = PXP2_REG_PSWRQ_SRC0_L2P; 753 break; 754 case ILT_CLIENT_TM: 755 start_reg = PXP2_REG_PSWRQ_TM0_L2P; 756 break; 757 } 758 REG_WR(pdev, start_reg + PDEV_FUNC(pdev)*4, 759 ILT_RANGE((ilt_start + ilt_cli->start), 760 (ilt_start + ilt_cli->end))); 761 } else { 762 switch (ilt_cli->client_num) { 763 case ILT_CLIENT_CDU: 764 start_reg = PXP2_REG_RQ_CDU_FIRST_ILT; 765 end_reg = PXP2_REG_RQ_CDU_LAST_ILT; 766 break; 767 case ILT_CLIENT_QM: 768 start_reg = PXP2_REG_RQ_QM_FIRST_ILT; 769 end_reg = PXP2_REG_RQ_QM_LAST_ILT; 770 break; 771 case ILT_CLIENT_SRC: 772 start_reg = PXP2_REG_RQ_SRC_FIRST_ILT; 773 end_reg = PXP2_REG_RQ_SRC_LAST_ILT; 774 break; 775 case ILT_CLIENT_TM: 776 start_reg = PXP2_REG_RQ_TM_FIRST_ILT; 777 end_reg = PXP2_REG_RQ_TM_LAST_ILT; 778 break; 779 } 780 REG_WR(pdev, start_reg, (ilt_start + ilt_cli->start)); 781 REG_WR(pdev, end_reg, (ilt_start + ilt_cli->end)); 782 } 783 } 784 785 static void ecore_ilt_client_init_op_ilt(struct _lm_device_t *pdev, 786 struct ecore_ilt *ilt, 787 struct ilt_client_info *ilt_cli, 788 u8 initop) 789 { 790 int i; 791 792 if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT) 793 return; 794 795 for (i = ilt_cli->start; i <= ilt_cli->end; i++) 796 ecore_ilt_line_init_op(pdev, ilt, i, initop); 797 798 /* init/clear the ILT boundries */ 799 ecore_ilt_boundry_init_op(pdev, ilt_cli, ilt->start_line, initop); 800 } 801 802 static void ecore_ilt_client_init_op(struct _lm_device_t *pdev, 803 struct ilt_client_info *ilt_cli, u8 initop) 804 { 805 struct ecore_ilt *ilt = PDEV_ILT(pdev); 806 807 ecore_ilt_client_init_op_ilt(pdev, ilt, ilt_cli, initop); 808 } 809 810 static void ecore_ilt_client_id_init_op(struct _lm_device_t *pdev, 811 int cli_num, u8 initop) 812 { 813 struct ecore_ilt *ilt = PDEV_ILT(pdev); 814 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num]; 815 816 ecore_ilt_client_init_op(pdev, ilt_cli, initop); 817 } 818 819 static void ecore_ilt_init_op_cnic(struct _lm_device_t *pdev, u8 initop) 820 { 821 if (CONFIGURE_NIC_MODE(pdev)) 822 ecore_ilt_client_id_init_op(pdev, ILT_CLIENT_SRC, initop); 823 ecore_ilt_client_id_init_op(pdev, ILT_CLIENT_TM, initop); 824 } 825 826 static void ecore_ilt_init_op(struct _lm_device_t *pdev, u8 initop) 827 { 828 ecore_ilt_client_id_init_op(pdev, ILT_CLIENT_CDU, initop); 829 ecore_ilt_client_id_init_op(pdev, ILT_CLIENT_QM, initop); 830 if (CNIC_SUPPORT(pdev) && !CONFIGURE_NIC_MODE(pdev)) 831 ecore_ilt_client_id_init_op(pdev, ILT_CLIENT_SRC, initop); 832 } 833 834 static void ecore_ilt_init_client_psz(struct _lm_device_t *pdev, int cli_num, 835 u32 psz_reg, u8 initop) 836 { 837 struct ecore_ilt *ilt = PDEV_ILT(pdev); 838 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num]; 839 840 if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT) 841 return; 842 843 switch (initop) { 844 case INITOP_INIT: 845 /* set in the init-value array */ 846 case INITOP_SET: 847 REG_WR(pdev, psz_reg, ILOG2(ilt_cli->page_size >> 12)); 848 break; 849 case INITOP_CLEAR: 850 break; 851 } 852 } 853 854 /* 855 * called during init common stage, ilt clients should be initialized 856 * prioir to calling this function 857 */ 858 static void ecore_ilt_init_page_size(struct _lm_device_t *pdev, u8 initop) 859 { 860 ecore_ilt_init_client_psz(pdev, ILT_CLIENT_CDU, 861 PXP2_REG_RQ_CDU_P_SIZE, initop); 862 ecore_ilt_init_client_psz(pdev, ILT_CLIENT_QM, 863 PXP2_REG_RQ_QM_P_SIZE, initop); 864 ecore_ilt_init_client_psz(pdev, ILT_CLIENT_SRC, 865 PXP2_REG_RQ_SRC_P_SIZE, initop); 866 ecore_ilt_init_client_psz(pdev, ILT_CLIENT_TM, 867 PXP2_REG_RQ_TM_P_SIZE, initop); 868 } 869 870 /**************************************************************************** 871 * QM initializations 872 ****************************************************************************/ 873 #define QM_QUEUES_PER_FUNC 16 /* E1 has 32, but only 16 are used */ 874 #define QM_INIT_MIN_CID_COUNT 31 875 #define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT) 876 877 /* called during init port stage */ 878 static void ecore_qm_init_cid_count(struct _lm_device_t *pdev, int qm_cid_count, 879 u8 initop) 880 { 881 int port = PDEV_PORT(pdev); 882 883 if (QM_INIT(qm_cid_count)) { 884 switch (initop) { 885 case INITOP_INIT: 886 /* set in the init-value array */ 887 case INITOP_SET: 888 REG_WR(pdev, QM_REG_CONNNUM_0 + port*4, 889 qm_cid_count/16 - 1); 890 break; 891 case INITOP_CLEAR: 892 break; 893 } 894 } 895 } 896 897 static void ecore_qm_set_ptr_table(struct _lm_device_t *pdev, int qm_cid_count, 898 u32 base_reg, u32 reg) 899 { 900 int i; 901 u32 wb_data[2] = {0, 0}; 902 for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) { 903 REG_WR(pdev, base_reg + i*4, 904 qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC)); 905 ecore_init_wr_wb(pdev, reg + i*8, 906 wb_data, 2); 907 } 908 } 909 910 /* called during init common stage */ 911 static void ecore_qm_init_ptr_table(struct _lm_device_t *pdev, int qm_cid_count, 912 u8 initop) 913 { 914 if (!QM_INIT(qm_cid_count)) 915 return; 916 917 switch (initop) { 918 case INITOP_INIT: 919 /* set in the init-value array */ 920 case INITOP_SET: 921 ecore_qm_set_ptr_table(pdev, qm_cid_count, 922 QM_REG_BASEADDR, QM_REG_PTRTBL); 923 if (CHIP_IS_E1H(pdev)) 924 ecore_qm_set_ptr_table(pdev, qm_cid_count, 925 QM_REG_BASEADDR_EXT_A, 926 QM_REG_PTRTBL_EXT_A); 927 break; 928 case INITOP_CLEAR: 929 break; 930 } 931 } 932 933 #endif 934 /**************************************************************************** 935 * SRC initializations 936 ****************************************************************************/ 937 #ifdef ECORE_L5 938 /* called during init func stage */ 939 static void ecore_src_init_t2(struct _lm_device_t *pdev, struct src_ent *t2, 940 lm_address_t t2_mapping, int src_cid_count) 941 { 942 int i; 943 int port = PDEV_PORT(pdev); 944 945 /* Initialize T2 */ 946 for (i = 0; i < src_cid_count-1; i++) 947 t2[i].next = (u64)(t2_mapping.as_u64 + 948 (i+1)*sizeof(struct src_ent)); 949 950 /* tell the searcher where the T2 table is */ 951 REG_WR(pdev, SRC_REG_COUNTFREE0 + port*4, src_cid_count); 952 953 ecore_wr_64(pdev, SRC_REG_FIRSTFREE0 + port*16, 954 U64_LO(t2_mapping.as_u64), U64_HI(t2_mapping.as_u64)); 955 956 ecore_wr_64(pdev, SRC_REG_LASTFREE0 + port*16, 957 U64_LO((u64)t2_mapping.as_u64 + 958 (src_cid_count-1) * sizeof(struct src_ent)), 959 U64_HI((u64)t2_mapping.as_u64 + 960 (src_cid_count-1) * sizeof(struct src_ent))); 961 } 962 #endif 963 #endif /* ECORE_INIT_OPS_H */ 964