1 #ifndef ECORE_INIT_H
2 #define ECORE_INIT_H
3
4 #include "init_defs.h"
5 #include "aeu_inputs.h"
6
7 #if defined(_B10KD_EXT)
8 #include "b10ext_redefs.h"
9 #include "b10ext.h"
10 #endif
11
12 /* Returns the index of start or end of a specific block stage in ops array*/
13 #define BLOCK_OPS_IDX(block, stage, end) \
14 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
15
16
17 #define INITOP_SET 0 /* set the HW directly */
18 #define INITOP_CLEAR 1 /* clear the HW directly */
19 #define INITOP_INIT 2 /* set the init-value array */
20
21 /****************************************************************************
22 * ILT management
23 ****************************************************************************/
24 struct ilt_line {
25 lm_address_t page_mapping;
26 void *page;
27 u32 size;
28 };
29
30 struct ilt_client_info {
31 u32 page_size;
32 u16 start;
33 u16 end;
34 u16 client_num;
35 u16 flags;
36 #define ILT_CLIENT_SKIP_INIT 0x1
37 #define ILT_CLIENT_SKIP_MEM 0x2
38 };
39
40 struct ecore_ilt {
41 u32 start_line;
42 struct ilt_line *lines;
43 struct ilt_client_info clients[4];
44 #define ILT_CLIENT_CDU 0
45 #define ILT_CLIENT_QM 1
46 #define ILT_CLIENT_SRC 2
47 #define ILT_CLIENT_TM 3
48 };
49
50 /****************************************************************************
51 * SRC configuration
52 ****************************************************************************/
53 struct src_ent {
54 u8 opaque[56];
55 u64 next;
56 };
57
58 /****************************************************************************
59 * Parity configuration
60 ****************************************************************************/
61 #define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \
62 { \
63 block##_REG_##block##_PRTY_MASK, \
64 block##_REG_##block##_PRTY_STS_CLR, \
65 en_mask, {m1, m1h, m2, m3}, #block \
66 }
67
68 #define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \
69 { \
70 block##_REG_##block##_PRTY_MASK_0, \
71 block##_REG_##block##_PRTY_STS_CLR_0, \
72 en_mask, {m1, m1h, m2, m3}, #block"_0" \
73 }
74
75 #define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \
76 { \
77 block##_REG_##block##_PRTY_MASK_1, \
78 block##_REG_##block##_PRTY_STS_CLR_1, \
79 en_mask, {m1, m1h, m2, m3}, #block"_1" \
80 }
81
82 static const struct {
83 u32 mask_addr;
84 u32 sts_clr_addr;
85 u32 en_mask; /* Mask to enable parity attentions */
86 struct {
87 u32 e1; /* 57710 */
88 u32 e1h; /* 57711 */
89 u32 e2; /* 57712 */
90 u32 e3; /* 578xx */
91 } reg_mask; /* Register mask (all valid bits) */
92 char name[8]; /* Block's longest name is 7 characters long
93 * (name + suffix)
94 */
95 } ecore_blocks_parity_data[] = {
96 /* bit 19 masked */
97 /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
98 /* bit 5,18,20-31 */
99 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
100 /* bit 5 */
101 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
102 /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
103 /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
104
105 /* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
106 * want to handle "system kill" flow at the moment.
107 */
108 BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,
109 0x7ffffff),
110 BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
111 0xffffffff),
112 BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),
113 BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),
114 BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),
115 BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff, 0xffffffff),
116 BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xff, 0xffff),
117 BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),
118 BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
119 BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
120 BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),
121 BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),
122 BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),
123 {GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
124 GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
125 {0xf, 0xf, 0xf, 0xf}, "UPB"},
126 {GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
127 GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
128 {0xf, 0xf, 0xf, 0xf}, "XPB"},
129 BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),
130 BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),
131 BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),
132 BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),
133 BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),
134 BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),
135 BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff, 0xff),
136 BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),
137 BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),
138 BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
139 BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
140 BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
141 BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
142 BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
143 BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
144 BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
145 BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
146 BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
147 0xffffffff),
148 BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
149 BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
150 0xffffffff),
151 BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
152 BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
153 0xffffffff),
154 BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
155 BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
156 0xffffffff),
157 BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
158 };
159
160
161 /* [28] MCP Latched rom_parity
162 * [29] MCP Latched ump_rx_parity
163 * [30] MCP Latched ump_tx_parity
164 * [31] MCP Latched scpad_parity
165 */
166 #define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \
167 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
168 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
169 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
170
171 #define MISC_AEU_ENABLE_MCP_PRTY_BITS \
172 (MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \
173 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
174
175 /* Below registers control the MCP parity attention output. When
176 * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
177 * enabled, when cleared - disabled.
178 */
179 static const struct {
180 u32 addr;
181 u32 bits;
182 } mcp_attn_ctl_regs[] = {
183 { MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
184 MISC_AEU_ENABLE_MCP_PRTY_BITS },
185 { MISC_REG_AEU_ENABLE4_NIG_0,
186 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
187 { MISC_REG_AEU_ENABLE4_PXP_0,
188 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
189 { MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
190 MISC_AEU_ENABLE_MCP_PRTY_BITS },
191 { MISC_REG_AEU_ENABLE4_NIG_1,
192 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
193 { MISC_REG_AEU_ENABLE4_PXP_1,
194 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }
195 };
196
ecore_set_mcp_parity(struct _lm_device_t * pdev,u8 enable)197 static __inline void ecore_set_mcp_parity(struct _lm_device_t *pdev, u8 enable)
198 {
199 int i;
200 u32 reg_val;
201
202 for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
203 reg_val = REG_RD(pdev, mcp_attn_ctl_regs[i].addr);
204
205 if (enable)
206 reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */
207 else
208 reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */
209
210 REG_WR(pdev, mcp_attn_ctl_regs[i].addr, reg_val);
211 }
212 }
213
ecore_parity_reg_mask(struct _lm_device_t * pdev,int idx)214 static __inline u32 ecore_parity_reg_mask(struct _lm_device_t *pdev, int idx)
215 {
216 if (CHIP_IS_E1(pdev))
217 return ecore_blocks_parity_data[idx].reg_mask.e1;
218 else if (CHIP_IS_E1H(pdev))
219 return ecore_blocks_parity_data[idx].reg_mask.e1h;
220 else if (CHIP_IS_E2(pdev))
221 return ecore_blocks_parity_data[idx].reg_mask.e2;
222 else /* CHIP_IS_E3 */
223 return ecore_blocks_parity_data[idx].reg_mask.e3;
224 }
225
ecore_disable_blocks_parity(struct _lm_device_t * pdev)226 static __inline void ecore_disable_blocks_parity(struct _lm_device_t *pdev)
227 {
228 int i;
229
230 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
231 u32 dis_mask = ecore_parity_reg_mask(pdev, i);
232
233 if (dis_mask) {
234 REG_WR(pdev, ecore_blocks_parity_data[i].mask_addr,
235 dis_mask);
236 DbgMessage(pdev, WARNi, "Setting parity mask "
237 "for %s to\t\t0x%x\n",
238 ecore_blocks_parity_data[i].name, dis_mask);
239 }
240 }
241
242 /* Disable MCP parity attentions */
243 ecore_set_mcp_parity(pdev, FALSE);
244 }
245
246 /**
247 * Clear the parity error status registers.
248 */
ecore_clear_blocks_parity(struct _lm_device_t * pdev)249 static __inline void ecore_clear_blocks_parity(struct _lm_device_t *pdev)
250 {
251 int i;
252 u32 reg_val, mcp_aeu_bits =
253 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
254 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
255 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
256 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
257
258 /* Clear SEM_FAST parities */
259 REG_WR(pdev, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
260 REG_WR(pdev, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
261 REG_WR(pdev, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
262 REG_WR(pdev, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
263
264 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
265 u32 reg_mask = ecore_parity_reg_mask(pdev, i);
266
267 if (reg_mask) {
268 reg_val = REG_RD(pdev, ecore_blocks_parity_data[i].
269 sts_clr_addr);
270 if (reg_val & reg_mask) {
271 DbgMessage(pdev, WARNi,
272 "Parity errors in %s: 0x%x\n",
273 ecore_blocks_parity_data[i].name,
274 reg_val & reg_mask);
275 }
276 }
277 }
278
279 /* Check if there were parity attentions in MCP */
280 reg_val = REG_RD(pdev, MISC_REG_AEU_AFTER_INVERT_4_MCP);
281 if (reg_val & mcp_aeu_bits) {
282 DbgMessage(pdev, WARNi, "Parity error in MCP: 0x%x\n",
283 reg_val & mcp_aeu_bits);
284 }
285
286 /* Clear parity attentions in MCP:
287 * [7] clears Latched rom_parity
288 * [8] clears Latched ump_rx_parity
289 * [9] clears Latched ump_tx_parity
290 * [10] clears Latched scpad_parity (both ports)
291 */
292 REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
293 }
294
ecore_enable_blocks_parity(struct _lm_device_t * pdev)295 static __inline void ecore_enable_blocks_parity(struct _lm_device_t *pdev)
296 {
297 int i;
298
299 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
300 u32 reg_mask = ecore_parity_reg_mask(pdev, i);
301
302 if (reg_mask)
303 REG_WR(pdev, ecore_blocks_parity_data[i].mask_addr,
304 ecore_blocks_parity_data[i].en_mask & reg_mask);
305 }
306
307 /* Enable MCP parity attentions */
308 ecore_set_mcp_parity(pdev, TRUE);
309 }
310
311
312 #endif /* ECORE_INIT_H */
313
314