1 /*
2 * SPDX-License-Identifier: GPL-2.0
3 *
4 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
5 *
6 * Authors:
7 * Md Sadre Alam <quic_mdalam@quicinc.com>
8 * Sricharan R <quic_srichara@quicinc.com>
9 * Varadarajan Narayanan <quic_varada@quicinc.com>
10 */
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dma/qcom_adm.h>
17 #include <linux/dma/qcom_bam_dma.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <linux/mtd/nand-qpic-common.h>
23 #include <linux/mtd/spinand.h>
24 #include <linux/bitfield.h>
25
26 #define NAND_FLASH_SPI_CFG 0xc0
27 #define NAND_NUM_ADDR_CYCLES 0xc4
28 #define NAND_BUSY_CHECK_WAIT_CNT 0xc8
29 #define NAND_FLASH_FEATURES 0xf64
30
31 /* QSPI NAND config reg bits */
32 #define LOAD_CLK_CNTR_INIT_EN BIT(28)
33 #define CLK_CNTR_INIT_VAL_VEC 0x924
34 #define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16)
35 #define FEA_STATUS_DEV_ADDR 0xc0
36 #define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8)
37 #define SPI_CFG BIT(0)
38 #define SPI_NUM_ADDR 0xDA4DB
39 #define SPI_WAIT_CNT 0x10
40 #define QPIC_QSPI_NUM_CS 1
41 #define SPI_TRANSFER_MODE_x1 BIT(29)
42 #define SPI_TRANSFER_MODE_x4 (3 << 29)
43 #define SPI_WP BIT(28)
44 #define SPI_HOLD BIT(27)
45 #define QPIC_SET_FEATURE BIT(31)
46
47 #define SPINAND_RESET 0xff
48 #define SPINAND_READID 0x9f
49 #define SPINAND_GET_FEATURE 0x0f
50 #define SPINAND_SET_FEATURE 0x1f
51 #define SPINAND_READ 0x13
52 #define SPINAND_ERASE 0xd8
53 #define SPINAND_WRITE_EN 0x06
54 #define SPINAND_PROGRAM_EXECUTE 0x10
55 #define SPINAND_PROGRAM_LOAD 0x84
56
57 #define ACC_FEATURE 0xe
58 #define BAD_BLOCK_MARKER_SIZE 0x2
59 #define OOB_BUF_SIZE 128
60 #define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng)
61
62 struct qpic_snand_op {
63 u32 cmd_reg;
64 u32 addr1_reg;
65 u32 addr2_reg;
66 };
67
68 struct snandc_read_status {
69 __le32 snandc_flash;
70 __le32 snandc_buffer;
71 __le32 snandc_erased_cw;
72 };
73
74 /*
75 * ECC state struct
76 * @corrected: ECC corrected
77 * @bitflips: Max bit flip
78 * @failed: ECC failed
79 */
80 struct qcom_ecc_stats {
81 u32 corrected;
82 u32 bitflips;
83 u32 failed;
84 };
85
86 struct qpic_ecc {
87 struct device *dev;
88 int ecc_bytes_hw;
89 int spare_bytes;
90 int bbm_size;
91 int ecc_mode;
92 int bytes;
93 int steps;
94 int step_size;
95 int strength;
96 int cw_size;
97 int cw_data;
98 u32 cfg0;
99 u32 cfg1;
100 u32 cfg0_raw;
101 u32 cfg1_raw;
102 u32 ecc_buf_cfg;
103 u32 ecc_bch_cfg;
104 u32 clrflashstatus;
105 u32 clrreadstatus;
106 bool bch_enabled;
107 };
108
109 struct qpic_spi_nand {
110 struct qcom_nand_controller *snandc;
111 struct spi_controller *ctlr;
112 struct mtd_info *mtd;
113 struct clk *iomacro_clk;
114 struct qpic_ecc *ecc;
115 struct qcom_ecc_stats ecc_stats;
116 struct nand_ecc_engine ecc_eng;
117 u8 *data_buf;
118 u8 *oob_buf;
119 __le32 addr1;
120 __le32 addr2;
121 __le32 cmd;
122 u32 num_cw;
123 bool oob_rw;
124 bool page_rw;
125 bool raw_rw;
126 };
127
qcom_spi_set_read_loc_first(struct qcom_nand_controller * snandc,int reg,int cw_offset,int read_size,int is_last_read_loc)128 static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc,
129 int reg, int cw_offset, int read_size,
130 int is_last_read_loc)
131 {
132 __le32 locreg_val;
133 u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
134 FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
135 FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
136
137 locreg_val = cpu_to_le32(val);
138
139 if (reg == NAND_READ_LOCATION_0)
140 snandc->regs->read_location0 = locreg_val;
141 else if (reg == NAND_READ_LOCATION_1)
142 snandc->regs->read_location1 = locreg_val;
143 else if (reg == NAND_READ_LOCATION_2)
144 snandc->regs->read_location2 = locreg_val;
145 else if (reg == NAND_READ_LOCATION_3)
146 snandc->regs->read_location3 = locreg_val;
147 }
148
qcom_spi_set_read_loc_last(struct qcom_nand_controller * snandc,int reg,int cw_offset,int read_size,int is_last_read_loc)149 static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc,
150 int reg, int cw_offset, int read_size,
151 int is_last_read_loc)
152 {
153 __le32 locreg_val;
154 u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
155 FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
156 FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
157
158 locreg_val = cpu_to_le32(val);
159
160 if (reg == NAND_READ_LOCATION_LAST_CW_0)
161 snandc->regs->read_location_last0 = locreg_val;
162 else if (reg == NAND_READ_LOCATION_LAST_CW_1)
163 snandc->regs->read_location_last1 = locreg_val;
164 else if (reg == NAND_READ_LOCATION_LAST_CW_2)
165 snandc->regs->read_location_last2 = locreg_val;
166 else if (reg == NAND_READ_LOCATION_LAST_CW_3)
167 snandc->regs->read_location_last3 = locreg_val;
168 }
169
nand_to_qcom_snand(struct nand_device * nand)170 static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand)
171 {
172 struct nand_ecc_engine *eng = nand->ecc.engine;
173 struct qpic_spi_nand *qspi = ecceng_to_qspi(eng);
174
175 return qspi->snandc;
176 }
177
qcom_spi_init(struct qcom_nand_controller * snandc)178 static int qcom_spi_init(struct qcom_nand_controller *snandc)
179 {
180 u32 snand_cfg_val = 0x0;
181 int ret;
182
183 snand_cfg_val = FIELD_PREP(CLK_CNTR_INIT_VAL_VEC_MASK, CLK_CNTR_INIT_VAL_VEC) |
184 FIELD_PREP(LOAD_CLK_CNTR_INIT_EN, 0) |
185 FIELD_PREP(FEA_STATUS_DEV_ADDR_MASK, FEA_STATUS_DEV_ADDR) |
186 FIELD_PREP(SPI_CFG, 0);
187
188 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
189 snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR);
190 snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT);
191
192 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
193
194 snand_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN;
195 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
196
197 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
198
199 qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0);
200 qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1,
201 NAND_BAM_NEXT_SGL);
202
203 ret = qcom_submit_descs(snandc);
204 if (ret) {
205 dev_err(snandc->dev, "failure in submitting spi init descriptor\n");
206 return ret;
207 }
208
209 return ret;
210 }
211
qcom_spi_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)212 static int qcom_spi_ooblayout_ecc(struct mtd_info *mtd, int section,
213 struct mtd_oob_region *oobregion)
214 {
215 struct nand_device *nand = mtd_to_nanddev(mtd);
216 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
217 struct qpic_ecc *qecc = snandc->qspi->ecc;
218
219 if (section > 1)
220 return -ERANGE;
221
222 oobregion->length = qecc->ecc_bytes_hw + qecc->spare_bytes;
223 oobregion->offset = mtd->oobsize - oobregion->length;
224
225 return 0;
226 }
227
qcom_spi_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)228 static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section,
229 struct mtd_oob_region *oobregion)
230 {
231 struct nand_device *nand = mtd_to_nanddev(mtd);
232 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
233 struct qpic_ecc *qecc = snandc->qspi->ecc;
234
235 if (section)
236 return -ERANGE;
237
238 oobregion->length = qecc->steps * 4;
239 oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size;
240
241 return 0;
242 }
243
244 static const struct mtd_ooblayout_ops qcom_spi_ooblayout = {
245 .ecc = qcom_spi_ooblayout_ecc,
246 .free = qcom_spi_ooblayout_free,
247 };
248
qcom_spi_ecc_init_ctx_pipelined(struct nand_device * nand)249 static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand)
250 {
251 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
252 struct nand_ecc_props *reqs = &nand->ecc.requirements;
253 struct nand_ecc_props *user = &nand->ecc.user_conf;
254 struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
255 struct mtd_info *mtd = nanddev_to_mtd(nand);
256 int cwperpage, bad_block_byte, ret;
257 struct qpic_ecc *ecc_cfg;
258
259 cwperpage = mtd->writesize / NANDC_STEP_SIZE;
260 snandc->qspi->num_cw = cwperpage;
261
262 ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
263 if (!ecc_cfg)
264 return -ENOMEM;
265
266 if (user->step_size && user->strength) {
267 ecc_cfg->step_size = user->step_size;
268 ecc_cfg->strength = user->strength;
269 } else if (reqs->step_size && reqs->strength) {
270 ecc_cfg->step_size = reqs->step_size;
271 ecc_cfg->strength = reqs->strength;
272 } else {
273 /* use defaults */
274 ecc_cfg->step_size = NANDC_STEP_SIZE;
275 ecc_cfg->strength = 4;
276 }
277
278 if (ecc_cfg->step_size != NANDC_STEP_SIZE) {
279 dev_err(snandc->dev,
280 "only %u bytes ECC step size is supported\n",
281 NANDC_STEP_SIZE);
282 ret = -EOPNOTSUPP;
283 goto err_free_ecc_cfg;
284 }
285
286 if (ecc_cfg->strength != 4) {
287 dev_err(snandc->dev,
288 "only 4 bits ECC strength is supported\n");
289 ret = -EOPNOTSUPP;
290 goto err_free_ecc_cfg;
291 }
292
293 snandc->qspi->oob_buf = kmalloc(mtd->writesize + mtd->oobsize,
294 GFP_KERNEL);
295 if (!snandc->qspi->oob_buf) {
296 ret = -ENOMEM;
297 goto err_free_ecc_cfg;
298 }
299
300 memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize);
301
302 nand->ecc.ctx.priv = ecc_cfg;
303 snandc->qspi->mtd = mtd;
304
305 ecc_cfg->ecc_bytes_hw = 7;
306 ecc_cfg->spare_bytes = 4;
307 ecc_cfg->bbm_size = 1;
308 ecc_cfg->bch_enabled = true;
309 ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
310
311 ecc_cfg->steps = 4;
312 ecc_cfg->cw_data = 516;
313 ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes;
314 bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1;
315
316 mtd_set_ooblayout(mtd, &qcom_spi_ooblayout);
317
318 ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
319 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) |
320 FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) |
321 FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
322 FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) |
323 FIELD_PREP(STATUS_BFR_READ, 0) |
324 FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) |
325 FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes);
326
327 ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
328 FIELD_PREP(CS_ACTIVE_BSY, 0) |
329 FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) |
330 FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) |
331 FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
332 FIELD_PREP(WIDE_FLASH, 0) |
333 FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled);
334
335 ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
336 FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
337 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) |
338 FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
339
340 ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
341 FIELD_PREP(CS_ACTIVE_BSY, 0) |
342 FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
343 FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
344 FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
345 FIELD_PREP(WIDE_FLASH, 0) |
346 FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
347
348 ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) |
349 FIELD_PREP(ECC_SW_RESET, 0) |
350 FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
351 FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
352 FIELD_PREP(ECC_MODE_MASK, 0) |
353 FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
354
355 ecc_cfg->ecc_buf_cfg = FIELD_PREP(NUM_STEPS_MASK, 0x203);
356 ecc_cfg->clrflashstatus = FS_READY_BSY_N;
357 ecc_cfg->clrreadstatus = 0xc0;
358
359 conf->step_size = ecc_cfg->step_size;
360 conf->strength = ecc_cfg->strength;
361
362 snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET);
363 snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET);
364
365 dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n",
366 ecc_cfg->strength, ecc_cfg->step_size);
367
368 return 0;
369
370 err_free_ecc_cfg:
371 kfree(ecc_cfg);
372 return ret;
373 }
374
qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device * nand)375 static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand)
376 {
377 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
378
379 kfree(ecc_cfg);
380 }
381
qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device * nand,struct nand_page_io_req * req)382 static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand,
383 struct nand_page_io_req *req)
384 {
385 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
386 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
387
388 snandc->qspi->ecc = ecc_cfg;
389 snandc->qspi->raw_rw = false;
390 snandc->qspi->oob_rw = false;
391 snandc->qspi->page_rw = false;
392
393 if (req->datalen)
394 snandc->qspi->page_rw = true;
395
396 if (req->ooblen)
397 snandc->qspi->oob_rw = true;
398
399 if (req->mode == MTD_OPS_RAW)
400 snandc->qspi->raw_rw = true;
401
402 return 0;
403 }
404
qcom_spi_ecc_finish_io_req_pipelined(struct nand_device * nand,struct nand_page_io_req * req)405 static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand,
406 struct nand_page_io_req *req)
407 {
408 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
409 struct mtd_info *mtd = nanddev_to_mtd(nand);
410
411 if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ)
412 return 0;
413
414 if (snandc->qspi->ecc_stats.failed)
415 mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed;
416 else
417 mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected;
418
419 if (snandc->qspi->ecc_stats.failed)
420 return -EBADMSG;
421 else
422 return snandc->qspi->ecc_stats.bitflips;
423 }
424
425 static struct nand_ecc_engine_ops qcom_spi_ecc_engine_ops_pipelined = {
426 .init_ctx = qcom_spi_ecc_init_ctx_pipelined,
427 .cleanup_ctx = qcom_spi_ecc_cleanup_ctx_pipelined,
428 .prepare_io_req = qcom_spi_ecc_prepare_io_req_pipelined,
429 .finish_io_req = qcom_spi_ecc_finish_io_req_pipelined,
430 };
431
432 /* helper to configure location register values */
qcom_spi_set_read_loc(struct qcom_nand_controller * snandc,int cw,int reg,int cw_offset,int read_size,int is_last_read_loc)433 static void qcom_spi_set_read_loc(struct qcom_nand_controller *snandc, int cw, int reg,
434 int cw_offset, int read_size, int is_last_read_loc)
435 {
436 int reg_base = NAND_READ_LOCATION_0;
437 int num_cw = snandc->qspi->num_cw;
438
439 if (cw == (num_cw - 1))
440 reg_base = NAND_READ_LOCATION_LAST_CW_0;
441
442 reg_base += reg * 4;
443
444 if (cw == (num_cw - 1))
445 return qcom_spi_set_read_loc_last(snandc, reg_base, cw_offset,
446 read_size, is_last_read_loc);
447 else
448 return qcom_spi_set_read_loc_first(snandc, reg_base, cw_offset,
449 read_size, is_last_read_loc);
450 }
451
452 static void
qcom_spi_config_cw_read(struct qcom_nand_controller * snandc,bool use_ecc,int cw)453 qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int cw)
454 {
455 __le32 *reg = &snandc->regs->read_location0;
456 int num_cw = snandc->qspi->num_cw;
457
458 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL);
459 if (cw == (num_cw - 1)) {
460 reg = &snandc->regs->read_location_last0;
461 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4,
462 NAND_BAM_NEXT_SGL);
463 }
464
465 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
466 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
467
468 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
469 qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
470 NAND_BAM_NEXT_SGL);
471 }
472
qcom_spi_block_erase(struct qcom_nand_controller * snandc)473 static int qcom_spi_block_erase(struct qcom_nand_controller *snandc)
474 {
475 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
476 int ret;
477
478 snandc->buf_count = 0;
479 snandc->buf_start = 0;
480 qcom_clear_read_regs(snandc);
481 qcom_clear_bam_transaction(snandc);
482
483 snandc->regs->cmd = snandc->qspi->cmd;
484 snandc->regs->addr0 = snandc->qspi->addr1;
485 snandc->regs->addr1 = snandc->qspi->addr2;
486 snandc->regs->cfg0 = cpu_to_le32((ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
487 FIELD_PREP(CW_PER_PAGE_MASK, 0));
488 snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw);
489 snandc->regs->exec = cpu_to_le32(1);
490
491 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
492 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
493 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
494
495 ret = qcom_submit_descs(snandc);
496 if (ret) {
497 dev_err(snandc->dev, "failure to erase block\n");
498 return ret;
499 }
500
501 return 0;
502 }
503
qcom_spi_config_single_cw_page_read(struct qcom_nand_controller * snandc,bool use_ecc,int cw)504 static void qcom_spi_config_single_cw_page_read(struct qcom_nand_controller *snandc,
505 bool use_ecc, int cw)
506 {
507 __le32 *reg = &snandc->regs->read_location0;
508 int num_cw = snandc->qspi->num_cw;
509
510 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
511 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
512 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
513 NAND_ERASED_CW_DETECT_CFG, 1, 0);
514 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
515 NAND_ERASED_CW_DETECT_CFG, 1,
516 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
517
518 if (cw == (num_cw - 1)) {
519 reg = &snandc->regs->read_location_last0;
520 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, NAND_BAM_NEXT_SGL);
521 }
522 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
523 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
524
525 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 0);
526 }
527
qcom_spi_check_raw_flash_errors(struct qcom_nand_controller * snandc,int cw_cnt)528 static int qcom_spi_check_raw_flash_errors(struct qcom_nand_controller *snandc, int cw_cnt)
529 {
530 int i;
531
532 qcom_nandc_dev_to_mem(snandc, true);
533
534 for (i = 0; i < cw_cnt; i++) {
535 u32 flash = le32_to_cpu(snandc->reg_read_buf[i]);
536
537 if (flash & (FS_OP_ERR | FS_MPU_ERR))
538 return -EIO;
539 }
540
541 return 0;
542 }
543
qcom_spi_read_last_cw(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)544 static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc,
545 const struct spi_mem_op *op)
546 {
547 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
548 struct mtd_info *mtd = snandc->qspi->mtd;
549 int size, ret = 0;
550 int col, bbpos;
551 u32 cfg0, cfg1, ecc_bch_cfg;
552 u32 num_cw = snandc->qspi->num_cw;
553
554 qcom_clear_bam_transaction(snandc);
555 qcom_clear_read_regs(snandc);
556
557 size = ecc_cfg->cw_size;
558 col = ecc_cfg->cw_size * (num_cw - 1);
559
560 memset(snandc->data_buffer, 0xff, size);
561 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
562 snandc->regs->addr1 = snandc->qspi->addr2;
563
564 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
565 FIELD_PREP(CW_PER_PAGE_MASK, 0);
566 cfg1 = ecc_cfg->cfg1_raw;
567 ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
568
569 snandc->regs->cmd = snandc->qspi->cmd;
570 snandc->regs->cfg0 = cpu_to_le32(cfg0);
571 snandc->regs->cfg1 = cpu_to_le32(cfg1);
572 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
573 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
574 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
575 snandc->regs->exec = cpu_to_le32(1);
576
577 qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1);
578
579 qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1);
580
581 qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0);
582
583 ret = qcom_submit_descs(snandc);
584 if (ret) {
585 dev_err(snandc->dev, "failed to read last cw\n");
586 return ret;
587 }
588
589 ret = qcom_spi_check_raw_flash_errors(snandc, 1);
590 if (ret)
591 return ret;
592
593 bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
594
595 if (snandc->data_buffer[bbpos] == 0xff)
596 snandc->data_buffer[bbpos + 1] = 0xff;
597 if (snandc->data_buffer[bbpos] != 0xff)
598 snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos];
599
600 memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes);
601
602 return ret;
603 }
604
qcom_spi_check_error(struct qcom_nand_controller * snandc)605 static int qcom_spi_check_error(struct qcom_nand_controller *snandc)
606 {
607 struct snandc_read_status *buf;
608 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
609 int i, num_cw = snandc->qspi->num_cw;
610 bool flash_op_err = false, erased;
611 unsigned int max_bitflips = 0;
612 unsigned int uncorrectable_cws = 0;
613
614 snandc->qspi->ecc_stats.failed = 0;
615 snandc->qspi->ecc_stats.corrected = 0;
616
617 qcom_nandc_dev_to_mem(snandc, true);
618 buf = (struct snandc_read_status *)snandc->reg_read_buf;
619
620 for (i = 0; i < num_cw; i++, buf++) {
621 u32 flash, buffer, erased_cw;
622
623 flash = le32_to_cpu(buf->snandc_flash);
624 buffer = le32_to_cpu(buf->snandc_buffer);
625 erased_cw = le32_to_cpu(buf->snandc_erased_cw);
626
627 if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) {
628 if (ecc_cfg->bch_enabled)
629 erased = (erased_cw & ERASED_CW) == ERASED_CW;
630 else
631 erased = false;
632
633 if (!erased)
634 uncorrectable_cws |= BIT(i);
635
636 } else if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
637 flash_op_err = true;
638 } else {
639 unsigned int stat;
640
641 stat = buffer & BS_CORRECTABLE_ERR_MSK;
642
643 /*
644 * The exact number of the corrected bits is
645 * unknown because the hardware only reports the
646 * number of the corrected bytes.
647 *
648 * Since we have no better solution at the moment,
649 * report that value as the number of bit errors
650 * despite that it is inaccurate in most cases.
651 */
652 if (stat && stat != ecc_cfg->strength)
653 dev_warn_once(snandc->dev,
654 "Warning: due to hw limitation, the reported number of the corrected bits may be inaccurate\n");
655
656 snandc->qspi->ecc_stats.corrected += stat;
657 max_bitflips = max(max_bitflips, stat);
658 }
659 }
660
661 if (flash_op_err)
662 return -EIO;
663
664 if (!uncorrectable_cws)
665 snandc->qspi->ecc_stats.bitflips = max_bitflips;
666 else
667 snandc->qspi->ecc_stats.failed++;
668
669 return 0;
670 }
671
qcom_spi_read_cw_raw(struct qcom_nand_controller * snandc,u8 * data_buf,u8 * oob_buf,int cw)672 static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *data_buf,
673 u8 *oob_buf, int cw)
674 {
675 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
676 struct mtd_info *mtd = snandc->qspi->mtd;
677 int data_size1, data_size2, oob_size1, oob_size2;
678 int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
679 int raw_cw = cw;
680 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
681 int col;
682
683 snandc->buf_count = 0;
684 snandc->buf_start = 0;
685 qcom_clear_read_regs(snandc);
686 qcom_clear_bam_transaction(snandc);
687 raw_cw = num_cw - 1;
688
689 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
690 FIELD_PREP(CW_PER_PAGE_MASK, 0);
691 cfg1 = ecc_cfg->cfg1_raw;
692 ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
693
694 col = ecc_cfg->cw_size * cw;
695
696 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
697 snandc->regs->addr1 = snandc->qspi->addr2;
698 snandc->regs->cmd = snandc->qspi->cmd;
699 snandc->regs->cfg0 = cpu_to_le32(cfg0);
700 snandc->regs->cfg1 = cpu_to_le32(cfg1);
701 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
702 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
703 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
704 snandc->regs->exec = cpu_to_le32(1);
705
706 qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1);
707
708 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
709 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
710 qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0);
711
712 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
713 NAND_ERASED_CW_DETECT_CFG, 1, 0);
714 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
715 NAND_ERASED_CW_DETECT_CFG, 1,
716 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
717
718 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
719 oob_size1 = ecc_cfg->bbm_size;
720
721 if (cw == (num_cw - 1)) {
722 data_size2 = NANDC_STEP_SIZE - data_size1 -
723 ((num_cw - 1) * 4);
724 oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw +
725 ecc_cfg->spare_bytes;
726 } else {
727 data_size2 = ecc_cfg->cw_data - data_size1;
728 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
729 }
730
731 qcom_spi_set_read_loc(snandc, cw, 0, read_loc, data_size1, 0);
732 read_loc += data_size1;
733
734 qcom_spi_set_read_loc(snandc, cw, 1, read_loc, oob_size1, 0);
735 read_loc += oob_size1;
736
737 qcom_spi_set_read_loc(snandc, cw, 2, read_loc, data_size2, 0);
738 read_loc += data_size2;
739
740 qcom_spi_set_read_loc(snandc, cw, 3, read_loc, oob_size2, 1);
741
742 qcom_spi_config_cw_read(snandc, false, raw_cw);
743
744 qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0);
745 reg_off += data_size1;
746
747 qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0);
748 reg_off += oob_size1;
749
750 qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0);
751 reg_off += data_size2;
752
753 qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
754
755 ret = qcom_submit_descs(snandc);
756 if (ret) {
757 dev_err(snandc->dev, "failure to read raw cw %d\n", cw);
758 return ret;
759 }
760
761 return qcom_spi_check_raw_flash_errors(snandc, 1);
762 }
763
qcom_spi_read_page_raw(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)764 static int qcom_spi_read_page_raw(struct qcom_nand_controller *snandc,
765 const struct spi_mem_op *op)
766 {
767 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
768 u8 *data_buf = NULL, *oob_buf = NULL;
769 int ret, cw;
770 u32 num_cw = snandc->qspi->num_cw;
771
772 if (snandc->qspi->page_rw)
773 data_buf = op->data.buf.in;
774
775 oob_buf = snandc->qspi->oob_buf;
776 memset(oob_buf, 0xff, OOB_BUF_SIZE);
777
778 for (cw = 0; cw < num_cw; cw++) {
779 ret = qcom_spi_read_cw_raw(snandc, data_buf, oob_buf, cw);
780 if (ret)
781 return ret;
782
783 if (data_buf)
784 data_buf += ecc_cfg->cw_data;
785 if (oob_buf)
786 oob_buf += ecc_cfg->bytes;
787 }
788
789 return 0;
790 }
791
qcom_spi_read_page_ecc(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)792 static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc,
793 const struct spi_mem_op *op)
794 {
795 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
796 u8 *data_buf = NULL, *oob_buf = NULL;
797 int ret, i;
798 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
799
800 data_buf = op->data.buf.in;
801 oob_buf = snandc->qspi->oob_buf;
802
803 snandc->buf_count = 0;
804 snandc->buf_start = 0;
805 qcom_clear_read_regs(snandc);
806
807 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
808 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
809 cfg1 = ecc_cfg->cfg1;
810 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
811
812 snandc->regs->addr0 = snandc->qspi->addr1;
813 snandc->regs->addr1 = snandc->qspi->addr2;
814 snandc->regs->cmd = snandc->qspi->cmd;
815 snandc->regs->cfg0 = cpu_to_le32(cfg0);
816 snandc->regs->cfg1 = cpu_to_le32(cfg1);
817 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
818 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
819 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
820 snandc->regs->exec = cpu_to_le32(1);
821
822 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
823
824 qcom_clear_bam_transaction(snandc);
825
826 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
827 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
828 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
829 NAND_ERASED_CW_DETECT_CFG, 1, 0);
830 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
831 NAND_ERASED_CW_DETECT_CFG, 1,
832 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
833
834 for (i = 0; i < num_cw; i++) {
835 int data_size, oob_size;
836
837 if (i == (num_cw - 1)) {
838 data_size = 512 - ((num_cw - 1) << 2);
839 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
840 ecc_cfg->spare_bytes;
841 } else {
842 data_size = ecc_cfg->cw_data;
843 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
844 }
845
846 if (data_buf && oob_buf) {
847 qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 0);
848 qcom_spi_set_read_loc(snandc, i, 1, data_size, oob_size, 1);
849 } else if (data_buf) {
850 qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 1);
851 } else {
852 qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
853 }
854
855 qcom_spi_config_cw_read(snandc, true, i);
856
857 if (data_buf)
858 qcom_read_data_dma(snandc, FLASH_BUF_ACC, data_buf,
859 data_size, 0);
860 if (oob_buf) {
861 int j;
862
863 for (j = 0; j < ecc_cfg->bbm_size; j++)
864 *oob_buf++ = 0xff;
865
866 qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
867 oob_buf, oob_size, 0);
868 }
869
870 if (data_buf)
871 data_buf += data_size;
872 if (oob_buf)
873 oob_buf += oob_size;
874 }
875
876 ret = qcom_submit_descs(snandc);
877 if (ret) {
878 dev_err(snandc->dev, "failure to read page\n");
879 return ret;
880 }
881
882 return qcom_spi_check_error(snandc);
883 }
884
qcom_spi_read_page_oob(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)885 static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc,
886 const struct spi_mem_op *op)
887 {
888 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
889 u8 *oob_buf = NULL;
890 int ret, i;
891 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
892
893 oob_buf = op->data.buf.in;
894
895 snandc->buf_count = 0;
896 snandc->buf_start = 0;
897 qcom_clear_read_regs(snandc);
898 qcom_clear_bam_transaction(snandc);
899
900 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
901 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
902 cfg1 = ecc_cfg->cfg1;
903 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
904
905 snandc->regs->addr0 = snandc->qspi->addr1;
906 snandc->regs->addr1 = snandc->qspi->addr2;
907 snandc->regs->cmd = snandc->qspi->cmd;
908 snandc->regs->cfg0 = cpu_to_le32(cfg0);
909 snandc->regs->cfg1 = cpu_to_le32(cfg1);
910 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
911 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
912 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
913 snandc->regs->exec = cpu_to_le32(1);
914
915 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
916
917 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
918 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
919 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
920 NAND_ERASED_CW_DETECT_CFG, 1, 0);
921 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
922 NAND_ERASED_CW_DETECT_CFG, 1,
923 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
924
925 for (i = 0; i < num_cw; i++) {
926 int data_size, oob_size;
927
928 if (i == (num_cw - 1)) {
929 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
930 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
931 ecc_cfg->spare_bytes;
932 } else {
933 data_size = ecc_cfg->cw_data;
934 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
935 }
936
937 qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
938
939 qcom_spi_config_cw_read(snandc, true, i);
940
941 if (oob_buf) {
942 int j;
943
944 for (j = 0; j < ecc_cfg->bbm_size; j++)
945 *oob_buf++ = 0xff;
946
947 qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
948 oob_buf, oob_size, 0);
949 }
950
951 if (oob_buf)
952 oob_buf += oob_size;
953 }
954
955 ret = qcom_submit_descs(snandc);
956 if (ret) {
957 dev_err(snandc->dev, "failure to read oob\n");
958 return ret;
959 }
960
961 return qcom_spi_check_error(snandc);
962 }
963
qcom_spi_read_page(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)964 static int qcom_spi_read_page(struct qcom_nand_controller *snandc,
965 const struct spi_mem_op *op)
966 {
967 if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
968 return qcom_spi_read_page_raw(snandc, op);
969
970 if (snandc->qspi->page_rw)
971 return qcom_spi_read_page_ecc(snandc, op);
972
973 if (snandc->qspi->oob_rw && snandc->qspi->raw_rw)
974 return qcom_spi_read_last_cw(snandc, op);
975
976 if (snandc->qspi->oob_rw)
977 return qcom_spi_read_page_oob(snandc, op);
978
979 return 0;
980 }
981
qcom_spi_config_page_write(struct qcom_nand_controller * snandc)982 static void qcom_spi_config_page_write(struct qcom_nand_controller *snandc)
983 {
984 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
985 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
986 qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG,
987 1, NAND_BAM_NEXT_SGL);
988 }
989
qcom_spi_config_cw_write(struct qcom_nand_controller * snandc)990 static void qcom_spi_config_cw_write(struct qcom_nand_controller *snandc)
991 {
992 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
993 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
994 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
995
996 qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
997 qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1,
998 NAND_BAM_NEXT_SGL);
999 }
1000
qcom_spi_program_raw(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1001 static int qcom_spi_program_raw(struct qcom_nand_controller *snandc,
1002 const struct spi_mem_op *op)
1003 {
1004 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1005 struct mtd_info *mtd = snandc->qspi->mtd;
1006 u8 *data_buf = NULL, *oob_buf = NULL;
1007 int i, ret;
1008 int num_cw = snandc->qspi->num_cw;
1009 u32 cfg0, cfg1, ecc_bch_cfg;
1010
1011 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
1012 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
1013 cfg1 = ecc_cfg->cfg1_raw;
1014 ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
1015
1016 data_buf = snandc->qspi->data_buf;
1017
1018 oob_buf = snandc->qspi->oob_buf;
1019 memset(oob_buf, 0xff, OOB_BUF_SIZE);
1020
1021 snandc->buf_count = 0;
1022 snandc->buf_start = 0;
1023 qcom_clear_read_regs(snandc);
1024 qcom_clear_bam_transaction(snandc);
1025
1026 snandc->regs->addr0 = snandc->qspi->addr1;
1027 snandc->regs->addr1 = snandc->qspi->addr2;
1028 snandc->regs->cmd = snandc->qspi->cmd;
1029 snandc->regs->cfg0 = cpu_to_le32(cfg0);
1030 snandc->regs->cfg1 = cpu_to_le32(cfg1);
1031 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1032 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
1033 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
1034 snandc->regs->exec = cpu_to_le32(1);
1035
1036 qcom_spi_config_page_write(snandc);
1037
1038 for (i = 0; i < num_cw; i++) {
1039 int data_size1, data_size2, oob_size1, oob_size2;
1040 int reg_off = FLASH_BUF_ACC;
1041
1042 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
1043 oob_size1 = ecc_cfg->bbm_size;
1044
1045 if (i == (num_cw - 1)) {
1046 data_size2 = NANDC_STEP_SIZE - data_size1 -
1047 ((num_cw - 1) << 2);
1048 oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1049 ecc_cfg->spare_bytes;
1050 } else {
1051 data_size2 = ecc_cfg->cw_data - data_size1;
1052 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
1053 }
1054
1055 qcom_write_data_dma(snandc, reg_off, data_buf, data_size1,
1056 NAND_BAM_NO_EOT);
1057 reg_off += data_size1;
1058 data_buf += data_size1;
1059
1060 qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1,
1061 NAND_BAM_NO_EOT);
1062 oob_buf += oob_size1;
1063 reg_off += oob_size1;
1064
1065 qcom_write_data_dma(snandc, reg_off, data_buf, data_size2,
1066 NAND_BAM_NO_EOT);
1067 reg_off += data_size2;
1068 data_buf += data_size2;
1069
1070 qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0);
1071 oob_buf += oob_size2;
1072
1073 qcom_spi_config_cw_write(snandc);
1074 }
1075
1076 ret = qcom_submit_descs(snandc);
1077 if (ret) {
1078 dev_err(snandc->dev, "failure to write raw page\n");
1079 return ret;
1080 }
1081
1082 return 0;
1083 }
1084
qcom_spi_program_ecc(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1085 static int qcom_spi_program_ecc(struct qcom_nand_controller *snandc,
1086 const struct spi_mem_op *op)
1087 {
1088 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1089 u8 *data_buf = NULL, *oob_buf = NULL;
1090 int i, ret;
1091 int num_cw = snandc->qspi->num_cw;
1092 u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1093
1094 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
1095 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
1096 cfg1 = ecc_cfg->cfg1;
1097 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1098 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1099
1100 if (snandc->qspi->data_buf)
1101 data_buf = snandc->qspi->data_buf;
1102
1103 oob_buf = snandc->qspi->oob_buf;
1104
1105 snandc->buf_count = 0;
1106 snandc->buf_start = 0;
1107 qcom_clear_read_regs(snandc);
1108 qcom_clear_bam_transaction(snandc);
1109
1110 snandc->regs->addr0 = snandc->qspi->addr1;
1111 snandc->regs->addr1 = snandc->qspi->addr2;
1112 snandc->regs->cmd = snandc->qspi->cmd;
1113 snandc->regs->cfg0 = cpu_to_le32(cfg0);
1114 snandc->regs->cfg1 = cpu_to_le32(cfg1);
1115 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1116 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1117 snandc->regs->exec = cpu_to_le32(1);
1118
1119 qcom_spi_config_page_write(snandc);
1120
1121 for (i = 0; i < num_cw; i++) {
1122 int data_size, oob_size;
1123
1124 if (i == (num_cw - 1)) {
1125 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1126 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1127 ecc_cfg->spare_bytes;
1128 } else {
1129 data_size = ecc_cfg->cw_data;
1130 oob_size = ecc_cfg->bytes;
1131 }
1132
1133 if (data_buf)
1134 qcom_write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size,
1135 i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0);
1136
1137 if (i == (num_cw - 1)) {
1138 if (oob_buf) {
1139 oob_buf += ecc_cfg->bbm_size;
1140 qcom_write_data_dma(snandc, FLASH_BUF_ACC + data_size,
1141 oob_buf, oob_size, 0);
1142 }
1143 }
1144
1145 qcom_spi_config_cw_write(snandc);
1146
1147 if (data_buf)
1148 data_buf += data_size;
1149 if (oob_buf)
1150 oob_buf += oob_size;
1151 }
1152
1153 ret = qcom_submit_descs(snandc);
1154 if (ret) {
1155 dev_err(snandc->dev, "failure to write page\n");
1156 return ret;
1157 }
1158
1159 return 0;
1160 }
1161
qcom_spi_program_oob(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1162 static int qcom_spi_program_oob(struct qcom_nand_controller *snandc,
1163 const struct spi_mem_op *op)
1164 {
1165 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1166 u8 *oob_buf = NULL;
1167 int ret, col, data_size, oob_size;
1168 int num_cw = snandc->qspi->num_cw;
1169 u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1170
1171 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
1172 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
1173 cfg1 = ecc_cfg->cfg1;
1174 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1175 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1176
1177 col = ecc_cfg->cw_size * (num_cw - 1);
1178
1179 oob_buf = snandc->qspi->data_buf;
1180
1181 snandc->buf_count = 0;
1182 snandc->buf_start = 0;
1183 qcom_clear_read_regs(snandc);
1184 qcom_clear_bam_transaction(snandc);
1185 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
1186 snandc->regs->addr1 = snandc->qspi->addr2;
1187 snandc->regs->cmd = snandc->qspi->cmd;
1188 snandc->regs->cfg0 = cpu_to_le32(cfg0);
1189 snandc->regs->cfg1 = cpu_to_le32(cfg1);
1190 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1191 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1192 snandc->regs->exec = cpu_to_le32(1);
1193
1194 /* calculate the data and oob size for the last codeword/step */
1195 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1196 oob_size = snandc->qspi->mtd->oobavail;
1197
1198 memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data);
1199 /* override new oob content to last codeword */
1200 mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size,
1201 oob_buf, 0, snandc->qspi->mtd->oobavail);
1202 qcom_spi_config_page_write(snandc);
1203 qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0);
1204 qcom_spi_config_cw_write(snandc);
1205
1206 ret = qcom_submit_descs(snandc);
1207 if (ret) {
1208 dev_err(snandc->dev, "failure to write oob\n");
1209 return ret;
1210 }
1211
1212 return 0;
1213 }
1214
qcom_spi_program_execute(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1215 static int qcom_spi_program_execute(struct qcom_nand_controller *snandc,
1216 const struct spi_mem_op *op)
1217 {
1218 if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
1219 return qcom_spi_program_raw(snandc, op);
1220
1221 if (snandc->qspi->page_rw)
1222 return qcom_spi_program_ecc(snandc, op);
1223
1224 if (snandc->qspi->oob_rw)
1225 return qcom_spi_program_oob(snandc, op);
1226
1227 return 0;
1228 }
1229
qcom_spi_cmd_mapping(struct qcom_nand_controller * snandc,u32 opcode,u32 * cmd)1230 static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, u32 *cmd)
1231 {
1232 switch (opcode) {
1233 case SPINAND_RESET:
1234 *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
1235 break;
1236 case SPINAND_READID:
1237 *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
1238 break;
1239 case SPINAND_GET_FEATURE:
1240 *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
1241 break;
1242 case SPINAND_SET_FEATURE:
1243 *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
1244 QPIC_SET_FEATURE);
1245 break;
1246 case SPINAND_READ:
1247 if (snandc->qspi->raw_rw) {
1248 *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1249 SPI_WP | SPI_HOLD | OP_PAGE_READ);
1250 } else {
1251 *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1252 SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
1253 }
1254
1255 break;
1256 case SPINAND_ERASE:
1257 *cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
1258 SPI_HOLD | SPI_TRANSFER_MODE_x1;
1259 break;
1260 case SPINAND_WRITE_EN:
1261 *cmd = SPINAND_WRITE_EN;
1262 break;
1263 case SPINAND_PROGRAM_EXECUTE:
1264 *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1265 SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
1266 break;
1267 case SPINAND_PROGRAM_LOAD:
1268 *cmd = SPINAND_PROGRAM_LOAD;
1269 break;
1270 default:
1271 dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
1272 return -EOPNOTSUPP;
1273 }
1274
1275 return 0;
1276 }
1277
qcom_spi_write_page(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1278 static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
1279 const struct spi_mem_op *op)
1280 {
1281 int ret;
1282 u32 cmd;
1283
1284 ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
1285 if (ret < 0)
1286 return ret;
1287
1288 if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
1289 snandc->qspi->data_buf = (u8 *)op->data.buf.out;
1290
1291 return 0;
1292 }
1293
qcom_spi_send_cmdaddr(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1294 static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
1295 const struct spi_mem_op *op)
1296 {
1297 struct qpic_snand_op s_op = {};
1298 u32 cmd;
1299 int ret, opcode;
1300
1301 ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
1302 if (ret < 0)
1303 return ret;
1304
1305 s_op.cmd_reg = cmd;
1306 s_op.addr1_reg = op->addr.val;
1307 s_op.addr2_reg = 0;
1308
1309 opcode = op->cmd.opcode;
1310
1311 switch (opcode) {
1312 case SPINAND_WRITE_EN:
1313 return 0;
1314 case SPINAND_PROGRAM_EXECUTE:
1315 s_op.addr1_reg = op->addr.val << 16;
1316 s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1317 snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1318 snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1319 snandc->qspi->cmd = cpu_to_le32(cmd);
1320 return qcom_spi_program_execute(snandc, op);
1321 case SPINAND_READ:
1322 s_op.addr1_reg = (op->addr.val << 16);
1323 s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1324 snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1325 snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1326 snandc->qspi->cmd = cpu_to_le32(cmd);
1327 return 0;
1328 case SPINAND_ERASE:
1329 s_op.addr2_reg = (op->addr.val >> 16) & 0xffff;
1330 s_op.addr1_reg = op->addr.val;
1331 snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg << 16);
1332 snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1333 snandc->qspi->cmd = cpu_to_le32(cmd);
1334 return qcom_spi_block_erase(snandc);
1335 default:
1336 break;
1337 }
1338
1339 snandc->buf_count = 0;
1340 snandc->buf_start = 0;
1341 qcom_clear_read_regs(snandc);
1342 qcom_clear_bam_transaction(snandc);
1343
1344 snandc->regs->cmd = cpu_to_le32(s_op.cmd_reg);
1345 snandc->regs->exec = cpu_to_le32(1);
1346 snandc->regs->addr0 = cpu_to_le32(s_op.addr1_reg);
1347 snandc->regs->addr1 = cpu_to_le32(s_op.addr2_reg);
1348
1349 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
1350 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1351
1352 ret = qcom_submit_descs(snandc);
1353 if (ret)
1354 dev_err(snandc->dev, "failure in submitting cmd descriptor\n");
1355
1356 return ret;
1357 }
1358
qcom_spi_io_op(struct qcom_nand_controller * snandc,const struct spi_mem_op * op)1359 static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_mem_op *op)
1360 {
1361 int ret, val, opcode;
1362 bool copy = false, copy_ftr = false;
1363
1364 ret = qcom_spi_send_cmdaddr(snandc, op);
1365 if (ret)
1366 return ret;
1367
1368 snandc->buf_count = 0;
1369 snandc->buf_start = 0;
1370 qcom_clear_read_regs(snandc);
1371 qcom_clear_bam_transaction(snandc);
1372 opcode = op->cmd.opcode;
1373
1374 switch (opcode) {
1375 case SPINAND_READID:
1376 snandc->buf_count = 4;
1377 qcom_read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1378 copy = true;
1379 break;
1380 case SPINAND_GET_FEATURE:
1381 snandc->buf_count = 4;
1382 qcom_read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1383 copy_ftr = true;
1384 break;
1385 case SPINAND_SET_FEATURE:
1386 snandc->regs->flash_feature = cpu_to_le32(*(u32 *)op->data.buf.out);
1387 qcom_write_reg_dma(snandc, &snandc->regs->flash_feature,
1388 NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1389 break;
1390 case SPINAND_PROGRAM_EXECUTE:
1391 case SPINAND_WRITE_EN:
1392 case SPINAND_RESET:
1393 case SPINAND_ERASE:
1394 case SPINAND_READ:
1395 return 0;
1396 default:
1397 return -EOPNOTSUPP;
1398 }
1399
1400 ret = qcom_submit_descs(snandc);
1401 if (ret) {
1402 dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode);
1403 return ret;
1404 }
1405
1406 if (copy) {
1407 qcom_nandc_dev_to_mem(snandc, true);
1408 memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
1409 }
1410
1411 if (copy_ftr) {
1412 qcom_nandc_dev_to_mem(snandc, true);
1413 val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf);
1414 val >>= 8;
1415 memcpy(op->data.buf.in, &val, snandc->buf_count);
1416 }
1417
1418 return 0;
1419 }
1420
qcom_spi_is_page_op(const struct spi_mem_op * op)1421 static bool qcom_spi_is_page_op(const struct spi_mem_op *op)
1422 {
1423 if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4)
1424 return false;
1425
1426 if (op->data.dir == SPI_MEM_DATA_IN) {
1427 if (op->addr.buswidth == 4 && op->data.buswidth == 4)
1428 return true;
1429
1430 if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1431 return true;
1432
1433 } else if (op->data.dir == SPI_MEM_DATA_OUT) {
1434 if (op->data.buswidth == 4)
1435 return true;
1436 if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1437 return true;
1438 }
1439
1440 return false;
1441 }
1442
qcom_spi_supports_op(struct spi_mem * mem,const struct spi_mem_op * op)1443 static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
1444 {
1445 if (!spi_mem_default_supports_op(mem, op))
1446 return false;
1447
1448 if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
1449 return false;
1450
1451 if (qcom_spi_is_page_op(op))
1452 return true;
1453
1454 return ((!op->addr.nbytes || op->addr.buswidth == 1) &&
1455 (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
1456 (!op->data.nbytes || op->data.buswidth == 1));
1457 }
1458
qcom_spi_exec_op(struct spi_mem * mem,const struct spi_mem_op * op)1459 static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
1460 {
1461 struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller);
1462
1463 dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
1464 op->addr.val, op->addr.buswidth, op->addr.nbytes,
1465 op->data.buswidth, op->data.nbytes);
1466
1467 if (qcom_spi_is_page_op(op)) {
1468 if (op->data.dir == SPI_MEM_DATA_IN)
1469 return qcom_spi_read_page(snandc, op);
1470 if (op->data.dir == SPI_MEM_DATA_OUT)
1471 return qcom_spi_write_page(snandc, op);
1472 } else {
1473 return qcom_spi_io_op(snandc, op);
1474 }
1475
1476 return 0;
1477 }
1478
1479 static const struct spi_controller_mem_ops qcom_spi_mem_ops = {
1480 .supports_op = qcom_spi_supports_op,
1481 .exec_op = qcom_spi_exec_op,
1482 };
1483
1484 static const struct spi_controller_mem_caps qcom_spi_mem_caps = {
1485 .ecc = true,
1486 };
1487
qcom_spi_probe(struct platform_device * pdev)1488 static int qcom_spi_probe(struct platform_device *pdev)
1489 {
1490 struct device *dev = &pdev->dev;
1491 struct spi_controller *ctlr;
1492 struct qcom_nand_controller *snandc;
1493 struct qpic_spi_nand *qspi;
1494 struct qpic_ecc *ecc;
1495 struct resource *res;
1496 const void *dev_data;
1497 int ret;
1498
1499 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
1500 if (!ecc)
1501 return -ENOMEM;
1502
1503 qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
1504 if (!qspi)
1505 return -ENOMEM;
1506
1507 ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false);
1508 if (!ctlr)
1509 return -ENOMEM;
1510
1511 platform_set_drvdata(pdev, ctlr);
1512
1513 snandc = spi_controller_get_devdata(ctlr);
1514 qspi->snandc = snandc;
1515
1516 snandc->dev = dev;
1517 snandc->qspi = qspi;
1518 snandc->qspi->ctlr = ctlr;
1519 snandc->qspi->ecc = ecc;
1520
1521 dev_data = of_device_get_match_data(dev);
1522 if (!dev_data) {
1523 dev_err(&pdev->dev, "failed to get device data\n");
1524 return -ENODEV;
1525 }
1526
1527 snandc->props = dev_data;
1528 snandc->dev = &pdev->dev;
1529
1530 snandc->core_clk = devm_clk_get(dev, "core");
1531 if (IS_ERR(snandc->core_clk))
1532 return PTR_ERR(snandc->core_clk);
1533
1534 snandc->aon_clk = devm_clk_get(dev, "aon");
1535 if (IS_ERR(snandc->aon_clk))
1536 return PTR_ERR(snandc->aon_clk);
1537
1538 snandc->qspi->iomacro_clk = devm_clk_get(dev, "iom");
1539 if (IS_ERR(snandc->qspi->iomacro_clk))
1540 return PTR_ERR(snandc->qspi->iomacro_clk);
1541
1542 snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1543 if (IS_ERR(snandc->base))
1544 return PTR_ERR(snandc->base);
1545
1546 snandc->base_phys = res->start;
1547 snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res),
1548 DMA_BIDIRECTIONAL, 0);
1549 if (dma_mapping_error(dev, snandc->base_dma))
1550 return -ENXIO;
1551
1552 ret = clk_prepare_enable(snandc->core_clk);
1553 if (ret)
1554 goto err_dis_core_clk;
1555
1556 ret = clk_prepare_enable(snandc->aon_clk);
1557 if (ret)
1558 goto err_dis_aon_clk;
1559
1560 ret = clk_prepare_enable(snandc->qspi->iomacro_clk);
1561 if (ret)
1562 goto err_dis_iom_clk;
1563
1564 ret = qcom_nandc_alloc(snandc);
1565 if (ret)
1566 goto err_snand_alloc;
1567
1568 ret = qcom_spi_init(snandc);
1569 if (ret)
1570 goto err_spi_init;
1571
1572 /* setup ECC engine */
1573 snandc->qspi->ecc_eng.dev = &pdev->dev;
1574 snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
1575 snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined;
1576 snandc->qspi->ecc_eng.priv = snandc;
1577
1578 ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng);
1579 if (ret) {
1580 dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret);
1581 goto err_spi_init;
1582 }
1583
1584 ctlr->num_chipselect = QPIC_QSPI_NUM_CS;
1585 ctlr->mem_ops = &qcom_spi_mem_ops;
1586 ctlr->mem_caps = &qcom_spi_mem_caps;
1587 ctlr->dev.of_node = pdev->dev.of_node;
1588 ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL |
1589 SPI_TX_QUAD | SPI_RX_QUAD;
1590
1591 ret = spi_register_controller(ctlr);
1592 if (ret) {
1593 dev_err(&pdev->dev, "spi_register_controller failed.\n");
1594 goto err_spi_init;
1595 }
1596
1597 return 0;
1598
1599 err_spi_init:
1600 qcom_nandc_unalloc(snandc);
1601 err_snand_alloc:
1602 clk_disable_unprepare(snandc->qspi->iomacro_clk);
1603 err_dis_iom_clk:
1604 clk_disable_unprepare(snandc->aon_clk);
1605 err_dis_aon_clk:
1606 clk_disable_unprepare(snandc->core_clk);
1607 err_dis_core_clk:
1608 dma_unmap_resource(dev, res->start, resource_size(res),
1609 DMA_BIDIRECTIONAL, 0);
1610 return ret;
1611 }
1612
qcom_spi_remove(struct platform_device * pdev)1613 static void qcom_spi_remove(struct platform_device *pdev)
1614 {
1615 struct spi_controller *ctlr = platform_get_drvdata(pdev);
1616 struct qcom_nand_controller *snandc = spi_controller_get_devdata(ctlr);
1617 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1618
1619 spi_unregister_controller(ctlr);
1620
1621 qcom_nandc_unalloc(snandc);
1622
1623 clk_disable_unprepare(snandc->aon_clk);
1624 clk_disable_unprepare(snandc->core_clk);
1625 clk_disable_unprepare(snandc->qspi->iomacro_clk);
1626
1627 dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res),
1628 DMA_BIDIRECTIONAL, 0);
1629 }
1630
1631 static const struct qcom_nandc_props ipq9574_snandc_props = {
1632 .dev_cmd_reg_start = 0x7000,
1633 .bam_offset = 0x30000,
1634 .supports_bam = true,
1635 };
1636
1637 static const struct of_device_id qcom_snandc_of_match[] = {
1638 {
1639 .compatible = "qcom,ipq9574-snand",
1640 .data = &ipq9574_snandc_props,
1641 },
1642 {}
1643 };
1644 MODULE_DEVICE_TABLE(of, qcom_snandc_of_match);
1645
1646 static struct platform_driver qcom_spi_driver = {
1647 .driver = {
1648 .name = "qcom_snand",
1649 .of_match_table = qcom_snandc_of_match,
1650 },
1651 .probe = qcom_spi_probe,
1652 .remove = qcom_spi_remove,
1653 };
1654 module_platform_driver(qcom_spi_driver);
1655
1656 MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores");
1657 MODULE_AUTHOR("Md Sadre Alam <quic_mdalam@quicinc.com>");
1658 MODULE_LICENSE("GPL");
1659
1660