1 //===-- EmulateInstructionARM.h ---------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_SOURCE_PLUGINS_INSTRUCTION_ARM_EMULATEINSTRUCTIONARM_H 10 #define LLDB_SOURCE_PLUGINS_INSTRUCTION_ARM_EMULATEINSTRUCTIONARM_H 11 12 #include "Plugins/Process/Utility/ARMDefines.h" 13 #include "lldb/Core/EmulateInstruction.h" 14 #include "lldb/Utility/Status.h" 15 #include <optional> 16 17 namespace lldb_private { 18 19 class ARMSingleStepBreakpointLocationsPredictor 20 : public SingleStepBreakpointLocationsPredictor { 21 public: ARMSingleStepBreakpointLocationsPredictor(std::unique_ptr<EmulateInstruction> emulator_up)22 ARMSingleStepBreakpointLocationsPredictor( 23 std::unique_ptr<EmulateInstruction> emulator_up) 24 : SingleStepBreakpointLocationsPredictor{std::move(emulator_up)} {} 25 26 llvm::Expected<unsigned> GetBreakpointSize(lldb::addr_t bp_addr) override; 27 }; 28 29 // ITSession - Keep track of the IT Block progression. 30 class ITSession { 31 public: 32 ITSession() = default; 33 ~ITSession() = default; 34 35 // InitIT - Initializes ITCounter/ITState. 36 bool InitIT(uint32_t bits7_0); 37 38 // ITAdvance - Updates ITCounter/ITState as IT Block progresses. 39 void ITAdvance(); 40 41 // InITBlock - Returns true if we're inside an IT Block. 42 bool InITBlock(); 43 44 // LastInITBlock - Returns true if we're the last instruction inside an IT 45 // Block. 46 bool LastInITBlock(); 47 48 // GetCond - Gets condition bits for the current thumb instruction. 49 uint32_t GetCond(); 50 51 private: 52 uint32_t ITCounter = 0; // Possible values: 0, 1, 2, 3, 4. 53 uint32_t ITState = 0; // A2.5.2 Consists of IT[7:5] and IT[4:0] initially. 54 }; 55 56 class EmulateInstructionARM : public EmulateInstruction { 57 public: 58 enum ARMEncoding { 59 eEncodingA1, 60 eEncodingA2, 61 eEncodingA3, 62 eEncodingA4, 63 eEncodingA5, 64 eEncodingT1, 65 eEncodingT2, 66 eEncodingT3, 67 eEncodingT4, 68 eEncodingT5 69 }; 70 71 static void Initialize(); 72 73 static void Terminate(); 74 GetPluginNameStatic()75 static llvm::StringRef GetPluginNameStatic() { return "arm"; } 76 77 static llvm::StringRef GetPluginDescriptionStatic(); 78 79 static lldb_private::EmulateInstruction * 80 CreateInstance(const lldb_private::ArchSpec &arch, InstructionType inst_type); 81 82 static bool SupportsEmulatingInstructionsOfTypeStatic(InstructionType inst_type)83 SupportsEmulatingInstructionsOfTypeStatic(InstructionType inst_type) { 84 switch (inst_type) { 85 case eInstructionTypeAny: 86 case eInstructionTypePrologueEpilogue: 87 case eInstructionTypePCModifying: 88 return true; 89 90 case eInstructionTypeAll: 91 return false; 92 } 93 return false; 94 } 95 GetPluginName()96 llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); } 97 98 bool SetTargetTriple(const ArchSpec &arch) override; 99 100 enum Mode { eModeInvalid = -1, eModeARM, eModeThumb }; 101 EmulateInstructionARM(const ArchSpec & arch)102 EmulateInstructionARM(const ArchSpec &arch) 103 : EmulateInstruction(arch), m_arm_isa(0), m_opcode_mode(eModeInvalid), 104 m_opcode_cpsr(0), m_new_inst_cpsr(0), m_it_session(), 105 m_ignore_conditions(false) { 106 SetArchitecture(arch); 107 } 108 109 // EmulateInstructionARM (const ArchSpec &arch, 110 // bool ignore_conditions, 111 // void *baton, 112 // ReadMemory read_mem_callback, 113 // WriteMemory write_mem_callback, 114 // ReadRegister read_reg_callback, 115 // WriteRegister write_reg_callback) : 116 // EmulateInstruction (arch, 117 // ignore_conditions, 118 // baton, 119 // read_mem_callback, 120 // write_mem_callback, 121 // read_reg_callback, 122 // write_reg_callback), 123 // m_arm_isa (0), 124 // m_opcode_mode (eModeInvalid), 125 // m_opcode_cpsr (0), 126 // m_it_session () 127 // { 128 // } 129 SupportsEmulatingInstructionsOfType(InstructionType inst_type)130 bool SupportsEmulatingInstructionsOfType(InstructionType inst_type) override { 131 return SupportsEmulatingInstructionsOfTypeStatic(inst_type); 132 } 133 134 virtual bool SetArchitecture(const ArchSpec &arch); 135 136 bool ReadInstruction() override; 137 138 bool SetInstruction(const Opcode &insn_opcode, const Address &inst_addr, 139 Target *target) override; 140 141 bool EvaluateInstruction(uint32_t evaluate_options) override; 142 143 InstructionCondition GetInstructionCondition() override; 144 145 bool TestEmulation(Stream &out_stream, ArchSpec &arch, 146 OptionValueDictionary *test_data) override; 147 148 std::optional<RegisterInfo> GetRegisterInfo(lldb::RegisterKind reg_kind, 149 uint32_t reg_num) override; 150 151 bool CreateFunctionEntryUnwind(UnwindPlan &unwind_plan) override; 152 153 uint32_t ArchVersion(); 154 155 bool ConditionPassed(const uint32_t opcode); 156 157 uint32_t CurrentCond(const uint32_t opcode); 158 159 // InITBlock - Returns true if we're in Thumb mode and inside an IT Block. 160 bool InITBlock(); 161 162 // LastInITBlock - Returns true if we're in Thumb mode and the last 163 // instruction inside an IT Block. 164 bool LastInITBlock(); 165 166 bool BadMode(uint32_t mode); 167 168 bool CurrentModeIsPrivileged(); 169 170 void CPSRWriteByInstr(uint32_t value, uint32_t bytemask, 171 bool affect_execstate); 172 173 bool BranchWritePC(const Context &context, uint32_t addr); 174 175 bool BXWritePC(Context &context, uint32_t addr); 176 177 bool LoadWritePC(Context &context, uint32_t addr); 178 179 bool ALUWritePC(Context &context, uint32_t addr); 180 181 Mode CurrentInstrSet(); 182 183 bool SelectInstrSet(Mode arm_or_thumb); 184 185 bool WriteBits32Unknown(int n); 186 187 bool WriteBits32UnknownToMemory(lldb::addr_t address); 188 189 bool UnalignedSupport(); 190 191 typedef struct { 192 uint32_t result; 193 uint8_t carry_out; 194 uint8_t overflow; 195 } AddWithCarryResult; 196 197 AddWithCarryResult AddWithCarry(uint32_t x, uint32_t y, uint8_t carry_in); 198 199 // Helper method to read the content of an ARM core register. 200 uint32_t ReadCoreReg(uint32_t regnum, bool *success); 201 202 // See A8.6.96 MOV (immediate) Operation. 203 // Default arguments are specified for carry and overflow parameters, which 204 // means 205 // not to update the respective flags even if setflags is true. 206 bool WriteCoreRegOptionalFlags(Context &context, const uint32_t result, 207 const uint32_t Rd, bool setflags, 208 const uint32_t carry = ~0u, 209 const uint32_t overflow = ~0u); 210 WriteCoreReg(Context & context,const uint32_t result,const uint32_t Rd)211 bool WriteCoreReg(Context &context, const uint32_t result, 212 const uint32_t Rd) { 213 // Don't set the flags. 214 return WriteCoreRegOptionalFlags(context, result, Rd, false); 215 } 216 217 // See A8.6.35 CMP (immediate) Operation. 218 // Default arguments are specified for carry and overflow parameters, which 219 // means 220 // not to update the respective flags. 221 bool WriteFlags(Context &context, const uint32_t result, 222 const uint32_t carry = ~0u, const uint32_t overflow = ~0u); 223 MemARead(EmulateInstruction::Context & context,lldb::addr_t address,uint32_t size,uint64_t fail_value,bool * success_ptr)224 inline uint64_t MemARead(EmulateInstruction::Context &context, 225 lldb::addr_t address, uint32_t size, 226 uint64_t fail_value, bool *success_ptr) { 227 // This is a stub function corresponding to "MemA[]" in the ARM manual 228 // pseudocode, for 229 // aligned reads from memory. Since we are not trying to write a full 230 // hardware simulator, and since 231 // we are running in User mode (rather than Kernel mode) and therefore won't 232 // have access to many of the 233 // system registers we would need in order to fully implement this function, 234 // we will just call 235 // ReadMemoryUnsigned from here. In the future, if we decide we do need to 236 // do more faithful emulation of 237 // the hardware, we can update this function appropriately. 238 239 return ReadMemoryUnsigned(context, address, size, fail_value, success_ptr); 240 } 241 MemAWrite(EmulateInstruction::Context & context,lldb::addr_t address,uint64_t data_val,uint32_t size)242 inline bool MemAWrite(EmulateInstruction::Context &context, 243 lldb::addr_t address, uint64_t data_val, uint32_t size) 244 245 { 246 // This is a stub function corresponding to "MemA[]" in the ARM manual 247 // pseudocode, for 248 // aligned writes to memory. Since we are not trying to write a full 249 // hardware simulator, and since 250 // we are running in User mode (rather than Kernel mode) and therefore won't 251 // have access to many of the 252 // system registers we would need in order to fully implement this function, 253 // we will just call 254 // WriteMemoryUnsigned from here. In the future, if we decide we do need to 255 // do more faithful emulation of 256 // the hardware, we can update this function appropriately. 257 258 return WriteMemoryUnsigned(context, address, data_val, size); 259 } 260 MemURead(EmulateInstruction::Context & context,lldb::addr_t address,uint32_t size,uint64_t fail_value,bool * success_ptr)261 inline uint64_t MemURead(EmulateInstruction::Context &context, 262 lldb::addr_t address, uint32_t size, 263 uint64_t fail_value, bool *success_ptr) { 264 // This is a stub function corresponding to "MemU[]" in the ARM manual 265 // pseudocode, for 266 // unaligned reads from memory. Since we are not trying to write a full 267 // hardware simulator, and since 268 // we are running in User mode (rather than Kernel mode) and therefore won't 269 // have access to many of the 270 // system registers we would need in order to fully implement this function, 271 // we will just call 272 // ReadMemoryUnsigned from here. In the future, if we decide we do need to 273 // do more faithful emulation of 274 // the hardware, we can update this function appropriately. 275 276 return ReadMemoryUnsigned(context, address, size, fail_value, success_ptr); 277 } 278 MemUWrite(EmulateInstruction::Context & context,lldb::addr_t address,uint64_t data_val,uint32_t size)279 inline bool MemUWrite(EmulateInstruction::Context &context, 280 lldb::addr_t address, uint64_t data_val, uint32_t size) 281 282 { 283 // This is a stub function corresponding to "MemU[]" in the ARM manual 284 // pseudocode, for 285 // unaligned writes to memory. Since we are not trying to write a full 286 // hardware simulator, and since 287 // we are running in User mode (rather than Kernel mode) and therefore won't 288 // have access to many of the 289 // system registers we would need in order to fully implement this function, 290 // we will just call 291 // WriteMemoryUnsigned from here. In the future, if we decide we do need to 292 // do more faithful emulation of 293 // the hardware, we can update this function appropriately. 294 295 return WriteMemoryUnsigned(context, address, data_val, size); 296 } 297 298 protected: 299 // Typedef for the callback function used during the emulation. 300 // Pass along (ARMEncoding)encoding as the callback data. 301 enum ARMInstrSize { eSize16, eSize32 }; 302 303 typedef struct { 304 uint32_t mask; 305 uint32_t value; 306 uint32_t variants; 307 EmulateInstructionARM::ARMEncoding encoding; 308 uint32_t vfp_variants; 309 ARMInstrSize size; 310 bool (EmulateInstructionARM::*callback)( 311 const uint32_t opcode, 312 const EmulateInstructionARM::ARMEncoding encoding); 313 const char *name; 314 } ARMOpcode; 315 316 uint32_t GetFramePointerRegisterNumber() const; 317 318 uint32_t GetFramePointerDWARFRegisterNumber() const; 319 320 static ARMOpcode *GetARMOpcodeForInstruction(const uint32_t opcode, 321 uint32_t isa_mask); 322 323 static ARMOpcode *GetThumbOpcodeForInstruction(const uint32_t opcode, 324 uint32_t isa_mask); 325 326 // A8.6.123 PUSH 327 bool EmulatePUSH(const uint32_t opcode, const ARMEncoding encoding); 328 329 // A8.6.122 POP 330 bool EmulatePOP(const uint32_t opcode, const ARMEncoding encoding); 331 332 // A8.6.8 ADD (SP plus immediate) 333 bool EmulateADDRdSPImm(const uint32_t opcode, const ARMEncoding encoding); 334 335 // A8.6.97 MOV (register) -- Rd == r7|ip and Rm == sp 336 bool EmulateMOVRdSP(const uint32_t opcode, const ARMEncoding encoding); 337 338 // A8.6.97 MOV (register) -- move from r8-r15 to r0-r7 339 bool EmulateMOVLowHigh(const uint32_t opcode, const ARMEncoding encoding); 340 341 // A8.6.59 LDR (literal) 342 bool EmulateLDRRtPCRelative(const uint32_t opcode, 343 const ARMEncoding encoding); 344 345 // A8.6.8 ADD (SP plus immediate) 346 bool EmulateADDSPImm(const uint32_t opcode, const ARMEncoding encoding); 347 348 // A8.6.9 ADD (SP plus register) 349 bool EmulateADDSPRm(const uint32_t opcode, const ARMEncoding encoding); 350 351 // A8.6.23 BL, BLX (immediate) 352 bool EmulateBLXImmediate(const uint32_t opcode, const ARMEncoding encoding); 353 354 // A8.6.24 BLX (register) 355 bool EmulateBLXRm(const uint32_t opcode, const ARMEncoding encoding); 356 357 // A8.6.25 BX 358 bool EmulateBXRm(const uint32_t opcode, const ARMEncoding encoding); 359 360 // A8.6.26 BXJ 361 bool EmulateBXJRm(const uint32_t opcode, const ARMEncoding encoding); 362 363 // A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip 364 bool EmulateSUBR7IPImm(const uint32_t opcode, const ARMEncoding encoding); 365 366 // A8.6.215 SUB (SP minus immediate) -- Rd == ip 367 bool EmulateSUBIPSPImm(const uint32_t opcode, const ARMEncoding encoding); 368 369 // A8.6.215 SUB (SP minus immediate) 370 bool EmulateSUBSPImm(const uint32_t opcode, const ARMEncoding encoding); 371 372 // A8.6.216 SUB (SP minus register) 373 bool EmulateSUBSPReg(const uint32_t opcode, const ARMEncoding encoding); 374 375 // A8.6.194 STR (immediate, ARM) -- Rn == sp 376 bool EmulateSTRRtSP(const uint32_t opcode, const ARMEncoding encoding); 377 378 // A8.6.355 VPUSH 379 bool EmulateVPUSH(const uint32_t opcode, const ARMEncoding encoding); 380 381 // A8.6.354 VPOP 382 bool EmulateVPOP(const uint32_t opcode, const ARMEncoding encoding); 383 384 // A8.6.218 SVC (previously SWI) 385 bool EmulateSVC(const uint32_t opcode, const ARMEncoding encoding); 386 387 // A8.6.50 IT 388 bool EmulateIT(const uint32_t opcode, const ARMEncoding encoding); 389 390 // NOP 391 bool EmulateNop(const uint32_t opcode, const ARMEncoding encoding); 392 393 // A8.6.16 B 394 bool EmulateB(const uint32_t opcode, const ARMEncoding encoding); 395 396 // A8.6.27 CBNZ, CBZ 397 bool EmulateCB(const uint32_t opcode, const ARMEncoding encoding); 398 399 // A8.6.226 TBB, TBH 400 bool EmulateTB(const uint32_t opcode, const ARMEncoding encoding); 401 402 // A8.6.4 ADD (immediate, Thumb) 403 bool EmulateADDImmThumb(const uint32_t opcode, const ARMEncoding encoding); 404 405 // A8.6.5 ADD (immediate, ARM) 406 bool EmulateADDImmARM(const uint32_t opcode, const ARMEncoding encoding); 407 408 // A8.6.6 ADD (register) 409 bool EmulateADDReg(const uint32_t opcode, const ARMEncoding encoding); 410 411 // A8.6.7 ADD (register-shifted register) 412 bool EmulateADDRegShift(const uint32_t opcode, const ARMEncoding encoding); 413 414 // A8.6.97 MOV (register) 415 bool EmulateMOVRdRm(const uint32_t opcode, const ARMEncoding encoding); 416 417 // A8.6.96 MOV (immediate) 418 bool EmulateMOVRdImm(const uint32_t opcode, const ARMEncoding encoding); 419 420 // A8.6.35 CMP (immediate) 421 bool EmulateCMPImm(const uint32_t opcode, const ARMEncoding encoding); 422 423 // A8.6.36 CMP (register) 424 bool EmulateCMPReg(const uint32_t opcode, const ARMEncoding encoding); 425 426 // A8.6.14 ASR (immediate) 427 bool EmulateASRImm(const uint32_t opcode, const ARMEncoding encoding); 428 429 // A8.6.15 ASR (register) 430 bool EmulateASRReg(const uint32_t opcode, const ARMEncoding encoding); 431 432 // A8.6.88 LSL (immediate) 433 bool EmulateLSLImm(const uint32_t opcode, const ARMEncoding encoding); 434 435 // A8.6.89 LSL (register) 436 bool EmulateLSLReg(const uint32_t opcode, const ARMEncoding encoding); 437 438 // A8.6.90 LSR (immediate) 439 bool EmulateLSRImm(const uint32_t opcode, const ARMEncoding encoding); 440 441 // A8.6.91 LSR (register) 442 bool EmulateLSRReg(const uint32_t opcode, const ARMEncoding encoding); 443 444 // A8.6.139 ROR (immediate) 445 bool EmulateRORImm(const uint32_t opcode, const ARMEncoding encoding); 446 447 // A8.6.140 ROR (register) 448 bool EmulateRORReg(const uint32_t opcode, const ARMEncoding encoding); 449 450 // A8.6.141 RRX 451 bool EmulateRRX(const uint32_t opcode, const ARMEncoding encoding); 452 453 // Helper method for ASR, LSL, LSR, ROR (immediate), and RRX 454 bool EmulateShiftImm(const uint32_t opcode, const ARMEncoding encoding, 455 ARM_ShifterType shift_type); 456 457 // Helper method for ASR, LSL, LSR, and ROR (register) 458 bool EmulateShiftReg(const uint32_t opcode, const ARMEncoding encoding, 459 ARM_ShifterType shift_type); 460 461 // LOAD FUNCTIONS 462 463 // A8.6.53 LDM/LDMIA/LDMFD 464 bool EmulateLDM(const uint32_t opcode, const ARMEncoding encoding); 465 466 // A8.6.54 LDMDA/LDMFA 467 bool EmulateLDMDA(const uint32_t opcode, const ARMEncoding encoding); 468 469 // A8.6.55 LDMDB/LDMEA 470 bool EmulateLDMDB(const uint32_t opcode, const ARMEncoding encoding); 471 472 // A8.6.56 LDMIB/LDMED 473 bool EmulateLDMIB(const uint32_t opcode, const ARMEncoding encoding); 474 475 // A8.6.57 LDR (immediate, Thumb) -- Encoding T1 476 bool EmulateLDRRtRnImm(const uint32_t opcode, const ARMEncoding encoding); 477 478 // A8.6.58 LDR (immediate, ARM) - Encoding A1 479 bool EmulateLDRImmediateARM(const uint32_t opcode, 480 const ARMEncoding encoding); 481 482 // A8.6.59 LDR (literal) 483 bool EmulateLDRLiteral(const uint32_t, const ARMEncoding encoding); 484 485 // A8.6.60 LDR (register) - Encoding T1, T2, A1 486 bool EmulateLDRRegister(const uint32_t opcode, const ARMEncoding encoding); 487 488 // A8.6.61 LDRB (immediate, Thumb) - Encoding T1, T2, T3 489 bool EmulateLDRBImmediate(const uint32_t opcode, const ARMEncoding encoding); 490 491 // A8.6.62 LDRB (immediate, ARM) 492 bool EmulateLDRBImmediateARM(const uint32_t opcode, 493 const ARMEncoding encoding); 494 495 // A8.6.63 LDRB (literal) - Encoding T1, A1 496 bool EmulateLDRBLiteral(const uint32_t opcode, const ARMEncoding encoding); 497 498 // A8.6.64 LDRB (register) - Encoding T1, T2, A1 499 bool EmulateLDRBRegister(const uint32_t opcode, const ARMEncoding encoding); 500 501 // A8.6.65 LDRBT 502 bool EmulateLDRBT(const uint32_t opcode, const ARMEncoding encoding); 503 504 // A8.6.66 LDRD (immediate) 505 bool EmulateLDRDImmediate(const uint32_t opcode, const ARMEncoding encoding); 506 507 // A8.6.67 508 bool EmulateLDRDLiteral(const uint32_t opcode, const ARMEncoding encoding); 509 510 // A8.6.68 LDRD (register) 511 bool EmulateLDRDRegister(const uint32_t opcode, const ARMEncoding encoding); 512 513 // A8.6.69 LDREX 514 bool EmulateLDREX(const uint32_t opcode, const ARMEncoding encoding); 515 516 // A8.6.70 LDREXB 517 bool EmulateLDREXB(const uint32_t opcode, const ARMEncoding encoding); 518 519 // A8.6.71 LDREXD 520 bool EmulateLDREXD(const uint32_t opcode, const ARMEncoding encoding); 521 522 // A8.6.72 LDREXH 523 bool EmulateLDREXH(const uint32_t opcode, const ARMEncoding encoding); 524 525 // A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2, T3 526 bool EmulateLDRHImmediate(const uint32_t opcode, const ARMEncoding encoding); 527 528 // A8.6.74 LDRS (immediate, ARM) 529 bool EmulateLDRHImmediateARM(const uint32_t opcode, 530 const ARMEncoding encoding); 531 532 // A8.6.75 LDRH (literal) - Encoding T1, A1 533 bool EmulateLDRHLiteral(const uint32_t opcode, const ARMEncoding encoding); 534 535 // A8.6.76 LDRH (register) - Encoding T1, T2, A1 536 bool EmulateLDRHRegister(const uint32_t opcode, const ARMEncoding encoding); 537 538 // A8.6.77 LDRHT 539 bool EmulateLDRHT(const uint32_t opcode, const ARMEncoding encoding); 540 541 // A8.6.78 LDRSB (immediate) - Encoding T1, T2, A1 542 bool EmulateLDRSBImmediate(const uint32_t opcode, const ARMEncoding encoding); 543 544 // A8.6.79 LDRSB (literal) - Encoding T1, A1 545 bool EmulateLDRSBLiteral(const uint32_t opcode, const ARMEncoding encoding); 546 547 // A8.6.80 LDRSB (register) - Encoding T1, T2, A1 548 bool EmulateLDRSBRegister(const uint32_t opcode, const ARMEncoding encoding); 549 550 // A8.6.81 LDRSBT 551 bool EmulateLDRSBT(const uint32_t opcode, const ARMEncoding encoding); 552 553 // A8.6.82 LDRSH (immediate) - Encoding T1, T2, A1 554 bool EmulateLDRSHImmediate(const uint32_t opcode, const ARMEncoding encoding); 555 556 // A8.6.83 LDRSH (literal) - Encoding T1, A1 557 bool EmulateLDRSHLiteral(const uint32_t opcode, const ARMEncoding encoding); 558 559 // A8.6.84 LDRSH (register) - Encoding T1, T2, A1 560 bool EmulateLDRSHRegister(const uint32_t opcode, const ARMEncoding encoding); 561 562 // A8.6.85 LDRSHT 563 bool EmulateLDRSHT(const uint32_t opcode, const ARMEncoding encoding); 564 565 // A8.6.86 566 bool EmulateLDRT(const uint32_t opcode, const ARMEncoding encoding); 567 568 // STORE FUNCTIONS 569 570 // A8.6.189 STM/STMIA/STMEA 571 bool EmulateSTM(const uint32_t opcode, const ARMEncoding encoding); 572 573 // A8.6.190 STMDA/STMED 574 bool EmulateSTMDA(const uint32_t opcode, const ARMEncoding encoding); 575 576 // A8.6.191 STMDB/STMFD 577 bool EmulateSTMDB(const uint32_t opcode, const ARMEncoding encoding); 578 579 // A8.6.192 STMIB/STMFA 580 bool EmulateSTMIB(const uint32_t opcode, const ARMEncoding encoding); 581 582 // A8.6.193 STR (immediate, Thumb) 583 bool EmulateSTRThumb(const uint32_t opcode, const ARMEncoding encoding); 584 585 // A8.6.194 STR (immediate, ARM) 586 bool EmulateSTRImmARM(const uint32_t opcode, const ARMEncoding encoding); 587 588 // A8.6.195 STR (register) 589 bool EmulateSTRRegister(const uint32_t opcode, const ARMEncoding encoding); 590 591 // A8.6.196 STRB (immediate, Thumb) 592 bool EmulateSTRBThumb(const uint32_t opcode, const ARMEncoding encoding); 593 594 // A8.6.197 STRB (immediate, ARM) 595 bool EmulateSTRBImmARM(const uint32_t opcode, const ARMEncoding encoding); 596 597 // A8.6.198 STRB (register) 598 bool EmulateSTRBReg(const uint32_t opcode, const ARMEncoding encoding); 599 600 // A8.6.199 STRBT 601 bool EmulateSTRBT(const uint32_t opcode, const ARMEncoding encoding); 602 603 // A8.6.200 STRD (immediate) 604 bool EmulateSTRDImm(const uint32_t opcode, const ARMEncoding encoding); 605 606 // A8.6.201 STRD (register) 607 bool EmulateSTRDReg(const uint32_t opcode, const ARMEncoding encoding); 608 609 // A8.6.202 STREX 610 bool EmulateSTREX(const uint32_t opcode, const ARMEncoding encoding); 611 612 // A8.6.203 STREXB 613 bool EmulateSTREXB(const uint32_t opcode, const ARMEncoding encoding); 614 615 // A8.6.204 STREXD 616 bool EmulateSTREXD(const uint32_t opcode, const ARMEncoding encoding); 617 618 // A8.6.205 STREXH 619 bool EmulateSTREXH(const uint32_t opcode, const ARMEncoding encoding); 620 621 // A8.6.206 STRH (immediate, Thumb) 622 bool EmulateSTRHImmThumb(const uint32_t opcode, const ARMEncoding encoding); 623 624 // A8.6.207 STRH (immediate, ARM) 625 bool EmulateSTRHImmARM(const uint32_t opcode, const ARMEncoding encoding); 626 627 // A8.6.208 STRH (register) 628 bool EmulateSTRHRegister(const uint32_t opcode, const ARMEncoding encoding); 629 630 // A8.6.209 STRHT 631 bool EmulateSTRHT(const uint32_t opcode, const ARMEncoding encoding); 632 633 // A8.6.210 STRT 634 bool EmulateSTRT(const uint32_t opcode, const ARMEncoding encoding); 635 636 // A8.6.1 ADC (immediate) 637 bool EmulateADCImm(const uint32_t opcode, const ARMEncoding encoding); 638 639 // A8.6.2 ADC (Register) 640 bool EmulateADCReg(const uint32_t opcode, const ARMEncoding encoding); 641 642 // A8.6.10 ADR 643 bool EmulateADR(const uint32_t opcode, const ARMEncoding encoding); 644 645 // A8.6.11 AND (immediate) 646 bool EmulateANDImm(const uint32_t opcode, const ARMEncoding encoding); 647 648 // A8.6.12 AND (register) 649 bool EmulateANDReg(const uint32_t opcode, const ARMEncoding encoding); 650 651 // A8.6.19 BIC (immediate) 652 bool EmulateBICImm(const uint32_t opcode, const ARMEncoding encoding); 653 654 // A8.6.20 BIC (register) 655 bool EmulateBICReg(const uint32_t opcode, const ARMEncoding encoding); 656 657 // A8.6.26 BXJ 658 bool EmulateBXJ(const uint32_t opcode, const ARMEncoding encoding); 659 660 // A8.6.32 CMN (immediate) 661 bool EmulateCMNImm(const uint32_t opcode, const ARMEncoding encoding); 662 663 // A8.6.33 CMN (register) 664 bool EmulateCMNReg(const uint32_t opcode, const ARMEncoding encoding); 665 666 // A8.6.44 EOR (immediate) 667 bool EmulateEORImm(const uint32_t opcode, const ARMEncoding encoding); 668 669 // A8.6.45 EOR (register) 670 bool EmulateEORReg(const uint32_t opcode, const ARMEncoding encoding); 671 672 // A8.6.105 MUL 673 bool EmulateMUL(const uint32_t opcode, const ARMEncoding encoding); 674 675 // A8.6.106 MVN (immediate) 676 bool EmulateMVNImm(const uint32_t opcode, const ARMEncoding encoding); 677 678 // A8.6.107 MVN (register) 679 bool EmulateMVNReg(const uint32_t opcode, const ARMEncoding encoding); 680 681 // A8.6.113 ORR (immediate) 682 bool EmulateORRImm(const uint32_t opcode, const ARMEncoding encoding); 683 684 // A8.6.114 ORR (register) 685 bool EmulateORRReg(const uint32_t opcode, const ARMEncoding encoding); 686 687 // A8.6.117 PLD (immediate, literal) - Encoding T1, T2, T3, A1 688 bool EmulatePLDImmediate(const uint32_t opcode, const ARMEncoding encoding); 689 690 // A8.6.119 PLI (immediate,literal) - Encoding T3, A1 691 bool EmulatePLIImmediate(const uint32_t opcode, const ARMEncoding encoding); 692 693 // A8.6.120 PLI (register) - Encoding T1, A1 694 bool EmulatePLIRegister(const uint32_t opcode, const ARMEncoding encoding); 695 696 // A8.6.141 RSB (immediate) 697 bool EmulateRSBImm(const uint32_t opcode, const ARMEncoding encoding); 698 699 // A8.6.142 RSB (register) 700 bool EmulateRSBReg(const uint32_t opcode, const ARMEncoding encoding); 701 702 // A8.6.144 RSC (immediate) 703 bool EmulateRSCImm(const uint32_t opcode, const ARMEncoding encoding); 704 705 // A8.6.145 RSC (register) 706 bool EmulateRSCReg(const uint32_t opcode, const ARMEncoding encoding); 707 708 // A8.6.150 SBC (immediate) 709 bool EmulateSBCImm(const uint32_t opcode, const ARMEncoding encoding); 710 711 // A8.6.151 SBC (register) 712 bool EmulateSBCReg(const uint32_t opcode, const ARMEncoding encoding); 713 714 // A8.6.211 SUB (immediate, Thumb) 715 bool EmulateSUBImmThumb(const uint32_t opcode, const ARMEncoding encoding); 716 717 // A8.6.212 SUB (immediate, ARM) 718 bool EmulateSUBImmARM(const uint32_t opcode, const ARMEncoding encoding); 719 720 // A8.6.213 SUB (register) 721 bool EmulateSUBReg(const uint32_t opcode, const ARMEncoding encoding); 722 723 // A8.6.214 SUB (register-shifted register) 724 bool EmulateSUBRegShift(const uint32_t opcode, const ARMEncoding encoding); 725 726 // A8.6.222 SXTB - Encoding T1 727 bool EmulateSXTB(const uint32_t opcode, const ARMEncoding encoding); 728 729 // A8.6.224 SXTH - EncodingT1 730 bool EmulateSXTH(const uint32_t opcode, const ARMEncoding encoding); 731 732 // A8.6.227 TEQ (immediate) - Encoding A1 733 bool EmulateTEQImm(const uint32_t opcode, const ARMEncoding encoding); 734 735 // A8.6.228 TEQ (register) - Encoding A1 736 bool EmulateTEQReg(const uint32_t opcode, const ARMEncoding encoding); 737 738 // A8.6.230 TST (immediate) - Encoding A1 739 bool EmulateTSTImm(const uint32_t opcode, const ARMEncoding encoding); 740 741 // A8.6.231 TST (register) - Encoding T1, A1 742 bool EmulateTSTReg(const uint32_t opcode, const ARMEncoding encoding); 743 744 // A8.6.262 UXTB - Encoding T1 745 bool EmulateUXTB(const uint32_t opcode, const ARMEncoding encoding); 746 747 // A8.6.264 UXTH - Encoding T1 748 bool EmulateUXTH(const uint32_t opcode, const ARMEncoding encoding); 749 750 // B6.1.8 RFE 751 bool EmulateRFE(const uint32_t opcode, const ARMEncoding encoding); 752 753 // A8.6.319 VLDM 754 bool EmulateVLDM(const uint32_t opcode, const ARMEncoding encoding); 755 756 // A8.6.399 VSTM 757 bool EmulateVSTM(const uint32_t opcode, const ARMEncoding encoding); 758 759 // A8.6.307 VLD1 (multiple single elements) 760 bool EmulateVLD1Multiple(const uint32_t opcode, const ARMEncoding encoding); 761 762 // A8.6.308 VLD1 (single element to one lane) 763 bool EmulateVLD1Single(const uint32_t opcode, const ARMEncoding encoding); 764 765 // A8.6.309 VLD1 (single element to all lanes) 766 bool EmulateVLD1SingleAll(const uint32_t opcode, const ARMEncoding encoding); 767 768 // A8.6.391 VST1 (multiple single elements) 769 bool EmulateVST1Multiple(const uint32_t opcode, const ARMEncoding encoding); 770 771 // A8.6.392 VST1 (single element from one lane) 772 bool EmulateVST1Single(const uint32_t opcode, const ARMEncoding encoding); 773 774 // A8.6.317 VLDR 775 bool EmulateVLDR(const uint32_t opcode, const ARMEncoding encoding); 776 777 // A8.6.400 VSTR 778 bool EmulateVSTR(const uint32_t opcode, const ARMEncoding encoding); 779 780 // B6.2.13 SUBS PC, LR and related instructions 781 bool EmulateSUBSPcLrEtc(const uint32_t opcode, const ARMEncoding encoding); 782 783 BreakpointLocationsPredictorCreator GetSingleStepBreakpointLocationsPredictorCreator()784 GetSingleStepBreakpointLocationsPredictorCreator() override { 785 return [](std::unique_ptr<EmulateInstruction> emulator_up) { 786 return std::make_unique<ARMSingleStepBreakpointLocationsPredictor>( 787 std::move(emulator_up)); 788 }; 789 } 790 791 uint32_t m_arm_isa; 792 Mode m_opcode_mode; 793 uint32_t m_opcode_cpsr; 794 uint32_t m_new_inst_cpsr; // This can get updated by the opcode. 795 ITSession m_it_session; 796 bool m_ignore_conditions; 797 }; 798 799 } // namespace lldb_private 800 801 #endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_ARM_EMULATEINSTRUCTIONARM_H 802