1 /*- 2 * Copyright (c) 2015 Semihalf 3 * Copyright (c) 2015 Stormshield 4 * Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include "opt_platform.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/errno.h> 35 #include <sys/kernel.h> 36 #include <sys/kthread.h> 37 #include <sys/module.h> 38 #include <sys/taskqueue.h> 39 #include <sys/socket.h> 40 #include <sys/sockio.h> 41 42 #include <net/if.h> 43 #include <net/if_media.h> 44 #include <net/if_types.h> 45 46 #include <dev/etherswitch/etherswitch.h> 47 #include <dev/mii/mii.h> 48 #include <dev/mii/miivar.h> 49 50 #ifdef FDT 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 #else 54 #include <machine/stdarg.h> 55 #endif 56 57 #include "e6000swreg.h" 58 #include "etherswitch_if.h" 59 #include "miibus_if.h" 60 #include "mdio_if.h" 61 62 MALLOC_DECLARE(M_E6000SW); 63 MALLOC_DEFINE(M_E6000SW, "e6000sw", "e6000sw switch"); 64 65 #define E6000SW_LOCK(_sc) sx_xlock(&(_sc)->sx) 66 #define E6000SW_UNLOCK(_sc) sx_unlock(&(_sc)->sx) 67 #define E6000SW_LOCK_ASSERT(_sc, _what) sx_assert(&(_sc)->sx, (_what)) 68 #define E6000SW_TRYLOCK(_sc) sx_tryxlock(&(_sc)->sx) 69 #define E6000SW_LOCKED(_sc) sx_xlocked(&(_sc)->sx) 70 #define E6000SW_WAITREADY(_sc, _reg, _bit) \ 71 e6000sw_waitready((_sc), REG_GLOBAL, (_reg), (_bit)) 72 #define E6000SW_WAITREADY2(_sc, _reg, _bit) \ 73 e6000sw_waitready((_sc), REG_GLOBAL2, (_reg), (_bit)) 74 #define MDIO_READ(dev, addr, reg) \ 75 MDIO_READREG(device_get_parent(dev), (addr), (reg)) 76 #define MDIO_WRITE(dev, addr, reg, val) \ 77 MDIO_WRITEREG(device_get_parent(dev), (addr), (reg), (val)) 78 79 80 typedef struct e6000sw_softc { 81 device_t dev; 82 #ifdef FDT 83 phandle_t node; 84 #endif 85 86 struct sx sx; 87 if_t ifp[E6000SW_MAX_PORTS]; 88 char *ifname[E6000SW_MAX_PORTS]; 89 device_t miibus[E6000SW_MAX_PORTS]; 90 struct taskqueue *sc_tq; 91 struct timeout_task sc_tt; 92 93 int vlans[E6000SW_NUM_VLANS]; 94 uint32_t swid; 95 uint32_t vlan_mode; 96 uint32_t cpuports_mask; 97 uint32_t fixed_mask; 98 uint32_t fixed25_mask; 99 uint32_t ports_mask; 100 int phy_base; 101 int sw_addr; 102 int num_ports; 103 } e6000sw_softc_t; 104 105 static etherswitch_info_t etherswitch_info = { 106 .es_nports = 0, 107 .es_nvlangroups = 0, 108 .es_vlan_caps = ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOT1Q, 109 .es_name = "Marvell 6000 series switch" 110 }; 111 112 static void e6000sw_identify(driver_t *, device_t); 113 static int e6000sw_probe(device_t); 114 #ifdef FDT 115 static int e6000sw_parse_fixed_link(e6000sw_softc_t *, phandle_t, uint32_t); 116 static int e6000sw_parse_ethernet(e6000sw_softc_t *, phandle_t, uint32_t); 117 #endif 118 static int e6000sw_attach(device_t); 119 static int e6000sw_detach(device_t); 120 static int e6000sw_read_xmdio(device_t, int, int, int); 121 static int e6000sw_write_xmdio(device_t, int, int, int, int); 122 static int e6000sw_readphy(device_t, int, int); 123 static int e6000sw_writephy(device_t, int, int, int); 124 static int e6000sw_readphy_locked(device_t, int, int); 125 static int e6000sw_writephy_locked(device_t, int, int, int); 126 static etherswitch_info_t* e6000sw_getinfo(device_t); 127 static int e6000sw_getconf(device_t, etherswitch_conf_t *); 128 static int e6000sw_setconf(device_t, etherswitch_conf_t *); 129 static void e6000sw_lock(device_t); 130 static void e6000sw_unlock(device_t); 131 static int e6000sw_getport(device_t, etherswitch_port_t *); 132 static int e6000sw_setport(device_t, etherswitch_port_t *); 133 static int e6000sw_set_vlan_mode(e6000sw_softc_t *, uint32_t); 134 static int e6000sw_readreg_wrapper(device_t, int); 135 static int e6000sw_writereg_wrapper(device_t, int, int); 136 static int e6000sw_getvgroup_wrapper(device_t, etherswitch_vlangroup_t *); 137 static int e6000sw_setvgroup_wrapper(device_t, etherswitch_vlangroup_t *); 138 static int e6000sw_setvgroup(device_t, etherswitch_vlangroup_t *); 139 static int e6000sw_getvgroup(device_t, etherswitch_vlangroup_t *); 140 static void e6000sw_setup(device_t, e6000sw_softc_t *); 141 static void e6000sw_tick(void *, int); 142 static void e6000sw_set_atustat(device_t, e6000sw_softc_t *, int, int); 143 static int e6000sw_atu_flush(device_t, e6000sw_softc_t *, int); 144 static int e6000sw_vtu_flush(e6000sw_softc_t *); 145 static int e6000sw_vtu_update(e6000sw_softc_t *, int, int, int, int, int); 146 static __inline void e6000sw_writereg(e6000sw_softc_t *, int, int, int); 147 static __inline uint32_t e6000sw_readreg(e6000sw_softc_t *, int, int); 148 static int e6000sw_ifmedia_upd(if_t); 149 static void e6000sw_ifmedia_sts(if_t, struct ifmediareq *); 150 static int e6000sw_atu_mac_table(device_t, e6000sw_softc_t *, struct atu_opt *, 151 int); 152 static int e6000sw_get_pvid(e6000sw_softc_t *, int, int *); 153 static void e6000sw_set_pvid(e6000sw_softc_t *, int, int); 154 static __inline bool e6000sw_is_cpuport(e6000sw_softc_t *, int); 155 static __inline bool e6000sw_is_fixedport(e6000sw_softc_t *, int); 156 static __inline bool e6000sw_is_fixed25port(e6000sw_softc_t *, int); 157 static __inline bool e6000sw_is_phyport(e6000sw_softc_t *, int); 158 static __inline bool e6000sw_is_portenabled(e6000sw_softc_t *, int); 159 static __inline struct mii_data *e6000sw_miiforphy(e6000sw_softc_t *, 160 unsigned int); 161 162 static device_method_t e6000sw_methods[] = { 163 /* device interface */ 164 DEVMETHOD(device_identify, e6000sw_identify), 165 DEVMETHOD(device_probe, e6000sw_probe), 166 DEVMETHOD(device_attach, e6000sw_attach), 167 DEVMETHOD(device_detach, e6000sw_detach), 168 169 /* bus interface */ 170 DEVMETHOD(bus_add_child, device_add_child_ordered), 171 172 /* mii interface */ 173 DEVMETHOD(miibus_readreg, e6000sw_readphy), 174 DEVMETHOD(miibus_writereg, e6000sw_writephy), 175 176 /* etherswitch interface */ 177 DEVMETHOD(etherswitch_getinfo, e6000sw_getinfo), 178 DEVMETHOD(etherswitch_getconf, e6000sw_getconf), 179 DEVMETHOD(etherswitch_setconf, e6000sw_setconf), 180 DEVMETHOD(etherswitch_lock, e6000sw_lock), 181 DEVMETHOD(etherswitch_unlock, e6000sw_unlock), 182 DEVMETHOD(etherswitch_getport, e6000sw_getport), 183 DEVMETHOD(etherswitch_setport, e6000sw_setport), 184 DEVMETHOD(etherswitch_readreg, e6000sw_readreg_wrapper), 185 DEVMETHOD(etherswitch_writereg, e6000sw_writereg_wrapper), 186 DEVMETHOD(etherswitch_readphyreg, e6000sw_readphy), 187 DEVMETHOD(etherswitch_writephyreg, e6000sw_writephy), 188 DEVMETHOD(etherswitch_setvgroup, e6000sw_setvgroup_wrapper), 189 DEVMETHOD(etherswitch_getvgroup, e6000sw_getvgroup_wrapper), 190 191 DEVMETHOD_END 192 }; 193 194 DEFINE_CLASS_0(e6000sw, e6000sw_driver, e6000sw_methods, 195 sizeof(e6000sw_softc_t)); 196 197 DRIVER_MODULE(e6000sw, mdio, e6000sw_driver, 0, 0); 198 DRIVER_MODULE(etherswitch, e6000sw, etherswitch_driver, 0, 0); 199 DRIVER_MODULE(miibus, e6000sw, miibus_driver, 0, 0); 200 MODULE_DEPEND(e6000sw, mdio, 1, 1, 1); 201 202 203 static void 204 e6000sw_identify(driver_t *driver, device_t parent) 205 { 206 207 if (device_find_child(parent, "e6000sw", -1) == NULL) 208 BUS_ADD_CHILD(parent, 0, "e6000sw", DEVICE_UNIT_ANY); 209 } 210 211 static int 212 e6000sw_probe(device_t dev) 213 { 214 e6000sw_softc_t *sc; 215 const char *description; 216 #ifdef FDT 217 phandle_t switch_node; 218 #else 219 int is_6190; 220 #endif 221 222 sc = device_get_softc(dev); 223 sc->dev = dev; 224 225 #ifdef FDT 226 switch_node = ofw_bus_find_compatible(OF_finddevice("/"), 227 "marvell,mv88e6085"); 228 if (switch_node == 0) { 229 switch_node = ofw_bus_find_compatible(OF_finddevice("/"), 230 "marvell,mv88e6190"); 231 232 if (switch_node == 0) 233 return (ENXIO); 234 235 /* 236 * Trust DTS and fix the port register offset for the MV88E6190 237 * detection bellow. 238 */ 239 sc->swid = MV88E6190; 240 } 241 242 if (bootverbose) 243 device_printf(dev, "Found switch_node: 0x%x\n", switch_node); 244 245 sc->node = switch_node; 246 247 if (OF_getencprop(sc->node, "reg", &sc->sw_addr, 248 sizeof(sc->sw_addr)) < 0) 249 return (ENXIO); 250 #else 251 if (resource_int_value(device_get_name(sc->dev), 252 device_get_unit(sc->dev), "addr", &sc->sw_addr) != 0) 253 return (ENXIO); 254 if (resource_int_value(device_get_name(sc->dev), 255 device_get_unit(sc->dev), "is6190", &is_6190) != 0) 256 /* 257 * Check "is8190" to keep backward compatibility with 258 * older setups. 259 */ 260 resource_int_value(device_get_name(sc->dev), 261 device_get_unit(sc->dev), "is8190", &is_6190); 262 if (is_6190 != 0) 263 sc->swid = MV88E6190; 264 #endif 265 if (sc->sw_addr < 0 || sc->sw_addr > 32) 266 return (ENXIO); 267 268 /* 269 * Create temporary lock, just to satisfy assertions, 270 * when obtaining the switch ID. Destroy immediately afterwards. 271 */ 272 sx_init(&sc->sx, "e6000sw_tmp"); 273 E6000SW_LOCK(sc); 274 sc->swid = e6000sw_readreg(sc, REG_PORT(sc, 0), SWITCH_ID) & 0xfff0; 275 E6000SW_UNLOCK(sc); 276 sx_destroy(&sc->sx); 277 278 switch (sc->swid) { 279 case MV88E6141: 280 description = "Marvell 88E6141"; 281 sc->phy_base = 0x10; 282 sc->num_ports = 6; 283 break; 284 case MV88E6341: 285 description = "Marvell 88E6341"; 286 sc->phy_base = 0x10; 287 sc->num_ports = 6; 288 break; 289 case MV88E6352: 290 description = "Marvell 88E6352"; 291 sc->num_ports = 7; 292 break; 293 case MV88E6172: 294 description = "Marvell 88E6172"; 295 sc->num_ports = 7; 296 break; 297 case MV88E6176: 298 description = "Marvell 88E6176"; 299 sc->num_ports = 7; 300 break; 301 case MV88E6190: 302 description = "Marvell 88E6190"; 303 sc->num_ports = 11; 304 break; 305 default: 306 device_printf(dev, "Unrecognized device, id 0x%x.\n", sc->swid); 307 return (ENXIO); 308 } 309 310 device_set_desc(dev, description); 311 312 return (BUS_PROBE_DEFAULT); 313 } 314 315 #ifdef FDT 316 static int 317 e6000sw_parse_fixed_link(e6000sw_softc_t *sc, phandle_t node, uint32_t port) 318 { 319 int speed; 320 phandle_t fixed_link; 321 322 fixed_link = ofw_bus_find_child(node, "fixed-link"); 323 324 if (fixed_link != 0) { 325 sc->fixed_mask |= (1 << port); 326 327 if (OF_getencprop(fixed_link, 328 "speed", &speed, sizeof(speed)) < 0) { 329 device_printf(sc->dev, 330 "Port %d has a fixed-link node without a speed " 331 "property\n", port); 332 return (ENXIO); 333 } 334 if (speed == 2500 && (MVSWITCH(sc, MV88E6141) || 335 MVSWITCH(sc, MV88E6341) || MVSWITCH(sc, MV88E6190))) 336 sc->fixed25_mask |= (1 << port); 337 } 338 339 return (0); 340 } 341 342 static int 343 e6000sw_parse_ethernet(e6000sw_softc_t *sc, phandle_t port_handle, uint32_t port) { 344 phandle_t switch_eth, switch_eth_handle; 345 346 if (OF_getencprop(port_handle, "ethernet", (void*)&switch_eth_handle, 347 sizeof(switch_eth_handle)) > 0) { 348 if (switch_eth_handle > 0) { 349 switch_eth = OF_node_from_xref(switch_eth_handle); 350 351 device_printf(sc->dev, "CPU port at %d\n", port); 352 sc->cpuports_mask |= (1 << port); 353 354 return (e6000sw_parse_fixed_link(sc, switch_eth, port)); 355 } else 356 device_printf(sc->dev, 357 "Port %d has ethernet property but it points " 358 "to an invalid location\n", port); 359 } 360 361 return (0); 362 } 363 364 static int 365 e6000sw_parse_child_fdt(e6000sw_softc_t *sc, phandle_t child, int *pport) 366 { 367 uint32_t port; 368 369 if (pport == NULL) 370 return (ENXIO); 371 372 if (OF_getencprop(child, "reg", (void *)&port, sizeof(port)) < 0) 373 return (ENXIO); 374 if (port >= sc->num_ports) 375 return (ENXIO); 376 *pport = port; 377 378 if (e6000sw_parse_fixed_link(sc, child, port) != 0) 379 return (ENXIO); 380 381 if (e6000sw_parse_ethernet(sc, child, port) != 0) 382 return (ENXIO); 383 384 if ((sc->fixed_mask & (1 << port)) != 0) 385 device_printf(sc->dev, "fixed port at %d\n", port); 386 else 387 device_printf(sc->dev, "PHY at port %d\n", port); 388 389 return (0); 390 } 391 #else 392 393 static int 394 e6000sw_check_hint_val(device_t dev, int *val, char *fmt, ...) 395 { 396 char *resname; 397 int err, len; 398 va_list ap; 399 400 len = min(strlen(fmt) * 2, 128); 401 if (len == 0) 402 return (-1); 403 resname = malloc(len, M_E6000SW, M_WAITOK); 404 memset(resname, 0, len); 405 va_start(ap, fmt); 406 vsnprintf(resname, len - 1, fmt, ap); 407 va_end(ap); 408 err = resource_int_value(device_get_name(dev), device_get_unit(dev), 409 resname, val); 410 free(resname, M_E6000SW); 411 412 return (err); 413 } 414 415 static int 416 e6000sw_parse_hinted_port(e6000sw_softc_t *sc, int port) 417 { 418 int err, val; 419 420 err = e6000sw_check_hint_val(sc->dev, &val, "port%ddisabled", port); 421 if (err == 0 && val != 0) 422 return (1); 423 424 err = e6000sw_check_hint_val(sc->dev, &val, "port%dcpu", port); 425 if (err == 0 && val != 0) { 426 sc->cpuports_mask |= (1 << port); 427 sc->fixed_mask |= (1 << port); 428 if (bootverbose) 429 device_printf(sc->dev, "CPU port at %d\n", port); 430 } 431 err = e6000sw_check_hint_val(sc->dev, &val, "port%dspeed", port); 432 if (err == 0 && val != 0) { 433 sc->fixed_mask |= (1 << port); 434 if (val == 2500) 435 sc->fixed25_mask |= (1 << port); 436 } 437 438 if (bootverbose) { 439 if ((sc->fixed_mask & (1 << port)) != 0) 440 device_printf(sc->dev, "fixed port at %d\n", port); 441 else 442 device_printf(sc->dev, "PHY at port %d\n", port); 443 } 444 445 return (0); 446 } 447 #endif 448 449 static int 450 e6000sw_init_interface(e6000sw_softc_t *sc, int port) 451 { 452 char name[IFNAMSIZ]; 453 454 snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(sc->dev)); 455 456 sc->ifp[port] = if_alloc(IFT_ETHER); 457 if_setsoftc(sc->ifp[port], sc); 458 if_setflagbits(sc->ifp[port], IFF_UP | IFF_BROADCAST | 459 IFF_DRV_RUNNING | IFF_SIMPLEX, 0); 460 sc->ifname[port] = malloc(strlen(name) + 1, M_E6000SW, M_NOWAIT); 461 if (sc->ifname[port] == NULL) { 462 if_free(sc->ifp[port]); 463 return (ENOMEM); 464 } 465 memcpy(sc->ifname[port], name, strlen(name) + 1); 466 if_initname(sc->ifp[port], sc->ifname[port], port); 467 468 return (0); 469 } 470 471 static int 472 e6000sw_attach_miibus(e6000sw_softc_t *sc, int port) 473 { 474 int err; 475 476 err = mii_attach(sc->dev, &sc->miibus[port], sc->ifp[port], 477 e6000sw_ifmedia_upd, e6000sw_ifmedia_sts, BMSR_DEFCAPMASK, 478 port + sc->phy_base, MII_OFFSET_ANY, 0); 479 if (err != 0) 480 return (err); 481 482 return (0); 483 } 484 485 static void 486 e6000sw_serdes_power(device_t dev, int port, bool sgmii) 487 { 488 uint32_t reg; 489 490 /* SGMII */ 491 reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV, 492 E6000SW_SERDES_SGMII_CTL); 493 if (sgmii) 494 reg &= ~E6000SW_SERDES_PDOWN; 495 else 496 reg |= E6000SW_SERDES_PDOWN; 497 e6000sw_write_xmdio(dev, port, E6000SW_SERDES_DEV, 498 E6000SW_SERDES_SGMII_CTL, reg); 499 500 /* 10GBASE-R/10GBASE-X4/X2 */ 501 reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV, 502 E6000SW_SERDES_PCS_CTL1); 503 if (sgmii) 504 reg |= E6000SW_SERDES_PDOWN; 505 else 506 reg &= ~E6000SW_SERDES_PDOWN; 507 e6000sw_write_xmdio(dev, port, E6000SW_SERDES_DEV, 508 E6000SW_SERDES_PCS_CTL1, reg); 509 } 510 511 static int 512 e6000sw_attach(device_t dev) 513 { 514 bool sgmii; 515 e6000sw_softc_t *sc; 516 #ifdef FDT 517 phandle_t child, ports; 518 #endif 519 int err, port; 520 uint32_t reg; 521 522 err = 0; 523 sc = device_get_softc(dev); 524 525 /* 526 * According to the Linux source code, all of the Switch IDs we support 527 * are multi_chip capable, and should go into multi-chip mode if the 528 * sw_addr != 0. 529 */ 530 if (MVSWITCH_MULTICHIP(sc)) 531 device_printf(dev, "multi-chip addressing mode (%#x)\n", 532 sc->sw_addr); 533 else 534 device_printf(dev, "single-chip addressing mode\n"); 535 536 sx_init(&sc->sx, "e6000sw"); 537 538 E6000SW_LOCK(sc); 539 e6000sw_setup(dev, sc); 540 541 sc->sc_tq = taskqueue_create("e6000sw_taskq", M_NOWAIT, 542 taskqueue_thread_enqueue, &sc->sc_tq); 543 544 TIMEOUT_TASK_INIT(sc->sc_tq, &sc->sc_tt, 0, e6000sw_tick, sc); 545 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 546 device_get_nameunit(dev)); 547 548 #ifdef FDT 549 ports = ofw_bus_find_child(sc->node, "ports"); 550 if (ports == 0) { 551 device_printf(dev, "failed to parse DTS: no ports found for " 552 "switch\n"); 553 E6000SW_UNLOCK(sc); 554 return (ENXIO); 555 } 556 557 for (child = OF_child(ports); child != 0; child = OF_peer(child)) { 558 err = e6000sw_parse_child_fdt(sc, child, &port); 559 if (err != 0) { 560 device_printf(sc->dev, "failed to parse DTS\n"); 561 goto out_fail; 562 } 563 #else 564 for (port = 0; port < sc->num_ports; port++) { 565 err = e6000sw_parse_hinted_port(sc, port); 566 if (err != 0) 567 continue; 568 #endif 569 570 /* Port is in use. */ 571 sc->ports_mask |= (1 << port); 572 573 err = e6000sw_init_interface(sc, port); 574 if (err != 0) { 575 device_printf(sc->dev, "failed to init interface\n"); 576 goto out_fail; 577 } 578 579 if (e6000sw_is_fixedport(sc, port)) { 580 /* Link must be down to change speed force value. */ 581 reg = e6000sw_readreg(sc, REG_PORT(sc, port), 582 PSC_CONTROL); 583 reg &= ~PSC_CONTROL_LINK_UP; 584 reg |= PSC_CONTROL_FORCED_LINK; 585 e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL, 586 reg); 587 588 /* 589 * Force speed, full-duplex, EEE off and flow-control 590 * on. 591 */ 592 reg &= ~(PSC_CONTROL_SPD2500 | PSC_CONTROL_ALT_SPD | 593 PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON | 594 PSC_CONTROL_FORCED_EEE); 595 if (e6000sw_is_fixed25port(sc, port)) 596 reg |= PSC_CONTROL_SPD2500; 597 else 598 reg |= PSC_CONTROL_SPD1000; 599 if (MVSWITCH(sc, MV88E6190) && 600 e6000sw_is_fixed25port(sc, port)) 601 reg |= PSC_CONTROL_ALT_SPD; 602 reg |= PSC_CONTROL_FORCED_DPX | PSC_CONTROL_FULLDPX | 603 PSC_CONTROL_FORCED_LINK | PSC_CONTROL_LINK_UP | 604 PSC_CONTROL_FORCED_SPD; 605 if (!MVSWITCH(sc, MV88E6190)) 606 reg |= PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON; 607 if (MVSWITCH(sc, MV88E6141) || 608 MVSWITCH(sc, MV88E6341) || 609 MVSWITCH(sc, MV88E6190)) 610 reg |= PSC_CONTROL_FORCED_EEE; 611 e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL, 612 reg); 613 /* Power on the SERDES interfaces. */ 614 if (MVSWITCH(sc, MV88E6190) && 615 (port == 9 || port == 10)) { 616 if (e6000sw_is_fixed25port(sc, port)) 617 sgmii = false; 618 else 619 sgmii = true; 620 e6000sw_serdes_power(sc->dev, port, sgmii); 621 } 622 } 623 624 /* Don't attach miibus at CPU/fixed ports */ 625 if (!e6000sw_is_phyport(sc, port)) 626 continue; 627 628 err = e6000sw_attach_miibus(sc, port); 629 if (err != 0) { 630 device_printf(sc->dev, "failed to attach miibus\n"); 631 goto out_fail; 632 } 633 } 634 635 etherswitch_info.es_nports = sc->num_ports; 636 637 /* Default to port vlan. */ 638 e6000sw_set_vlan_mode(sc, ETHERSWITCH_VLAN_PORT); 639 640 reg = e6000sw_readreg(sc, REG_GLOBAL, SWITCH_GLOBAL_STATUS); 641 if (reg & SWITCH_GLOBAL_STATUS_IR) 642 device_printf(dev, "switch is ready.\n"); 643 E6000SW_UNLOCK(sc); 644 645 bus_generic_probe(dev); 646 bus_generic_attach(dev); 647 648 taskqueue_enqueue_timeout(sc->sc_tq, &sc->sc_tt, hz); 649 650 return (0); 651 652 out_fail: 653 e6000sw_detach(dev); 654 655 return (err); 656 } 657 658 static int 659 e6000sw_waitready(e6000sw_softc_t *sc, uint32_t phy, uint32_t reg, 660 uint32_t busybit) 661 { 662 int i; 663 664 for (i = 0; i < E6000SW_RETRIES; i++) { 665 if ((e6000sw_readreg(sc, phy, reg) & busybit) == 0) 666 return (0); 667 DELAY(1); 668 } 669 670 return (1); 671 } 672 673 /* XMDIO/Clause 45 access. */ 674 static int 675 e6000sw_read_xmdio(device_t dev, int phy, int devaddr, int devreg) 676 { 677 e6000sw_softc_t *sc; 678 uint32_t reg; 679 680 sc = device_get_softc(dev); 681 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 682 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 683 device_printf(dev, "Timeout while waiting for switch\n"); 684 return (ETIMEDOUT); 685 } 686 687 reg = devaddr & SMI_CMD_REG_ADDR_MASK; 688 reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK; 689 690 /* Load C45 register address. */ 691 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 692 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 693 reg | SMI_CMD_OP_C45_ADDR); 694 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 695 device_printf(dev, "Timeout while waiting for switch\n"); 696 return (ETIMEDOUT); 697 } 698 699 /* Start C45 read operation. */ 700 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 701 reg | SMI_CMD_OP_C45_READ); 702 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 703 device_printf(dev, "Timeout while waiting for switch\n"); 704 return (ETIMEDOUT); 705 } 706 707 /* Read C45 data. */ 708 reg = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG); 709 710 return (reg & PHY_DATA_MASK); 711 } 712 713 static int 714 e6000sw_write_xmdio(device_t dev, int phy, int devaddr, int devreg, int val) 715 { 716 e6000sw_softc_t *sc; 717 uint32_t reg; 718 719 sc = device_get_softc(dev); 720 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 721 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 722 device_printf(dev, "Timeout while waiting for switch\n"); 723 return (ETIMEDOUT); 724 } 725 726 reg = devaddr & SMI_CMD_REG_ADDR_MASK; 727 reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK; 728 729 /* Load C45 register address. */ 730 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 731 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 732 reg | SMI_CMD_OP_C45_ADDR); 733 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 734 device_printf(dev, "Timeout while waiting for switch\n"); 735 return (ETIMEDOUT); 736 } 737 738 /* Load data and start the C45 write operation. */ 739 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 740 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 741 reg | SMI_CMD_OP_C45_WRITE); 742 743 return (0); 744 } 745 746 static int 747 e6000sw_readphy(device_t dev, int phy, int reg) 748 { 749 e6000sw_softc_t *sc; 750 int locked, ret; 751 752 sc = device_get_softc(dev); 753 754 locked = E6000SW_LOCKED(sc); 755 if (!locked) 756 E6000SW_LOCK(sc); 757 ret = e6000sw_readphy_locked(dev, phy, reg); 758 if (!locked) 759 E6000SW_UNLOCK(sc); 760 761 return (ret); 762 } 763 764 /* 765 * PHY registers are paged. Put page index in reg 22 (accessible from every 766 * page), then access specific register. 767 */ 768 static int 769 e6000sw_readphy_locked(device_t dev, int phy, int reg) 770 { 771 e6000sw_softc_t *sc; 772 uint32_t val; 773 774 sc = device_get_softc(dev); 775 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 776 777 if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) { 778 device_printf(dev, "Wrong register address.\n"); 779 return (EINVAL); 780 } 781 782 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 783 device_printf(dev, "Timeout while waiting for switch\n"); 784 return (ETIMEDOUT); 785 } 786 787 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 788 SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) | 789 ((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 790 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 791 device_printf(dev, "Timeout while waiting for switch\n"); 792 return (ETIMEDOUT); 793 } 794 795 val = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG); 796 797 return (val & PHY_DATA_MASK); 798 } 799 800 static int 801 e6000sw_writephy(device_t dev, int phy, int reg, int data) 802 { 803 e6000sw_softc_t *sc; 804 int locked, ret; 805 806 sc = device_get_softc(dev); 807 808 locked = E6000SW_LOCKED(sc); 809 if (!locked) 810 E6000SW_LOCK(sc); 811 ret = e6000sw_writephy_locked(dev, phy, reg, data); 812 if (!locked) 813 E6000SW_UNLOCK(sc); 814 815 return (ret); 816 } 817 818 static int 819 e6000sw_writephy_locked(device_t dev, int phy, int reg, int data) 820 { 821 e6000sw_softc_t *sc; 822 823 sc = device_get_softc(dev); 824 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 825 826 if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) { 827 device_printf(dev, "Wrong register address.\n"); 828 return (EINVAL); 829 } 830 831 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 832 device_printf(dev, "Timeout while waiting for switch\n"); 833 return (ETIMEDOUT); 834 } 835 836 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, 837 data & PHY_DATA_MASK); 838 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 839 SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) | 840 ((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 841 842 return (0); 843 } 844 845 static int 846 e6000sw_detach(device_t dev) 847 { 848 int phy; 849 e6000sw_softc_t *sc; 850 851 sc = device_get_softc(dev); 852 853 if (device_is_attached(dev)) 854 taskqueue_drain_timeout(sc->sc_tq, &sc->sc_tt); 855 856 if (sc->sc_tq != NULL) 857 taskqueue_free(sc->sc_tq); 858 859 device_delete_children(dev); 860 861 sx_destroy(&sc->sx); 862 for (phy = 0; phy < sc->num_ports; phy++) { 863 if (sc->ifp[phy] != NULL) 864 if_free(sc->ifp[phy]); 865 if (sc->ifname[phy] != NULL) 866 free(sc->ifname[phy], M_E6000SW); 867 } 868 869 return (0); 870 } 871 872 static etherswitch_info_t* 873 e6000sw_getinfo(device_t dev) 874 { 875 876 return (ðerswitch_info); 877 } 878 879 static int 880 e6000sw_getconf(device_t dev, etherswitch_conf_t *conf) 881 { 882 struct e6000sw_softc *sc; 883 884 /* Return the VLAN mode. */ 885 sc = device_get_softc(dev); 886 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 887 conf->vlan_mode = sc->vlan_mode; 888 889 return (0); 890 } 891 892 static int 893 e6000sw_setconf(device_t dev, etherswitch_conf_t *conf) 894 { 895 struct e6000sw_softc *sc; 896 897 /* Set the VLAN mode. */ 898 sc = device_get_softc(dev); 899 if (conf->cmd & ETHERSWITCH_CONF_VLAN_MODE) { 900 E6000SW_LOCK(sc); 901 e6000sw_set_vlan_mode(sc, conf->vlan_mode); 902 E6000SW_UNLOCK(sc); 903 } 904 905 return (0); 906 } 907 908 static void 909 e6000sw_lock(device_t dev) 910 { 911 struct e6000sw_softc *sc; 912 913 sc = device_get_softc(dev); 914 915 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 916 E6000SW_LOCK(sc); 917 } 918 919 static void 920 e6000sw_unlock(device_t dev) 921 { 922 struct e6000sw_softc *sc; 923 924 sc = device_get_softc(dev); 925 926 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 927 E6000SW_UNLOCK(sc); 928 } 929 930 static int 931 e6000sw_getport(device_t dev, etherswitch_port_t *p) 932 { 933 struct mii_data *mii; 934 int err; 935 struct ifmediareq *ifmr; 936 uint32_t reg; 937 938 e6000sw_softc_t *sc = device_get_softc(dev); 939 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 940 941 if (p->es_port >= sc->num_ports || p->es_port < 0) 942 return (EINVAL); 943 if (!e6000sw_is_portenabled(sc, p->es_port)) 944 return (0); 945 946 E6000SW_LOCK(sc); 947 e6000sw_get_pvid(sc, p->es_port, &p->es_pvid); 948 949 /* Port flags. */ 950 reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2); 951 if (reg & PORT_CONTROL2_DISC_TAGGED) 952 p->es_flags |= ETHERSWITCH_PORT_DROPTAGGED; 953 if (reg & PORT_CONTROL2_DISC_UNTAGGED) 954 p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED; 955 956 err = 0; 957 if (e6000sw_is_fixedport(sc, p->es_port)) { 958 if (e6000sw_is_cpuport(sc, p->es_port)) 959 p->es_flags |= ETHERSWITCH_PORT_CPU; 960 ifmr = &p->es_ifmr; 961 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 962 ifmr->ifm_count = 0; 963 if (e6000sw_is_fixed25port(sc, p->es_port)) 964 ifmr->ifm_active = IFM_2500_T; 965 else 966 ifmr->ifm_active = IFM_1000_T; 967 ifmr->ifm_active |= IFM_ETHER | IFM_FDX; 968 ifmr->ifm_current = ifmr->ifm_active; 969 ifmr->ifm_mask = 0; 970 } else { 971 mii = e6000sw_miiforphy(sc, p->es_port); 972 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, 973 &mii->mii_media, SIOCGIFMEDIA); 974 } 975 E6000SW_UNLOCK(sc); 976 977 return (err); 978 } 979 980 static int 981 e6000sw_setport(device_t dev, etherswitch_port_t *p) 982 { 983 e6000sw_softc_t *sc; 984 int err; 985 struct mii_data *mii; 986 uint32_t reg; 987 988 sc = device_get_softc(dev); 989 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 990 991 if (p->es_port >= sc->num_ports || p->es_port < 0) 992 return (EINVAL); 993 if (!e6000sw_is_portenabled(sc, p->es_port)) 994 return (0); 995 996 E6000SW_LOCK(sc); 997 998 /* Port flags. */ 999 reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2); 1000 if (p->es_flags & ETHERSWITCH_PORT_DROPTAGGED) 1001 reg |= PORT_CONTROL2_DISC_TAGGED; 1002 else 1003 reg &= ~PORT_CONTROL2_DISC_TAGGED; 1004 if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED) 1005 reg |= PORT_CONTROL2_DISC_UNTAGGED; 1006 else 1007 reg &= ~PORT_CONTROL2_DISC_UNTAGGED; 1008 e6000sw_writereg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2, reg); 1009 1010 err = 0; 1011 if (p->es_pvid != 0) 1012 e6000sw_set_pvid(sc, p->es_port, p->es_pvid); 1013 if (e6000sw_is_phyport(sc, p->es_port)) { 1014 mii = e6000sw_miiforphy(sc, p->es_port); 1015 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, &mii->mii_media, 1016 SIOCSIFMEDIA); 1017 } 1018 E6000SW_UNLOCK(sc); 1019 1020 return (err); 1021 } 1022 1023 static __inline void 1024 e6000sw_port_vlan_assign(e6000sw_softc_t *sc, int port, uint32_t fid, 1025 uint32_t members) 1026 { 1027 uint32_t reg; 1028 1029 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP); 1030 reg &= ~(PORT_MASK(sc) | PORT_VLAN_MAP_FID_MASK); 1031 reg |= members & PORT_MASK(sc) & ~(1 << port); 1032 reg |= (fid << PORT_VLAN_MAP_FID) & PORT_VLAN_MAP_FID_MASK; 1033 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VLAN_MAP, reg); 1034 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1); 1035 reg &= ~PORT_CONTROL1_FID_MASK; 1036 reg |= (fid >> 4) & PORT_CONTROL1_FID_MASK; 1037 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL1, reg); 1038 } 1039 1040 static int 1041 e6000sw_init_vlan(struct e6000sw_softc *sc) 1042 { 1043 int i, port, ret; 1044 uint32_t members; 1045 1046 /* Disable all ports */ 1047 for (port = 0; port < sc->num_ports; port++) { 1048 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 1049 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, 1050 (ret & ~PORT_CONTROL_ENABLE)); 1051 } 1052 1053 /* Flush VTU. */ 1054 e6000sw_vtu_flush(sc); 1055 1056 for (port = 0; port < sc->num_ports; port++) { 1057 /* Reset the egress and frame mode. */ 1058 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 1059 ret &= ~(PORT_CONTROL_EGRESS | PORT_CONTROL_FRAME); 1060 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, ret); 1061 1062 /* Set the 802.1q mode. */ 1063 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL2); 1064 ret &= ~PORT_CONTROL2_DOT1Q; 1065 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1066 ret |= PORT_CONTROL2_DOT1Q; 1067 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL2, ret); 1068 } 1069 1070 for (port = 0; port < sc->num_ports; port++) { 1071 if (!e6000sw_is_portenabled(sc, port)) 1072 continue; 1073 1074 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID); 1075 1076 /* Set port priority */ 1077 ret &= ~PORT_VID_PRIORITY_MASK; 1078 1079 /* Set VID map */ 1080 ret &= ~PORT_VID_DEF_VID_MASK; 1081 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1082 ret |= 1; 1083 else 1084 ret |= (port + 1); 1085 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, ret); 1086 } 1087 1088 /* Assign the member ports to each origin port. */ 1089 for (port = 0; port < sc->num_ports; port++) { 1090 members = 0; 1091 if (e6000sw_is_portenabled(sc, port)) { 1092 for (i = 0; i < sc->num_ports; i++) { 1093 if (i == port || !e6000sw_is_portenabled(sc, i)) 1094 continue; 1095 members |= (1 << i); 1096 } 1097 } 1098 /* Default to FID 0. */ 1099 e6000sw_port_vlan_assign(sc, port, 0, members); 1100 } 1101 1102 /* Reset internal VLAN table. */ 1103 for (i = 0; i < nitems(sc->vlans); i++) 1104 sc->vlans[i] = 0; 1105 1106 /* Create default VLAN (1). */ 1107 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 1108 sc->vlans[0] = 1; 1109 e6000sw_vtu_update(sc, 0, sc->vlans[0], 1, 0, sc->ports_mask); 1110 } 1111 1112 /* Enable all ports */ 1113 for (port = 0; port < sc->num_ports; port++) { 1114 if (!e6000sw_is_portenabled(sc, port)) 1115 continue; 1116 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 1117 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, 1118 (ret | PORT_CONTROL_ENABLE)); 1119 } 1120 1121 return (0); 1122 } 1123 1124 static int 1125 e6000sw_set_vlan_mode(struct e6000sw_softc *sc, uint32_t mode) 1126 { 1127 1128 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1129 switch (mode) { 1130 case ETHERSWITCH_VLAN_PORT: 1131 sc->vlan_mode = ETHERSWITCH_VLAN_PORT; 1132 etherswitch_info.es_nvlangroups = sc->num_ports; 1133 return (e6000sw_init_vlan(sc)); 1134 break; 1135 case ETHERSWITCH_VLAN_DOT1Q: 1136 sc->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 1137 etherswitch_info.es_nvlangroups = E6000SW_NUM_VLANS; 1138 return (e6000sw_init_vlan(sc)); 1139 break; 1140 default: 1141 return (EINVAL); 1142 } 1143 } 1144 1145 /* 1146 * Registers in this switch are divided into sections, specified in 1147 * documentation. So as to access any of them, section index and reg index 1148 * is necessary. etherswitchcfg uses only one variable, so indexes were 1149 * compressed into addr_reg: 32 * section_index + reg_index. 1150 */ 1151 static int 1152 e6000sw_readreg_wrapper(device_t dev, int addr_reg) 1153 { 1154 e6000sw_softc_t *sc; 1155 1156 sc = device_get_softc(dev); 1157 if ((addr_reg > (REG_GLOBAL2 * 32 + REG_NUM_MAX)) || 1158 (addr_reg < (REG_PORT(sc, 0) * 32))) { 1159 device_printf(dev, "Wrong register address.\n"); 1160 return (EINVAL); 1161 } 1162 1163 return (e6000sw_readreg(device_get_softc(dev), addr_reg / 32, 1164 addr_reg % 32)); 1165 } 1166 1167 static int 1168 e6000sw_writereg_wrapper(device_t dev, int addr_reg, int val) 1169 { 1170 e6000sw_softc_t *sc; 1171 1172 sc = device_get_softc(dev); 1173 if ((addr_reg > (REG_GLOBAL2 * 32 + REG_NUM_MAX)) || 1174 (addr_reg < (REG_PORT(sc, 0) * 32))) { 1175 device_printf(dev, "Wrong register address.\n"); 1176 return (EINVAL); 1177 } 1178 e6000sw_writereg(device_get_softc(dev), addr_reg / 32, 1179 addr_reg % 32, val); 1180 1181 return (0); 1182 } 1183 1184 /* 1185 * setvgroup/getvgroup called from etherswitchfcg need to be locked, 1186 * while internal calls do not. 1187 */ 1188 static int 1189 e6000sw_setvgroup_wrapper(device_t dev, etherswitch_vlangroup_t *vg) 1190 { 1191 e6000sw_softc_t *sc; 1192 int ret; 1193 1194 sc = device_get_softc(dev); 1195 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1196 1197 E6000SW_LOCK(sc); 1198 ret = e6000sw_setvgroup(dev, vg); 1199 E6000SW_UNLOCK(sc); 1200 1201 return (ret); 1202 } 1203 1204 static int 1205 e6000sw_getvgroup_wrapper(device_t dev, etherswitch_vlangroup_t *vg) 1206 { 1207 e6000sw_softc_t *sc; 1208 int ret; 1209 1210 sc = device_get_softc(dev); 1211 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1212 1213 E6000SW_LOCK(sc); 1214 ret = e6000sw_getvgroup(dev, vg); 1215 E6000SW_UNLOCK(sc); 1216 1217 return (ret); 1218 } 1219 1220 static int 1221 e6000sw_set_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1222 { 1223 uint32_t port; 1224 1225 port = vg->es_vlangroup; 1226 if (port > sc->num_ports) 1227 return (EINVAL); 1228 1229 if (vg->es_member_ports != vg->es_untagged_ports) { 1230 device_printf(sc->dev, "Tagged ports not supported.\n"); 1231 return (EINVAL); 1232 } 1233 1234 e6000sw_port_vlan_assign(sc, port, 0, vg->es_untagged_ports); 1235 vg->es_vid = port | ETHERSWITCH_VID_VALID; 1236 1237 return (0); 1238 } 1239 1240 static int 1241 e6000sw_set_dot1q_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1242 { 1243 int i, vlan; 1244 1245 vlan = vg->es_vid & ETHERSWITCH_VID_MASK; 1246 1247 /* Set VLAN to '0' removes it from table. */ 1248 if (vlan == 0) { 1249 e6000sw_vtu_update(sc, VTU_PURGE, 1250 sc->vlans[vg->es_vlangroup], 0, 0, 0); 1251 sc->vlans[vg->es_vlangroup] = 0; 1252 return (0); 1253 } 1254 1255 /* Is this VLAN already in table ? */ 1256 for (i = 0; i < etherswitch_info.es_nvlangroups; i++) 1257 if (i != vg->es_vlangroup && vlan == sc->vlans[i]) 1258 return (EINVAL); 1259 1260 sc->vlans[vg->es_vlangroup] = vlan; 1261 e6000sw_vtu_update(sc, 0, vlan, vg->es_vlangroup + 1, 1262 vg->es_member_ports & sc->ports_mask, 1263 vg->es_untagged_ports & sc->ports_mask); 1264 1265 return (0); 1266 } 1267 1268 static int 1269 e6000sw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 1270 { 1271 e6000sw_softc_t *sc; 1272 1273 sc = device_get_softc(dev); 1274 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1275 1276 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) 1277 return (e6000sw_set_port_vlan(sc, vg)); 1278 else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1279 return (e6000sw_set_dot1q_vlan(sc, vg)); 1280 1281 return (EINVAL); 1282 } 1283 1284 static int 1285 e6000sw_get_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1286 { 1287 uint32_t port, reg; 1288 1289 port = vg->es_vlangroup; 1290 if (port > sc->num_ports) 1291 return (EINVAL); 1292 1293 if (!e6000sw_is_portenabled(sc, port)) { 1294 vg->es_vid = port; 1295 return (0); 1296 } 1297 1298 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP); 1299 vg->es_untagged_ports = vg->es_member_ports = reg & PORT_MASK(sc); 1300 vg->es_vid = port | ETHERSWITCH_VID_VALID; 1301 vg->es_fid = (reg & PORT_VLAN_MAP_FID_MASK) >> PORT_VLAN_MAP_FID; 1302 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1); 1303 vg->es_fid |= (reg & PORT_CONTROL1_FID_MASK) << 4; 1304 1305 return (0); 1306 } 1307 1308 static int 1309 e6000sw_get_dot1q_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1310 { 1311 int i, port; 1312 uint32_t reg; 1313 1314 vg->es_fid = 0; 1315 vg->es_vid = sc->vlans[vg->es_vlangroup]; 1316 vg->es_untagged_ports = vg->es_member_ports = 0; 1317 if (vg->es_vid == 0) 1318 return (0); 1319 1320 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1321 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1322 return (EBUSY); 1323 } 1324 1325 e6000sw_writereg(sc, REG_GLOBAL, VTU_VID, vg->es_vid - 1); 1326 1327 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_OPERATION); 1328 reg &= ~VTU_OP_MASK; 1329 reg |= VTU_GET_NEXT | VTU_BUSY; 1330 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, reg); 1331 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1332 device_printf(sc->dev, "Timeout while reading\n"); 1333 return (EBUSY); 1334 } 1335 1336 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_VID); 1337 if (reg == VTU_VID_MASK || (reg & VTU_VID_VALID) == 0) 1338 return (EINVAL); 1339 if ((reg & VTU_VID_MASK) != vg->es_vid) 1340 return (EINVAL); 1341 1342 vg->es_vid |= ETHERSWITCH_VID_VALID; 1343 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA); 1344 for (i = 0; i < sc->num_ports; i++) { 1345 if (i == VTU_PPREG(sc)) 1346 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA2); 1347 port = (reg >> VTU_PORT(sc, i)) & VTU_PORT_MASK; 1348 if (port == VTU_PORT_UNTAGGED) { 1349 vg->es_untagged_ports |= (1 << i); 1350 vg->es_member_ports |= (1 << i); 1351 } else if (port == VTU_PORT_TAGGED) 1352 vg->es_member_ports |= (1 << i); 1353 } 1354 1355 return (0); 1356 } 1357 1358 static int 1359 e6000sw_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 1360 { 1361 e6000sw_softc_t *sc; 1362 1363 sc = device_get_softc(dev); 1364 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1365 1366 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) 1367 return (e6000sw_get_port_vlan(sc, vg)); 1368 else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1369 return (e6000sw_get_dot1q_vlan(sc, vg)); 1370 1371 return (EINVAL); 1372 } 1373 1374 static __inline struct mii_data* 1375 e6000sw_miiforphy(e6000sw_softc_t *sc, unsigned int phy) 1376 { 1377 1378 if (!e6000sw_is_phyport(sc, phy)) 1379 return (NULL); 1380 1381 return (device_get_softc(sc->miibus[phy])); 1382 } 1383 1384 static int 1385 e6000sw_ifmedia_upd(if_t ifp) 1386 { 1387 e6000sw_softc_t *sc; 1388 struct mii_data *mii; 1389 1390 sc = if_getsoftc(ifp); 1391 mii = e6000sw_miiforphy(sc, if_getdunit(ifp)); 1392 if (mii == NULL) 1393 return (ENXIO); 1394 mii_mediachg(mii); 1395 1396 return (0); 1397 } 1398 1399 static void 1400 e6000sw_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1401 { 1402 e6000sw_softc_t *sc; 1403 struct mii_data *mii; 1404 1405 sc = if_getsoftc(ifp); 1406 mii = e6000sw_miiforphy(sc, if_getdunit(ifp)); 1407 1408 if (mii == NULL) 1409 return; 1410 1411 mii_pollstat(mii); 1412 ifmr->ifm_active = mii->mii_media_active; 1413 ifmr->ifm_status = mii->mii_media_status; 1414 } 1415 1416 static int 1417 e6000sw_smi_waitready(e6000sw_softc_t *sc, int phy) 1418 { 1419 int i; 1420 1421 for (i = 0; i < E6000SW_SMI_TIMEOUT; i++) { 1422 if ((MDIO_READ(sc->dev, phy, SMI_CMD) & SMI_CMD_BUSY) == 0) 1423 return (0); 1424 DELAY(1); 1425 } 1426 1427 return (1); 1428 } 1429 1430 static __inline uint32_t 1431 e6000sw_readreg(e6000sw_softc_t *sc, int addr, int reg) 1432 { 1433 1434 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1435 1436 if (!MVSWITCH_MULTICHIP(sc)) 1437 return (MDIO_READ(sc->dev, addr, reg) & 0xffff); 1438 1439 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1440 printf("e6000sw: readreg timeout\n"); 1441 return (0xffff); 1442 } 1443 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_CMD, 1444 SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) | 1445 ((addr << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 1446 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1447 printf("e6000sw: readreg timeout\n"); 1448 return (0xffff); 1449 } 1450 1451 return (MDIO_READ(sc->dev, sc->sw_addr, SMI_DATA) & 0xffff); 1452 } 1453 1454 static __inline void 1455 e6000sw_writereg(e6000sw_softc_t *sc, int addr, int reg, int val) 1456 { 1457 1458 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1459 1460 if (!MVSWITCH_MULTICHIP(sc)) { 1461 MDIO_WRITE(sc->dev, addr, reg, val); 1462 return; 1463 } 1464 1465 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1466 printf("e6000sw: readreg timeout\n"); 1467 return; 1468 } 1469 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_DATA, val); 1470 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_CMD, 1471 SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) | 1472 ((addr << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 1473 } 1474 1475 static __inline bool 1476 e6000sw_is_cpuport(e6000sw_softc_t *sc, int port) 1477 { 1478 1479 return ((sc->cpuports_mask & (1 << port)) ? true : false); 1480 } 1481 1482 static __inline bool 1483 e6000sw_is_fixedport(e6000sw_softc_t *sc, int port) 1484 { 1485 1486 return ((sc->fixed_mask & (1 << port)) ? true : false); 1487 } 1488 1489 static __inline bool 1490 e6000sw_is_fixed25port(e6000sw_softc_t *sc, int port) 1491 { 1492 1493 return ((sc->fixed25_mask & (1 << port)) ? true : false); 1494 } 1495 1496 static __inline bool 1497 e6000sw_is_phyport(e6000sw_softc_t *sc, int port) 1498 { 1499 uint32_t phy_mask; 1500 phy_mask = ~(sc->fixed_mask | sc->cpuports_mask); 1501 1502 return ((phy_mask & (1 << port)) ? true : false); 1503 } 1504 1505 static __inline bool 1506 e6000sw_is_portenabled(e6000sw_softc_t *sc, int port) 1507 { 1508 1509 return ((sc->ports_mask & (1 << port)) ? true : false); 1510 } 1511 1512 static __inline void 1513 e6000sw_set_pvid(e6000sw_softc_t *sc, int port, int pvid) 1514 { 1515 uint32_t reg; 1516 1517 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID); 1518 reg &= ~PORT_VID_DEF_VID_MASK; 1519 reg |= (pvid & PORT_VID_DEF_VID_MASK); 1520 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, reg); 1521 } 1522 1523 static __inline int 1524 e6000sw_get_pvid(e6000sw_softc_t *sc, int port, int *pvid) 1525 { 1526 1527 if (pvid == NULL) 1528 return (ENXIO); 1529 1530 *pvid = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID) & 1531 PORT_VID_DEF_VID_MASK; 1532 1533 return (0); 1534 } 1535 1536 /* 1537 * Convert port status to ifmedia. 1538 */ 1539 static void 1540 e6000sw_update_ifmedia(uint16_t portstatus, u_int *media_status, u_int *media_active) 1541 { 1542 *media_active = IFM_ETHER; 1543 *media_status = IFM_AVALID; 1544 1545 if ((portstatus & PORT_STATUS_LINK_MASK) != 0) 1546 *media_status |= IFM_ACTIVE; 1547 else { 1548 *media_active |= IFM_NONE; 1549 return; 1550 } 1551 1552 switch (portstatus & PORT_STATUS_SPEED_MASK) { 1553 case PORT_STATUS_SPEED_10: 1554 *media_active |= IFM_10_T; 1555 break; 1556 case PORT_STATUS_SPEED_100: 1557 *media_active |= IFM_100_TX; 1558 break; 1559 case PORT_STATUS_SPEED_1000: 1560 *media_active |= IFM_1000_T; 1561 break; 1562 } 1563 1564 if ((portstatus & PORT_STATUS_DUPLEX_MASK) == 0) 1565 *media_active |= IFM_FDX; 1566 else 1567 *media_active |= IFM_HDX; 1568 } 1569 1570 static void 1571 e6000sw_tick(void *arg, int p __unused) 1572 { 1573 e6000sw_softc_t *sc; 1574 struct mii_data *mii; 1575 struct mii_softc *miisc; 1576 uint16_t portstatus; 1577 int port; 1578 1579 sc = arg; 1580 1581 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1582 1583 E6000SW_LOCK(sc); 1584 for (port = 0; port < sc->num_ports; port++) { 1585 /* Tick only on PHY ports */ 1586 if (!e6000sw_is_portenabled(sc, port) || 1587 !e6000sw_is_phyport(sc, port)) 1588 continue; 1589 1590 mii = e6000sw_miiforphy(sc, port); 1591 if (mii == NULL) 1592 continue; 1593 1594 portstatus = e6000sw_readreg(sc, REG_PORT(sc, port), 1595 PORT_STATUS); 1596 1597 e6000sw_update_ifmedia(portstatus, 1598 &mii->mii_media_status, &mii->mii_media_active); 1599 1600 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1601 if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) 1602 != miisc->mii_inst) 1603 continue; 1604 mii_phy_update(miisc, MII_POLLSTAT); 1605 } 1606 } 1607 E6000SW_UNLOCK(sc); 1608 } 1609 1610 static void 1611 e6000sw_setup(device_t dev, e6000sw_softc_t *sc) 1612 { 1613 uint32_t atu_ctrl; 1614 1615 /* Set aging time. */ 1616 atu_ctrl = e6000sw_readreg(sc, REG_GLOBAL, ATU_CONTROL); 1617 atu_ctrl &= ~ATU_CONTROL_AGETIME_MASK; 1618 atu_ctrl |= E6000SW_DEFAULT_AGETIME << ATU_CONTROL_AGETIME; 1619 e6000sw_writereg(sc, REG_GLOBAL, ATU_CONTROL, atu_ctrl); 1620 1621 /* Send all with specific mac address to cpu port */ 1622 e6000sw_writereg(sc, REG_GLOBAL2, MGMT_EN_2x, MGMT_EN_ALL); 1623 e6000sw_writereg(sc, REG_GLOBAL2, MGMT_EN_0x, MGMT_EN_ALL); 1624 1625 /* Disable Remote Management */ 1626 e6000sw_writereg(sc, REG_GLOBAL, SWITCH_GLOBAL_CONTROL2, 0); 1627 1628 /* Disable loopback filter and flow control messages */ 1629 e6000sw_writereg(sc, REG_GLOBAL2, SWITCH_MGMT, 1630 SWITCH_MGMT_PRI_MASK | 1631 (1 << SWITCH_MGMT_RSVD2CPU) | 1632 SWITCH_MGMT_FC_PRI_MASK | 1633 (1 << SWITCH_MGMT_FORCEFLOW)); 1634 1635 e6000sw_atu_flush(dev, sc, NO_OPERATION); 1636 e6000sw_atu_mac_table(dev, sc, NULL, NO_OPERATION); 1637 e6000sw_set_atustat(dev, sc, 0, COUNT_ALL); 1638 } 1639 1640 static void 1641 e6000sw_set_atustat(device_t dev, e6000sw_softc_t *sc, int bin, int flag) 1642 { 1643 1644 e6000sw_readreg(sc, REG_GLOBAL2, ATU_STATS); 1645 e6000sw_writereg(sc, REG_GLOBAL2, ATU_STATS, (bin << ATU_STATS_BIN ) | 1646 (flag << ATU_STATS_FLAG)); 1647 } 1648 1649 static int 1650 e6000sw_atu_mac_table(device_t dev, e6000sw_softc_t *sc, struct atu_opt *atu, 1651 int flag) 1652 { 1653 uint16_t ret_opt; 1654 uint16_t ret_data; 1655 1656 if (flag == NO_OPERATION) 1657 return (0); 1658 else if ((flag & (LOAD_FROM_FIB | PURGE_FROM_FIB | GET_NEXT_IN_FIB | 1659 GET_VIOLATION_DATA | CLEAR_VIOLATION_DATA)) == 0) { 1660 device_printf(dev, "Wrong Opcode for ATU operation\n"); 1661 return (EINVAL); 1662 } 1663 1664 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) { 1665 device_printf(dev, "ATU unit is busy, cannot access\n"); 1666 return (EBUSY); 1667 } 1668 1669 ret_opt = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION); 1670 if (flag & LOAD_FROM_FIB) { 1671 ret_data = e6000sw_readreg(sc, REG_GLOBAL, ATU_DATA); 1672 e6000sw_writereg(sc, REG_GLOBAL2, ATU_DATA, (ret_data & 1673 ~ENTRY_STATE)); 1674 } 1675 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR01, atu->mac_01); 1676 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR23, atu->mac_23); 1677 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR45, atu->mac_45); 1678 e6000sw_writereg(sc, REG_GLOBAL, ATU_FID, atu->fid); 1679 1680 e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION, 1681 (ret_opt | ATU_UNIT_BUSY | flag)); 1682 1683 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) 1684 device_printf(dev, "Timeout while waiting ATU\n"); 1685 else if (flag & GET_NEXT_IN_FIB) { 1686 atu->mac_01 = e6000sw_readreg(sc, REG_GLOBAL, 1687 ATU_MAC_ADDR01); 1688 atu->mac_23 = e6000sw_readreg(sc, REG_GLOBAL, 1689 ATU_MAC_ADDR23); 1690 atu->mac_45 = e6000sw_readreg(sc, REG_GLOBAL, 1691 ATU_MAC_ADDR45); 1692 } 1693 1694 return (0); 1695 } 1696 1697 static int 1698 e6000sw_atu_flush(device_t dev, e6000sw_softc_t *sc, int flag) 1699 { 1700 uint32_t reg; 1701 1702 if (flag == NO_OPERATION) 1703 return (0); 1704 1705 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) { 1706 device_printf(dev, "ATU unit is busy, cannot access\n"); 1707 return (EBUSY); 1708 } 1709 reg = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION); 1710 e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION, 1711 (reg | ATU_UNIT_BUSY | flag)); 1712 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) 1713 device_printf(dev, "Timeout while flushing ATU\n"); 1714 1715 return (0); 1716 } 1717 1718 static int 1719 e6000sw_vtu_flush(e6000sw_softc_t *sc) 1720 { 1721 1722 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1723 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1724 return (EBUSY); 1725 } 1726 1727 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, VTU_FLUSH | VTU_BUSY); 1728 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1729 device_printf(sc->dev, "Timeout while flushing VTU\n"); 1730 return (ETIMEDOUT); 1731 } 1732 1733 return (0); 1734 } 1735 1736 static int 1737 e6000sw_vtu_update(e6000sw_softc_t *sc, int purge, int vid, int fid, 1738 int members, int untagged) 1739 { 1740 int i, op; 1741 uint32_t data[2]; 1742 1743 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1744 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1745 return (EBUSY); 1746 } 1747 1748 *data = (vid & VTU_VID_MASK); 1749 if (purge == 0) 1750 *data |= VTU_VID_VALID; 1751 e6000sw_writereg(sc, REG_GLOBAL, VTU_VID, *data); 1752 1753 if (purge == 0) { 1754 data[0] = 0; 1755 data[1] = 0; 1756 for (i = 0; i < sc->num_ports; i++) { 1757 if ((untagged & (1 << i)) != 0) 1758 data[i / VTU_PPREG(sc)] |= 1759 VTU_PORT_UNTAGGED << VTU_PORT(sc, i); 1760 else if ((members & (1 << i)) != 0) 1761 data[i / VTU_PPREG(sc)] |= 1762 VTU_PORT_TAGGED << VTU_PORT(sc, i); 1763 else 1764 data[i / VTU_PPREG(sc)] |= 1765 VTU_PORT_DISCARD << VTU_PORT(sc, i); 1766 } 1767 e6000sw_writereg(sc, REG_GLOBAL, VTU_DATA, data[0]); 1768 e6000sw_writereg(sc, REG_GLOBAL, VTU_DATA2, data[1]); 1769 e6000sw_writereg(sc, REG_GLOBAL, VTU_FID, 1770 fid & VTU_FID_MASK(sc)); 1771 op = VTU_LOAD; 1772 } else 1773 op = VTU_PURGE; 1774 1775 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, op | VTU_BUSY); 1776 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1777 device_printf(sc->dev, "Timeout while flushing VTU\n"); 1778 return (ETIMEDOUT); 1779 } 1780 1781 return (0); 1782 } 1783