1 /******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #include "e1000_api.h"
36
37 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read, bool page_set);
40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
43
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_m88_cable_length_table) / \
49 sizeof(e1000_m88_cable_length_table[0]))
50
51 static const u16 e1000_igp_2_cable_length_table[] = {
52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
59 124};
60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
61 (sizeof(e1000_igp_2_cable_length_table) / \
62 sizeof(e1000_igp_2_cable_length_table[0]))
63
64 /**
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
66 * @hw: pointer to the HW structure
67 *
68 * Setups up the function pointers to no-op functions
69 **/
e1000_init_phy_ops_generic(struct e1000_hw * hw)70 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
71 {
72 struct e1000_phy_info *phy = &hw->phy;
73 DEBUGFUNC("e1000_init_phy_ops_generic");
74
75 /* Initialize function pointers */
76 phy->ops.init_params = e1000_null_ops_generic;
77 phy->ops.acquire = e1000_null_ops_generic;
78 phy->ops.check_polarity = e1000_null_ops_generic;
79 phy->ops.check_reset_block = e1000_null_ops_generic;
80 phy->ops.commit = e1000_null_ops_generic;
81 phy->ops.force_speed_duplex = e1000_null_ops_generic;
82 phy->ops.get_cfg_done = e1000_null_ops_generic;
83 phy->ops.get_cable_length = e1000_null_ops_generic;
84 phy->ops.get_info = e1000_null_ops_generic;
85 phy->ops.set_page = e1000_null_set_page;
86 phy->ops.read_reg = e1000_null_read_reg;
87 phy->ops.read_reg_locked = e1000_null_read_reg;
88 phy->ops.read_reg_page = e1000_null_read_reg;
89 phy->ops.release = e1000_null_phy_generic;
90 phy->ops.reset = e1000_null_ops_generic;
91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
93 phy->ops.write_reg = e1000_null_write_reg;
94 phy->ops.write_reg_locked = e1000_null_write_reg;
95 phy->ops.write_reg_page = e1000_null_write_reg;
96 phy->ops.power_up = e1000_null_phy_generic;
97 phy->ops.power_down = e1000_null_phy_generic;
98 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
99 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
100 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
101 }
102
103 /**
104 * e1000_null_set_page - No-op function, return 0
105 * @hw: pointer to the HW structure
106 **/
e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG * hw,u16 E1000_UNUSEDARG data)107 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
108 u16 E1000_UNUSEDARG data)
109 {
110 DEBUGFUNC("e1000_null_set_page");
111 return E1000_SUCCESS;
112 }
113
114 /**
115 * e1000_null_read_reg - No-op function, return 0
116 * @hw: pointer to the HW structure
117 **/
e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG * hw,u32 E1000_UNUSEDARG offset,u16 E1000_UNUSEDARG * data)118 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
119 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
120 {
121 DEBUGFUNC("e1000_null_read_reg");
122 return E1000_SUCCESS;
123 }
124
125 /**
126 * e1000_null_phy_generic - No-op function, return void
127 * @hw: pointer to the HW structure
128 **/
e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG * hw)129 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
130 {
131 DEBUGFUNC("e1000_null_phy_generic");
132 return;
133 }
134
135 /**
136 * e1000_null_lplu_state - No-op function, return 0
137 * @hw: pointer to the HW structure
138 **/
e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG * hw,bool E1000_UNUSEDARG active)139 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
140 bool E1000_UNUSEDARG active)
141 {
142 DEBUGFUNC("e1000_null_lplu_state");
143 return E1000_SUCCESS;
144 }
145
146 /**
147 * e1000_null_write_reg - No-op function, return 0
148 * @hw: pointer to the HW structure
149 **/
e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG * hw,u32 E1000_UNUSEDARG offset,u16 E1000_UNUSEDARG data)150 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
151 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
152 {
153 DEBUGFUNC("e1000_null_write_reg");
154 return E1000_SUCCESS;
155 }
156
157 /**
158 * e1000_read_i2c_byte_null - No-op function, return 0
159 * @hw: pointer to hardware structure
160 * @byte_offset: byte offset to write
161 * @dev_addr: device address
162 * @data: data value read
163 *
164 **/
e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG * hw,u8 E1000_UNUSEDARG byte_offset,u8 E1000_UNUSEDARG dev_addr,u8 E1000_UNUSEDARG * data)165 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
166 u8 E1000_UNUSEDARG byte_offset,
167 u8 E1000_UNUSEDARG dev_addr,
168 u8 E1000_UNUSEDARG *data)
169 {
170 DEBUGFUNC("e1000_read_i2c_byte_null");
171 return E1000_SUCCESS;
172 }
173
174 /**
175 * e1000_write_i2c_byte_null - No-op function, return 0
176 * @hw: pointer to hardware structure
177 * @byte_offset: byte offset to write
178 * @dev_addr: device address
179 * @data: data value to write
180 *
181 **/
e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG * hw,u8 E1000_UNUSEDARG byte_offset,u8 E1000_UNUSEDARG dev_addr,u8 E1000_UNUSEDARG data)182 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
183 u8 E1000_UNUSEDARG byte_offset,
184 u8 E1000_UNUSEDARG dev_addr,
185 u8 E1000_UNUSEDARG data)
186 {
187 DEBUGFUNC("e1000_write_i2c_byte_null");
188 return E1000_SUCCESS;
189 }
190
191 /**
192 * e1000_check_reset_block_generic - Check if PHY reset is blocked
193 * @hw: pointer to the HW structure
194 *
195 * Read the PHY management control register and check whether a PHY reset
196 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
197 * return E1000_BLK_PHY_RESET (12).
198 **/
e1000_check_reset_block_generic(struct e1000_hw * hw)199 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
200 {
201 u32 manc;
202
203 DEBUGFUNC("e1000_check_reset_block");
204
205 manc = E1000_READ_REG(hw, E1000_MANC);
206
207 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
208 E1000_BLK_PHY_RESET : E1000_SUCCESS;
209 }
210
211 /**
212 * e1000_get_phy_id - Retrieve the PHY ID and revision
213 * @hw: pointer to the HW structure
214 *
215 * Reads the PHY registers and stores the PHY ID and possibly the PHY
216 * revision in the hardware structure.
217 **/
e1000_get_phy_id(struct e1000_hw * hw)218 s32 e1000_get_phy_id(struct e1000_hw *hw)
219 {
220 struct e1000_phy_info *phy = &hw->phy;
221 s32 ret_val = E1000_SUCCESS;
222 u16 phy_id;
223 u16 retry_count = 0;
224
225 DEBUGFUNC("e1000_get_phy_id");
226
227 if (!phy->ops.read_reg)
228 return E1000_SUCCESS;
229
230 while (retry_count < 2) {
231 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
232 if (ret_val)
233 return ret_val;
234
235 phy->id = (u32)(phy_id << 16);
236 usec_delay(20);
237 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
238 if (ret_val)
239 return ret_val;
240
241 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
242 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
243
244 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
245 return E1000_SUCCESS;
246
247 retry_count++;
248 }
249
250 return E1000_SUCCESS;
251 }
252
253 /**
254 * e1000_phy_reset_dsp_generic - Reset PHY DSP
255 * @hw: pointer to the HW structure
256 *
257 * Reset the digital signal processor.
258 **/
e1000_phy_reset_dsp_generic(struct e1000_hw * hw)259 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
260 {
261 s32 ret_val;
262
263 DEBUGFUNC("e1000_phy_reset_dsp_generic");
264
265 if (!hw->phy.ops.write_reg)
266 return E1000_SUCCESS;
267
268 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
269 if (ret_val)
270 return ret_val;
271
272 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
273 }
274
275 /**
276 * e1000_read_phy_reg_mdic - Read MDI control register
277 * @hw: pointer to the HW structure
278 * @offset: register offset to be read
279 * @data: pointer to the read data
280 *
281 * Reads the MDI control register in the PHY at offset and stores the
282 * information read to data.
283 **/
e1000_read_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 * data)284 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
285 {
286 struct e1000_phy_info *phy = &hw->phy;
287 u32 i, mdic = 0;
288
289 DEBUGFUNC("e1000_read_phy_reg_mdic");
290
291 if (offset > MAX_PHY_REG_ADDRESS) {
292 DEBUGOUT1("PHY Address %d is out of range\n", offset);
293 return -E1000_ERR_PARAM;
294 }
295
296 /* Set up Op-code, Phy Address, and register offset in the MDI
297 * Control register. The MAC will take care of interfacing with the
298 * PHY to retrieve the desired data.
299 */
300 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
301 (phy->addr << E1000_MDIC_PHY_SHIFT) |
302 (E1000_MDIC_OP_READ));
303
304 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
305
306 /* Poll the ready bit to see if the MDI read completed
307 * Increasing the time out as testing showed failures with
308 * the lower time out
309 */
310 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
311 usec_delay_irq(50);
312 mdic = E1000_READ_REG(hw, E1000_MDIC);
313 if (mdic & E1000_MDIC_READY)
314 break;
315 }
316 if (!(mdic & E1000_MDIC_READY)) {
317 DEBUGOUT("MDI Read did not complete\n");
318 return -E1000_ERR_PHY;
319 }
320 if (mdic & E1000_MDIC_ERROR) {
321 DEBUGOUT("MDI Error\n");
322 return -E1000_ERR_PHY;
323 }
324 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
325 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
326 offset,
327 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
328 return -E1000_ERR_PHY;
329 }
330 *data = (u16) mdic;
331
332 /* Allow some time after each MDIC transaction to avoid
333 * reading duplicate data in the next MDIC transaction.
334 */
335 if (hw->mac.type == e1000_pch2lan)
336 usec_delay_irq(100);
337
338 return E1000_SUCCESS;
339 }
340
341 /**
342 * e1000_write_phy_reg_mdic - Write MDI control register
343 * @hw: pointer to the HW structure
344 * @offset: register offset to write to
345 * @data: data to write to register at offset
346 *
347 * Writes data to MDI control register in the PHY at offset.
348 **/
e1000_write_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 data)349 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
350 {
351 struct e1000_phy_info *phy = &hw->phy;
352 u32 i, mdic = 0;
353
354 DEBUGFUNC("e1000_write_phy_reg_mdic");
355
356 if (offset > MAX_PHY_REG_ADDRESS) {
357 DEBUGOUT1("PHY Address %d is out of range\n", offset);
358 return -E1000_ERR_PARAM;
359 }
360
361 /* Set up Op-code, Phy Address, and register offset in the MDI
362 * Control register. The MAC will take care of interfacing with the
363 * PHY to retrieve the desired data.
364 */
365 mdic = (((u32)data) |
366 (offset << E1000_MDIC_REG_SHIFT) |
367 (phy->addr << E1000_MDIC_PHY_SHIFT) |
368 (E1000_MDIC_OP_WRITE));
369
370 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
371
372 /* Poll the ready bit to see if the MDI read completed
373 * Increasing the time out as testing showed failures with
374 * the lower time out
375 */
376 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
377 usec_delay_irq(50);
378 mdic = E1000_READ_REG(hw, E1000_MDIC);
379 if (mdic & E1000_MDIC_READY)
380 break;
381 }
382 if (!(mdic & E1000_MDIC_READY)) {
383 DEBUGOUT("MDI Write did not complete\n");
384 return -E1000_ERR_PHY;
385 }
386 if (mdic & E1000_MDIC_ERROR) {
387 DEBUGOUT("MDI Error\n");
388 return -E1000_ERR_PHY;
389 }
390 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
391 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
392 offset,
393 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
394 return -E1000_ERR_PHY;
395 }
396
397 /* Allow some time after each MDIC transaction to avoid
398 * reading duplicate data in the next MDIC transaction.
399 */
400 if (hw->mac.type == e1000_pch2lan)
401 usec_delay_irq(100);
402
403 return E1000_SUCCESS;
404 }
405
406 /**
407 * e1000_read_phy_reg_i2c - Read PHY register using i2c
408 * @hw: pointer to the HW structure
409 * @offset: register offset to be read
410 * @data: pointer to the read data
411 *
412 * Reads the PHY register at offset using the i2c interface and stores the
413 * retrieved information in data.
414 **/
e1000_read_phy_reg_i2c(struct e1000_hw * hw,u32 offset,u16 * data)415 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
416 {
417 struct e1000_phy_info *phy = &hw->phy;
418 u32 i, i2ccmd = 0;
419
420 DEBUGFUNC("e1000_read_phy_reg_i2c");
421
422 /* Set up Op-code, Phy Address, and register address in the I2CCMD
423 * register. The MAC will take care of interfacing with the
424 * PHY to retrieve the desired data.
425 */
426 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
427 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
428 (E1000_I2CCMD_OPCODE_READ));
429
430 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
431
432 /* Poll the ready bit to see if the I2C read completed */
433 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
434 usec_delay(50);
435 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
436 if (i2ccmd & E1000_I2CCMD_READY)
437 break;
438 }
439 if (!(i2ccmd & E1000_I2CCMD_READY)) {
440 DEBUGOUT("I2CCMD Read did not complete\n");
441 return -E1000_ERR_PHY;
442 }
443 if (i2ccmd & E1000_I2CCMD_ERROR) {
444 DEBUGOUT("I2CCMD Error bit set\n");
445 return -E1000_ERR_PHY;
446 }
447
448 /* Need to byte-swap the 16-bit value. */
449 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
450
451 return E1000_SUCCESS;
452 }
453
454 /**
455 * e1000_write_phy_reg_i2c - Write PHY register using i2c
456 * @hw: pointer to the HW structure
457 * @offset: register offset to write to
458 * @data: data to write at register offset
459 *
460 * Writes the data to PHY register at the offset using the i2c interface.
461 **/
e1000_write_phy_reg_i2c(struct e1000_hw * hw,u32 offset,u16 data)462 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
463 {
464 struct e1000_phy_info *phy = &hw->phy;
465 u32 i, i2ccmd = 0;
466 u16 phy_data_swapped;
467
468 DEBUGFUNC("e1000_write_phy_reg_i2c");
469
470 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
471 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
472 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
473 hw->phy.addr);
474 return -E1000_ERR_CONFIG;
475 }
476
477 /* Swap the data bytes for the I2C interface */
478 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
479
480 /* Set up Op-code, Phy Address, and register address in the I2CCMD
481 * register. The MAC will take care of interfacing with the
482 * PHY to retrieve the desired data.
483 */
484 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
485 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
486 E1000_I2CCMD_OPCODE_WRITE |
487 phy_data_swapped);
488
489 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
490
491 /* Poll the ready bit to see if the I2C read completed */
492 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
493 usec_delay(50);
494 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
495 if (i2ccmd & E1000_I2CCMD_READY)
496 break;
497 }
498 if (!(i2ccmd & E1000_I2CCMD_READY)) {
499 DEBUGOUT("I2CCMD Write did not complete\n");
500 return -E1000_ERR_PHY;
501 }
502 if (i2ccmd & E1000_I2CCMD_ERROR) {
503 DEBUGOUT("I2CCMD Error bit set\n");
504 return -E1000_ERR_PHY;
505 }
506
507 return E1000_SUCCESS;
508 }
509
510 /**
511 * e1000_read_sfp_data_byte - Reads SFP module data.
512 * @hw: pointer to the HW structure
513 * @offset: byte location offset to be read
514 * @data: read data buffer pointer
515 *
516 * Reads one byte from SFP module data stored
517 * in SFP resided EEPROM memory or SFP diagnostic area.
518 * Function should be called with
519 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
520 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
521 * access
522 **/
e1000_read_sfp_data_byte(struct e1000_hw * hw,u16 offset,u8 * data)523 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
524 {
525 u32 i = 0;
526 u32 i2ccmd = 0;
527 u32 data_local = 0;
528
529 DEBUGFUNC("e1000_read_sfp_data_byte");
530
531 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
532 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
533 return -E1000_ERR_PHY;
534 }
535
536 /* Set up Op-code, EEPROM Address,in the I2CCMD
537 * register. The MAC will take care of interfacing with the
538 * EEPROM to retrieve the desired data.
539 */
540 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
541 E1000_I2CCMD_OPCODE_READ);
542
543 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
544
545 /* Poll the ready bit to see if the I2C read completed */
546 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
547 usec_delay(50);
548 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
549 if (data_local & E1000_I2CCMD_READY)
550 break;
551 }
552 if (!(data_local & E1000_I2CCMD_READY)) {
553 DEBUGOUT("I2CCMD Read did not complete\n");
554 return -E1000_ERR_PHY;
555 }
556 if (data_local & E1000_I2CCMD_ERROR) {
557 DEBUGOUT("I2CCMD Error bit set\n");
558 return -E1000_ERR_PHY;
559 }
560 *data = (u8) data_local & 0xFF;
561
562 return E1000_SUCCESS;
563 }
564
565 /**
566 * e1000_write_sfp_data_byte - Writes SFP module data.
567 * @hw: pointer to the HW structure
568 * @offset: byte location offset to write to
569 * @data: data to write
570 *
571 * Writes one byte to SFP module data stored
572 * in SFP resided EEPROM memory or SFP diagnostic area.
573 * Function should be called with
574 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
575 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
576 * access
577 **/
e1000_write_sfp_data_byte(struct e1000_hw * hw,u16 offset,u8 data)578 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
579 {
580 u32 i = 0;
581 u32 i2ccmd = 0;
582 u32 data_local = 0;
583
584 DEBUGFUNC("e1000_write_sfp_data_byte");
585
586 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
587 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
588 return -E1000_ERR_PHY;
589 }
590 /* The programming interface is 16 bits wide
591 * so we need to read the whole word first
592 * then update appropriate byte lane and write
593 * the updated word back.
594 */
595 /* Set up Op-code, EEPROM Address,in the I2CCMD
596 * register. The MAC will take care of interfacing
597 * with an EEPROM to write the data given.
598 */
599 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
600 E1000_I2CCMD_OPCODE_READ);
601 /* Set a command to read single word */
602 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
603 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
604 usec_delay(50);
605 /* Poll the ready bit to see if lastly
606 * launched I2C operation completed
607 */
608 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
609 if (i2ccmd & E1000_I2CCMD_READY) {
610 /* Check if this is READ or WRITE phase */
611 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
612 E1000_I2CCMD_OPCODE_READ) {
613 /* Write the selected byte
614 * lane and update whole word
615 */
616 data_local = i2ccmd & 0xFF00;
617 data_local |= data;
618 i2ccmd = ((offset <<
619 E1000_I2CCMD_REG_ADDR_SHIFT) |
620 E1000_I2CCMD_OPCODE_WRITE | data_local);
621 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
622 } else {
623 break;
624 }
625 }
626 }
627 if (!(i2ccmd & E1000_I2CCMD_READY)) {
628 DEBUGOUT("I2CCMD Write did not complete\n");
629 return -E1000_ERR_PHY;
630 }
631 if (i2ccmd & E1000_I2CCMD_ERROR) {
632 DEBUGOUT("I2CCMD Error bit set\n");
633 return -E1000_ERR_PHY;
634 }
635 return E1000_SUCCESS;
636 }
637
638 /**
639 * e1000_read_phy_reg_m88 - Read m88 PHY register
640 * @hw: pointer to the HW structure
641 * @offset: register offset to be read
642 * @data: pointer to the read data
643 *
644 * Acquires semaphore, if necessary, then reads the PHY register at offset
645 * and storing the retrieved information in data. Release any acquired
646 * semaphores before exiting.
647 **/
e1000_read_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 * data)648 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
649 {
650 s32 ret_val;
651
652 DEBUGFUNC("e1000_read_phy_reg_m88");
653
654 if (!hw->phy.ops.acquire)
655 return E1000_SUCCESS;
656
657 ret_val = hw->phy.ops.acquire(hw);
658 if (ret_val)
659 return ret_val;
660
661 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
662 data);
663
664 hw->phy.ops.release(hw);
665
666 return ret_val;
667 }
668
669 /**
670 * e1000_write_phy_reg_m88 - Write m88 PHY register
671 * @hw: pointer to the HW structure
672 * @offset: register offset to write to
673 * @data: data to write at register offset
674 *
675 * Acquires semaphore, if necessary, then writes the data to PHY register
676 * at the offset. Release any acquired semaphores before exiting.
677 **/
e1000_write_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 data)678 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
679 {
680 s32 ret_val;
681
682 DEBUGFUNC("e1000_write_phy_reg_m88");
683
684 if (!hw->phy.ops.acquire)
685 return E1000_SUCCESS;
686
687 ret_val = hw->phy.ops.acquire(hw);
688 if (ret_val)
689 return ret_val;
690
691 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
692 data);
693
694 hw->phy.ops.release(hw);
695
696 return ret_val;
697 }
698
699 /**
700 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
701 * @hw: pointer to the HW structure
702 * @page: page to set (shifted left when necessary)
703 *
704 * Sets PHY page required for PHY register access. Assumes semaphore is
705 * already acquired. Note, this function sets phy.addr to 1 so the caller
706 * must set it appropriately (if necessary) after this function returns.
707 **/
e1000_set_page_igp(struct e1000_hw * hw,u16 page)708 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
709 {
710 DEBUGFUNC("e1000_set_page_igp");
711
712 DEBUGOUT1("Setting page 0x%x\n", page);
713
714 hw->phy.addr = 1;
715
716 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
717 }
718
719 /**
720 * __e1000_read_phy_reg_igp - Read igp PHY register
721 * @hw: pointer to the HW structure
722 * @offset: register offset to be read
723 * @data: pointer to the read data
724 * @locked: semaphore has already been acquired or not
725 *
726 * Acquires semaphore, if necessary, then reads the PHY register at offset
727 * and stores the retrieved information in data. Release any acquired
728 * semaphores before exiting.
729 **/
__e1000_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)730 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
731 bool locked)
732 {
733 s32 ret_val = E1000_SUCCESS;
734
735 DEBUGFUNC("__e1000_read_phy_reg_igp");
736
737 if (!locked) {
738 if (!hw->phy.ops.acquire)
739 return E1000_SUCCESS;
740
741 ret_val = hw->phy.ops.acquire(hw);
742 if (ret_val)
743 return ret_val;
744 }
745
746 if (offset > MAX_PHY_MULTI_PAGE_REG)
747 ret_val = e1000_write_phy_reg_mdic(hw,
748 IGP01E1000_PHY_PAGE_SELECT,
749 (u16)offset);
750 if (!ret_val)
751 ret_val = e1000_read_phy_reg_mdic(hw,
752 MAX_PHY_REG_ADDRESS & offset,
753 data);
754 if (!locked)
755 hw->phy.ops.release(hw);
756
757 return ret_val;
758 }
759
760 /**
761 * e1000_read_phy_reg_igp - Read igp PHY register
762 * @hw: pointer to the HW structure
763 * @offset: register offset to be read
764 * @data: pointer to the read data
765 *
766 * Acquires semaphore then reads the PHY register at offset and stores the
767 * retrieved information in data.
768 * Release the acquired semaphore before exiting.
769 **/
e1000_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data)770 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
771 {
772 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE);
773 }
774
775 /**
776 * e1000_read_phy_reg_igp_locked - Read igp PHY register
777 * @hw: pointer to the HW structure
778 * @offset: register offset to be read
779 * @data: pointer to the read data
780 *
781 * Reads the PHY register at offset and stores the retrieved information
782 * in data. Assumes semaphore already acquired.
783 **/
e1000_read_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 * data)784 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
785 {
786 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE);
787 }
788
789 /**
790 * e1000_write_phy_reg_igp - Write igp PHY register
791 * @hw: pointer to the HW structure
792 * @offset: register offset to write to
793 * @data: data to write at register offset
794 * @locked: semaphore has already been acquired or not
795 *
796 * Acquires semaphore, if necessary, then writes the data to PHY register
797 * at the offset. Release any acquired semaphores before exiting.
798 **/
__e1000_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data,bool locked)799 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
800 bool locked)
801 {
802 s32 ret_val = E1000_SUCCESS;
803
804 DEBUGFUNC("e1000_write_phy_reg_igp");
805
806 if (!locked) {
807 if (!hw->phy.ops.acquire)
808 return E1000_SUCCESS;
809
810 ret_val = hw->phy.ops.acquire(hw);
811 if (ret_val)
812 return ret_val;
813 }
814
815 if (offset > MAX_PHY_MULTI_PAGE_REG)
816 ret_val = e1000_write_phy_reg_mdic(hw,
817 IGP01E1000_PHY_PAGE_SELECT,
818 (u16)offset);
819 if (!ret_val)
820 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
821 offset,
822 data);
823 if (!locked)
824 hw->phy.ops.release(hw);
825
826 return ret_val;
827 }
828
829 /**
830 * e1000_write_phy_reg_igp - Write igp PHY register
831 * @hw: pointer to the HW structure
832 * @offset: register offset to write to
833 * @data: data to write at register offset
834 *
835 * Acquires semaphore then writes the data to PHY register
836 * at the offset. Release any acquired semaphores before exiting.
837 **/
e1000_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data)838 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
839 {
840 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE);
841 }
842
843 /**
844 * e1000_write_phy_reg_igp_locked - Write igp PHY register
845 * @hw: pointer to the HW structure
846 * @offset: register offset to write to
847 * @data: data to write at register offset
848 *
849 * Writes the data to PHY register at the offset.
850 * Assumes semaphore already acquired.
851 **/
e1000_write_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 data)852 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
853 {
854 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE);
855 }
856
857 /**
858 * __e1000_read_kmrn_reg - Read kumeran register
859 * @hw: pointer to the HW structure
860 * @offset: register offset to be read
861 * @data: pointer to the read data
862 * @locked: semaphore has already been acquired or not
863 *
864 * Acquires semaphore, if necessary. Then reads the PHY register at offset
865 * using the kumeran interface. The information retrieved is stored in data.
866 * Release any acquired semaphores before exiting.
867 **/
__e1000_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)868 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
869 bool locked)
870 {
871 u32 kmrnctrlsta;
872
873 DEBUGFUNC("__e1000_read_kmrn_reg");
874
875 if (!locked) {
876 s32 ret_val = E1000_SUCCESS;
877
878 if (!hw->phy.ops.acquire)
879 return E1000_SUCCESS;
880
881 ret_val = hw->phy.ops.acquire(hw);
882 if (ret_val)
883 return ret_val;
884 }
885
886 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
887 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
888 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
889 E1000_WRITE_FLUSH(hw);
890
891 usec_delay(2);
892
893 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
894 *data = (u16)kmrnctrlsta;
895
896 if (!locked)
897 hw->phy.ops.release(hw);
898
899 return E1000_SUCCESS;
900 }
901
902 /**
903 * e1000_read_kmrn_reg_generic - Read kumeran register
904 * @hw: pointer to the HW structure
905 * @offset: register offset to be read
906 * @data: pointer to the read data
907 *
908 * Acquires semaphore then reads the PHY register at offset using the
909 * kumeran interface. The information retrieved is stored in data.
910 * Release the acquired semaphore before exiting.
911 **/
e1000_read_kmrn_reg_generic(struct e1000_hw * hw,u32 offset,u16 * data)912 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
913 {
914 return __e1000_read_kmrn_reg(hw, offset, data, FALSE);
915 }
916
917 /**
918 * e1000_read_kmrn_reg_locked - Read kumeran register
919 * @hw: pointer to the HW structure
920 * @offset: register offset to be read
921 * @data: pointer to the read data
922 *
923 * Reads the PHY register at offset using the kumeran interface. The
924 * information retrieved is stored in data.
925 * Assumes semaphore already acquired.
926 **/
e1000_read_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 * data)927 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
928 {
929 return __e1000_read_kmrn_reg(hw, offset, data, TRUE);
930 }
931
932 /**
933 * __e1000_write_kmrn_reg - Write kumeran register
934 * @hw: pointer to the HW structure
935 * @offset: register offset to write to
936 * @data: data to write at register offset
937 * @locked: semaphore has already been acquired or not
938 *
939 * Acquires semaphore, if necessary. Then write the data to PHY register
940 * at the offset using the kumeran interface. Release any acquired semaphores
941 * before exiting.
942 **/
__e1000_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data,bool locked)943 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
944 bool locked)
945 {
946 u32 kmrnctrlsta;
947
948 DEBUGFUNC("e1000_write_kmrn_reg_generic");
949
950 if (!locked) {
951 s32 ret_val = E1000_SUCCESS;
952
953 if (!hw->phy.ops.acquire)
954 return E1000_SUCCESS;
955
956 ret_val = hw->phy.ops.acquire(hw);
957 if (ret_val)
958 return ret_val;
959 }
960
961 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
962 E1000_KMRNCTRLSTA_OFFSET) | data;
963 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
964 E1000_WRITE_FLUSH(hw);
965
966 usec_delay(2);
967
968 if (!locked)
969 hw->phy.ops.release(hw);
970
971 return E1000_SUCCESS;
972 }
973
974 /**
975 * e1000_write_kmrn_reg_generic - Write kumeran register
976 * @hw: pointer to the HW structure
977 * @offset: register offset to write to
978 * @data: data to write at register offset
979 *
980 * Acquires semaphore then writes the data to the PHY register at the offset
981 * using the kumeran interface. Release the acquired semaphore before exiting.
982 **/
e1000_write_kmrn_reg_generic(struct e1000_hw * hw,u32 offset,u16 data)983 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
984 {
985 return __e1000_write_kmrn_reg(hw, offset, data, FALSE);
986 }
987
988 /**
989 * e1000_write_kmrn_reg_locked - Write kumeran register
990 * @hw: pointer to the HW structure
991 * @offset: register offset to write to
992 * @data: data to write at register offset
993 *
994 * Write the data to PHY register at the offset using the kumeran interface.
995 * Assumes semaphore already acquired.
996 **/
e1000_write_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 data)997 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
998 {
999 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
1000 }
1001
1002 /**
1003 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
1004 * @hw: pointer to the HW structure
1005 *
1006 * Sets up Master/slave mode
1007 **/
e1000_set_master_slave_mode(struct e1000_hw * hw)1008 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1009 {
1010 s32 ret_val;
1011 u16 phy_data;
1012
1013 /* Resolve Master/Slave mode */
1014 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1015 if (ret_val)
1016 return ret_val;
1017
1018 /* load defaults for future use */
1019 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1020 ((phy_data & CR_1000T_MS_VALUE) ?
1021 e1000_ms_force_master :
1022 e1000_ms_force_slave) : e1000_ms_auto;
1023
1024 switch (hw->phy.ms_type) {
1025 case e1000_ms_force_master:
1026 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1027 break;
1028 case e1000_ms_force_slave:
1029 phy_data |= CR_1000T_MS_ENABLE;
1030 phy_data &= ~(CR_1000T_MS_VALUE);
1031 break;
1032 case e1000_ms_auto:
1033 phy_data &= ~CR_1000T_MS_ENABLE;
1034 /* fall-through */
1035 default:
1036 break;
1037 }
1038
1039 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1040 }
1041
1042 /**
1043 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1044 * @hw: pointer to the HW structure
1045 *
1046 * Sets up Carrier-sense on Transmit and downshift values.
1047 **/
e1000_copper_link_setup_82577(struct e1000_hw * hw)1048 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1049 {
1050 s32 ret_val;
1051 u16 phy_data;
1052
1053 DEBUGFUNC("e1000_copper_link_setup_82577");
1054
1055 if (hw->phy.type == e1000_phy_82580) {
1056 ret_val = hw->phy.ops.reset(hw);
1057 if (ret_val) {
1058 DEBUGOUT("Error resetting the PHY.\n");
1059 return ret_val;
1060 }
1061 }
1062
1063 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1064 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1065 if (ret_val)
1066 return ret_val;
1067
1068 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1069
1070 /* Enable downshift */
1071 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1072
1073 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1074 if (ret_val)
1075 return ret_val;
1076
1077 /* Set MDI/MDIX mode */
1078 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1079 if (ret_val)
1080 return ret_val;
1081 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1082 /* Options:
1083 * 0 - Auto (default)
1084 * 1 - MDI mode
1085 * 2 - MDI-X mode
1086 */
1087 switch (hw->phy.mdix) {
1088 case 1:
1089 break;
1090 case 2:
1091 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1092 break;
1093 case 0:
1094 default:
1095 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1096 break;
1097 }
1098 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1099 if (ret_val)
1100 return ret_val;
1101
1102 return e1000_set_master_slave_mode(hw);
1103 }
1104
1105 /**
1106 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1107 * @hw: pointer to the HW structure
1108 *
1109 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1110 * and downshift values are set also.
1111 **/
e1000_copper_link_setup_m88(struct e1000_hw * hw)1112 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1113 {
1114 struct e1000_phy_info *phy = &hw->phy;
1115 s32 ret_val;
1116 u16 phy_data;
1117
1118 DEBUGFUNC("e1000_copper_link_setup_m88");
1119
1120
1121 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1122 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1123 if (ret_val)
1124 return ret_val;
1125
1126 /* For BM PHY this bit is downshift enable */
1127 if (phy->type != e1000_phy_bm)
1128 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1129
1130 /* Options:
1131 * MDI/MDI-X = 0 (default)
1132 * 0 - Auto for all speeds
1133 * 1 - MDI mode
1134 * 2 - MDI-X mode
1135 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1136 */
1137 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1138
1139 switch (phy->mdix) {
1140 case 1:
1141 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1142 break;
1143 case 2:
1144 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1145 break;
1146 case 3:
1147 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1148 break;
1149 case 0:
1150 default:
1151 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1152 break;
1153 }
1154
1155 /* Options:
1156 * disable_polarity_correction = 0 (default)
1157 * Automatic Correction for Reversed Cable Polarity
1158 * 0 - Disabled
1159 * 1 - Enabled
1160 */
1161 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1162 if (phy->disable_polarity_correction)
1163 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1164
1165 /* Enable downshift on BM (disabled by default) */
1166 if (phy->type == e1000_phy_bm) {
1167 /* For 82574/82583, first disable then enable downshift */
1168 if (phy->id == BME1000_E_PHY_ID_R2) {
1169 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1170 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1171 phy_data);
1172 if (ret_val)
1173 return ret_val;
1174 /* Commit the changes. */
1175 ret_val = phy->ops.commit(hw);
1176 if (ret_val) {
1177 DEBUGOUT("Error committing the PHY changes\n");
1178 return ret_val;
1179 }
1180 }
1181
1182 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1183 }
1184
1185 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1186 if (ret_val)
1187 return ret_val;
1188
1189 if ((phy->type == e1000_phy_m88) &&
1190 (phy->revision < E1000_REVISION_4) &&
1191 (phy->id != BME1000_E_PHY_ID_R2)) {
1192 /* Force TX_CLK in the Extended PHY Specific Control Register
1193 * to 25MHz clock.
1194 */
1195 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1196 &phy_data);
1197 if (ret_val)
1198 return ret_val;
1199
1200 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1201
1202 if ((phy->revision == E1000_REVISION_2) &&
1203 (phy->id == M88E1111_I_PHY_ID)) {
1204 /* 82573L PHY - set the downshift counter to 5x. */
1205 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1206 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1207 } else {
1208 /* Configure Master and Slave downshift values */
1209 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1210 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1211 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1212 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1213 }
1214 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1215 phy_data);
1216 if (ret_val)
1217 return ret_val;
1218 }
1219
1220 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1221 /* Set PHY page 0, register 29 to 0x0003 */
1222 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1223 if (ret_val)
1224 return ret_val;
1225
1226 /* Set PHY page 0, register 30 to 0x0000 */
1227 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1228 if (ret_val)
1229 return ret_val;
1230 }
1231
1232 /* Commit the changes. */
1233 ret_val = phy->ops.commit(hw);
1234 if (ret_val) {
1235 DEBUGOUT("Error committing the PHY changes\n");
1236 return ret_val;
1237 }
1238
1239 if (phy->type == e1000_phy_82578) {
1240 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1241 &phy_data);
1242 if (ret_val)
1243 return ret_val;
1244
1245 /* 82578 PHY - set the downshift count to 1x. */
1246 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1247 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1248 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1249 phy_data);
1250 if (ret_val)
1251 return ret_val;
1252 }
1253
1254 return E1000_SUCCESS;
1255 }
1256
1257 /**
1258 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1259 * @hw: pointer to the HW structure
1260 *
1261 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1262 * Also enables and sets the downshift parameters.
1263 **/
e1000_copper_link_setup_m88_gen2(struct e1000_hw * hw)1264 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1265 {
1266 struct e1000_phy_info *phy = &hw->phy;
1267 s32 ret_val;
1268 u16 phy_data;
1269
1270 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1271
1272
1273 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1274 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1275 if (ret_val)
1276 return ret_val;
1277
1278 /* Options:
1279 * MDI/MDI-X = 0 (default)
1280 * 0 - Auto for all speeds
1281 * 1 - MDI mode
1282 * 2 - MDI-X mode
1283 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1284 */
1285 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1286
1287 switch (phy->mdix) {
1288 case 1:
1289 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1290 break;
1291 case 2:
1292 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1293 break;
1294 case 3:
1295 /* M88E1112 does not support this mode) */
1296 if (phy->id != M88E1112_E_PHY_ID) {
1297 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1298 break;
1299 }
1300 case 0:
1301 default:
1302 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1303 break;
1304 }
1305
1306 /* Options:
1307 * disable_polarity_correction = 0 (default)
1308 * Automatic Correction for Reversed Cable Polarity
1309 * 0 - Disabled
1310 * 1 - Enabled
1311 */
1312 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1313 if (phy->disable_polarity_correction)
1314 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1315
1316 /* Enable downshift and setting it to X6 */
1317 if (phy->id == M88E1543_E_PHY_ID) {
1318 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1319 ret_val =
1320 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1321 if (ret_val)
1322 return ret_val;
1323
1324 ret_val = phy->ops.commit(hw);
1325 if (ret_val) {
1326 DEBUGOUT("Error committing the PHY changes\n");
1327 return ret_val;
1328 }
1329 }
1330
1331 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1332 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1333 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1334
1335 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1336 if (ret_val)
1337 return ret_val;
1338
1339 /* Commit the changes. */
1340 ret_val = phy->ops.commit(hw);
1341 if (ret_val) {
1342 DEBUGOUT("Error committing the PHY changes\n");
1343 return ret_val;
1344 }
1345
1346 ret_val = e1000_set_master_slave_mode(hw);
1347 if (ret_val)
1348 return ret_val;
1349
1350 return E1000_SUCCESS;
1351 }
1352
1353 /**
1354 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1355 * @hw: pointer to the HW structure
1356 *
1357 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1358 * igp PHY's.
1359 **/
e1000_copper_link_setup_igp(struct e1000_hw * hw)1360 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1361 {
1362 struct e1000_phy_info *phy = &hw->phy;
1363 s32 ret_val;
1364 u16 data;
1365
1366 DEBUGFUNC("e1000_copper_link_setup_igp");
1367
1368
1369 ret_val = hw->phy.ops.reset(hw);
1370 if (ret_val) {
1371 DEBUGOUT("Error resetting the PHY.\n");
1372 return ret_val;
1373 }
1374
1375 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1376 * timeout issues when LFS is enabled.
1377 */
1378 msec_delay(100);
1379
1380 /* The NVM settings will configure LPLU in D3 for
1381 * non-IGP1 PHYs.
1382 */
1383 if (phy->type == e1000_phy_igp) {
1384 /* disable lplu d3 during driver init */
1385 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
1386 if (ret_val) {
1387 DEBUGOUT("Error Disabling LPLU D3\n");
1388 return ret_val;
1389 }
1390 }
1391
1392 /* disable lplu d0 during driver init */
1393 if (hw->phy.ops.set_d0_lplu_state) {
1394 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1395 if (ret_val) {
1396 DEBUGOUT("Error Disabling LPLU D0\n");
1397 return ret_val;
1398 }
1399 }
1400 /* Configure mdi-mdix settings */
1401 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1402 if (ret_val)
1403 return ret_val;
1404
1405 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1406
1407 switch (phy->mdix) {
1408 case 1:
1409 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1410 break;
1411 case 2:
1412 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1413 break;
1414 case 0:
1415 default:
1416 data |= IGP01E1000_PSCR_AUTO_MDIX;
1417 break;
1418 }
1419 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1420 if (ret_val)
1421 return ret_val;
1422
1423 /* set auto-master slave resolution settings */
1424 if (hw->mac.autoneg) {
1425 /* when autonegotiation advertisement is only 1000Mbps then we
1426 * should disable SmartSpeed and enable Auto MasterSlave
1427 * resolution as hardware default.
1428 */
1429 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1430 /* Disable SmartSpeed */
1431 ret_val = phy->ops.read_reg(hw,
1432 IGP01E1000_PHY_PORT_CONFIG,
1433 &data);
1434 if (ret_val)
1435 return ret_val;
1436
1437 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1438 ret_val = phy->ops.write_reg(hw,
1439 IGP01E1000_PHY_PORT_CONFIG,
1440 data);
1441 if (ret_val)
1442 return ret_val;
1443
1444 /* Set auto Master/Slave resolution process */
1445 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1446 if (ret_val)
1447 return ret_val;
1448
1449 data &= ~CR_1000T_MS_ENABLE;
1450 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1451 if (ret_val)
1452 return ret_val;
1453 }
1454
1455 ret_val = e1000_set_master_slave_mode(hw);
1456 }
1457
1458 return ret_val;
1459 }
1460
1461 /**
1462 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1463 * @hw: pointer to the HW structure
1464 *
1465 * Reads the MII auto-neg advertisement register and/or the 1000T control
1466 * register and if the PHY is already setup for auto-negotiation, then
1467 * return successful. Otherwise, setup advertisement and flow control to
1468 * the appropriate values for the wanted auto-negotiation.
1469 **/
e1000_phy_setup_autoneg(struct e1000_hw * hw)1470 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1471 {
1472 struct e1000_phy_info *phy = &hw->phy;
1473 s32 ret_val;
1474 u16 mii_autoneg_adv_reg;
1475 u16 mii_1000t_ctrl_reg = 0;
1476
1477 DEBUGFUNC("e1000_phy_setup_autoneg");
1478
1479 phy->autoneg_advertised &= phy->autoneg_mask;
1480
1481 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1482 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1483 if (ret_val)
1484 return ret_val;
1485
1486 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1487 /* Read the MII 1000Base-T Control Register (Address 9). */
1488 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1489 &mii_1000t_ctrl_reg);
1490 if (ret_val)
1491 return ret_val;
1492 }
1493
1494 /* Need to parse both autoneg_advertised and fc and set up
1495 * the appropriate PHY registers. First we will parse for
1496 * autoneg_advertised software override. Since we can advertise
1497 * a plethora of combinations, we need to check each bit
1498 * individually.
1499 */
1500
1501 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1502 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1503 * the 1000Base-T Control Register (Address 9).
1504 */
1505 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1506 NWAY_AR_100TX_HD_CAPS |
1507 NWAY_AR_10T_FD_CAPS |
1508 NWAY_AR_10T_HD_CAPS);
1509 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1510
1511 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1512
1513 /* Do we want to advertise 10 Mb Half Duplex? */
1514 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1515 DEBUGOUT("Advertise 10mb Half duplex\n");
1516 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1517 }
1518
1519 /* Do we want to advertise 10 Mb Full Duplex? */
1520 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1521 DEBUGOUT("Advertise 10mb Full duplex\n");
1522 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1523 }
1524
1525 /* Do we want to advertise 100 Mb Half Duplex? */
1526 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1527 DEBUGOUT("Advertise 100mb Half duplex\n");
1528 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1529 }
1530
1531 /* Do we want to advertise 100 Mb Full Duplex? */
1532 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1533 DEBUGOUT("Advertise 100mb Full duplex\n");
1534 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1535 }
1536
1537 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1538 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1539 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1540
1541 /* Do we want to advertise 1000 Mb Full Duplex? */
1542 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1543 DEBUGOUT("Advertise 1000mb Full duplex\n");
1544 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1545 }
1546
1547 /* Check for a software override of the flow control settings, and
1548 * setup the PHY advertisement registers accordingly. If
1549 * auto-negotiation is enabled, then software will have to set the
1550 * "PAUSE" bits to the correct value in the Auto-Negotiation
1551 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1552 * negotiation.
1553 *
1554 * The possible values of the "fc" parameter are:
1555 * 0: Flow control is completely disabled
1556 * 1: Rx flow control is enabled (we can receive pause frames
1557 * but not send pause frames).
1558 * 2: Tx flow control is enabled (we can send pause frames
1559 * but we do not support receiving pause frames).
1560 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1561 * other: No software override. The flow control configuration
1562 * in the EEPROM is used.
1563 */
1564 switch (hw->fc.current_mode) {
1565 case e1000_fc_none:
1566 /* Flow control (Rx & Tx) is completely disabled by a
1567 * software over-ride.
1568 */
1569 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1570 break;
1571 case e1000_fc_rx_pause:
1572 /* Rx Flow control is enabled, and Tx Flow control is
1573 * disabled, by a software over-ride.
1574 *
1575 * Since there really isn't a way to advertise that we are
1576 * capable of Rx Pause ONLY, we will advertise that we
1577 * support both symmetric and asymmetric Rx PAUSE. Later
1578 * (in e1000_config_fc_after_link_up) we will disable the
1579 * hw's ability to send PAUSE frames.
1580 */
1581 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1582 break;
1583 case e1000_fc_tx_pause:
1584 /* Tx Flow control is enabled, and Rx Flow control is
1585 * disabled, by a software over-ride.
1586 */
1587 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1588 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1589 break;
1590 case e1000_fc_full:
1591 /* Flow control (both Rx and Tx) is enabled by a software
1592 * over-ride.
1593 */
1594 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1595 break;
1596 default:
1597 DEBUGOUT("Flow control param set incorrectly\n");
1598 return -E1000_ERR_CONFIG;
1599 }
1600
1601 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1602 if (ret_val)
1603 return ret_val;
1604
1605 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1606
1607 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1608 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1609 mii_1000t_ctrl_reg);
1610
1611 return ret_val;
1612 }
1613
1614 /**
1615 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1616 * @hw: pointer to the HW structure
1617 *
1618 * Performs initial bounds checking on autoneg advertisement parameter, then
1619 * configure to advertise the full capability. Setup the PHY to autoneg
1620 * and restart the negotiation process between the link partner. If
1621 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1622 **/
e1000_copper_link_autoneg(struct e1000_hw * hw)1623 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1624 {
1625 struct e1000_phy_info *phy = &hw->phy;
1626 s32 ret_val;
1627 u16 phy_ctrl;
1628
1629 DEBUGFUNC("e1000_copper_link_autoneg");
1630
1631 /* Perform some bounds checking on the autoneg advertisement
1632 * parameter.
1633 */
1634 phy->autoneg_advertised &= phy->autoneg_mask;
1635
1636 /* If autoneg_advertised is zero, we assume it was not defaulted
1637 * by the calling code so we set to advertise full capability.
1638 */
1639 if (!phy->autoneg_advertised)
1640 phy->autoneg_advertised = phy->autoneg_mask;
1641
1642 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1643 ret_val = e1000_phy_setup_autoneg(hw);
1644 if (ret_val) {
1645 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1646 return ret_val;
1647 }
1648 DEBUGOUT("Restarting Auto-Neg\n");
1649
1650 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1651 * the Auto Neg Restart bit in the PHY control register.
1652 */
1653 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1654 if (ret_val)
1655 return ret_val;
1656
1657 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1658 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1659 if (ret_val)
1660 return ret_val;
1661
1662 /* Does the user want to wait for Auto-Neg to complete here, or
1663 * check at a later time (for example, callback routine).
1664 */
1665 if (phy->autoneg_wait_to_complete) {
1666 ret_val = e1000_wait_autoneg(hw);
1667 if (ret_val) {
1668 DEBUGOUT("Error while waiting for autoneg to complete\n");
1669 return ret_val;
1670 }
1671 }
1672
1673 hw->mac.get_link_status = TRUE;
1674
1675 return ret_val;
1676 }
1677
1678 /**
1679 * e1000_setup_copper_link_generic - Configure copper link settings
1680 * @hw: pointer to the HW structure
1681 *
1682 * Calls the appropriate function to configure the link for auto-neg or forced
1683 * speed and duplex. Then we check for link, once link is established calls
1684 * to configure collision distance and flow control are called. If link is
1685 * not established, we return -E1000_ERR_PHY (-2).
1686 **/
e1000_setup_copper_link_generic(struct e1000_hw * hw)1687 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1688 {
1689 s32 ret_val;
1690 bool link;
1691
1692 DEBUGFUNC("e1000_setup_copper_link_generic");
1693
1694 if (hw->mac.autoneg) {
1695 /* Setup autoneg and flow control advertisement and perform
1696 * autonegotiation.
1697 */
1698 ret_val = e1000_copper_link_autoneg(hw);
1699 if (ret_val)
1700 return ret_val;
1701 } else {
1702 /* PHY will be set to 10H, 10F, 100H or 100F
1703 * depending on user settings.
1704 */
1705 DEBUGOUT("Forcing Speed and Duplex\n");
1706 ret_val = hw->phy.ops.force_speed_duplex(hw);
1707 if (ret_val) {
1708 DEBUGOUT("Error Forcing Speed and Duplex\n");
1709 return ret_val;
1710 }
1711 }
1712
1713 /* Check link status. Wait up to 100 microseconds for link to become
1714 * valid.
1715 */
1716 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1717 &link);
1718 if (ret_val)
1719 return ret_val;
1720
1721 if (link) {
1722 DEBUGOUT("Valid link established!!!\n");
1723 hw->mac.ops.config_collision_dist(hw);
1724 ret_val = e1000_config_fc_after_link_up_generic(hw);
1725 } else {
1726 DEBUGOUT("Unable to establish link!!!\n");
1727 }
1728
1729 return ret_val;
1730 }
1731
1732 /**
1733 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1734 * @hw: pointer to the HW structure
1735 *
1736 * Calls the PHY setup function to force speed and duplex. Clears the
1737 * auto-crossover to force MDI manually. Waits for link and returns
1738 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1739 **/
e1000_phy_force_speed_duplex_igp(struct e1000_hw * hw)1740 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1741 {
1742 struct e1000_phy_info *phy = &hw->phy;
1743 s32 ret_val;
1744 u16 phy_data;
1745 bool link;
1746
1747 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1748
1749 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1750 if (ret_val)
1751 return ret_val;
1752
1753 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1754
1755 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1756 if (ret_val)
1757 return ret_val;
1758
1759 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1760 * forced whenever speed and duplex are forced.
1761 */
1762 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1763 if (ret_val)
1764 return ret_val;
1765
1766 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1767 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1768
1769 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1770 if (ret_val)
1771 return ret_val;
1772
1773 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1774
1775 usec_delay(1);
1776
1777 if (phy->autoneg_wait_to_complete) {
1778 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1779
1780 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1781 100000, &link);
1782 if (ret_val)
1783 return ret_val;
1784
1785 if (!link)
1786 DEBUGOUT("Link taking longer than expected.\n");
1787
1788 /* Try once more */
1789 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1790 100000, &link);
1791 }
1792
1793 return ret_val;
1794 }
1795
1796 /**
1797 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1798 * @hw: pointer to the HW structure
1799 *
1800 * Calls the PHY setup function to force speed and duplex. Clears the
1801 * auto-crossover to force MDI manually. Resets the PHY to commit the
1802 * changes. If time expires while waiting for link up, we reset the DSP.
1803 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1804 * successful completion, else return corresponding error code.
1805 **/
e1000_phy_force_speed_duplex_m88(struct e1000_hw * hw)1806 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1807 {
1808 struct e1000_phy_info *phy = &hw->phy;
1809 s32 ret_val;
1810 u16 phy_data;
1811 bool link;
1812
1813 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1814
1815 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1816 if (phy->type != e1000_phy_i210) {
1817 /* Clear Auto-Crossover to force MDI manually. M88E1000
1818 * requires MDI forced whenever speed and duplex are forced.
1819 */
1820 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1821 &phy_data);
1822 if (ret_val)
1823 return ret_val;
1824
1825 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1826 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1827 phy_data);
1828 if (ret_val)
1829 return ret_val;
1830
1831 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1832 }
1833
1834 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1835 if (ret_val)
1836 return ret_val;
1837
1838 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1839
1840 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1841 if (ret_val)
1842 return ret_val;
1843
1844 /* Reset the phy to commit changes. */
1845 ret_val = hw->phy.ops.commit(hw);
1846 if (ret_val)
1847 return ret_val;
1848
1849 if (phy->autoneg_wait_to_complete) {
1850 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1851
1852 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1853 100000, &link);
1854 if (ret_val)
1855 return ret_val;
1856
1857 if (!link) {
1858 bool reset_dsp = TRUE;
1859
1860 switch (hw->phy.id) {
1861 case I347AT4_E_PHY_ID:
1862 case M88E1340M_E_PHY_ID:
1863 case M88E1112_E_PHY_ID:
1864 case M88E1543_E_PHY_ID:
1865 case M88E1512_E_PHY_ID:
1866 case I210_I_PHY_ID:
1867 reset_dsp = FALSE;
1868 break;
1869 default:
1870 if (hw->phy.type != e1000_phy_m88)
1871 reset_dsp = FALSE;
1872 break;
1873 }
1874
1875 if (!reset_dsp) {
1876 DEBUGOUT("Link taking longer than expected.\n");
1877 } else {
1878 /* We didn't get link.
1879 * Reset the DSP and cross our fingers.
1880 */
1881 ret_val = phy->ops.write_reg(hw,
1882 M88E1000_PHY_PAGE_SELECT,
1883 0x001d);
1884 if (ret_val)
1885 return ret_val;
1886 ret_val = e1000_phy_reset_dsp_generic(hw);
1887 if (ret_val)
1888 return ret_val;
1889 }
1890 }
1891
1892 /* Try once more */
1893 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1894 100000, &link);
1895 if (ret_val)
1896 return ret_val;
1897 }
1898
1899 if (hw->phy.type != e1000_phy_m88)
1900 return E1000_SUCCESS;
1901
1902 if (hw->phy.id == I347AT4_E_PHY_ID ||
1903 hw->phy.id == M88E1340M_E_PHY_ID ||
1904 hw->phy.id == M88E1112_E_PHY_ID)
1905 return E1000_SUCCESS;
1906 if (hw->phy.id == I210_I_PHY_ID)
1907 return E1000_SUCCESS;
1908 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1909 (hw->phy.id == M88E1512_E_PHY_ID))
1910 return E1000_SUCCESS;
1911 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1912 if (ret_val)
1913 return ret_val;
1914
1915 /* Resetting the phy means we need to re-force TX_CLK in the
1916 * Extended PHY Specific Control Register to 25MHz clock from
1917 * the reset value of 2.5MHz.
1918 */
1919 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1920 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1921 if (ret_val)
1922 return ret_val;
1923
1924 /* In addition, we must re-enable CRS on Tx for both half and full
1925 * duplex.
1926 */
1927 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1928 if (ret_val)
1929 return ret_val;
1930
1931 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1932 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1933
1934 return ret_val;
1935 }
1936
1937 /**
1938 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1939 * @hw: pointer to the HW structure
1940 *
1941 * Forces the speed and duplex settings of the PHY.
1942 * This is a function pointer entry point only called by
1943 * PHY setup routines.
1944 **/
e1000_phy_force_speed_duplex_ife(struct e1000_hw * hw)1945 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1946 {
1947 struct e1000_phy_info *phy = &hw->phy;
1948 s32 ret_val;
1949 u16 data;
1950 bool link;
1951
1952 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1953
1954 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1955 if (ret_val)
1956 return ret_val;
1957
1958 e1000_phy_force_speed_duplex_setup(hw, &data);
1959
1960 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1961 if (ret_val)
1962 return ret_val;
1963
1964 /* Disable MDI-X support for 10/100 */
1965 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1966 if (ret_val)
1967 return ret_val;
1968
1969 data &= ~IFE_PMC_AUTO_MDIX;
1970 data &= ~IFE_PMC_FORCE_MDIX;
1971
1972 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1973 if (ret_val)
1974 return ret_val;
1975
1976 DEBUGOUT1("IFE PMC: %X\n", data);
1977
1978 usec_delay(1);
1979
1980 if (phy->autoneg_wait_to_complete) {
1981 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1982
1983 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1984 100000, &link);
1985 if (ret_val)
1986 return ret_val;
1987
1988 if (!link)
1989 DEBUGOUT("Link taking longer than expected.\n");
1990
1991 /* Try once more */
1992 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1993 100000, &link);
1994 if (ret_val)
1995 return ret_val;
1996 }
1997
1998 return E1000_SUCCESS;
1999 }
2000
2001 /**
2002 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
2003 * @hw: pointer to the HW structure
2004 * @phy_ctrl: pointer to current value of PHY_CONTROL
2005 *
2006 * Forces speed and duplex on the PHY by doing the following: disable flow
2007 * control, force speed/duplex on the MAC, disable auto speed detection,
2008 * disable auto-negotiation, configure duplex, configure speed, configure
2009 * the collision distance, write configuration to CTRL register. The
2010 * caller must write to the PHY_CONTROL register for these settings to
2011 * take affect.
2012 **/
e1000_phy_force_speed_duplex_setup(struct e1000_hw * hw,u16 * phy_ctrl)2013 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
2014 {
2015 struct e1000_mac_info *mac = &hw->mac;
2016 u32 ctrl;
2017
2018 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
2019
2020 /* Turn off flow control when forcing speed/duplex */
2021 hw->fc.current_mode = e1000_fc_none;
2022
2023 /* Force speed/duplex on the mac */
2024 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2025 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2026 ctrl &= ~E1000_CTRL_SPD_SEL;
2027
2028 /* Disable Auto Speed Detection */
2029 ctrl &= ~E1000_CTRL_ASDE;
2030
2031 /* Disable autoneg on the phy */
2032 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2033
2034 /* Forcing Full or Half Duplex? */
2035 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2036 ctrl &= ~E1000_CTRL_FD;
2037 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2038 DEBUGOUT("Half Duplex\n");
2039 } else {
2040 ctrl |= E1000_CTRL_FD;
2041 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2042 DEBUGOUT("Full Duplex\n");
2043 }
2044
2045 /* Forcing 10mb or 100mb? */
2046 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2047 ctrl |= E1000_CTRL_SPD_100;
2048 *phy_ctrl |= MII_CR_SPEED_100;
2049 *phy_ctrl &= ~MII_CR_SPEED_1000;
2050 DEBUGOUT("Forcing 100mb\n");
2051 } else {
2052 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2053 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2054 DEBUGOUT("Forcing 10mb\n");
2055 }
2056
2057 hw->mac.ops.config_collision_dist(hw);
2058
2059 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2060 }
2061
2062 /**
2063 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2064 * @hw: pointer to the HW structure
2065 * @active: boolean used to enable/disable lplu
2066 *
2067 * Success returns 0, Failure returns 1
2068 *
2069 * The low power link up (lplu) state is set to the power management level D3
2070 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
2071 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2072 * is used during Dx states where the power conservation is most important.
2073 * During driver activity, SmartSpeed should be enabled so performance is
2074 * maintained.
2075 **/
e1000_set_d3_lplu_state_generic(struct e1000_hw * hw,bool active)2076 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2077 {
2078 struct e1000_phy_info *phy = &hw->phy;
2079 s32 ret_val;
2080 u16 data;
2081
2082 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2083
2084 if (!hw->phy.ops.read_reg)
2085 return E1000_SUCCESS;
2086
2087 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2088 if (ret_val)
2089 return ret_val;
2090
2091 if (!active) {
2092 data &= ~IGP02E1000_PM_D3_LPLU;
2093 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2094 data);
2095 if (ret_val)
2096 return ret_val;
2097 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2098 * during Dx states where the power conservation is most
2099 * important. During driver activity we should enable
2100 * SmartSpeed, so performance is maintained.
2101 */
2102 if (phy->smart_speed == e1000_smart_speed_on) {
2103 ret_val = phy->ops.read_reg(hw,
2104 IGP01E1000_PHY_PORT_CONFIG,
2105 &data);
2106 if (ret_val)
2107 return ret_val;
2108
2109 data |= IGP01E1000_PSCFR_SMART_SPEED;
2110 ret_val = phy->ops.write_reg(hw,
2111 IGP01E1000_PHY_PORT_CONFIG,
2112 data);
2113 if (ret_val)
2114 return ret_val;
2115 } else if (phy->smart_speed == e1000_smart_speed_off) {
2116 ret_val = phy->ops.read_reg(hw,
2117 IGP01E1000_PHY_PORT_CONFIG,
2118 &data);
2119 if (ret_val)
2120 return ret_val;
2121
2122 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2123 ret_val = phy->ops.write_reg(hw,
2124 IGP01E1000_PHY_PORT_CONFIG,
2125 data);
2126 if (ret_val)
2127 return ret_val;
2128 }
2129 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2130 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2131 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2132 data |= IGP02E1000_PM_D3_LPLU;
2133 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2134 data);
2135 if (ret_val)
2136 return ret_val;
2137
2138 /* When LPLU is enabled, we should disable SmartSpeed */
2139 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2140 &data);
2141 if (ret_val)
2142 return ret_val;
2143
2144 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2145 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2146 data);
2147 }
2148
2149 return ret_val;
2150 }
2151
2152 /**
2153 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2154 * @hw: pointer to the HW structure
2155 *
2156 * Success returns 0, Failure returns 1
2157 *
2158 * A downshift is detected by querying the PHY link health.
2159 **/
e1000_check_downshift_generic(struct e1000_hw * hw)2160 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2161 {
2162 struct e1000_phy_info *phy = &hw->phy;
2163 s32 ret_val;
2164 u16 phy_data, offset, mask;
2165
2166 DEBUGFUNC("e1000_check_downshift_generic");
2167
2168 switch (phy->type) {
2169 case e1000_phy_i210:
2170 case e1000_phy_m88:
2171 case e1000_phy_gg82563:
2172 case e1000_phy_bm:
2173 case e1000_phy_82578:
2174 offset = M88E1000_PHY_SPEC_STATUS;
2175 mask = M88E1000_PSSR_DOWNSHIFT;
2176 break;
2177 case e1000_phy_igp:
2178 case e1000_phy_igp_2:
2179 case e1000_phy_igp_3:
2180 offset = IGP01E1000_PHY_LINK_HEALTH;
2181 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2182 break;
2183 default:
2184 /* speed downshift not supported */
2185 phy->speed_downgraded = FALSE;
2186 return E1000_SUCCESS;
2187 }
2188
2189 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2190
2191 if (!ret_val)
2192 phy->speed_downgraded = !!(phy_data & mask);
2193
2194 return ret_val;
2195 }
2196
2197 /**
2198 * e1000_check_polarity_m88 - Checks the polarity.
2199 * @hw: pointer to the HW structure
2200 *
2201 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2202 *
2203 * Polarity is determined based on the PHY specific status register.
2204 **/
e1000_check_polarity_m88(struct e1000_hw * hw)2205 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2206 {
2207 struct e1000_phy_info *phy = &hw->phy;
2208 s32 ret_val;
2209 u16 data;
2210
2211 DEBUGFUNC("e1000_check_polarity_m88");
2212
2213 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2214
2215 if (!ret_val)
2216 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2217 ? e1000_rev_polarity_reversed
2218 : e1000_rev_polarity_normal);
2219
2220 return ret_val;
2221 }
2222
2223 /**
2224 * e1000_check_polarity_igp - Checks the polarity.
2225 * @hw: pointer to the HW structure
2226 *
2227 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2228 *
2229 * Polarity is determined based on the PHY port status register, and the
2230 * current speed (since there is no polarity at 100Mbps).
2231 **/
e1000_check_polarity_igp(struct e1000_hw * hw)2232 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2233 {
2234 struct e1000_phy_info *phy = &hw->phy;
2235 s32 ret_val;
2236 u16 data, offset, mask;
2237
2238 DEBUGFUNC("e1000_check_polarity_igp");
2239
2240 /* Polarity is determined based on the speed of
2241 * our connection.
2242 */
2243 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2244 if (ret_val)
2245 return ret_val;
2246
2247 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2248 IGP01E1000_PSSR_SPEED_1000MBPS) {
2249 offset = IGP01E1000_PHY_PCS_INIT_REG;
2250 mask = IGP01E1000_PHY_POLARITY_MASK;
2251 } else {
2252 /* This really only applies to 10Mbps since
2253 * there is no polarity for 100Mbps (always 0).
2254 */
2255 offset = IGP01E1000_PHY_PORT_STATUS;
2256 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2257 }
2258
2259 ret_val = phy->ops.read_reg(hw, offset, &data);
2260
2261 if (!ret_val)
2262 phy->cable_polarity = ((data & mask)
2263 ? e1000_rev_polarity_reversed
2264 : e1000_rev_polarity_normal);
2265
2266 return ret_val;
2267 }
2268
2269 /**
2270 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2271 * @hw: pointer to the HW structure
2272 *
2273 * Polarity is determined on the polarity reversal feature being enabled.
2274 **/
e1000_check_polarity_ife(struct e1000_hw * hw)2275 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2276 {
2277 struct e1000_phy_info *phy = &hw->phy;
2278 s32 ret_val;
2279 u16 phy_data, offset, mask;
2280
2281 DEBUGFUNC("e1000_check_polarity_ife");
2282
2283 /* Polarity is determined based on the reversal feature being enabled.
2284 */
2285 if (phy->polarity_correction) {
2286 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2287 mask = IFE_PESC_POLARITY_REVERSED;
2288 } else {
2289 offset = IFE_PHY_SPECIAL_CONTROL;
2290 mask = IFE_PSC_FORCE_POLARITY;
2291 }
2292
2293 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2294
2295 if (!ret_val)
2296 phy->cable_polarity = ((phy_data & mask)
2297 ? e1000_rev_polarity_reversed
2298 : e1000_rev_polarity_normal);
2299
2300 return ret_val;
2301 }
2302
2303 /**
2304 * e1000_wait_autoneg - Wait for auto-neg completion
2305 * @hw: pointer to the HW structure
2306 *
2307 * Waits for auto-negotiation to complete or for the auto-negotiation time
2308 * limit to expire, which ever happens first.
2309 **/
e1000_wait_autoneg(struct e1000_hw * hw)2310 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2311 {
2312 s32 ret_val = E1000_SUCCESS;
2313 u16 i, phy_status;
2314
2315 DEBUGFUNC("e1000_wait_autoneg");
2316
2317 if (!hw->phy.ops.read_reg)
2318 return E1000_SUCCESS;
2319
2320 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2321 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2322 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2323 if (ret_val)
2324 break;
2325 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2326 if (ret_val)
2327 break;
2328 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2329 break;
2330 msec_delay(100);
2331 }
2332
2333 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2334 * has completed.
2335 */
2336 return ret_val;
2337 }
2338
2339 /**
2340 * e1000_phy_has_link_generic - Polls PHY for link
2341 * @hw: pointer to the HW structure
2342 * @iterations: number of times to poll for link
2343 * @usec_interval: delay between polling attempts
2344 * @success: pointer to whether polling was successful or not
2345 *
2346 * Polls the PHY status register for link, 'iterations' number of times.
2347 **/
e1000_phy_has_link_generic(struct e1000_hw * hw,u32 iterations,u32 usec_interval,bool * success)2348 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2349 u32 usec_interval, bool *success)
2350 {
2351 s32 ret_val = E1000_SUCCESS;
2352 u16 i, phy_status;
2353
2354 DEBUGFUNC("e1000_phy_has_link_generic");
2355
2356 if (!hw->phy.ops.read_reg)
2357 return E1000_SUCCESS;
2358
2359 for (i = 0; i < iterations; i++) {
2360 /* Some PHYs require the PHY_STATUS register to be read
2361 * twice due to the link bit being sticky. No harm doing
2362 * it across the board.
2363 */
2364 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2365 if (ret_val) {
2366 /* If the first read fails, another entity may have
2367 * ownership of the resources, wait and try again to
2368 * see if they have relinquished the resources yet.
2369 */
2370 if (usec_interval >= 1000)
2371 msec_delay(usec_interval/1000);
2372 else
2373 usec_delay(usec_interval);
2374 }
2375 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2376 if (ret_val)
2377 break;
2378 if (phy_status & MII_SR_LINK_STATUS)
2379 break;
2380 if (usec_interval >= 1000)
2381 msec_delay(usec_interval/1000);
2382 else
2383 usec_delay(usec_interval);
2384 }
2385
2386 *success = (i < iterations);
2387
2388 return ret_val;
2389 }
2390
2391 /**
2392 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2393 * @hw: pointer to the HW structure
2394 *
2395 * Reads the PHY specific status register to retrieve the cable length
2396 * information. The cable length is determined by averaging the minimum and
2397 * maximum values to get the "average" cable length. The m88 PHY has four
2398 * possible cable length values, which are:
2399 * Register Value Cable Length
2400 * 0 < 50 meters
2401 * 1 50 - 80 meters
2402 * 2 80 - 110 meters
2403 * 3 110 - 140 meters
2404 * 4 > 140 meters
2405 **/
e1000_get_cable_length_m88(struct e1000_hw * hw)2406 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2407 {
2408 struct e1000_phy_info *phy = &hw->phy;
2409 s32 ret_val;
2410 u16 phy_data, index;
2411
2412 DEBUGFUNC("e1000_get_cable_length_m88");
2413
2414 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2415 if (ret_val)
2416 return ret_val;
2417
2418 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2419 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2420
2421 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2422 return -E1000_ERR_PHY;
2423
2424 phy->min_cable_length = e1000_m88_cable_length_table[index];
2425 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2426
2427 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2428
2429 return E1000_SUCCESS;
2430 }
2431
e1000_get_cable_length_m88_gen2(struct e1000_hw * hw)2432 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2433 {
2434 struct e1000_phy_info *phy = &hw->phy;
2435 s32 ret_val;
2436 u16 phy_data, phy_data2, is_cm;
2437 u16 index, default_page;
2438
2439 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2440
2441 switch (hw->phy.id) {
2442 case I210_I_PHY_ID:
2443 /* Get cable length from PHY Cable Diagnostics Control Reg */
2444 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2445 (I347AT4_PCDL + phy->addr),
2446 &phy_data);
2447 if (ret_val)
2448 return ret_val;
2449
2450 /* Check if the unit of cable length is meters or cm */
2451 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2452 I347AT4_PCDC, &phy_data2);
2453 if (ret_val)
2454 return ret_val;
2455
2456 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2457
2458 /* Populate the phy structure with cable length in meters */
2459 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2460 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2461 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2462 break;
2463 case M88E1543_E_PHY_ID:
2464 case M88E1512_E_PHY_ID:
2465 case M88E1340M_E_PHY_ID:
2466 case I347AT4_E_PHY_ID:
2467 /* Remember the original page select and set it to 7 */
2468 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2469 &default_page);
2470 if (ret_val)
2471 return ret_val;
2472
2473 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2474 if (ret_val)
2475 return ret_val;
2476
2477 /* Get cable length from PHY Cable Diagnostics Control Reg */
2478 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2479 &phy_data);
2480 if (ret_val)
2481 return ret_val;
2482
2483 /* Check if the unit of cable length is meters or cm */
2484 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2485 if (ret_val)
2486 return ret_val;
2487
2488 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2489
2490 /* Populate the phy structure with cable length in meters */
2491 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2492 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2493 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2494
2495 /* Reset the page select to its original value */
2496 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2497 default_page);
2498 if (ret_val)
2499 return ret_val;
2500 break;
2501
2502 case M88E1112_E_PHY_ID:
2503 /* Remember the original page select and set it to 5 */
2504 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2505 &default_page);
2506 if (ret_val)
2507 return ret_val;
2508
2509 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2510 if (ret_val)
2511 return ret_val;
2512
2513 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2514 &phy_data);
2515 if (ret_val)
2516 return ret_val;
2517
2518 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2519 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2520
2521 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2522 return -E1000_ERR_PHY;
2523
2524 phy->min_cable_length = e1000_m88_cable_length_table[index];
2525 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2526
2527 phy->cable_length = (phy->min_cable_length +
2528 phy->max_cable_length) / 2;
2529
2530 /* Reset the page select to its original value */
2531 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2532 default_page);
2533 if (ret_val)
2534 return ret_val;
2535
2536 break;
2537 default:
2538 return -E1000_ERR_PHY;
2539 }
2540
2541 return ret_val;
2542 }
2543
2544 /**
2545 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2546 * @hw: pointer to the HW structure
2547 *
2548 * The automatic gain control (agc) normalizes the amplitude of the
2549 * received signal, adjusting for the attenuation produced by the
2550 * cable. By reading the AGC registers, which represent the
2551 * combination of coarse and fine gain value, the value can be put
2552 * into a lookup table to obtain the approximate cable length
2553 * for each channel.
2554 **/
e1000_get_cable_length_igp_2(struct e1000_hw * hw)2555 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2556 {
2557 struct e1000_phy_info *phy = &hw->phy;
2558 s32 ret_val;
2559 u16 phy_data, i, agc_value = 0;
2560 u16 cur_agc_index, max_agc_index = 0;
2561 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2562 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2563 IGP02E1000_PHY_AGC_A,
2564 IGP02E1000_PHY_AGC_B,
2565 IGP02E1000_PHY_AGC_C,
2566 IGP02E1000_PHY_AGC_D
2567 };
2568
2569 DEBUGFUNC("e1000_get_cable_length_igp_2");
2570
2571 /* Read the AGC registers for all channels */
2572 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2573 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2574 if (ret_val)
2575 return ret_val;
2576
2577 /* Getting bits 15:9, which represent the combination of
2578 * coarse and fine gain values. The result is a number
2579 * that can be put into the lookup table to obtain the
2580 * approximate cable length.
2581 */
2582 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2583 IGP02E1000_AGC_LENGTH_MASK);
2584
2585 /* Array index bound check. */
2586 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2587 (cur_agc_index == 0))
2588 return -E1000_ERR_PHY;
2589
2590 /* Remove min & max AGC values from calculation. */
2591 if (e1000_igp_2_cable_length_table[min_agc_index] >
2592 e1000_igp_2_cable_length_table[cur_agc_index])
2593 min_agc_index = cur_agc_index;
2594 if (e1000_igp_2_cable_length_table[max_agc_index] <
2595 e1000_igp_2_cable_length_table[cur_agc_index])
2596 max_agc_index = cur_agc_index;
2597
2598 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2599 }
2600
2601 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2602 e1000_igp_2_cable_length_table[max_agc_index]);
2603 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2604
2605 /* Calculate cable length with the error range of +/- 10 meters. */
2606 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2607 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2608 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2609
2610 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2611
2612 return E1000_SUCCESS;
2613 }
2614
2615 /**
2616 * e1000_get_phy_info_m88 - Retrieve PHY information
2617 * @hw: pointer to the HW structure
2618 *
2619 * Valid for only copper links. Read the PHY status register (sticky read)
2620 * to verify that link is up. Read the PHY special control register to
2621 * determine the polarity and 10base-T extended distance. Read the PHY
2622 * special status register to determine MDI/MDIx and current speed. If
2623 * speed is 1000, then determine cable length, local and remote receiver.
2624 **/
e1000_get_phy_info_m88(struct e1000_hw * hw)2625 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2626 {
2627 struct e1000_phy_info *phy = &hw->phy;
2628 s32 ret_val;
2629 u16 phy_data;
2630 bool link;
2631
2632 DEBUGFUNC("e1000_get_phy_info_m88");
2633
2634 if (phy->media_type != e1000_media_type_copper) {
2635 DEBUGOUT("Phy info is only valid for copper media\n");
2636 return -E1000_ERR_CONFIG;
2637 }
2638
2639 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2640 if (ret_val)
2641 return ret_val;
2642
2643 if (!link) {
2644 DEBUGOUT("Phy info is only valid if link is up\n");
2645 return -E1000_ERR_CONFIG;
2646 }
2647
2648 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2649 if (ret_val)
2650 return ret_val;
2651
2652 phy->polarity_correction = !!(phy_data &
2653 M88E1000_PSCR_POLARITY_REVERSAL);
2654
2655 ret_val = e1000_check_polarity_m88(hw);
2656 if (ret_val)
2657 return ret_val;
2658
2659 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2660 if (ret_val)
2661 return ret_val;
2662
2663 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2664
2665 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2666 ret_val = hw->phy.ops.get_cable_length(hw);
2667 if (ret_val)
2668 return ret_val;
2669
2670 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2671 if (ret_val)
2672 return ret_val;
2673
2674 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2675 ? e1000_1000t_rx_status_ok
2676 : e1000_1000t_rx_status_not_ok;
2677
2678 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2679 ? e1000_1000t_rx_status_ok
2680 : e1000_1000t_rx_status_not_ok;
2681 } else {
2682 /* Set values to "undefined" */
2683 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2684 phy->local_rx = e1000_1000t_rx_status_undefined;
2685 phy->remote_rx = e1000_1000t_rx_status_undefined;
2686 }
2687
2688 return ret_val;
2689 }
2690
2691 /**
2692 * e1000_get_phy_info_igp - Retrieve igp PHY information
2693 * @hw: pointer to the HW structure
2694 *
2695 * Read PHY status to determine if link is up. If link is up, then
2696 * set/determine 10base-T extended distance and polarity correction. Read
2697 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2698 * determine on the cable length, local and remote receiver.
2699 **/
e1000_get_phy_info_igp(struct e1000_hw * hw)2700 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2701 {
2702 struct e1000_phy_info *phy = &hw->phy;
2703 s32 ret_val;
2704 u16 data;
2705 bool link;
2706
2707 DEBUGFUNC("e1000_get_phy_info_igp");
2708
2709 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2710 if (ret_val)
2711 return ret_val;
2712
2713 if (!link) {
2714 DEBUGOUT("Phy info is only valid if link is up\n");
2715 return -E1000_ERR_CONFIG;
2716 }
2717
2718 phy->polarity_correction = TRUE;
2719
2720 ret_val = e1000_check_polarity_igp(hw);
2721 if (ret_val)
2722 return ret_val;
2723
2724 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2725 if (ret_val)
2726 return ret_val;
2727
2728 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2729
2730 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2731 IGP01E1000_PSSR_SPEED_1000MBPS) {
2732 ret_val = phy->ops.get_cable_length(hw);
2733 if (ret_val)
2734 return ret_val;
2735
2736 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2737 if (ret_val)
2738 return ret_val;
2739
2740 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2741 ? e1000_1000t_rx_status_ok
2742 : e1000_1000t_rx_status_not_ok;
2743
2744 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2745 ? e1000_1000t_rx_status_ok
2746 : e1000_1000t_rx_status_not_ok;
2747 } else {
2748 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2749 phy->local_rx = e1000_1000t_rx_status_undefined;
2750 phy->remote_rx = e1000_1000t_rx_status_undefined;
2751 }
2752
2753 return ret_val;
2754 }
2755
2756 /**
2757 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2758 * @hw: pointer to the HW structure
2759 *
2760 * Populates "phy" structure with various feature states.
2761 **/
e1000_get_phy_info_ife(struct e1000_hw * hw)2762 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2763 {
2764 struct e1000_phy_info *phy = &hw->phy;
2765 s32 ret_val;
2766 u16 data;
2767 bool link;
2768
2769 DEBUGFUNC("e1000_get_phy_info_ife");
2770
2771 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2772 if (ret_val)
2773 return ret_val;
2774
2775 if (!link) {
2776 DEBUGOUT("Phy info is only valid if link is up\n");
2777 return -E1000_ERR_CONFIG;
2778 }
2779
2780 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2781 if (ret_val)
2782 return ret_val;
2783 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2784
2785 if (phy->polarity_correction) {
2786 ret_val = e1000_check_polarity_ife(hw);
2787 if (ret_val)
2788 return ret_val;
2789 } else {
2790 /* Polarity is forced */
2791 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2792 ? e1000_rev_polarity_reversed
2793 : e1000_rev_polarity_normal);
2794 }
2795
2796 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2797 if (ret_val)
2798 return ret_val;
2799
2800 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2801
2802 /* The following parameters are undefined for 10/100 operation. */
2803 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2804 phy->local_rx = e1000_1000t_rx_status_undefined;
2805 phy->remote_rx = e1000_1000t_rx_status_undefined;
2806
2807 return E1000_SUCCESS;
2808 }
2809
2810 /**
2811 * e1000_phy_sw_reset_generic - PHY software reset
2812 * @hw: pointer to the HW structure
2813 *
2814 * Does a software reset of the PHY by reading the PHY control register and
2815 * setting/write the control register reset bit to the PHY.
2816 **/
e1000_phy_sw_reset_generic(struct e1000_hw * hw)2817 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2818 {
2819 s32 ret_val;
2820 u16 phy_ctrl;
2821
2822 DEBUGFUNC("e1000_phy_sw_reset_generic");
2823
2824 if (!hw->phy.ops.read_reg)
2825 return E1000_SUCCESS;
2826
2827 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2828 if (ret_val)
2829 return ret_val;
2830
2831 phy_ctrl |= MII_CR_RESET;
2832 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2833 if (ret_val)
2834 return ret_val;
2835
2836 usec_delay(1);
2837
2838 return ret_val;
2839 }
2840
2841 /**
2842 * e1000_phy_hw_reset_generic - PHY hardware reset
2843 * @hw: pointer to the HW structure
2844 *
2845 * Verify the reset block is not blocking us from resetting. Acquire
2846 * semaphore (if necessary) and read/set/write the device control reset
2847 * bit in the PHY. Wait the appropriate delay time for the device to
2848 * reset and release the semaphore (if necessary).
2849 **/
e1000_phy_hw_reset_generic(struct e1000_hw * hw)2850 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2851 {
2852 struct e1000_phy_info *phy = &hw->phy;
2853 s32 ret_val;
2854 u32 ctrl;
2855
2856 DEBUGFUNC("e1000_phy_hw_reset_generic");
2857
2858 if (phy->ops.check_reset_block) {
2859 ret_val = phy->ops.check_reset_block(hw);
2860 if (ret_val)
2861 return E1000_SUCCESS;
2862 }
2863
2864 ret_val = phy->ops.acquire(hw);
2865 if (ret_val)
2866 return ret_val;
2867
2868 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2869 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2870 E1000_WRITE_FLUSH(hw);
2871
2872 usec_delay(phy->reset_delay_us);
2873
2874 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2875 E1000_WRITE_FLUSH(hw);
2876
2877 usec_delay(150);
2878
2879 phy->ops.release(hw);
2880
2881 return phy->ops.get_cfg_done(hw);
2882 }
2883
2884 /**
2885 * e1000_get_cfg_done_generic - Generic configuration done
2886 * @hw: pointer to the HW structure
2887 *
2888 * Generic function to wait 10 milli-seconds for configuration to complete
2889 * and return success.
2890 **/
e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG * hw)2891 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2892 {
2893 DEBUGFUNC("e1000_get_cfg_done_generic");
2894
2895 msec_delay_irq(10);
2896
2897 return E1000_SUCCESS;
2898 }
2899
2900 /**
2901 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2902 * @hw: pointer to the HW structure
2903 *
2904 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2905 **/
e1000_phy_init_script_igp3(struct e1000_hw * hw)2906 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2907 {
2908 DEBUGOUT("Running IGP 3 PHY init script\n");
2909
2910 /* PHY init IGP 3 */
2911 /* Enable rise/fall, 10-mode work in class-A */
2912 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2913 /* Remove all caps from Replica path filter */
2914 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2915 /* Bias trimming for ADC, AFE and Driver (Default) */
2916 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2917 /* Increase Hybrid poly bias */
2918 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2919 /* Add 4% to Tx amplitude in Gig mode */
2920 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2921 /* Disable trimming (TTT) */
2922 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2923 /* Poly DC correction to 94.6% + 2% for all channels */
2924 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2925 /* ABS DC correction to 95.9% */
2926 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2927 /* BG temp curve trim */
2928 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2929 /* Increasing ADC OPAMP stage 1 currents to max */
2930 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2931 /* Force 1000 ( required for enabling PHY regs configuration) */
2932 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2933 /* Set upd_freq to 6 */
2934 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2935 /* Disable NPDFE */
2936 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2937 /* Disable adaptive fixed FFE (Default) */
2938 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2939 /* Enable FFE hysteresis */
2940 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2941 /* Fixed FFE for short cable lengths */
2942 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2943 /* Fixed FFE for medium cable lengths */
2944 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2945 /* Fixed FFE for long cable lengths */
2946 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2947 /* Enable Adaptive Clip Threshold */
2948 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2949 /* AHT reset limit to 1 */
2950 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2951 /* Set AHT master delay to 127 msec */
2952 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2953 /* Set scan bits for AHT */
2954 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2955 /* Set AHT Preset bits */
2956 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2957 /* Change integ_factor of channel A to 3 */
2958 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2959 /* Change prop_factor of channels BCD to 8 */
2960 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2961 /* Change cg_icount + enable integbp for channels BCD */
2962 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2963 /* Change cg_icount + enable integbp + change prop_factor_master
2964 * to 8 for channel A
2965 */
2966 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2967 /* Disable AHT in Slave mode on channel A */
2968 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2969 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2970 * Enable SPD+B2B
2971 */
2972 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2973 /* Enable restart AN on an1000_dis change */
2974 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2975 /* Enable wh_fifo read clock in 10/100 modes */
2976 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2977 /* Restart AN, Speed selection is 1000 */
2978 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2979
2980 return E1000_SUCCESS;
2981 }
2982
2983 /**
2984 * e1000_get_phy_type_from_id - Get PHY type from id
2985 * @phy_id: phy_id read from the phy
2986 *
2987 * Returns the phy type from the id.
2988 **/
e1000_get_phy_type_from_id(u32 phy_id)2989 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2990 {
2991 enum e1000_phy_type phy_type = e1000_phy_unknown;
2992
2993 switch (phy_id) {
2994 case M88E1000_I_PHY_ID:
2995 case M88E1000_E_PHY_ID:
2996 case M88E1111_I_PHY_ID:
2997 case M88E1011_I_PHY_ID:
2998 case M88E1543_E_PHY_ID:
2999 case M88E1512_E_PHY_ID:
3000 case I347AT4_E_PHY_ID:
3001 case M88E1112_E_PHY_ID:
3002 case M88E1340M_E_PHY_ID:
3003 phy_type = e1000_phy_m88;
3004 break;
3005 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
3006 phy_type = e1000_phy_igp_2;
3007 break;
3008 case GG82563_E_PHY_ID:
3009 phy_type = e1000_phy_gg82563;
3010 break;
3011 case IGP03E1000_E_PHY_ID:
3012 phy_type = e1000_phy_igp_3;
3013 break;
3014 case IFE_E_PHY_ID:
3015 case IFE_PLUS_E_PHY_ID:
3016 case IFE_C_E_PHY_ID:
3017 phy_type = e1000_phy_ife;
3018 break;
3019 case BME1000_E_PHY_ID:
3020 case BME1000_E_PHY_ID_R2:
3021 phy_type = e1000_phy_bm;
3022 break;
3023 case I82578_E_PHY_ID:
3024 phy_type = e1000_phy_82578;
3025 break;
3026 case I82577_E_PHY_ID:
3027 phy_type = e1000_phy_82577;
3028 break;
3029 case I82579_E_PHY_ID:
3030 phy_type = e1000_phy_82579;
3031 break;
3032 case I217_E_PHY_ID:
3033 phy_type = e1000_phy_i217;
3034 break;
3035 case I82580_I_PHY_ID:
3036 phy_type = e1000_phy_82580;
3037 break;
3038 case I210_I_PHY_ID:
3039 phy_type = e1000_phy_i210;
3040 break;
3041 default:
3042 phy_type = e1000_phy_unknown;
3043 break;
3044 }
3045 return phy_type;
3046 }
3047
3048 /**
3049 * e1000_determine_phy_address - Determines PHY address.
3050 * @hw: pointer to the HW structure
3051 *
3052 * This uses a trial and error method to loop through possible PHY
3053 * addresses. It tests each by reading the PHY ID registers and
3054 * checking for a match.
3055 **/
e1000_determine_phy_address(struct e1000_hw * hw)3056 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3057 {
3058 u32 phy_addr = 0;
3059 u32 i;
3060 enum e1000_phy_type phy_type = e1000_phy_unknown;
3061
3062 hw->phy.id = phy_type;
3063
3064 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3065 hw->phy.addr = phy_addr;
3066 i = 0;
3067
3068 do {
3069 e1000_get_phy_id(hw);
3070 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3071
3072 /* If phy_type is valid, break - we found our
3073 * PHY address
3074 */
3075 if (phy_type != e1000_phy_unknown)
3076 return E1000_SUCCESS;
3077
3078 msec_delay(1);
3079 i++;
3080 } while (i < 10);
3081 }
3082
3083 return -E1000_ERR_PHY_TYPE;
3084 }
3085
3086 /**
3087 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3088 * @page: page to access
3089 *
3090 * Returns the phy address for the page requested.
3091 **/
e1000_get_phy_addr_for_bm_page(u32 page,u32 reg)3092 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3093 {
3094 u32 phy_addr = 2;
3095
3096 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3097 phy_addr = 1;
3098
3099 return phy_addr;
3100 }
3101
3102 /**
3103 * e1000_write_phy_reg_bm - Write BM PHY register
3104 * @hw: pointer to the HW structure
3105 * @offset: register offset to write to
3106 * @data: data to write at register offset
3107 *
3108 * Acquires semaphore, if necessary, then writes the data to PHY register
3109 * at the offset. Release any acquired semaphores before exiting.
3110 **/
e1000_write_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 data)3111 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3112 {
3113 s32 ret_val;
3114 u32 page = offset >> IGP_PAGE_SHIFT;
3115
3116 DEBUGFUNC("e1000_write_phy_reg_bm");
3117
3118 ret_val = hw->phy.ops.acquire(hw);
3119 if (ret_val)
3120 return ret_val;
3121
3122 /* Page 800 works differently than the rest so it has its own func */
3123 if (page == BM_WUC_PAGE) {
3124 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3125 FALSE, false);
3126 goto release;
3127 }
3128
3129 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3130
3131 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3132 u32 page_shift, page_select;
3133
3134 /* Page select is register 31 for phy address 1 and 22 for
3135 * phy address 2 and 3. Page select is shifted only for
3136 * phy address 1.
3137 */
3138 if (hw->phy.addr == 1) {
3139 page_shift = IGP_PAGE_SHIFT;
3140 page_select = IGP01E1000_PHY_PAGE_SELECT;
3141 } else {
3142 page_shift = 0;
3143 page_select = BM_PHY_PAGE_SELECT;
3144 }
3145
3146 /* Page is shifted left, PHY expects (page x 32) */
3147 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3148 (page << page_shift));
3149 if (ret_val)
3150 goto release;
3151 }
3152
3153 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3154 data);
3155
3156 release:
3157 hw->phy.ops.release(hw);
3158 return ret_val;
3159 }
3160
3161 /**
3162 * e1000_read_phy_reg_bm - Read BM PHY register
3163 * @hw: pointer to the HW structure
3164 * @offset: register offset to be read
3165 * @data: pointer to the read data
3166 *
3167 * Acquires semaphore, if necessary, then reads the PHY register at offset
3168 * and storing the retrieved information in data. Release any acquired
3169 * semaphores before exiting.
3170 **/
e1000_read_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data)3171 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3172 {
3173 s32 ret_val;
3174 u32 page = offset >> IGP_PAGE_SHIFT;
3175
3176 DEBUGFUNC("e1000_read_phy_reg_bm");
3177
3178 ret_val = hw->phy.ops.acquire(hw);
3179 if (ret_val)
3180 return ret_val;
3181
3182 /* Page 800 works differently than the rest so it has its own func */
3183 if (page == BM_WUC_PAGE) {
3184 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3185 TRUE, FALSE);
3186 goto release;
3187 }
3188
3189 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3190
3191 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3192 u32 page_shift, page_select;
3193
3194 /* Page select is register 31 for phy address 1 and 22 for
3195 * phy address 2 and 3. Page select is shifted only for
3196 * phy address 1.
3197 */
3198 if (hw->phy.addr == 1) {
3199 page_shift = IGP_PAGE_SHIFT;
3200 page_select = IGP01E1000_PHY_PAGE_SELECT;
3201 } else {
3202 page_shift = 0;
3203 page_select = BM_PHY_PAGE_SELECT;
3204 }
3205
3206 /* Page is shifted left, PHY expects (page x 32) */
3207 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3208 (page << page_shift));
3209 if (ret_val)
3210 goto release;
3211 }
3212
3213 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3214 data);
3215 release:
3216 hw->phy.ops.release(hw);
3217 return ret_val;
3218 }
3219
3220 /**
3221 * e1000_read_phy_reg_bm2 - Read BM PHY register
3222 * @hw: pointer to the HW structure
3223 * @offset: register offset to be read
3224 * @data: pointer to the read data
3225 *
3226 * Acquires semaphore, if necessary, then reads the PHY register at offset
3227 * and storing the retrieved information in data. Release any acquired
3228 * semaphores before exiting.
3229 **/
e1000_read_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 * data)3230 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3231 {
3232 s32 ret_val;
3233 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3234
3235 DEBUGFUNC("e1000_read_phy_reg_bm2");
3236
3237 ret_val = hw->phy.ops.acquire(hw);
3238 if (ret_val)
3239 return ret_val;
3240
3241 /* Page 800 works differently than the rest so it has its own func */
3242 if (page == BM_WUC_PAGE) {
3243 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3244 TRUE, FALSE);
3245 goto release;
3246 }
3247
3248 hw->phy.addr = 1;
3249
3250 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3251 /* Page is shifted left, PHY expects (page x 32) */
3252 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3253 page);
3254
3255 if (ret_val)
3256 goto release;
3257 }
3258
3259 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3260 data);
3261 release:
3262 hw->phy.ops.release(hw);
3263 return ret_val;
3264 }
3265
3266 /**
3267 * e1000_write_phy_reg_bm2 - Write BM PHY register
3268 * @hw: pointer to the HW structure
3269 * @offset: register offset to write to
3270 * @data: data to write at register offset
3271 *
3272 * Acquires semaphore, if necessary, then writes the data to PHY register
3273 * at the offset. Release any acquired semaphores before exiting.
3274 **/
e1000_write_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 data)3275 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3276 {
3277 s32 ret_val;
3278 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3279
3280 DEBUGFUNC("e1000_write_phy_reg_bm2");
3281
3282 ret_val = hw->phy.ops.acquire(hw);
3283 if (ret_val)
3284 return ret_val;
3285
3286 /* Page 800 works differently than the rest so it has its own func */
3287 if (page == BM_WUC_PAGE) {
3288 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3289 FALSE, false);
3290 goto release;
3291 }
3292
3293 hw->phy.addr = 1;
3294
3295 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3296 /* Page is shifted left, PHY expects (page x 32) */
3297 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3298 page);
3299
3300 if (ret_val)
3301 goto release;
3302 }
3303
3304 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3305 data);
3306
3307 release:
3308 hw->phy.ops.release(hw);
3309 return ret_val;
3310 }
3311
3312 /**
3313 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3314 * @hw: pointer to the HW structure
3315 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3316 *
3317 * Assumes semaphore already acquired and phy_reg points to a valid memory
3318 * address to store contents of the BM_WUC_ENABLE_REG register.
3319 **/
e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)3320 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3321 {
3322 s32 ret_val;
3323 u16 temp;
3324
3325 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3326
3327 if (!phy_reg)
3328 return -E1000_ERR_PARAM;
3329
3330 /* All page select, port ctrl and wakeup registers use phy address 1 */
3331 hw->phy.addr = 1;
3332
3333 /* Select Port Control Registers page */
3334 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3335 if (ret_val) {
3336 DEBUGOUT("Could not set Port Control page\n");
3337 return ret_val;
3338 }
3339
3340 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3341 if (ret_val) {
3342 DEBUGOUT2("Could not read PHY register %d.%d\n",
3343 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3344 return ret_val;
3345 }
3346
3347 /* Enable both PHY wakeup mode and Wakeup register page writes.
3348 * Prevent a power state change by disabling ME and Host PHY wakeup.
3349 */
3350 temp = *phy_reg;
3351 temp |= BM_WUC_ENABLE_BIT;
3352 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3353
3354 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3355 if (ret_val) {
3356 DEBUGOUT2("Could not write PHY register %d.%d\n",
3357 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3358 return ret_val;
3359 }
3360
3361 /* Select Host Wakeup Registers page - caller now able to write
3362 * registers on the Wakeup registers page
3363 */
3364 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3365 }
3366
3367 /**
3368 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3369 * @hw: pointer to the HW structure
3370 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3371 *
3372 * Restore BM_WUC_ENABLE_REG to its original value.
3373 *
3374 * Assumes semaphore already acquired and *phy_reg is the contents of the
3375 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3376 * caller.
3377 **/
e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)3378 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3379 {
3380 s32 ret_val;
3381
3382 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3383
3384 if (!phy_reg)
3385 return -E1000_ERR_PARAM;
3386
3387 /* Select Port Control Registers page */
3388 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3389 if (ret_val) {
3390 DEBUGOUT("Could not set Port Control page\n");
3391 return ret_val;
3392 }
3393
3394 /* Restore 769.17 to its original value */
3395 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3396 if (ret_val)
3397 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3398 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3399
3400 return ret_val;
3401 }
3402
3403 /**
3404 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3405 * @hw: pointer to the HW structure
3406 * @offset: register offset to be read or written
3407 * @data: pointer to the data to read or write
3408 * @read: determines if operation is read or write
3409 * @page_set: BM_WUC_PAGE already set and access enabled
3410 *
3411 * Read the PHY register at offset and store the retrieved information in
3412 * data, or write data to PHY register at offset. Note the procedure to
3413 * access the PHY wakeup registers is different than reading the other PHY
3414 * registers. It works as such:
3415 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3416 * 2) Set page to 800 for host (801 if we were manageability)
3417 * 3) Write the address using the address opcode (0x11)
3418 * 4) Read or write the data using the data opcode (0x12)
3419 * 5) Restore 769.17.2 to its original value
3420 *
3421 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3422 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3423 *
3424 * Assumes semaphore is already acquired. When page_set==TRUE, assumes
3425 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3426 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3427 **/
e1000_access_phy_wakeup_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data,bool read,bool page_set)3428 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3429 u16 *data, bool read, bool page_set)
3430 {
3431 s32 ret_val;
3432 u16 reg = BM_PHY_REG_NUM(offset);
3433 u16 page = BM_PHY_REG_PAGE(offset);
3434 u16 phy_reg = 0;
3435
3436 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3437
3438 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3439 if ((hw->mac.type == e1000_pchlan) &&
3440 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3441 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3442 page);
3443
3444 if (!page_set) {
3445 /* Enable access to PHY wakeup registers */
3446 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3447 if (ret_val) {
3448 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3449 return ret_val;
3450 }
3451 }
3452
3453 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3454
3455 /* Write the Wakeup register page offset value using opcode 0x11 */
3456 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3457 if (ret_val) {
3458 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3459 return ret_val;
3460 }
3461
3462 if (read) {
3463 /* Read the Wakeup register page value using opcode 0x12 */
3464 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3465 data);
3466 } else {
3467 /* Write the Wakeup register page value using opcode 0x12 */
3468 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3469 *data);
3470 }
3471
3472 if (ret_val) {
3473 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3474 return ret_val;
3475 }
3476
3477 if (!page_set)
3478 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3479
3480 return ret_val;
3481 }
3482
3483 /**
3484 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3485 * @hw: pointer to the HW structure
3486 *
3487 * In the case of a PHY power down to save power, or to turn off link during a
3488 * driver unload, or wake on lan is not enabled, restore the link to previous
3489 * settings.
3490 **/
e1000_power_up_phy_copper(struct e1000_hw * hw)3491 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3492 {
3493 u16 mii_reg = 0;
3494
3495 /* The PHY will retain its settings across a power down/up cycle */
3496 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3497 mii_reg &= ~MII_CR_POWER_DOWN;
3498 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3499 }
3500
3501 /**
3502 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3503 * @hw: pointer to the HW structure
3504 *
3505 * In the case of a PHY power down to save power, or to turn off link during a
3506 * driver unload, or wake on lan is not enabled, restore the link to previous
3507 * settings.
3508 **/
e1000_power_down_phy_copper(struct e1000_hw * hw)3509 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3510 {
3511 u16 mii_reg = 0;
3512
3513 /* The PHY will retain its settings across a power down/up cycle */
3514 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3515 mii_reg |= MII_CR_POWER_DOWN;
3516 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3517 msec_delay(1);
3518 }
3519
3520 /**
3521 * __e1000_read_phy_reg_hv - Read HV PHY register
3522 * @hw: pointer to the HW structure
3523 * @offset: register offset to be read
3524 * @data: pointer to the read data
3525 * @locked: semaphore has already been acquired or not
3526 *
3527 * Acquires semaphore, if necessary, then reads the PHY register at offset
3528 * and stores the retrieved information in data. Release any acquired
3529 * semaphore before exiting.
3530 **/
__e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool locked,bool page_set)3531 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3532 bool locked, bool page_set)
3533 {
3534 s32 ret_val;
3535 u16 page = BM_PHY_REG_PAGE(offset);
3536 u16 reg = BM_PHY_REG_NUM(offset);
3537 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3538
3539 DEBUGFUNC("__e1000_read_phy_reg_hv");
3540
3541 if (!locked) {
3542 ret_val = hw->phy.ops.acquire(hw);
3543 if (ret_val)
3544 return ret_val;
3545 }
3546 /* Page 800 works differently than the rest so it has its own func */
3547 if (page == BM_WUC_PAGE) {
3548 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3549 TRUE, page_set);
3550 goto out;
3551 }
3552
3553 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3554 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3555 data, TRUE);
3556 goto out;
3557 }
3558
3559 if (!page_set) {
3560 if (page == HV_INTC_FC_PAGE_START)
3561 page = 0;
3562
3563 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3564 /* Page is shifted left, PHY expects (page x 32) */
3565 ret_val = e1000_set_page_igp(hw,
3566 (page << IGP_PAGE_SHIFT));
3567
3568 hw->phy.addr = phy_addr;
3569
3570 if (ret_val)
3571 goto out;
3572 }
3573 }
3574
3575 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3576 page << IGP_PAGE_SHIFT, reg);
3577
3578 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3579 data);
3580 out:
3581 if (!locked)
3582 hw->phy.ops.release(hw);
3583
3584 return ret_val;
3585 }
3586
3587 /**
3588 * e1000_read_phy_reg_hv - Read HV PHY register
3589 * @hw: pointer to the HW structure
3590 * @offset: register offset to be read
3591 * @data: pointer to the read data
3592 *
3593 * Acquires semaphore then reads the PHY register at offset and stores
3594 * the retrieved information in data. Release the acquired semaphore
3595 * before exiting.
3596 **/
e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data)3597 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3598 {
3599 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, false);
3600 }
3601
3602 /**
3603 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3604 * @hw: pointer to the HW structure
3605 * @offset: register offset to be read
3606 * @data: pointer to the read data
3607 *
3608 * Reads the PHY register at offset and stores the retrieved information
3609 * in data. Assumes semaphore already acquired.
3610 **/
e1000_read_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 * data)3611 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3612 {
3613 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3614 }
3615
3616 /**
3617 * e1000_read_phy_reg_page_hv - Read HV PHY register
3618 * @hw: pointer to the HW structure
3619 * @offset: register offset to write to
3620 * @data: data to write at register offset
3621 *
3622 * Reads the PHY register at offset and stores the retrieved information
3623 * in data. Assumes semaphore already acquired and page already set.
3624 **/
e1000_read_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 * data)3625 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3626 {
3627 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, true);
3628 }
3629
3630 /**
3631 * __e1000_write_phy_reg_hv - Write HV PHY register
3632 * @hw: pointer to the HW structure
3633 * @offset: register offset to write to
3634 * @data: data to write at register offset
3635 * @locked: semaphore has already been acquired or not
3636 *
3637 * Acquires semaphore, if necessary, then writes the data to PHY register
3638 * at the offset. Release any acquired semaphores before exiting.
3639 **/
__e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data,bool locked,bool page_set)3640 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3641 bool locked, bool page_set)
3642 {
3643 s32 ret_val;
3644 u16 page = BM_PHY_REG_PAGE(offset);
3645 u16 reg = BM_PHY_REG_NUM(offset);
3646 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3647
3648 DEBUGFUNC("__e1000_write_phy_reg_hv");
3649
3650 if (!locked) {
3651 ret_val = hw->phy.ops.acquire(hw);
3652 if (ret_val)
3653 return ret_val;
3654 }
3655 /* Page 800 works differently than the rest so it has its own func */
3656 if (page == BM_WUC_PAGE) {
3657 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3658 FALSE, page_set);
3659 goto out;
3660 }
3661
3662 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3663 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3664 &data, FALSE);
3665 goto out;
3666 }
3667
3668 if (!page_set) {
3669 if (page == HV_INTC_FC_PAGE_START)
3670 page = 0;
3671
3672 /* Workaround MDIO accesses being disabled after entering IEEE
3673 * Power Down (when bit 11 of the PHY Control register is set)
3674 */
3675 if ((hw->phy.type == e1000_phy_82578) &&
3676 (hw->phy.revision >= 1) &&
3677 (hw->phy.addr == 2) &&
3678 !(MAX_PHY_REG_ADDRESS & reg) &&
3679 (data & (1 << 11))) {
3680 u16 data2 = 0x7EFF;
3681 ret_val = e1000_access_phy_debug_regs_hv(hw,
3682 (1 << 6) | 0x3,
3683 &data2, FALSE);
3684 if (ret_val)
3685 goto out;
3686 }
3687
3688 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3689 /* Page is shifted left, PHY expects (page x 32) */
3690 ret_val = e1000_set_page_igp(hw,
3691 (page << IGP_PAGE_SHIFT));
3692
3693 hw->phy.addr = phy_addr;
3694
3695 if (ret_val)
3696 goto out;
3697 }
3698 }
3699
3700 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3701 page << IGP_PAGE_SHIFT, reg);
3702
3703 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3704 data);
3705
3706 out:
3707 if (!locked)
3708 hw->phy.ops.release(hw);
3709
3710 return ret_val;
3711 }
3712
3713 /**
3714 * e1000_write_phy_reg_hv - Write HV PHY register
3715 * @hw: pointer to the HW structure
3716 * @offset: register offset to write to
3717 * @data: data to write at register offset
3718 *
3719 * Acquires semaphore then writes the data to PHY register at the offset.
3720 * Release the acquired semaphores before exiting.
3721 **/
e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data)3722 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3723 {
3724 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, false);
3725 }
3726
3727 /**
3728 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3729 * @hw: pointer to the HW structure
3730 * @offset: register offset to write to
3731 * @data: data to write at register offset
3732 *
3733 * Writes the data to PHY register at the offset. Assumes semaphore
3734 * already acquired.
3735 **/
e1000_write_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 data)3736 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3737 {
3738 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3739 }
3740
3741 /**
3742 * e1000_write_phy_reg_page_hv - Write HV PHY register
3743 * @hw: pointer to the HW structure
3744 * @offset: register offset to write to
3745 * @data: data to write at register offset
3746 *
3747 * Writes the data to PHY register at the offset. Assumes semaphore
3748 * already acquired and page already set.
3749 **/
e1000_write_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 data)3750 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3751 {
3752 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, true);
3753 }
3754
3755 /**
3756 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3757 * @page: page to be accessed
3758 **/
e1000_get_phy_addr_for_hv_page(u32 page)3759 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3760 {
3761 u32 phy_addr = 2;
3762
3763 if (page >= HV_INTC_FC_PAGE_START)
3764 phy_addr = 1;
3765
3766 return phy_addr;
3767 }
3768
3769 /**
3770 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3771 * @hw: pointer to the HW structure
3772 * @offset: register offset to be read or written
3773 * @data: pointer to the data to be read or written
3774 * @read: determines if operation is read or write
3775 *
3776 * Reads the PHY register at offset and stores the retreived information
3777 * in data. Assumes semaphore already acquired. Note that the procedure
3778 * to access these regs uses the address port and data port to read/write.
3779 * These accesses done with PHY address 2 and without using pages.
3780 **/
e1000_access_phy_debug_regs_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool read)3781 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3782 u16 *data, bool read)
3783 {
3784 s32 ret_val;
3785 u32 addr_reg;
3786 u32 data_reg;
3787
3788 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3789
3790 /* This takes care of the difference with desktop vs mobile phy */
3791 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3792 I82578_ADDR_REG : I82577_ADDR_REG);
3793 data_reg = addr_reg + 1;
3794
3795 /* All operations in this function are phy address 2 */
3796 hw->phy.addr = 2;
3797
3798 /* masking with 0x3F to remove the page from offset */
3799 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3800 if (ret_val) {
3801 DEBUGOUT("Could not write the Address Offset port register\n");
3802 return ret_val;
3803 }
3804
3805 /* Read or write the data value next */
3806 if (read)
3807 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3808 else
3809 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3810
3811 if (ret_val)
3812 DEBUGOUT("Could not access the Data port register\n");
3813
3814 return ret_val;
3815 }
3816
3817 /**
3818 * e1000_link_stall_workaround_hv - Si workaround
3819 * @hw: pointer to the HW structure
3820 *
3821 * This function works around a Si bug where the link partner can get
3822 * a link up indication before the PHY does. If small packets are sent
3823 * by the link partner they can be placed in the packet buffer without
3824 * being properly accounted for by the PHY and will stall preventing
3825 * further packets from being received. The workaround is to clear the
3826 * packet buffer after the PHY detects link up.
3827 **/
e1000_link_stall_workaround_hv(struct e1000_hw * hw)3828 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3829 {
3830 s32 ret_val = E1000_SUCCESS;
3831 u16 data;
3832
3833 DEBUGFUNC("e1000_link_stall_workaround_hv");
3834
3835 if (hw->phy.type != e1000_phy_82578)
3836 return E1000_SUCCESS;
3837
3838 /* Do not apply workaround if in PHY loopback bit 14 set */
3839 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3840 if (data & PHY_CONTROL_LB)
3841 return E1000_SUCCESS;
3842
3843 /* check if link is up and at 1Gbps */
3844 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3845 if (ret_val)
3846 return ret_val;
3847
3848 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3849 BM_CS_STATUS_SPEED_MASK);
3850
3851 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3852 BM_CS_STATUS_SPEED_1000))
3853 return E1000_SUCCESS;
3854
3855 msec_delay(200);
3856
3857 /* flush the packets in the fifo buffer */
3858 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3859 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3860 HV_MUX_DATA_CTRL_FORCE_SPEED));
3861 if (ret_val)
3862 return ret_val;
3863
3864 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3865 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3866 }
3867
3868 /**
3869 * e1000_check_polarity_82577 - Checks the polarity.
3870 * @hw: pointer to the HW structure
3871 *
3872 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3873 *
3874 * Polarity is determined based on the PHY specific status register.
3875 **/
e1000_check_polarity_82577(struct e1000_hw * hw)3876 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3877 {
3878 struct e1000_phy_info *phy = &hw->phy;
3879 s32 ret_val;
3880 u16 data;
3881
3882 DEBUGFUNC("e1000_check_polarity_82577");
3883
3884 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3885
3886 if (!ret_val)
3887 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3888 ? e1000_rev_polarity_reversed
3889 : e1000_rev_polarity_normal);
3890
3891 return ret_val;
3892 }
3893
3894 /**
3895 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3896 * @hw: pointer to the HW structure
3897 *
3898 * Calls the PHY setup function to force speed and duplex.
3899 **/
e1000_phy_force_speed_duplex_82577(struct e1000_hw * hw)3900 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3901 {
3902 struct e1000_phy_info *phy = &hw->phy;
3903 s32 ret_val;
3904 u16 phy_data;
3905 bool link;
3906
3907 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3908
3909 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3910 if (ret_val)
3911 return ret_val;
3912
3913 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3914
3915 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3916 if (ret_val)
3917 return ret_val;
3918
3919 usec_delay(1);
3920
3921 if (phy->autoneg_wait_to_complete) {
3922 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3923
3924 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3925 100000, &link);
3926 if (ret_val)
3927 return ret_val;
3928
3929 if (!link)
3930 DEBUGOUT("Link taking longer than expected.\n");
3931
3932 /* Try once more */
3933 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3934 100000, &link);
3935 }
3936
3937 return ret_val;
3938 }
3939
3940 /**
3941 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3942 * @hw: pointer to the HW structure
3943 *
3944 * Read PHY status to determine if link is up. If link is up, then
3945 * set/determine 10base-T extended distance and polarity correction. Read
3946 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3947 * determine on the cable length, local and remote receiver.
3948 **/
e1000_get_phy_info_82577(struct e1000_hw * hw)3949 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3950 {
3951 struct e1000_phy_info *phy = &hw->phy;
3952 s32 ret_val;
3953 u16 data;
3954 bool link;
3955
3956 DEBUGFUNC("e1000_get_phy_info_82577");
3957
3958 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3959 if (ret_val)
3960 return ret_val;
3961
3962 if (!link) {
3963 DEBUGOUT("Phy info is only valid if link is up\n");
3964 return -E1000_ERR_CONFIG;
3965 }
3966
3967 phy->polarity_correction = TRUE;
3968
3969 ret_val = e1000_check_polarity_82577(hw);
3970 if (ret_val)
3971 return ret_val;
3972
3973 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3974 if (ret_val)
3975 return ret_val;
3976
3977 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3978
3979 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3980 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3981 ret_val = hw->phy.ops.get_cable_length(hw);
3982 if (ret_val)
3983 return ret_val;
3984
3985 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3986 if (ret_val)
3987 return ret_val;
3988
3989 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3990 ? e1000_1000t_rx_status_ok
3991 : e1000_1000t_rx_status_not_ok;
3992
3993 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3994 ? e1000_1000t_rx_status_ok
3995 : e1000_1000t_rx_status_not_ok;
3996 } else {
3997 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3998 phy->local_rx = e1000_1000t_rx_status_undefined;
3999 phy->remote_rx = e1000_1000t_rx_status_undefined;
4000 }
4001
4002 return E1000_SUCCESS;
4003 }
4004
4005 /**
4006 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
4007 * @hw: pointer to the HW structure
4008 *
4009 * Reads the diagnostic status register and verifies result is valid before
4010 * placing it in the phy_cable_length field.
4011 **/
e1000_get_cable_length_82577(struct e1000_hw * hw)4012 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
4013 {
4014 struct e1000_phy_info *phy = &hw->phy;
4015 s32 ret_val;
4016 u16 phy_data, length;
4017
4018 DEBUGFUNC("e1000_get_cable_length_82577");
4019
4020 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4021 if (ret_val)
4022 return ret_val;
4023
4024 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4025 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
4026
4027 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4028 return -E1000_ERR_PHY;
4029
4030 phy->cable_length = length;
4031
4032 return E1000_SUCCESS;
4033 }
4034
4035 /**
4036 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4037 * @hw: pointer to the HW structure
4038 * @offset: register offset to write to
4039 * @data: data to write at register offset
4040 *
4041 * Acquires semaphore, if necessary, then writes the data to PHY register
4042 * at the offset. Release any acquired semaphores before exiting.
4043 **/
e1000_write_phy_reg_gs40g(struct e1000_hw * hw,u32 offset,u16 data)4044 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4045 {
4046 s32 ret_val;
4047 u16 page = offset >> GS40G_PAGE_SHIFT;
4048
4049 DEBUGFUNC("e1000_write_phy_reg_gs40g");
4050
4051 offset = offset & GS40G_OFFSET_MASK;
4052 ret_val = hw->phy.ops.acquire(hw);
4053 if (ret_val)
4054 return ret_val;
4055
4056 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4057 if (ret_val)
4058 goto release;
4059 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4060
4061 release:
4062 hw->phy.ops.release(hw);
4063 return ret_val;
4064 }
4065
4066 /**
4067 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4068 * @hw: pointer to the HW structure
4069 * @offset: lower half is register offset to read to
4070 * upper half is page to use.
4071 * @data: data to read at register offset
4072 *
4073 * Acquires semaphore, if necessary, then reads the data in the PHY register
4074 * at the offset. Release any acquired semaphores before exiting.
4075 **/
e1000_read_phy_reg_gs40g(struct e1000_hw * hw,u32 offset,u16 * data)4076 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4077 {
4078 s32 ret_val;
4079 u16 page = offset >> GS40G_PAGE_SHIFT;
4080
4081 DEBUGFUNC("e1000_read_phy_reg_gs40g");
4082
4083 offset = offset & GS40G_OFFSET_MASK;
4084 ret_val = hw->phy.ops.acquire(hw);
4085 if (ret_val)
4086 return ret_val;
4087
4088 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4089 if (ret_val)
4090 goto release;
4091 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4092
4093 release:
4094 hw->phy.ops.release(hw);
4095 return ret_val;
4096 }
4097
4098 /**
4099 * e1000_read_phy_reg_mphy - Read mPHY control register
4100 * @hw: pointer to the HW structure
4101 * @address: address to be read
4102 * @data: pointer to the read data
4103 *
4104 * Reads the mPHY control register in the PHY at offset and stores the
4105 * information read to data.
4106 **/
e1000_read_phy_reg_mphy(struct e1000_hw * hw,u32 address,u32 * data)4107 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
4108 {
4109 u32 mphy_ctrl = 0;
4110 bool locked = FALSE;
4111 bool ready;
4112
4113 DEBUGFUNC("e1000_read_phy_reg_mphy");
4114
4115 /* Check if mPHY is ready to read/write operations */
4116 ready = e1000_is_mphy_ready(hw);
4117 if (!ready)
4118 return -E1000_ERR_PHY;
4119
4120 /* Check if mPHY access is disabled and enable it if so */
4121 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4122 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4123 locked = TRUE;
4124 ready = e1000_is_mphy_ready(hw);
4125 if (!ready)
4126 return -E1000_ERR_PHY;
4127 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4128 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4129 }
4130
4131 /* Set the address that we want to read */
4132 ready = e1000_is_mphy_ready(hw);
4133 if (!ready)
4134 return -E1000_ERR_PHY;
4135
4136 /* We mask address, because we want to use only current lane */
4137 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
4138 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |
4139 (address & E1000_MPHY_ADDRESS_MASK);
4140 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4141
4142 /* Read data from the address */
4143 ready = e1000_is_mphy_ready(hw);
4144 if (!ready)
4145 return -E1000_ERR_PHY;
4146 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
4147
4148 /* Disable access to mPHY if it was originally disabled */
4149 if (locked)
4150 ready = e1000_is_mphy_ready(hw);
4151 if (!ready)
4152 return -E1000_ERR_PHY;
4153 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4154 E1000_MPHY_DIS_ACCESS);
4155
4156 return E1000_SUCCESS;
4157 }
4158
4159 /**
4160 * e1000_write_phy_reg_mphy - Write mPHY control register
4161 * @hw: pointer to the HW structure
4162 * @address: address to write to
4163 * @data: data to write to register at offset
4164 * @line_override: used when we want to use different line than default one
4165 *
4166 * Writes data to mPHY control register.
4167 **/
e1000_write_phy_reg_mphy(struct e1000_hw * hw,u32 address,u32 data,bool line_override)4168 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
4169 bool line_override)
4170 {
4171 u32 mphy_ctrl = 0;
4172 bool locked = FALSE;
4173 bool ready;
4174
4175 DEBUGFUNC("e1000_write_phy_reg_mphy");
4176
4177 /* Check if mPHY is ready to read/write operations */
4178 ready = e1000_is_mphy_ready(hw);
4179 if (!ready)
4180 return -E1000_ERR_PHY;
4181
4182 /* Check if mPHY access is disabled and enable it if so */
4183 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4184 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4185 locked = TRUE;
4186 ready = e1000_is_mphy_ready(hw);
4187 if (!ready)
4188 return -E1000_ERR_PHY;
4189 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4190 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4191 }
4192
4193 /* Set the address that we want to read */
4194 ready = e1000_is_mphy_ready(hw);
4195 if (!ready)
4196 return -E1000_ERR_PHY;
4197
4198 /* We mask address, because we want to use only current lane */
4199 if (line_override)
4200 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4201 else
4202 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4203 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
4204 (address & E1000_MPHY_ADDRESS_MASK);
4205 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4206
4207 /* Read data from the address */
4208 ready = e1000_is_mphy_ready(hw);
4209 if (!ready)
4210 return -E1000_ERR_PHY;
4211 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
4212
4213 /* Disable access to mPHY if it was originally disabled */
4214 if (locked)
4215 ready = e1000_is_mphy_ready(hw);
4216 if (!ready)
4217 return -E1000_ERR_PHY;
4218 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4219 E1000_MPHY_DIS_ACCESS);
4220
4221 return E1000_SUCCESS;
4222 }
4223
4224 /**
4225 * e1000_is_mphy_ready - Check if mPHY control register is not busy
4226 * @hw: pointer to the HW structure
4227 *
4228 * Returns mPHY control register status.
4229 **/
e1000_is_mphy_ready(struct e1000_hw * hw)4230 bool e1000_is_mphy_ready(struct e1000_hw *hw)
4231 {
4232 u16 retry_count = 0;
4233 u32 mphy_ctrl = 0;
4234 bool ready = FALSE;
4235
4236 while (retry_count < 2) {
4237 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4238 if (mphy_ctrl & E1000_MPHY_BUSY) {
4239 usec_delay(20);
4240 retry_count++;
4241 continue;
4242 }
4243 ready = TRUE;
4244 break;
4245 }
4246
4247 if (!ready)
4248 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");
4249
4250 return ready;
4251 }
4252