1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34
35 #include "e1000_api.h"
36
37
38 static s32 e1000_acquire_nvm_i210(struct e1000_hw *hw);
39 static void e1000_release_nvm_i210(struct e1000_hw *hw);
40 static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw);
41 static s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
42 u16 *data);
43 static s32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw);
44 static s32 e1000_valid_led_default_i210(struct e1000_hw *hw, u16 *data);
45
46 /**
47 * e1000_acquire_nvm_i210 - Request for access to EEPROM
48 * @hw: pointer to the HW structure
49 *
50 * Acquire the necessary semaphores for exclusive access to the EEPROM.
51 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
52 * Return successful if access grant bit set, else clear the request for
53 * EEPROM access and return -E1000_ERR_NVM (-1).
54 **/
e1000_acquire_nvm_i210(struct e1000_hw * hw)55 static s32 e1000_acquire_nvm_i210(struct e1000_hw *hw)
56 {
57 s32 ret_val;
58
59 DEBUGFUNC("e1000_acquire_nvm_i210");
60
61 ret_val = e1000_acquire_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);
62
63 return ret_val;
64 }
65
66 /**
67 * e1000_release_nvm_i210 - Release exclusive access to EEPROM
68 * @hw: pointer to the HW structure
69 *
70 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
71 * then release the semaphores acquired.
72 **/
e1000_release_nvm_i210(struct e1000_hw * hw)73 static void e1000_release_nvm_i210(struct e1000_hw *hw)
74 {
75 DEBUGFUNC("e1000_release_nvm_i210");
76
77 e1000_release_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);
78 }
79
80 /**
81 * e1000_acquire_swfw_sync_i210 - Acquire SW/FW semaphore
82 * @hw: pointer to the HW structure
83 * @mask: specifies which semaphore to acquire
84 **/
e1000_acquire_swfw_sync_i210(struct e1000_hw * hw,u16 mask)85 s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
86 {
87 u32 swfw_sync;
88 u32 swmask = mask;
89 u32 fwmask = mask << 16;
90 s32 ret_val = E1000_SUCCESS;
91 s32 i = 0, timeout = 200;
92
93 DEBUGFUNC("e1000_acquire_swfw_sync_i210");
94 ASSERT_NO_LOCKS();
95
96 while (i < timeout) {
97 if (e1000_get_hw_semaphore_i210(hw)) {
98 ret_val = -E1000_ERR_SWFW_SYNC;
99 goto out;
100 }
101
102 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
103 if (!(swfw_sync & (fwmask | swmask)))
104 break;
105
106 e1000_put_hw_semaphore(hw);
107 msec_delay_irq(5);
108 i++;
109 }
110
111 if (i == timeout) {
112 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
113 ret_val = -E1000_ERR_SWFW_SYNC;
114 goto out;
115 }
116
117 swfw_sync |= swmask;
118 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
119 e1000_put_hw_semaphore(hw);
120
121 out:
122 return ret_val;
123 }
124
125 /**
126 * e1000_release_swfw_sync_i210 - Release SW/FW semaphore
127 * @hw: pointer to the HW structure
128 * @mask: specifies which semaphore to release
129 **/
e1000_release_swfw_sync_i210(struct e1000_hw * hw,u16 mask)130 void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
131 {
132 u32 swfw_sync;
133
134 DEBUGFUNC("e1000_release_swfw_sync_i210");
135
136 while (e1000_get_hw_semaphore_i210(hw) != E1000_SUCCESS)
137 ; /* Empty */
138
139 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
140 swfw_sync &= (u32)~mask;
141 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
142 e1000_put_hw_semaphore(hw);
143 }
144
145 /**
146 * e1000_get_hw_semaphore_i210 - Acquire hardware semaphore
147 * @hw: pointer to the HW structure
148 **/
e1000_get_hw_semaphore_i210(struct e1000_hw * hw)149 static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw)
150 {
151 u32 swsm;
152 s32 timeout = hw->nvm.word_size + 1;
153 s32 i = 0;
154
155 DEBUGFUNC("e1000_get_hw_semaphore_i210");
156
157 while (i < timeout) {
158 swsm = E1000_READ_REG(hw, E1000_SWSM);
159 if (!(swsm & E1000_SWSM_SMBI))
160 break;
161 usec_delay(50);
162 i++;
163 }
164
165 if (i == timeout) {
166 /* Clear an unintentionally retained semaphore once. */
167 if (hw->dev_spec._82575.clear_semaphore_once) {
168 hw->dev_spec._82575.clear_semaphore_once = false;
169 e1000_put_hw_semaphore(hw);
170 for (i = 0; i < timeout; i++) {
171 swsm = E1000_READ_REG(hw, E1000_SWSM);
172 if (!(swsm & E1000_SWSM_SMBI))
173 break;
174 usec_delay(50);
175 }
176 }
177 if (i == timeout) {
178 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
179 return -E1000_ERR_NVM;
180 }
181 }
182
183 for (i = 0; i < timeout; i++) {
184 swsm = E1000_READ_REG(hw, E1000_SWSM);
185 E1000_WRITE_REG(hw, E1000_SWSM,
186 swsm | E1000_SWSM_SWESMBI);
187 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
188 break;
189 usec_delay(50);
190 }
191
192 if (i == timeout) {
193 e1000_put_hw_semaphore(hw);
194 DEBUGOUT("Driver can't access the NVM\n");
195 return -E1000_ERR_NVM;
196 }
197
198 return E1000_SUCCESS;
199 }
200
201 /**
202 * e1000_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
203 * @hw: pointer to the HW structure
204 * @offset: offset of word in the Shadow Ram to read
205 * @words: number of words to read
206 * @data: word read from the Shadow Ram
207 *
208 * Reads a 16 bit word from the Shadow Ram using the EERD register.
209 * Uses necessary synchronization semaphores.
210 **/
e1000_read_nvm_srrd_i210(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)211 s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,
212 u16 *data)
213 {
214 s32 status = E1000_SUCCESS;
215 u16 i, count;
216
217 DEBUGFUNC("e1000_read_nvm_srrd_i210");
218
219 /* We cannot hold synchronization semaphores for too long,
220 * because of forceful takeover procedure. However it is more efficient
221 * to read in bursts than synchronizing access for each word. */
222 for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
223 count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
224 E1000_EERD_EEWR_MAX_COUNT : (words - i);
225 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
226 status = e1000_read_nvm_eerd(hw, offset, count,
227 data + i);
228 hw->nvm.ops.release(hw);
229 } else {
230 status = E1000_ERR_SWFW_SYNC;
231 }
232
233 if (status != E1000_SUCCESS)
234 break;
235 }
236
237 return status;
238 }
239
240 /**
241 * e1000_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
242 * @hw: pointer to the HW structure
243 * @offset: offset within the Shadow RAM to be written to
244 * @words: number of words to write
245 * @data: 16 bit word(s) to be written to the Shadow RAM
246 *
247 * Writes data to Shadow RAM at offset using EEWR register.
248 *
249 * If e1000_update_nvm_checksum is not called after this function , the
250 * data will not be committed to FLASH and also Shadow RAM will most likely
251 * contain an invalid checksum.
252 *
253 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
254 * partially written.
255 **/
e1000_write_nvm_srwr_i210(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)256 s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,
257 u16 *data)
258 {
259 s32 status = E1000_SUCCESS;
260 u16 i, count;
261
262 DEBUGFUNC("e1000_write_nvm_srwr_i210");
263
264 /* We cannot hold synchronization semaphores for too long,
265 * because of forceful takeover procedure. However it is more efficient
266 * to write in bursts than synchronizing access for each word. */
267 for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
268 count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
269 E1000_EERD_EEWR_MAX_COUNT : (words - i);
270 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
271 status = e1000_write_nvm_srwr(hw, offset, count,
272 data + i);
273 hw->nvm.ops.release(hw);
274 } else {
275 status = E1000_ERR_SWFW_SYNC;
276 }
277
278 if (status != E1000_SUCCESS)
279 break;
280 }
281
282 return status;
283 }
284
285 /**
286 * e1000_write_nvm_srwr - Write to Shadow Ram using EEWR
287 * @hw: pointer to the HW structure
288 * @offset: offset within the Shadow Ram to be written to
289 * @words: number of words to write
290 * @data: 16 bit word(s) to be written to the Shadow Ram
291 *
292 * Writes data to Shadow Ram at offset using EEWR register.
293 *
294 * If e1000_update_nvm_checksum is not called after this function , the
295 * Shadow Ram will most likely contain an invalid checksum.
296 **/
e1000_write_nvm_srwr(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)297 static s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
298 u16 *data)
299 {
300 struct e1000_nvm_info *nvm = &hw->nvm;
301 u32 i, k, eewr = 0;
302 u32 attempts = 100000;
303 s32 ret_val = E1000_SUCCESS;
304
305 DEBUGFUNC("e1000_write_nvm_srwr");
306
307 /*
308 * A check for invalid values: offset too large, too many words,
309 * too many words for the offset, and not enough words.
310 */
311 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
312 (words == 0)) {
313 DEBUGOUT("nvm parameter(s) out of bounds\n");
314 ret_val = -E1000_ERR_NVM;
315 goto out;
316 }
317
318 for (i = 0; i < words; i++) {
319 ret_val = -E1000_ERR_NVM;
320
321 eewr = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
322 (data[i] << E1000_NVM_RW_REG_DATA) |
323 E1000_NVM_RW_REG_START;
324
325 E1000_WRITE_REG(hw, E1000_SRWR, eewr);
326
327 for (k = 0; k < attempts; k++) {
328 if (E1000_NVM_RW_REG_DONE &
329 E1000_READ_REG(hw, E1000_SRWR)) {
330 ret_val = E1000_SUCCESS;
331 break;
332 }
333 usec_delay(5);
334 }
335
336 if (ret_val != E1000_SUCCESS) {
337 DEBUGOUT("Shadow RAM write EEWR timed out\n");
338 break;
339 }
340 }
341
342 out:
343 return ret_val;
344 }
345
346 /** e1000_read_invm_word_i210 - Reads OTP
347 * @hw: pointer to the HW structure
348 * @address: the word address (aka eeprom offset) to read
349 * @data: pointer to the data read
350 *
351 * Reads 16-bit words from the OTP. Return error when the word is not
352 * stored in OTP.
353 **/
e1000_read_invm_word_i210(struct e1000_hw * hw,u8 address,u16 * data)354 static s32 e1000_read_invm_word_i210(struct e1000_hw *hw, u8 address, u16 *data)
355 {
356 s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
357 u32 invm_dword;
358 u16 i;
359 u8 record_type, word_address;
360
361 DEBUGFUNC("e1000_read_invm_word_i210");
362
363 for (i = 0; i < E1000_INVM_SIZE; i++) {
364 invm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i));
365 /* Get record type */
366 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
367 if (record_type == E1000_INVM_UNINITIALIZED_STRUCTURE)
368 break;
369 if (record_type == E1000_INVM_CSR_AUTOLOAD_STRUCTURE)
370 i += E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
371 if (record_type == E1000_INVM_RSA_KEY_SHA256_STRUCTURE)
372 i += E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
373 if (record_type == E1000_INVM_WORD_AUTOLOAD_STRUCTURE) {
374 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
375 if (word_address == address) {
376 *data = INVM_DWORD_TO_WORD_DATA(invm_dword);
377 DEBUGOUT2("Read INVM Word 0x%02x = %x",
378 address, *data);
379 status = E1000_SUCCESS;
380 break;
381 }
382 }
383 }
384 if (status != E1000_SUCCESS)
385 DEBUGOUT1("Requested word 0x%02x not found in OTP\n", address);
386 return status;
387 }
388
389 /** e1000_read_invm_i210 - Read invm wrapper function for I210/I211
390 * @hw: pointer to the HW structure
391 * @address: the word address (aka eeprom offset) to read
392 * @data: pointer to the data read
393 *
394 * Wrapper function to return data formerly found in the NVM.
395 **/
e1000_read_invm_i210(struct e1000_hw * hw,u16 offset,u16 E1000_UNUSEDARG words,u16 * data)396 static s32 e1000_read_invm_i210(struct e1000_hw *hw, u16 offset,
397 u16 E1000_UNUSEDARG words, u16 *data)
398 {
399 s32 ret_val = E1000_SUCCESS;
400
401 DEBUGFUNC("e1000_read_invm_i210");
402
403 /* Only the MAC addr is required to be present in the iNVM */
404 switch (offset) {
405 case NVM_MAC_ADDR:
406 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, &data[0]);
407 ret_val |= e1000_read_invm_word_i210(hw, (u8)offset + 1,
408 &data[1]);
409 ret_val |= e1000_read_invm_word_i210(hw, (u8)offset + 2,
410 &data[2]);
411 if (ret_val != E1000_SUCCESS)
412 DEBUGOUT("MAC Addr not found in iNVM\n");
413 break;
414 case NVM_INIT_CTRL_2:
415 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
416 if (ret_val != E1000_SUCCESS) {
417 *data = NVM_INIT_CTRL_2_DEFAULT_I211;
418 ret_val = E1000_SUCCESS;
419 }
420 break;
421 case NVM_INIT_CTRL_4:
422 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
423 if (ret_val != E1000_SUCCESS) {
424 *data = NVM_INIT_CTRL_4_DEFAULT_I211;
425 ret_val = E1000_SUCCESS;
426 }
427 break;
428 case NVM_LED_1_CFG:
429 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
430 if (ret_val != E1000_SUCCESS) {
431 *data = NVM_LED_1_CFG_DEFAULT_I211;
432 ret_val = E1000_SUCCESS;
433 }
434 break;
435 case NVM_LED_0_2_CFG:
436 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
437 if (ret_val != E1000_SUCCESS) {
438 *data = NVM_LED_0_2_CFG_DEFAULT_I211;
439 ret_val = E1000_SUCCESS;
440 }
441 break;
442 case NVM_ID_LED_SETTINGS:
443 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
444 if (ret_val != E1000_SUCCESS) {
445 *data = ID_LED_RESERVED_FFFF;
446 ret_val = E1000_SUCCESS;
447 }
448 break;
449 case NVM_SUB_DEV_ID:
450 *data = hw->subsystem_device_id;
451 break;
452 case NVM_SUB_VEN_ID:
453 *data = hw->subsystem_vendor_id;
454 break;
455 case NVM_DEV_ID:
456 *data = hw->device_id;
457 break;
458 case NVM_VEN_ID:
459 *data = hw->vendor_id;
460 break;
461 default:
462 DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset);
463 *data = NVM_RESERVED_WORD;
464 break;
465 }
466 return ret_val;
467 }
468
469 /**
470 * e1000_read_invm_version - Reads iNVM version and image type
471 * @hw: pointer to the HW structure
472 * @invm_ver: version structure for the version read
473 *
474 * Reads iNVM version and image type.
475 **/
e1000_read_invm_version(struct e1000_hw * hw,struct e1000_fw_version * invm_ver)476 s32 e1000_read_invm_version(struct e1000_hw *hw,
477 struct e1000_fw_version *invm_ver)
478 {
479 u32 *record = NULL;
480 u32 *next_record = NULL;
481 u32 i = 0;
482 u32 invm_dword = 0;
483 u32 invm_blocks = E1000_INVM_SIZE - (E1000_INVM_ULT_BYTES_SIZE /
484 E1000_INVM_RECORD_SIZE_IN_BYTES);
485 u32 buffer[E1000_INVM_SIZE];
486 s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
487 u16 nvm_version = 0;
488
489 DEBUGFUNC("e1000_read_invm_version");
490
491 /* Read iNVM memory */
492 for (i = 0; i < E1000_INVM_SIZE; i++) {
493 invm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i));
494 buffer[i] = invm_dword;
495 }
496
497 /* Read version number */
498 for (i = 1; i < invm_blocks; i++) {
499 record = &buffer[invm_blocks - i];
500 next_record = &buffer[invm_blocks - i + 1];
501
502 /* Check if we have first version location used */
503 if ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) {
504 nvm_version = 0;
505 status = E1000_SUCCESS;
506 break;
507 }
508 /* Check if we have second version location used */
509 else if ((i == 1) &&
510 ((*record & E1000_INVM_VER_FIELD_TWO) == 0)) {
511 nvm_version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
512 status = E1000_SUCCESS;
513 break;
514 }
515 /*
516 * Check if we have odd version location
517 * used and it is the last one used
518 */
519 else if ((((*record & E1000_INVM_VER_FIELD_ONE) == 0) &&
520 ((*record & 0x3) == 0)) || (((*record & 0x3) != 0) &&
521 (i != 1))) {
522 nvm_version = (*next_record & E1000_INVM_VER_FIELD_TWO)
523 >> 13;
524 status = E1000_SUCCESS;
525 break;
526 }
527 /*
528 * Check if we have even version location
529 * used and it is the last one used
530 */
531 else if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) &&
532 ((*record & 0x3) == 0)) {
533 nvm_version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
534 status = E1000_SUCCESS;
535 break;
536 }
537 }
538
539 if (status == E1000_SUCCESS) {
540 invm_ver->invm_major = (nvm_version & E1000_INVM_MAJOR_MASK)
541 >> E1000_INVM_MAJOR_SHIFT;
542 invm_ver->invm_minor = nvm_version & E1000_INVM_MINOR_MASK;
543 }
544 /* Read Image Type */
545 for (i = 1; i < invm_blocks; i++) {
546 record = &buffer[invm_blocks - i];
547 next_record = &buffer[invm_blocks - i + 1];
548
549 /* Check if we have image type in first location used */
550 if ((i == 1) && ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) {
551 invm_ver->invm_img_type = 0;
552 status = E1000_SUCCESS;
553 break;
554 }
555 /* Check if we have image type in first location used */
556 else if ((((*record & 0x3) == 0) &&
557 ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) ||
558 ((((*record & 0x3) != 0) && (i != 1)))) {
559 invm_ver->invm_img_type =
560 (*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23;
561 status = E1000_SUCCESS;
562 break;
563 }
564 }
565 return status;
566 }
567
568 /**
569 * e1000_validate_nvm_checksum_i210 - Validate EEPROM checksum
570 * @hw: pointer to the HW structure
571 *
572 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
573 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
574 **/
e1000_validate_nvm_checksum_i210(struct e1000_hw * hw)575 s32 e1000_validate_nvm_checksum_i210(struct e1000_hw *hw)
576 {
577 s32 status = E1000_SUCCESS;
578 s32 (*read_op_ptr)(struct e1000_hw *, u16, u16, u16 *);
579
580 DEBUGFUNC("e1000_validate_nvm_checksum_i210");
581
582 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
583
584 /*
585 * Replace the read function with semaphore grabbing with
586 * the one that skips this for a while.
587 * We have semaphore taken already here.
588 */
589 read_op_ptr = hw->nvm.ops.read;
590 hw->nvm.ops.read = e1000_read_nvm_eerd;
591
592 status = e1000_validate_nvm_checksum_generic(hw);
593
594 /* Revert original read operation. */
595 hw->nvm.ops.read = read_op_ptr;
596
597 hw->nvm.ops.release(hw);
598 } else {
599 status = E1000_ERR_SWFW_SYNC;
600 }
601
602 return status;
603 }
604
605
606 /**
607 * e1000_update_nvm_checksum_i210 - Update EEPROM checksum
608 * @hw: pointer to the HW structure
609 *
610 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
611 * up to the checksum. Then calculates the EEPROM checksum and writes the
612 * value to the EEPROM. Next commit EEPROM data onto the Flash.
613 **/
e1000_update_nvm_checksum_i210(struct e1000_hw * hw)614 s32 e1000_update_nvm_checksum_i210(struct e1000_hw *hw)
615 {
616 s32 ret_val;
617 u16 checksum = 0;
618 u16 i, nvm_data;
619
620 DEBUGFUNC("e1000_update_nvm_checksum_i210");
621
622 /*
623 * Read the first word from the EEPROM. If this times out or fails, do
624 * not continue or we could be in for a very long wait while every
625 * EEPROM read fails
626 */
627 ret_val = e1000_read_nvm_eerd(hw, 0, 1, &nvm_data);
628 if (ret_val != E1000_SUCCESS) {
629 DEBUGOUT("EEPROM read failed\n");
630 goto out;
631 }
632
633 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
634 /*
635 * Do not use hw->nvm.ops.write, hw->nvm.ops.read
636 * because we do not want to take the synchronization
637 * semaphores twice here.
638 */
639
640 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
641 ret_val = e1000_read_nvm_eerd(hw, i, 1, &nvm_data);
642 if (ret_val) {
643 hw->nvm.ops.release(hw);
644 DEBUGOUT("NVM Read Error while updating checksum.\n");
645 goto out;
646 }
647 checksum += nvm_data;
648 }
649 checksum = (u16) NVM_SUM - checksum;
650 ret_val = e1000_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
651 &checksum);
652 if (ret_val != E1000_SUCCESS) {
653 hw->nvm.ops.release(hw);
654 DEBUGOUT("NVM Write Error while updating checksum.\n");
655 goto out;
656 }
657
658 hw->nvm.ops.release(hw);
659
660 ret_val = e1000_update_flash_i210(hw);
661 } else {
662 ret_val = E1000_ERR_SWFW_SYNC;
663 }
664 out:
665 return ret_val;
666 }
667
668 /**
669 * e1000_get_flash_presence_i210 - Check if flash device is detected.
670 * @hw: pointer to the HW structure
671 *
672 **/
e1000_get_flash_presence_i210(struct e1000_hw * hw)673 bool e1000_get_flash_presence_i210(struct e1000_hw *hw)
674 {
675 u32 eec = 0;
676 bool ret_val = false;
677
678 DEBUGFUNC("e1000_get_flash_presence_i210");
679
680 eec = E1000_READ_REG(hw, E1000_EECD);
681
682 if (eec & E1000_EECD_FLASH_DETECTED_I210)
683 ret_val = true;
684
685 return ret_val;
686 }
687
688 /**
689 * e1000_update_flash_i210 - Commit EEPROM to the flash
690 * @hw: pointer to the HW structure
691 *
692 **/
e1000_update_flash_i210(struct e1000_hw * hw)693 s32 e1000_update_flash_i210(struct e1000_hw *hw)
694 {
695 s32 ret_val;
696 u32 flup;
697
698 DEBUGFUNC("e1000_update_flash_i210");
699
700 ret_val = e1000_pool_flash_update_done_i210(hw);
701 if (ret_val == -E1000_ERR_NVM) {
702 DEBUGOUT("Flash update time out\n");
703 goto out;
704 }
705
706 flup = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD_I210;
707 E1000_WRITE_REG(hw, E1000_EECD, flup);
708
709 ret_val = e1000_pool_flash_update_done_i210(hw);
710 if (ret_val == E1000_SUCCESS)
711 DEBUGOUT("Flash update complete\n");
712 else
713 DEBUGOUT("Flash update time out\n");
714
715 out:
716 return ret_val;
717 }
718
719 /**
720 * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
721 * @hw: pointer to the HW structure
722 *
723 **/
e1000_pool_flash_update_done_i210(struct e1000_hw * hw)724 s32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
725 {
726 s32 ret_val = -E1000_ERR_NVM;
727 u32 i, reg;
728
729 DEBUGFUNC("e1000_pool_flash_update_done_i210");
730
731 for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
732 reg = E1000_READ_REG(hw, E1000_EECD);
733 if (reg & E1000_EECD_FLUDONE_I210) {
734 ret_val = E1000_SUCCESS;
735 break;
736 }
737 usec_delay(5);
738 }
739
740 return ret_val;
741 }
742
743 /**
744 * e1000_init_nvm_params_i210 - Initialize i210 NVM function pointers
745 * @hw: pointer to the HW structure
746 *
747 * Initialize the i210/i211 NVM parameters and function pointers.
748 **/
e1000_init_nvm_params_i210(struct e1000_hw * hw)749 static s32 e1000_init_nvm_params_i210(struct e1000_hw *hw)
750 {
751 s32 ret_val;
752 struct e1000_nvm_info *nvm = &hw->nvm;
753
754 DEBUGFUNC("e1000_init_nvm_params_i210");
755
756 ret_val = e1000_init_nvm_params_82575(hw);
757 nvm->ops.acquire = e1000_acquire_nvm_i210;
758 nvm->ops.release = e1000_release_nvm_i210;
759 nvm->ops.valid_led_default = e1000_valid_led_default_i210;
760 if (e1000_get_flash_presence_i210(hw)) {
761 hw->nvm.type = e1000_nvm_flash_hw;
762 nvm->ops.read = e1000_read_nvm_srrd_i210;
763 nvm->ops.write = e1000_write_nvm_srwr_i210;
764 nvm->ops.validate = e1000_validate_nvm_checksum_i210;
765 nvm->ops.update = e1000_update_nvm_checksum_i210;
766 } else {
767 hw->nvm.type = e1000_nvm_invm;
768 nvm->ops.read = e1000_read_invm_i210;
769 nvm->ops.write = e1000_null_write_nvm;
770 nvm->ops.validate = e1000_null_ops_generic;
771 nvm->ops.update = e1000_null_ops_generic;
772 }
773 return ret_val;
774 }
775
776 /**
777 * e1000_init_function_pointers_i210 - Init func ptrs.
778 * @hw: pointer to the HW structure
779 *
780 * Called to initialize all function pointers and parameters.
781 **/
e1000_init_function_pointers_i210(struct e1000_hw * hw)782 void e1000_init_function_pointers_i210(struct e1000_hw *hw)
783 {
784 e1000_init_function_pointers_82575(hw);
785 hw->nvm.ops.init_params = e1000_init_nvm_params_i210;
786 }
787
788 /**
789 * e1000_valid_led_default_i210 - Verify a valid default LED config
790 * @hw: pointer to the HW structure
791 * @data: pointer to the NVM (EEPROM)
792 *
793 * Read the EEPROM for the current default LED configuration. If the
794 * LED configuration is not valid, set to a valid LED configuration.
795 **/
e1000_valid_led_default_i210(struct e1000_hw * hw,u16 * data)796 static s32 e1000_valid_led_default_i210(struct e1000_hw *hw, u16 *data)
797 {
798 s32 ret_val;
799
800 DEBUGFUNC("e1000_valid_led_default_i210");
801
802 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
803 if (ret_val) {
804 DEBUGOUT("NVM Read Error\n");
805 goto out;
806 }
807
808 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
809 switch (hw->phy.media_type) {
810 case e1000_media_type_internal_serdes:
811 *data = ID_LED_DEFAULT_I210_SERDES;
812 break;
813 case e1000_media_type_copper:
814 default:
815 *data = ID_LED_DEFAULT_I210;
816 break;
817 }
818 }
819 out:
820 return ret_val;
821 }
822
823 /**
824 * e1000_pll_workaround_i210
825 * @hw: pointer to the HW structure
826 *
827 * Works around an errata in the PLL circuit where it occasionally
828 * provides the wrong clock frequency after power up.
829 **/
e1000_pll_workaround_i210(struct e1000_hw * hw)830 static s32 e1000_pll_workaround_i210(struct e1000_hw *hw)
831 {
832 s32 ret_val;
833 u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val;
834 u16 nvm_word, phy_word, pci_word, tmp_nvm;
835 int i;
836
837 /* Get PHY semaphore */
838 hw->phy.ops.acquire(hw);
839 /* Get and set needed register values */
840 wuc = E1000_READ_REG(hw, E1000_WUC);
841 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
842 reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO;
843 E1000_WRITE_REG(hw, E1000_MDICNFG, reg_val);
844
845 /* Get data from NVM, or set default */
846 ret_val = e1000_read_invm_word_i210(hw, E1000_INVM_AUTOLOAD,
847 &nvm_word);
848 if (ret_val != E1000_SUCCESS)
849 nvm_word = E1000_INVM_DEFAULT_AL;
850 tmp_nvm = nvm_word | E1000_INVM_PLL_WO_VAL;
851 phy_word = E1000_PHY_PLL_UNCONF;
852 for (i = 0; i < E1000_MAX_PLL_TRIES; i++) {
853 /* check current state directly from internal PHY */
854 e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, 0xFC);
855 usec_delay(20);
856 e1000_read_phy_reg_mdic(hw, E1000_PHY_PLL_FREQ_REG, &phy_word);
857 usec_delay(20);
858 e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, 0);
859 if ((phy_word & E1000_PHY_PLL_UNCONF)
860 != E1000_PHY_PLL_UNCONF) {
861 ret_val = E1000_SUCCESS;
862 break;
863 } else {
864 ret_val = -E1000_ERR_PHY;
865 }
866 /* directly reset the internal PHY */
867 ctrl = E1000_READ_REG(hw, E1000_CTRL);
868 E1000_WRITE_REG(hw, E1000_CTRL, ctrl|E1000_CTRL_PHY_RST);
869
870 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
871 ctrl_ext |= (E1000_CTRL_EXT_PHYPDEN | E1000_CTRL_EXT_SDLPE);
872 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
873
874 E1000_WRITE_REG(hw, E1000_WUC, 0);
875 reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16);
876 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val);
877
878 e1000_read_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);
879 pci_word |= E1000_PCI_PMCSR_D3;
880 e1000_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);
881 msec_delay(1);
882 pci_word &= ~E1000_PCI_PMCSR_D3;
883 e1000_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);
884 reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16);
885 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val);
886
887 /* restore WUC register */
888 E1000_WRITE_REG(hw, E1000_WUC, wuc);
889 }
890 /* restore MDICNFG setting */
891 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
892 /* Release PHY semaphore */
893 hw->phy.ops.release(hw);
894 return ret_val;
895 }
896
897 /**
898 * e1000_get_cfg_done_i210 - Read config done bit
899 * @hw: pointer to the HW structure
900 *
901 * Read the management control register for the config done bit for
902 * completion status. NOTE: silicon which is EEPROM-less will fail trying
903 * to read the config done bit, so an error is *ONLY* logged and returns
904 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
905 * would not be able to be reset or change link.
906 **/
e1000_get_cfg_done_i210(struct e1000_hw * hw)907 static s32 e1000_get_cfg_done_i210(struct e1000_hw *hw)
908 {
909 s32 timeout = PHY_CFG_TIMEOUT;
910 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
911
912 DEBUGFUNC("e1000_get_cfg_done_i210");
913
914 while (timeout) {
915 if (E1000_READ_REG(hw, E1000_EEMNGCTL_I210) & mask)
916 break;
917 msec_delay(1);
918 timeout--;
919 }
920 if (!timeout)
921 DEBUGOUT("MNG configuration cycle has not completed.\n");
922
923 return E1000_SUCCESS;
924 }
925
926 /**
927 * e1000_init_hw_i210 - Init hw for I210/I211
928 * @hw: pointer to the HW structure
929 *
930 * Called to initialize hw for i210 hw family.
931 **/
e1000_init_hw_i210(struct e1000_hw * hw)932 s32 e1000_init_hw_i210(struct e1000_hw *hw)
933 {
934 struct e1000_mac_info *mac = &hw->mac;
935 s32 ret_val;
936
937 DEBUGFUNC("e1000_init_hw_i210");
938 if ((hw->mac.type >= e1000_i210) &&
939 !(e1000_get_flash_presence_i210(hw))) {
940 ret_val = e1000_pll_workaround_i210(hw);
941 if (ret_val != E1000_SUCCESS)
942 return ret_val;
943 }
944 hw->phy.ops.get_cfg_done = e1000_get_cfg_done_i210;
945
946 /* Initialize identification LED */
947 mac->ops.id_led_init(hw);
948
949 ret_val = e1000_init_hw_base(hw);
950 return ret_val;
951 }
952