1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34
35 /*
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82576 Gigabit Network Connection
40 * 82576 Quad Port Gigabit Mezzanine Adapter
41 * 82580 Gigabit Network Connection
42 * I350 Gigabit Network Connection
43 */
44
45 #include "e1000_api.h"
46 #include "e1000_i210.h"
47
48 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
49 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
50 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
51 static void e1000_release_nvm_82575(struct e1000_hw *hw);
52 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
53 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
54 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
55 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
56 u16 *duplex);
57 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
58 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
59 u16 *data);
60 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
61 static s32 e1000_init_hw_82575(struct e1000_hw *hw);
62 static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
63 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
64 u32 offset, u16 *data);
65 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
66 u32 offset, u16 data);
67 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
68 bool active);
69 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
70 bool active);
71 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
72 bool active);
73 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
74 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
75 static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
76 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
77 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
78 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
79 u32 offset, u16 data);
80 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
81 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
82 u16 *speed, u16 *duplex);
83 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
84 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
85 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
86 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
87 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
88 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
89 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
90 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
91 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
92 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
93 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
94 u16 offset);
95 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
96 u16 offset);
97 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
98 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
99 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
100
101 static void e1000_i2c_start(struct e1000_hw *hw);
102 static void e1000_i2c_stop(struct e1000_hw *hw);
103 static void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
104 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
105 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
106 static void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
107 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
108 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
109 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
110 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
111 static bool e1000_get_i2c_data(u32 *i2cctl);
112
113 static const u16 e1000_82580_rxpbs_table[] = {
114 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
115 #define E1000_82580_RXPBS_TABLE_SIZE \
116 (sizeof(e1000_82580_rxpbs_table) / \
117 sizeof(e1000_82580_rxpbs_table[0]))
118
119
120 /**
121 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
122 * @hw: pointer to the HW structure
123 *
124 * Called to determine if the I2C pins are being used for I2C or as an
125 * external MDIO interface since the two options are mutually exclusive.
126 **/
e1000_sgmii_uses_mdio_82575(struct e1000_hw * hw)127 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
128 {
129 u32 reg = 0;
130 bool ext_mdio = false;
131
132 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
133
134 switch (hw->mac.type) {
135 case e1000_82575:
136 case e1000_82576:
137 reg = E1000_READ_REG(hw, E1000_MDIC);
138 ext_mdio = !!(reg & E1000_MDIC_DEST);
139 break;
140 case e1000_82580:
141 case e1000_i350:
142 case e1000_i354:
143 case e1000_i210:
144 case e1000_i211:
145 reg = E1000_READ_REG(hw, E1000_MDICNFG);
146 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
147 break;
148 default:
149 break;
150 }
151 return ext_mdio;
152 }
153
154 /**
155 * e1000_init_phy_params_82575 - Initialize PHY function ptrs
156 * @hw: pointer to the HW structure
157 **/
e1000_init_phy_params_82575(struct e1000_hw * hw)158 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
159 {
160 struct e1000_phy_info *phy = &hw->phy;
161 s32 ret_val = E1000_SUCCESS;
162 u32 ctrl_ext;
163
164 DEBUGFUNC("e1000_init_phy_params_82575");
165
166 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
167 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
168
169 if (hw->phy.media_type != e1000_media_type_copper) {
170 phy->type = e1000_phy_none;
171 goto out;
172 }
173
174 phy->ops.power_up = e1000_power_up_phy_copper;
175 phy->ops.power_down = e1000_power_down_phy_copper_base;
176
177 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
178 phy->reset_delay_us = 100;
179
180 phy->ops.acquire = e1000_acquire_phy_base;
181 phy->ops.check_reset_block = e1000_check_reset_block_generic;
182 phy->ops.commit = e1000_phy_sw_reset_generic;
183 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
184 phy->ops.release = e1000_release_phy_base;
185
186 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
187
188 if (e1000_sgmii_active_82575(hw)) {
189 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
190 ctrl_ext |= E1000_CTRL_I2C_ENA;
191 } else {
192 phy->ops.reset = e1000_phy_hw_reset_generic;
193 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
194 }
195
196 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
197 e1000_reset_mdicnfg_82580(hw);
198
199 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
200 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
201 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
202 } else {
203 switch (hw->mac.type) {
204 case e1000_82580:
205 case e1000_i350:
206 case e1000_i354:
207 phy->ops.read_reg = e1000_read_phy_reg_82580;
208 phy->ops.write_reg = e1000_write_phy_reg_82580;
209 break;
210 case e1000_i210:
211 case e1000_i211:
212 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
213 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
214 break;
215 default:
216 phy->ops.read_reg = e1000_read_phy_reg_igp;
217 phy->ops.write_reg = e1000_write_phy_reg_igp;
218 }
219 }
220
221 /* Set phy->phy_addr and phy->id. */
222 ret_val = e1000_get_phy_id_82575(hw);
223
224 /* Verify phy id and set remaining function pointers */
225 switch (phy->id) {
226 case M88E1543_E_PHY_ID:
227 case M88E1512_E_PHY_ID:
228 case I347AT4_E_PHY_ID:
229 case M88E1112_E_PHY_ID:
230 case M88E1340M_E_PHY_ID:
231 phy->type = e1000_phy_m88;
232 phy->ops.check_polarity = e1000_check_polarity_m88;
233 phy->ops.get_info = e1000_get_phy_info_m88;
234 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
235 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
236 break;
237 case M88E1111_I_PHY_ID:
238 phy->type = e1000_phy_m88;
239 phy->ops.check_polarity = e1000_check_polarity_m88;
240 phy->ops.get_info = e1000_get_phy_info_m88;
241 phy->ops.get_cable_length = e1000_get_cable_length_m88;
242 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
243 break;
244 case IGP03E1000_E_PHY_ID:
245 case IGP04E1000_E_PHY_ID:
246 phy->type = e1000_phy_igp_3;
247 phy->ops.check_polarity = e1000_check_polarity_igp;
248 phy->ops.get_info = e1000_get_phy_info_igp;
249 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
250 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
251 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
252 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
253 break;
254 case I82580_I_PHY_ID:
255 case I350_I_PHY_ID:
256 phy->type = e1000_phy_82580;
257 phy->ops.check_polarity = e1000_check_polarity_82577;
258 phy->ops.get_info = e1000_get_phy_info_82577;
259 phy->ops.get_cable_length = e1000_get_cable_length_82577;
260 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
261 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
262 phy->ops.force_speed_duplex =
263 e1000_phy_force_speed_duplex_82577;
264 break;
265 case I210_I_PHY_ID:
266 phy->type = e1000_phy_i210;
267 phy->ops.check_polarity = e1000_check_polarity_m88;
268 phy->ops.get_info = e1000_get_phy_info_m88;
269 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
270 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
271 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
272 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
273 break;
274 default:
275 ret_val = -E1000_ERR_PHY;
276 goto out;
277 }
278
279 /* Check if this PHY is configured for media swap. */
280 switch (phy->id) {
281 case M88E1112_E_PHY_ID:
282 {
283 u16 data;
284
285 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2);
286 if (ret_val)
287 goto out;
288 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1,
289 &data);
290 if (ret_val)
291 goto out;
292
293 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
294 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
295 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
296 data == E1000_M88E1112_AUTO_COPPER_BASEX)
297 hw->mac.ops.check_for_link =
298 e1000_check_for_link_media_swap;
299 break;
300 }
301 case M88E1512_E_PHY_ID:
302 {
303 ret_val = e1000_initialize_M88E1512_phy(hw);
304 break;
305 }
306 case M88E1543_E_PHY_ID:
307 {
308 ret_val = e1000_initialize_M88E1543_phy(hw);
309 break;
310 }
311 default:
312 goto out;
313 }
314
315 out:
316 return ret_val;
317 }
318
319 /**
320 * e1000_init_mac_params_82575 - Init MAC func ptrs.
321 * @hw: pointer to the HW structure
322 **/
e1000_init_mac_params_82575(struct e1000_hw * hw)323 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
324 {
325 struct e1000_mac_info *mac = &hw->mac;
326 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
327
328 DEBUGFUNC("e1000_init_mac_params_82575");
329
330 /* Initialize function pointer */
331 e1000_init_mac_ops_generic(hw);
332
333 /* Derives media type */
334 e1000_get_media_type_82575(hw);
335 /* Set MTA register count */
336 mac->mta_reg_count = 128;
337 /* Set UTA register count */
338 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
339 /* Set RAR entry count */
340 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
341 if (mac->type == e1000_82576)
342 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
343 if (mac->type == e1000_82580)
344 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
345 if (mac->type == e1000_i350 || mac->type == e1000_i354)
346 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
347
348 /* Enable EEE default settings for EEE supported devices */
349 if (mac->type >= e1000_i350)
350 dev_spec->eee_disable = false;
351
352 /* Allow a single clear of the SW semaphore on I210 and newer */
353 if (mac->type >= e1000_i210)
354 dev_spec->clear_semaphore_once = true;
355
356 /* Set if part includes ASF firmware */
357 mac->asf_firmware_present = true;
358 /* FWSM register */
359 mac->has_fwsm = true;
360 /* ARC supported; valid only if manageability features are enabled. */
361 mac->arc_subsystem_valid =
362 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
363
364 /* Function pointers */
365
366 /* bus type/speed/width */
367 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
368 /* reset */
369 if (mac->type >= e1000_82580)
370 mac->ops.reset_hw = e1000_reset_hw_82580;
371 else
372 mac->ops.reset_hw = e1000_reset_hw_82575;
373 /* HW initialization */
374 if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
375 mac->ops.init_hw = e1000_init_hw_i210;
376 else
377 mac->ops.init_hw = e1000_init_hw_82575;
378 /* link setup */
379 mac->ops.setup_link = e1000_setup_link_generic;
380 /* physical interface link setup */
381 mac->ops.setup_physical_interface =
382 (hw->phy.media_type == e1000_media_type_copper)
383 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
384 /* physical interface shutdown */
385 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
386 /* physical interface power up */
387 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
388 /* check for link */
389 mac->ops.check_for_link = e1000_check_for_link_82575;
390 /* read mac address */
391 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
392 /* configure collision distance */
393 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
394 /* multicast address update */
395 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
396 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
397 /* writing VFTA */
398 mac->ops.write_vfta = e1000_write_vfta_i350;
399 /* clearing VFTA */
400 mac->ops.clear_vfta = e1000_clear_vfta_i350;
401 } else {
402 /* writing VFTA */
403 mac->ops.write_vfta = e1000_write_vfta_generic;
404 /* clearing VFTA */
405 mac->ops.clear_vfta = e1000_clear_vfta_generic;
406 }
407 if (hw->mac.type >= e1000_82580)
408 mac->ops.validate_mdi_setting =
409 e1000_validate_mdi_setting_crossover_generic;
410 /* ID LED init */
411 mac->ops.id_led_init = e1000_id_led_init_generic;
412 /* blink LED */
413 mac->ops.blink_led = e1000_blink_led_generic;
414 /* setup LED */
415 mac->ops.setup_led = e1000_setup_led_generic;
416 /* cleanup LED */
417 mac->ops.cleanup_led = e1000_cleanup_led_generic;
418 /* turn on/off LED */
419 mac->ops.led_on = e1000_led_on_generic;
420 mac->ops.led_off = e1000_led_off_generic;
421 /* clear hardware counters */
422 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
423 /* link info */
424 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
425 /* acquire SW_FW sync */
426 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync;
427 /* release SW_FW sync */
428 mac->ops.release_swfw_sync = e1000_release_swfw_sync;
429 if (mac->type == e1000_i210 || mac->type == e1000_i211) {
430 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
431 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
432 }
433
434 /* set lan id for port to determine which phy lock to use */
435 hw->mac.ops.set_lan_id(hw);
436
437 return E1000_SUCCESS;
438 }
439
440 /**
441 * e1000_init_nvm_params_82575 - Initialize NVM function ptrs
442 * @hw: pointer to the HW structure
443 **/
e1000_init_nvm_params_82575(struct e1000_hw * hw)444 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
445 {
446 struct e1000_nvm_info *nvm = &hw->nvm;
447 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
448 u16 size;
449
450 DEBUGFUNC("e1000_init_nvm_params_82575");
451
452 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
453 E1000_EECD_SIZE_EX_SHIFT);
454 /* Added to a constant, "size" becomes the left-shift value
455 * for setting word_size.
456 */
457 size += NVM_WORD_SIZE_BASE_SHIFT;
458
459 /* Just in case size is out of range, cap it to the largest
460 * EEPROM size supported
461 */
462 if (size > 15)
463 size = 15;
464
465 nvm->word_size = 1 << size;
466 if (hw->mac.type < e1000_i210) {
467 nvm->opcode_bits = 8;
468 nvm->delay_usec = 1;
469
470 switch (nvm->override) {
471 case e1000_nvm_override_spi_large:
472 nvm->page_size = 32;
473 nvm->address_bits = 16;
474 break;
475 case e1000_nvm_override_spi_small:
476 nvm->page_size = 8;
477 nvm->address_bits = 8;
478 break;
479 default:
480 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
481 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
482 16 : 8;
483 break;
484 }
485 if (nvm->word_size == (1 << 15))
486 nvm->page_size = 128;
487
488 nvm->type = e1000_nvm_eeprom_spi;
489 } else {
490 nvm->type = e1000_nvm_flash_hw;
491 }
492
493 /* Function Pointers */
494 nvm->ops.acquire = e1000_acquire_nvm_82575;
495 nvm->ops.release = e1000_release_nvm_82575;
496 if (nvm->word_size < (1 << 15))
497 nvm->ops.read = e1000_read_nvm_eerd;
498 else
499 nvm->ops.read = e1000_read_nvm_spi;
500
501 nvm->ops.write = e1000_write_nvm_spi;
502 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
503 nvm->ops.update = e1000_update_nvm_checksum_generic;
504 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
505
506 /* override generic family function pointers for specific descendants */
507 switch (hw->mac.type) {
508 case e1000_82580:
509 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
510 nvm->ops.update = e1000_update_nvm_checksum_82580;
511 break;
512 case e1000_i350:
513 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
514 nvm->ops.update = e1000_update_nvm_checksum_i350;
515 break;
516 default:
517 break;
518 }
519
520 return E1000_SUCCESS;
521 }
522
523 /**
524 * e1000_init_function_pointers_82575 - Init func ptrs.
525 * @hw: pointer to the HW structure
526 *
527 * Called to initialize all function pointers and parameters.
528 **/
e1000_init_function_pointers_82575(struct e1000_hw * hw)529 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
530 {
531 DEBUGFUNC("e1000_init_function_pointers_82575");
532
533 hw->mac.ops.init_params = e1000_init_mac_params_82575;
534 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
535 hw->phy.ops.init_params = e1000_init_phy_params_82575;
536 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
537 }
538
539 /**
540 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
541 * @hw: pointer to the HW structure
542 * @offset: register offset to be read
543 * @data: pointer to the read data
544 *
545 * Reads the PHY register at offset using the serial gigabit media independent
546 * interface and stores the retrieved information in data.
547 **/
e1000_read_phy_reg_sgmii_82575(struct e1000_hw * hw,u32 offset,u16 * data)548 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
549 u16 *data)
550 {
551 s32 ret_val = -E1000_ERR_PARAM;
552
553 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
554
555 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
556 DEBUGOUT1("PHY Address %u is out of range\n", offset);
557 goto out;
558 }
559
560 ret_val = hw->phy.ops.acquire(hw);
561 if (ret_val)
562 goto out;
563
564 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
565
566 hw->phy.ops.release(hw);
567
568 out:
569 return ret_val;
570 }
571
572 /**
573 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
574 * @hw: pointer to the HW structure
575 * @offset: register offset to write to
576 * @data: data to write at register offset
577 *
578 * Writes the data to PHY register at the offset using the serial gigabit
579 * media independent interface.
580 **/
e1000_write_phy_reg_sgmii_82575(struct e1000_hw * hw,u32 offset,u16 data)581 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
582 u16 data)
583 {
584 s32 ret_val = -E1000_ERR_PARAM;
585
586 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
587
588 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
589 DEBUGOUT1("PHY Address %d is out of range\n", offset);
590 goto out;
591 }
592
593 ret_val = hw->phy.ops.acquire(hw);
594 if (ret_val)
595 goto out;
596
597 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
598
599 hw->phy.ops.release(hw);
600
601 out:
602 return ret_val;
603 }
604
605 /**
606 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
607 * @hw: pointer to the HW structure
608 *
609 * Retrieves the PHY address and ID for both PHY's which do and do not use
610 * sgmi interface.
611 **/
e1000_get_phy_id_82575(struct e1000_hw * hw)612 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
613 {
614 struct e1000_phy_info *phy = &hw->phy;
615 s32 ret_val = E1000_SUCCESS;
616 u16 phy_id;
617 u32 ctrl_ext;
618 u32 mdic;
619
620 DEBUGFUNC("e1000_get_phy_id_82575");
621
622 /* some i354 devices need an extra read for phy id */
623 if (hw->mac.type == e1000_i354)
624 e1000_get_phy_id(hw);
625
626 /*
627 * For SGMII PHYs, we try the list of possible addresses until
628 * we find one that works. For non-SGMII PHYs
629 * (e.g. integrated copper PHYs), an address of 1 should
630 * work. The result of this function should mean phy->phy_addr
631 * and phy->id are set correctly.
632 */
633 if (!e1000_sgmii_active_82575(hw)) {
634 phy->addr = 1;
635 ret_val = e1000_get_phy_id(hw);
636 goto out;
637 }
638
639 if (e1000_sgmii_uses_mdio_82575(hw)) {
640 switch (hw->mac.type) {
641 case e1000_82575:
642 case e1000_82576:
643 mdic = E1000_READ_REG(hw, E1000_MDIC);
644 mdic &= E1000_MDIC_PHY_MASK;
645 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
646 break;
647 case e1000_82580:
648 case e1000_i350:
649 case e1000_i354:
650 case e1000_i210:
651 case e1000_i211:
652 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
653 mdic &= E1000_MDICNFG_PHY_MASK;
654 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
655 break;
656 default:
657 ret_val = -E1000_ERR_PHY;
658 goto out;
659 break;
660 }
661 ret_val = e1000_get_phy_id(hw);
662 goto out;
663 }
664
665 /* Power on sgmii phy if it is disabled */
666 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
667 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
668 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
669 E1000_WRITE_FLUSH(hw);
670 msec_delay(300);
671
672 /*
673 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
674 * Therefore, we need to test 1-7
675 */
676 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
677 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
678 if (ret_val == E1000_SUCCESS) {
679 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
680 phy_id, phy->addr);
681 /*
682 * At the time of this writing, The M88 part is
683 * the only supported SGMII PHY product.
684 */
685 if (phy_id == M88_VENDOR)
686 break;
687 } else {
688 DEBUGOUT1("PHY address %u was unreadable\n",
689 phy->addr);
690 }
691 }
692
693 /* A valid PHY type couldn't be found. */
694 if (phy->addr == 8) {
695 phy->addr = 0;
696 ret_val = -E1000_ERR_PHY;
697 } else {
698 ret_val = e1000_get_phy_id(hw);
699 }
700
701 /* restore previous sfp cage power state */
702 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
703
704 out:
705 return ret_val;
706 }
707
708 /**
709 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
710 * @hw: pointer to the HW structure
711 *
712 * Resets the PHY using the serial gigabit media independent interface.
713 **/
e1000_phy_hw_reset_sgmii_82575(struct e1000_hw * hw)714 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
715 {
716 s32 ret_val = E1000_SUCCESS;
717 struct e1000_phy_info *phy = &hw->phy;
718
719 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
720
721 /*
722 * This isn't a true "hard" reset, but is the only reset
723 * available to us at this time.
724 */
725
726 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
727
728 if (!(hw->phy.ops.write_reg))
729 goto out;
730
731 /*
732 * SFP documentation requires the following to configure the SPF module
733 * to work on SGMII. No further documentation is given.
734 */
735 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
736 if (ret_val)
737 goto out;
738
739 ret_val = hw->phy.ops.commit(hw);
740 if (ret_val)
741 goto out;
742
743 if (phy->id == M88E1512_E_PHY_ID)
744 ret_val = e1000_initialize_M88E1512_phy(hw);
745 out:
746 return ret_val;
747 }
748
749 /**
750 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
751 * @hw: pointer to the HW structure
752 * @active: true to enable LPLU, false to disable
753 *
754 * Sets the LPLU D0 state according to the active flag. When
755 * activating LPLU this function also disables smart speed
756 * and vice versa. LPLU will not be activated unless the
757 * device autonegotiation advertisement meets standards of
758 * either 10 or 10/100 or 10/100/1000 at all duplexes.
759 * This is a function pointer entry point only called by
760 * PHY setup routines.
761 **/
e1000_set_d0_lplu_state_82575(struct e1000_hw * hw,bool active)762 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
763 {
764 struct e1000_phy_info *phy = &hw->phy;
765 s32 ret_val = E1000_SUCCESS;
766 u16 data;
767
768 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
769
770 if (!(hw->phy.ops.read_reg))
771 goto out;
772
773 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
774 if (ret_val)
775 goto out;
776
777 if (active) {
778 data |= IGP02E1000_PM_D0_LPLU;
779 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
780 data);
781 if (ret_val)
782 goto out;
783
784 /* When LPLU is enabled, we should disable SmartSpeed */
785 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
786 &data);
787 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
788 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
789 data);
790 if (ret_val)
791 goto out;
792 } else {
793 data &= ~IGP02E1000_PM_D0_LPLU;
794 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
795 data);
796 /*
797 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
798 * during Dx states where the power conservation is most
799 * important. During driver activity we should enable
800 * SmartSpeed, so performance is maintained.
801 */
802 if (phy->smart_speed == e1000_smart_speed_on) {
803 ret_val = phy->ops.read_reg(hw,
804 IGP01E1000_PHY_PORT_CONFIG,
805 &data);
806 if (ret_val)
807 goto out;
808
809 data |= IGP01E1000_PSCFR_SMART_SPEED;
810 ret_val = phy->ops.write_reg(hw,
811 IGP01E1000_PHY_PORT_CONFIG,
812 data);
813 if (ret_val)
814 goto out;
815 } else if (phy->smart_speed == e1000_smart_speed_off) {
816 ret_val = phy->ops.read_reg(hw,
817 IGP01E1000_PHY_PORT_CONFIG,
818 &data);
819 if (ret_val)
820 goto out;
821
822 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
823 ret_val = phy->ops.write_reg(hw,
824 IGP01E1000_PHY_PORT_CONFIG,
825 data);
826 if (ret_val)
827 goto out;
828 }
829 }
830
831 out:
832 return ret_val;
833 }
834
835 /**
836 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
837 * @hw: pointer to the HW structure
838 * @active: true to enable LPLU, false to disable
839 *
840 * Sets the LPLU D0 state according to the active flag. When
841 * activating LPLU this function also disables smart speed
842 * and vice versa. LPLU will not be activated unless the
843 * device autonegotiation advertisement meets standards of
844 * either 10 or 10/100 or 10/100/1000 at all duplexes.
845 * This is a function pointer entry point only called by
846 * PHY setup routines.
847 **/
e1000_set_d0_lplu_state_82580(struct e1000_hw * hw,bool active)848 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
849 {
850 struct e1000_phy_info *phy = &hw->phy;
851 u32 data;
852
853 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
854
855 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
856
857 if (active) {
858 data |= E1000_82580_PM_D0_LPLU;
859
860 /* When LPLU is enabled, we should disable SmartSpeed */
861 data &= ~E1000_82580_PM_SPD;
862 } else {
863 data &= ~E1000_82580_PM_D0_LPLU;
864
865 /*
866 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
867 * during Dx states where the power conservation is most
868 * important. During driver activity we should enable
869 * SmartSpeed, so performance is maintained.
870 */
871 if (phy->smart_speed == e1000_smart_speed_on)
872 data |= E1000_82580_PM_SPD;
873 else if (phy->smart_speed == e1000_smart_speed_off)
874 data &= ~E1000_82580_PM_SPD;
875 }
876
877 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
878 return E1000_SUCCESS;
879 }
880
881 /**
882 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
883 * @hw: pointer to the HW structure
884 * @active: boolean used to enable/disable lplu
885 *
886 * Success returns 0, Failure returns 1
887 *
888 * The low power link up (lplu) state is set to the power management level D3
889 * and SmartSpeed is disabled when active is true, else clear lplu for D3
890 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
891 * is used during Dx states where the power conservation is most important.
892 * During driver activity, SmartSpeed should be enabled so performance is
893 * maintained.
894 **/
e1000_set_d3_lplu_state_82580(struct e1000_hw * hw,bool active)895 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
896 {
897 struct e1000_phy_info *phy = &hw->phy;
898 u32 data;
899
900 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
901
902 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
903
904 if (!active) {
905 data &= ~E1000_82580_PM_D3_LPLU;
906 /*
907 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
908 * during Dx states where the power conservation is most
909 * important. During driver activity we should enable
910 * SmartSpeed, so performance is maintained.
911 */
912 if (phy->smart_speed == e1000_smart_speed_on)
913 data |= E1000_82580_PM_SPD;
914 else if (phy->smart_speed == e1000_smart_speed_off)
915 data &= ~E1000_82580_PM_SPD;
916 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
917 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
918 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
919 data |= E1000_82580_PM_D3_LPLU;
920 /* When LPLU is enabled, we should disable SmartSpeed */
921 data &= ~E1000_82580_PM_SPD;
922 }
923
924 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
925 return E1000_SUCCESS;
926 }
927
928 /**
929 * e1000_acquire_nvm_82575 - Request for access to EEPROM
930 * @hw: pointer to the HW structure
931 *
932 * Acquire the necessary semaphores for exclusive access to the EEPROM.
933 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
934 * Return successful if access grant bit set, else clear the request for
935 * EEPROM access and return -E1000_ERR_NVM (-1).
936 **/
e1000_acquire_nvm_82575(struct e1000_hw * hw)937 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
938 {
939 s32 ret_val = E1000_SUCCESS;
940
941 DEBUGFUNC("e1000_acquire_nvm_82575");
942
943 ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
944 if (ret_val)
945 goto out;
946
947 /*
948 * Check if there is some access
949 * error this access may hook on
950 */
951 if (hw->mac.type == e1000_i350) {
952 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
953 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
954 E1000_EECD_TIMEOUT)) {
955 /* Clear all access error flags */
956 E1000_WRITE_REG(hw, E1000_EECD, eecd |
957 E1000_EECD_ERROR_CLR);
958 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
959 }
960 }
961
962 if (hw->mac.type == e1000_82580) {
963 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
964 if (eecd & E1000_EECD_BLOCKED) {
965 /* Clear access error flag */
966 E1000_WRITE_REG(hw, E1000_EECD, eecd |
967 E1000_EECD_BLOCKED);
968 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
969 }
970 }
971
972 ret_val = e1000_acquire_nvm_generic(hw);
973 if (ret_val)
974 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
975
976 out:
977 return ret_val;
978 }
979
980 /**
981 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
982 * @hw: pointer to the HW structure
983 *
984 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
985 * then release the semaphores acquired.
986 **/
e1000_release_nvm_82575(struct e1000_hw * hw)987 static void e1000_release_nvm_82575(struct e1000_hw *hw)
988 {
989 DEBUGFUNC("e1000_release_nvm_82575");
990
991 e1000_release_nvm_generic(hw);
992
993 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
994 }
995
996 /**
997 * e1000_get_cfg_done_82575 - Read config done bit
998 * @hw: pointer to the HW structure
999 *
1000 * Read the management control register for the config done bit for
1001 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1002 * to read the config done bit, so an error is *ONLY* logged and returns
1003 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1004 * would not be able to be reset or change link.
1005 **/
e1000_get_cfg_done_82575(struct e1000_hw * hw)1006 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1007 {
1008 s32 timeout = PHY_CFG_TIMEOUT;
1009 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1010
1011 DEBUGFUNC("e1000_get_cfg_done_82575");
1012
1013 if (hw->bus.func == E1000_FUNC_1)
1014 mask = E1000_NVM_CFG_DONE_PORT_1;
1015 else if (hw->bus.func == E1000_FUNC_2)
1016 mask = E1000_NVM_CFG_DONE_PORT_2;
1017 else if (hw->bus.func == E1000_FUNC_3)
1018 mask = E1000_NVM_CFG_DONE_PORT_3;
1019 while (timeout) {
1020 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1021 break;
1022 msec_delay(1);
1023 timeout--;
1024 }
1025 if (!timeout)
1026 DEBUGOUT("MNG configuration cycle has not completed.\n");
1027
1028 /* If EEPROM is not marked present, init the PHY manually */
1029 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1030 (hw->phy.type == e1000_phy_igp_3))
1031 e1000_phy_init_script_igp3(hw);
1032
1033 return E1000_SUCCESS;
1034 }
1035
1036 /**
1037 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1038 * @hw: pointer to the HW structure
1039 * @speed: stores the current speed
1040 * @duplex: stores the current duplex
1041 *
1042 * This is a wrapper function, if using the serial gigabit media independent
1043 * interface, use PCS to retrieve the link speed and duplex information.
1044 * Otherwise, use the generic function to get the link speed and duplex info.
1045 **/
e1000_get_link_up_info_82575(struct e1000_hw * hw,u16 * speed,u16 * duplex)1046 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1047 u16 *duplex)
1048 {
1049 s32 ret_val;
1050
1051 DEBUGFUNC("e1000_get_link_up_info_82575");
1052
1053 if (hw->phy.media_type != e1000_media_type_copper)
1054 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1055 duplex);
1056 else
1057 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1058 duplex);
1059
1060 return ret_val;
1061 }
1062
1063 /**
1064 * e1000_check_for_link_82575 - Check for link
1065 * @hw: pointer to the HW structure
1066 *
1067 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1068 * use the generic interface for determining link.
1069 **/
e1000_check_for_link_82575(struct e1000_hw * hw)1070 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1071 {
1072 s32 ret_val;
1073 u16 speed, duplex;
1074
1075 DEBUGFUNC("e1000_check_for_link_82575");
1076
1077 if (hw->phy.media_type != e1000_media_type_copper) {
1078 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1079 &duplex);
1080 /*
1081 * Use this flag to determine if link needs to be checked or
1082 * not. If we have link clear the flag so that we do not
1083 * continue to check for link.
1084 */
1085 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1086
1087 /*
1088 * Configure Flow Control now that Auto-Neg has completed.
1089 * First, we need to restore the desired flow control
1090 * settings because we may have had to re-autoneg with a
1091 * different link partner.
1092 */
1093 ret_val = e1000_config_fc_after_link_up_generic(hw);
1094 if (ret_val)
1095 DEBUGOUT("Error configuring flow control\n");
1096 } else {
1097 ret_val = e1000_check_for_copper_link_generic(hw);
1098 }
1099
1100 return ret_val;
1101 }
1102
1103 /**
1104 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1105 * @hw: pointer to the HW structure
1106 *
1107 * Poll the M88E1112 interfaces to see which interface achieved link.
1108 */
e1000_check_for_link_media_swap(struct e1000_hw * hw)1109 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1110 {
1111 struct e1000_phy_info *phy = &hw->phy;
1112 s32 ret_val;
1113 u16 data;
1114 u8 port = 0;
1115
1116 DEBUGFUNC("e1000_check_for_link_media_swap");
1117
1118 /* Check for copper. */
1119 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1120 if (ret_val)
1121 return ret_val;
1122
1123 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1124 if (ret_val)
1125 return ret_val;
1126
1127 if (data & E1000_M88E1112_STATUS_LINK)
1128 port = E1000_MEDIA_PORT_COPPER;
1129
1130 /* Check for other. */
1131 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1132 if (ret_val)
1133 return ret_val;
1134
1135 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1136 if (ret_val)
1137 return ret_val;
1138
1139 if (data & E1000_M88E1112_STATUS_LINK)
1140 port = E1000_MEDIA_PORT_OTHER;
1141
1142 /* Determine if a swap needs to happen. */
1143 if (port && (hw->dev_spec._82575.media_port != port)) {
1144 hw->dev_spec._82575.media_port = port;
1145 hw->dev_spec._82575.media_changed = true;
1146 }
1147
1148 if (port == E1000_MEDIA_PORT_COPPER) {
1149 /* reset page to 0 */
1150 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1151 if (ret_val)
1152 return ret_val;
1153 e1000_check_for_link_82575(hw);
1154 } else {
1155 e1000_check_for_link_82575(hw);
1156 /* reset page to 0 */
1157 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1158 if (ret_val)
1159 return ret_val;
1160 }
1161
1162 return E1000_SUCCESS;
1163 }
1164
1165 /**
1166 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1167 * @hw: pointer to the HW structure
1168 **/
e1000_power_up_serdes_link_82575(struct e1000_hw * hw)1169 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1170 {
1171 u32 reg;
1172
1173 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1174
1175 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1176 !e1000_sgmii_active_82575(hw))
1177 return;
1178
1179 /* Enable PCS to turn on link */
1180 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1181 reg |= E1000_PCS_CFG_PCS_EN;
1182 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1183
1184 /* Power up the laser */
1185 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1186 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1187 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1188
1189 /* flush the write to verify completion */
1190 E1000_WRITE_FLUSH(hw);
1191 msec_delay(1);
1192 }
1193
1194 /**
1195 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1196 * @hw: pointer to the HW structure
1197 * @speed: stores the current speed
1198 * @duplex: stores the current duplex
1199 *
1200 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1201 * duplex, then store the values in the pointers provided.
1202 **/
e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw * hw,u16 * speed,u16 * duplex)1203 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1204 u16 *speed, u16 *duplex)
1205 {
1206 struct e1000_mac_info *mac = &hw->mac;
1207 u32 pcs;
1208 u32 status;
1209
1210 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1211
1212 /*
1213 * Read the PCS Status register for link state. For non-copper mode,
1214 * the status register is not accurate. The PCS status register is
1215 * used instead.
1216 */
1217 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1218
1219 /*
1220 * The link up bit determines when link is up on autoneg.
1221 */
1222 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1223 mac->serdes_has_link = true;
1224
1225 /* Detect and store PCS speed */
1226 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1227 *speed = SPEED_1000;
1228 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1229 *speed = SPEED_100;
1230 else
1231 *speed = SPEED_10;
1232
1233 /* Detect and store PCS duplex */
1234 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1235 *duplex = FULL_DUPLEX;
1236 else
1237 *duplex = HALF_DUPLEX;
1238
1239 /* Check if it is an I354 2.5Gb backplane connection. */
1240 if (mac->type == e1000_i354) {
1241 status = E1000_READ_REG(hw, E1000_STATUS);
1242 if ((status & E1000_STATUS_2P5_SKU) &&
1243 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1244 *speed = SPEED_2500;
1245 *duplex = FULL_DUPLEX;
1246 DEBUGOUT("2500 Mbs, ");
1247 DEBUGOUT("Full Duplex\n");
1248 }
1249 }
1250
1251 } else {
1252 mac->serdes_has_link = false;
1253 *speed = 0;
1254 *duplex = 0;
1255 }
1256
1257 return E1000_SUCCESS;
1258 }
1259
1260 /**
1261 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1262 * @hw: pointer to the HW structure
1263 *
1264 * In the case of serdes shut down sfp and PCS on driver unload
1265 * when management pass thru is not enabled.
1266 **/
e1000_shutdown_serdes_link_82575(struct e1000_hw * hw)1267 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1268 {
1269 u32 reg;
1270
1271 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1272
1273 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1274 !e1000_sgmii_active_82575(hw))
1275 return;
1276
1277 if (!e1000_enable_mng_pass_thru(hw)) {
1278 /* Disable PCS to turn off link */
1279 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1280 reg &= ~E1000_PCS_CFG_PCS_EN;
1281 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1282
1283 /* shutdown the laser */
1284 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1285 reg |= E1000_CTRL_EXT_SDP3_DATA;
1286 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1287
1288 /* flush the write to verify completion */
1289 E1000_WRITE_FLUSH(hw);
1290 msec_delay(1);
1291 }
1292
1293 return;
1294 }
1295
1296 /**
1297 * e1000_reset_hw_82575 - Reset hardware
1298 * @hw: pointer to the HW structure
1299 *
1300 * This resets the hardware into a known state.
1301 **/
e1000_reset_hw_82575(struct e1000_hw * hw)1302 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1303 {
1304 u32 ctrl;
1305 s32 ret_val;
1306
1307 DEBUGFUNC("e1000_reset_hw_82575");
1308
1309 /*
1310 * Prevent the PCI-E bus from sticking if there is no TLP connection
1311 * on the last TLP read/write transaction when MAC is reset.
1312 */
1313 ret_val = e1000_disable_pcie_master_generic(hw);
1314 if (ret_val)
1315 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1316
1317 /* set the completion timeout for interface */
1318 ret_val = e1000_set_pcie_completion_timeout(hw);
1319 if (ret_val)
1320 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1321
1322 DEBUGOUT("Masking off all interrupts\n");
1323 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1324
1325 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1326 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1327 E1000_WRITE_FLUSH(hw);
1328
1329 msec_delay(10);
1330
1331 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1332
1333 DEBUGOUT("Issuing a global reset to MAC\n");
1334 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1335
1336 ret_val = e1000_get_auto_rd_done_generic(hw);
1337 if (ret_val) {
1338 /*
1339 * When auto config read does not complete, do not
1340 * return with an error. This can happen in situations
1341 * where there is no eeprom and prevents getting link.
1342 */
1343 DEBUGOUT("Auto Read Done did not complete\n");
1344 }
1345
1346 /* If EEPROM is not present, run manual init scripts */
1347 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1348 e1000_reset_init_script_82575(hw);
1349
1350 /* Clear any pending interrupt events. */
1351 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1352 E1000_READ_REG(hw, E1000_ICR);
1353
1354 /* Install any alternate MAC address into RAR0 */
1355 ret_val = e1000_check_alt_mac_addr_generic(hw);
1356
1357 return ret_val;
1358 }
1359
1360 /**
1361 * e1000_init_hw_82575 - Initialize hardware
1362 * @hw: pointer to the HW structure
1363 *
1364 * This inits the hardware readying it for operation.
1365 **/
e1000_init_hw_82575(struct e1000_hw * hw)1366 static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1367 {
1368 struct e1000_mac_info *mac = &hw->mac;
1369 s32 ret_val;
1370
1371 DEBUGFUNC("e1000_init_hw_82575");
1372
1373 /* Initialize identification LED */
1374 ret_val = mac->ops.id_led_init(hw);
1375 if (ret_val) {
1376 DEBUGOUT("Error initializing identification LED\n");
1377 /* This is not fatal and we should not stop init due to this */
1378 }
1379
1380 /* Disabling VLAN filtering */
1381 DEBUGOUT("Initializing the IEEE VLAN\n");
1382 mac->ops.clear_vfta(hw);
1383
1384 ret_val = e1000_init_hw_base(hw);
1385
1386 /* Set the default MTU size */
1387 hw->dev_spec._82575.mtu = 1500;
1388
1389 /* Clear all of the statistics registers (clear on read). It is
1390 * important that we do this after we have tried to establish link
1391 * because the symbol error count will increment wildly if there
1392 * is no link.
1393 */
1394 e1000_clear_hw_cntrs_82575(hw);
1395
1396 return ret_val;
1397 }
1398 /**
1399 * e1000_setup_copper_link_82575 - Configure copper link settings
1400 * @hw: pointer to the HW structure
1401 *
1402 * Configures the link for auto-neg or forced speed and duplex. Then we check
1403 * for link, once link is established calls to configure collision distance
1404 * and flow control are called.
1405 **/
e1000_setup_copper_link_82575(struct e1000_hw * hw)1406 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1407 {
1408 u32 phpm_reg;
1409 u32 ctrl;
1410 s32 ret_val;
1411
1412 DEBUGFUNC("e1000_setup_copper_link_82575");
1413
1414 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1415 ctrl |= E1000_CTRL_SLU;
1416 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1417 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1418
1419 /* Clear Go Link Disconnect bit on supported devices */
1420 switch (hw->mac.type) {
1421 case e1000_82580:
1422 case e1000_i350:
1423 case e1000_i210:
1424 case e1000_i211:
1425 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1426 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1427 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1428 break;
1429 default:
1430 break;
1431 }
1432
1433 ret_val = e1000_setup_serdes_link_82575(hw);
1434 if (ret_val)
1435 goto out;
1436
1437 if (e1000_sgmii_active_82575(hw)) {
1438 /* allow time for SFP cage time to power up phy */
1439 msec_delay(300);
1440
1441 ret_val = hw->phy.ops.reset(hw);
1442 if (ret_val) {
1443 DEBUGOUT("Error resetting the PHY.\n");
1444 goto out;
1445 }
1446 }
1447 switch (hw->phy.type) {
1448 case e1000_phy_i210:
1449 /* FALLTHROUGH */
1450 case e1000_phy_m88:
1451 switch (hw->phy.id) {
1452 case I347AT4_E_PHY_ID:
1453 /* FALLTHROUGH */
1454 case M88E1112_E_PHY_ID:
1455 /* FALLTHROUGH */
1456 case M88E1340M_E_PHY_ID:
1457 /* FALLTHROUGH */
1458 case M88E1543_E_PHY_ID:
1459 /* FALLTHROUGH */
1460 case M88E1512_E_PHY_ID:
1461 /* FALLTHROUGH */
1462 case I210_I_PHY_ID:
1463 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1464 break;
1465 default:
1466 ret_val = e1000_copper_link_setup_m88(hw);
1467 break;
1468 }
1469 break;
1470 case e1000_phy_igp_3:
1471 ret_val = e1000_copper_link_setup_igp(hw);
1472 break;
1473 case e1000_phy_82580:
1474 ret_val = e1000_copper_link_setup_82577(hw);
1475 break;
1476 default:
1477 ret_val = -E1000_ERR_PHY;
1478 break;
1479 }
1480
1481 if (ret_val)
1482 goto out;
1483
1484 ret_val = e1000_setup_copper_link_generic(hw);
1485 out:
1486 return ret_val;
1487 }
1488
1489 /**
1490 * e1000_setup_serdes_link_82575 - Setup link for serdes
1491 * @hw: pointer to the HW structure
1492 *
1493 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1494 * used on copper connections where the serialized gigabit media independent
1495 * interface (sgmii), or serdes fiber is being used. Configures the link
1496 * for auto-negotiation or forces speed/duplex.
1497 **/
e1000_setup_serdes_link_82575(struct e1000_hw * hw)1498 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1499 {
1500 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1501 bool pcs_autoneg;
1502 s32 ret_val = E1000_SUCCESS;
1503 u16 data;
1504
1505 DEBUGFUNC("e1000_setup_serdes_link_82575");
1506
1507 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1508 !e1000_sgmii_active_82575(hw))
1509 return ret_val;
1510
1511 /*
1512 * On the 82575, SerDes loopback mode persists until it is
1513 * explicitly turned off or a power cycle is performed. A read to
1514 * the register does not indicate its status. Therefore, we ensure
1515 * loopback mode is disabled during initialization.
1516 */
1517 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1518
1519 /* power on the sfp cage if present */
1520 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1521 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1522 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1523
1524 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1525 ctrl_reg |= E1000_CTRL_SLU;
1526
1527 /* set both sw defined pins on 82575/82576*/
1528 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1529 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1530
1531 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1532
1533 /* default pcs_autoneg to the same setting as mac autoneg */
1534 pcs_autoneg = hw->mac.autoneg;
1535
1536 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1537 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1538 /* sgmii mode lets the phy handle forcing speed/duplex */
1539 pcs_autoneg = true;
1540 /* autoneg time out should be disabled for SGMII mode */
1541 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1542 break;
1543 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1544 /* disable PCS autoneg and support parallel detect only */
1545 pcs_autoneg = false;
1546 /* FALLTHROUGH */
1547 default:
1548 if (hw->mac.type == e1000_82575 ||
1549 hw->mac.type == e1000_82576) {
1550 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1551 if (ret_val) {
1552 DEBUGOUT("NVM Read Error\n");
1553 return ret_val;
1554 }
1555
1556 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1557 pcs_autoneg = false;
1558 }
1559
1560 /*
1561 * non-SGMII modes only supports a speed of 1000/Full for the
1562 * link so it is best to just force the MAC and let the pcs
1563 * link either autoneg or be forced to 1000/Full
1564 */
1565 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1566 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1567
1568 /* set speed of 1000/Full if speed/duplex is forced */
1569 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1570 break;
1571 }
1572
1573 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1574
1575 /*
1576 * New SerDes mode allows for forcing speed or autonegotiating speed
1577 * at 1gb. Autoneg should be default set by most drivers. This is the
1578 * mode that will be compatible with older link partners and switches.
1579 * However, both are supported by the hardware and some drivers/tools.
1580 */
1581 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1582 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1583
1584 if (pcs_autoneg) {
1585 /* Set PCS register for autoneg */
1586 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1587 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1588
1589 /* Disable force flow control for autoneg */
1590 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1591
1592 /* Configure flow control advertisement for autoneg */
1593 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1594 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1595
1596 switch (hw->fc.requested_mode) {
1597 case e1000_fc_full:
1598 case e1000_fc_rx_pause:
1599 anadv_reg |= E1000_TXCW_ASM_DIR;
1600 anadv_reg |= E1000_TXCW_PAUSE;
1601 break;
1602 case e1000_fc_tx_pause:
1603 anadv_reg |= E1000_TXCW_ASM_DIR;
1604 break;
1605 default:
1606 break;
1607 }
1608
1609 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1610
1611 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1612 } else {
1613 /* Set PCS register for forced link */
1614 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1615
1616 /* Force flow control for forced link */
1617 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1618
1619 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1620 }
1621
1622 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1623
1624 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1625 e1000_force_mac_fc_generic(hw);
1626
1627 return ret_val;
1628 }
1629
1630 /**
1631 * e1000_get_media_type_82575 - derives current media type.
1632 * @hw: pointer to the HW structure
1633 *
1634 * The media type is chosen reflecting few settings.
1635 * The following are taken into account:
1636 * - link mode set in the current port Init Control Word #3
1637 * - current link mode settings in CSR register
1638 * - MDIO vs. I2C PHY control interface chosen
1639 * - SFP module media type
1640 **/
e1000_get_media_type_82575(struct e1000_hw * hw)1641 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1642 {
1643 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1644 s32 ret_val = E1000_SUCCESS;
1645 u32 ctrl_ext = 0;
1646 u32 link_mode = 0;
1647
1648 /* Set internal phy as default */
1649 dev_spec->sgmii_active = false;
1650 dev_spec->module_plugged = false;
1651
1652 /* Get CSR setting */
1653 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1654
1655 /* extract link mode setting */
1656 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1657
1658 switch (link_mode) {
1659 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1660 hw->phy.media_type = e1000_media_type_internal_serdes;
1661 break;
1662 case E1000_CTRL_EXT_LINK_MODE_GMII:
1663 hw->phy.media_type = e1000_media_type_copper;
1664 break;
1665 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1666 /* Get phy control interface type set (MDIO vs. I2C)*/
1667 if (e1000_sgmii_uses_mdio_82575(hw)) {
1668 hw->phy.media_type = e1000_media_type_copper;
1669 dev_spec->sgmii_active = true;
1670 break;
1671 }
1672 /* fall through for I2C based SGMII */
1673 /* FALLTHROUGH */
1674 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1675 /* read media type from SFP EEPROM */
1676 ret_val = e1000_set_sfp_media_type_82575(hw);
1677 if ((ret_val != E1000_SUCCESS) ||
1678 (hw->phy.media_type == e1000_media_type_unknown)) {
1679 /*
1680 * If media type was not identified then return media
1681 * type defined by the CTRL_EXT settings.
1682 */
1683 hw->phy.media_type = e1000_media_type_internal_serdes;
1684
1685 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1686 hw->phy.media_type = e1000_media_type_copper;
1687 dev_spec->sgmii_active = true;
1688 }
1689
1690 break;
1691 }
1692
1693 /* change current link mode setting */
1694 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1695
1696 if (dev_spec->sgmii_active)
1697 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1698 else
1699 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1700
1701 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1702
1703 break;
1704 default:
1705 DEBUGOUT("e1000_get_media_type_82575 unknown link type\n");
1706 break;
1707 }
1708
1709 return ret_val;
1710 }
1711
1712 /**
1713 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1714 * @hw: pointer to the HW structure
1715 *
1716 * The media type is chosen based on SFP module.
1717 * compatibility flags retrieved from SFP ID EEPROM.
1718 **/
e1000_set_sfp_media_type_82575(struct e1000_hw * hw)1719 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1720 {
1721 s32 ret_val = E1000_ERR_CONFIG;
1722 u32 ctrl_ext = 0;
1723 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1724 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1725 u8 tranceiver_type = 0;
1726 s32 timeout = 3;
1727
1728 /* Turn I2C interface ON and power on sfp cage */
1729 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1730 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1731 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1732
1733 E1000_WRITE_FLUSH(hw);
1734
1735 /* Read SFP module data */
1736 while (timeout) {
1737 ret_val = e1000_read_sfp_data_byte(hw,
1738 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1739 &tranceiver_type);
1740 if (ret_val == E1000_SUCCESS)
1741 break;
1742 msec_delay(100);
1743 timeout--;
1744 }
1745 if (ret_val != E1000_SUCCESS)
1746 goto out;
1747
1748 ret_val = e1000_read_sfp_data_byte(hw,
1749 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1750 (u8 *)eth_flags);
1751 if (ret_val != E1000_SUCCESS)
1752 goto out;
1753
1754 /* Check if there is some SFP module plugged and powered */
1755 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1756 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF))
1757 dev_spec->module_plugged = true;
1758 else
1759 DEBUGOUT("PHY module is not SFP/SFF %x\n", tranceiver_type);
1760
1761 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1762 hw->phy.media_type = e1000_media_type_internal_serdes;
1763 DEBUGOUT("PHY module is 1000_base_lxsx\n");
1764 } else if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) {
1765 dev_spec->sgmii_active = true;
1766 hw->phy.media_type = e1000_media_type_internal_serdes;
1767 DEBUGOUT("PHY module is 100_base_fxlx\n");
1768 } else if (eth_flags->e1000_base_t) {
1769 dev_spec->sgmii_active = true;
1770 hw->phy.media_type = e1000_media_type_copper;
1771 DEBUGOUT("PHY module is 1000_base_t\n");
1772 } else {
1773 hw->phy.media_type = e1000_media_type_unknown;
1774 DEBUGOUT("PHY module has not been recognized\n");
1775 }
1776
1777 ret_val = E1000_SUCCESS;
1778 out:
1779 /* Restore I2C interface setting */
1780 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1781 return ret_val;
1782 }
1783
1784 /**
1785 * e1000_valid_led_default_82575 - Verify a valid default LED config
1786 * @hw: pointer to the HW structure
1787 * @data: pointer to the NVM (EEPROM)
1788 *
1789 * Read the EEPROM for the current default LED configuration. If the
1790 * LED configuration is not valid, set to a valid LED configuration.
1791 **/
e1000_valid_led_default_82575(struct e1000_hw * hw,u16 * data)1792 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1793 {
1794 s32 ret_val;
1795
1796 DEBUGFUNC("e1000_valid_led_default_82575");
1797
1798 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1799 if (ret_val) {
1800 DEBUGOUT("NVM Read Error\n");
1801 goto out;
1802 }
1803
1804 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1805 switch (hw->phy.media_type) {
1806 case e1000_media_type_internal_serdes:
1807 *data = ID_LED_DEFAULT_82575_SERDES;
1808 break;
1809 case e1000_media_type_copper:
1810 default:
1811 *data = ID_LED_DEFAULT;
1812 break;
1813 }
1814 }
1815 out:
1816 return ret_val;
1817 }
1818
1819 /**
1820 * e1000_sgmii_active_82575 - Return sgmii state
1821 * @hw: pointer to the HW structure
1822 *
1823 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1824 * which can be enabled for use in the embedded applications. Simply
1825 * return the current state of the sgmii interface.
1826 **/
e1000_sgmii_active_82575(struct e1000_hw * hw)1827 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1828 {
1829 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1830 return dev_spec->sgmii_active;
1831 }
1832
1833 /**
1834 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1835 * @hw: pointer to the HW structure
1836 *
1837 * Inits recommended HW defaults after a reset when there is no EEPROM
1838 * detected. This is only for the 82575.
1839 **/
e1000_reset_init_script_82575(struct e1000_hw * hw)1840 s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1841 {
1842 DEBUGFUNC("e1000_reset_init_script_82575");
1843
1844 if (hw->mac.type == e1000_82575) {
1845 DEBUGOUT("Running reset init script for 82575\n");
1846 /* SerDes configuration via SERDESCTRL */
1847 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1848 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1849 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1850 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1851
1852 /* CCM configuration via CCMCTL register */
1853 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1854 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1855
1856 /* PCIe lanes configuration */
1857 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1858 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1859 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1860 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1861
1862 /* PCIe PLL Configuration */
1863 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1864 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1865 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1866 }
1867
1868 return E1000_SUCCESS;
1869 }
1870
1871 /**
1872 * e1000_read_mac_addr_82575 - Read device MAC address
1873 * @hw: pointer to the HW structure
1874 **/
e1000_read_mac_addr_82575(struct e1000_hw * hw)1875 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1876 {
1877 s32 ret_val;
1878
1879 DEBUGFUNC("e1000_read_mac_addr_82575");
1880
1881 /*
1882 * If there's an alternate MAC address place it in RAR0
1883 * so that it will override the Si installed default perm
1884 * address.
1885 */
1886 ret_val = e1000_check_alt_mac_addr_generic(hw);
1887 if (ret_val)
1888 goto out;
1889
1890 ret_val = e1000_read_mac_addr_generic(hw);
1891
1892 out:
1893 return ret_val;
1894 }
1895
1896 /**
1897 * e1000_config_collision_dist_82575 - Configure collision distance
1898 * @hw: pointer to the HW structure
1899 *
1900 * Configures the collision distance to the default value and is used
1901 * during link setup.
1902 **/
e1000_config_collision_dist_82575(struct e1000_hw * hw)1903 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1904 {
1905 u32 tctl_ext;
1906
1907 DEBUGFUNC("e1000_config_collision_dist_82575");
1908
1909 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1910
1911 tctl_ext &= ~E1000_TCTL_EXT_COLD;
1912 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1913
1914 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1915 E1000_WRITE_FLUSH(hw);
1916 }
1917
1918 /**
1919 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1920 * @hw: pointer to the HW structure
1921 *
1922 * Clears the hardware counters by reading the counter registers.
1923 **/
e1000_clear_hw_cntrs_82575(struct e1000_hw * hw)1924 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1925 {
1926 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1927
1928 e1000_clear_hw_cntrs_base_generic(hw);
1929
1930 E1000_READ_REG(hw, E1000_PRC64);
1931 E1000_READ_REG(hw, E1000_PRC127);
1932 E1000_READ_REG(hw, E1000_PRC255);
1933 E1000_READ_REG(hw, E1000_PRC511);
1934 E1000_READ_REG(hw, E1000_PRC1023);
1935 E1000_READ_REG(hw, E1000_PRC1522);
1936 E1000_READ_REG(hw, E1000_PTC64);
1937 E1000_READ_REG(hw, E1000_PTC127);
1938 E1000_READ_REG(hw, E1000_PTC255);
1939 E1000_READ_REG(hw, E1000_PTC511);
1940 E1000_READ_REG(hw, E1000_PTC1023);
1941 E1000_READ_REG(hw, E1000_PTC1522);
1942
1943 E1000_READ_REG(hw, E1000_ALGNERRC);
1944 E1000_READ_REG(hw, E1000_RXERRC);
1945 E1000_READ_REG(hw, E1000_TNCRS);
1946 E1000_READ_REG(hw, E1000_CEXTERR);
1947 E1000_READ_REG(hw, E1000_TSCTC);
1948 E1000_READ_REG(hw, E1000_TSCTFC);
1949
1950 E1000_READ_REG(hw, E1000_MGTPRC);
1951 E1000_READ_REG(hw, E1000_MGTPDC);
1952 E1000_READ_REG(hw, E1000_MGTPTC);
1953
1954 E1000_READ_REG(hw, E1000_IAC);
1955 E1000_READ_REG(hw, E1000_ICRXOC);
1956
1957 E1000_READ_REG(hw, E1000_ICRXPTC);
1958 E1000_READ_REG(hw, E1000_ICRXATC);
1959 E1000_READ_REG(hw, E1000_ICTXPTC);
1960 E1000_READ_REG(hw, E1000_ICTXATC);
1961 E1000_READ_REG(hw, E1000_ICTXQEC);
1962 E1000_READ_REG(hw, E1000_ICTXQMTC);
1963 E1000_READ_REG(hw, E1000_ICRXDMTC);
1964
1965 E1000_READ_REG(hw, E1000_CBTMPC);
1966 E1000_READ_REG(hw, E1000_HTDPMC);
1967 E1000_READ_REG(hw, E1000_CBRMPC);
1968 E1000_READ_REG(hw, E1000_RPTHC);
1969 E1000_READ_REG(hw, E1000_HGPTC);
1970 E1000_READ_REG(hw, E1000_HTCBDPC);
1971 E1000_READ_REG(hw, E1000_HGORCL);
1972 E1000_READ_REG(hw, E1000_HGORCH);
1973 E1000_READ_REG(hw, E1000_HGOTCL);
1974 E1000_READ_REG(hw, E1000_HGOTCH);
1975 E1000_READ_REG(hw, E1000_LENERRS);
1976
1977 /* This register should not be read in copper configurations */
1978 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1979 e1000_sgmii_active_82575(hw))
1980 E1000_READ_REG(hw, E1000_SCVPC);
1981 }
1982
1983 /**
1984 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
1985 * @hw: pointer to the HW structure
1986 *
1987 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1988 * however the hardware default for these parts is 500us to 1ms which is less
1989 * than the 10ms recommended by the pci-e spec. To address this we need to
1990 * increase the value to either 10ms to 200ms for capability version 1 config,
1991 * or 16ms to 55ms for version 2.
1992 **/
e1000_set_pcie_completion_timeout(struct e1000_hw * hw)1993 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
1994 {
1995 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
1996 s32 ret_val = E1000_SUCCESS;
1997 u16 pcie_devctl2;
1998
1999 /* only take action if timeout value is defaulted to 0 */
2000 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2001 goto out;
2002
2003 /*
2004 * if capababilities version is type 1 we can write the
2005 * timeout of 10ms to 200ms through the GCR register
2006 */
2007 if (!(gcr & E1000_GCR_CAP_VER2)) {
2008 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2009 goto out;
2010 }
2011
2012 /*
2013 * for version 2 capabilities we need to write the config space
2014 * directly in order to set the completion timeout value for
2015 * 16ms to 55ms
2016 */
2017 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2018 &pcie_devctl2);
2019 if (ret_val)
2020 goto out;
2021
2022 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2023
2024 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2025 &pcie_devctl2);
2026 out:
2027 /* disable completion timeout resend */
2028 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2029
2030 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2031 return ret_val;
2032 }
2033
2034 /**
2035 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2036 * @hw: pointer to the hardware struct
2037 * @enable: state to enter, either enabled or disabled
2038 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2039 *
2040 * enables/disables L2 switch anti-spoofing functionality.
2041 **/
e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw * hw,bool enable,int pf)2042 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2043 {
2044 u32 reg_val, reg_offset;
2045
2046 switch (hw->mac.type) {
2047 case e1000_82576:
2048 reg_offset = E1000_DTXSWC;
2049 break;
2050 case e1000_i350:
2051 case e1000_i354:
2052 reg_offset = E1000_TXSWC;
2053 break;
2054 default:
2055 return;
2056 }
2057
2058 reg_val = E1000_READ_REG(hw, reg_offset);
2059 if (enable) {
2060 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2061 E1000_DTXSWC_VLAN_SPOOF_MASK);
2062 /* The PF can spoof - it has to in order to
2063 * support emulation mode NICs
2064 */
2065 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2066 } else {
2067 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2068 E1000_DTXSWC_VLAN_SPOOF_MASK);
2069 }
2070 E1000_WRITE_REG(hw, reg_offset, reg_val);
2071 }
2072
2073 /**
2074 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2075 * @hw: pointer to the hardware struct
2076 * @enable: state to enter, either enabled or disabled
2077 *
2078 * enables/disables L2 switch loopback functionality.
2079 **/
e1000_vmdq_set_loopback_pf(struct e1000_hw * hw,bool enable)2080 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2081 {
2082 u32 dtxswc;
2083
2084 switch (hw->mac.type) {
2085 case e1000_82576:
2086 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2087 if (enable)
2088 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2089 else
2090 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2091 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2092 break;
2093 case e1000_i350:
2094 case e1000_i354:
2095 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2096 if (enable)
2097 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2098 else
2099 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2100 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2101 break;
2102 default:
2103 /* Currently no other hardware supports loopback */
2104 break;
2105 }
2106
2107
2108 }
2109
2110 /**
2111 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2112 * @hw: pointer to the hardware struct
2113 * @enable: state to enter, either enabled or disabled
2114 *
2115 * enables/disables replication of packets across multiple pools.
2116 **/
e1000_vmdq_set_replication_pf(struct e1000_hw * hw,bool enable)2117 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2118 {
2119 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2120
2121 if (enable)
2122 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2123 else
2124 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2125
2126 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2127 }
2128
2129 /**
2130 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2131 * @hw: pointer to the HW structure
2132 * @offset: register offset to be read
2133 * @data: pointer to the read data
2134 *
2135 * Reads the MDI control register in the PHY at offset and stores the
2136 * information read to data.
2137 **/
e1000_read_phy_reg_82580(struct e1000_hw * hw,u32 offset,u16 * data)2138 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2139 {
2140 s32 ret_val;
2141
2142 DEBUGFUNC("e1000_read_phy_reg_82580");
2143
2144 ret_val = hw->phy.ops.acquire(hw);
2145 if (ret_val)
2146 goto out;
2147
2148 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2149
2150 hw->phy.ops.release(hw);
2151
2152 out:
2153 return ret_val;
2154 }
2155
2156 /**
2157 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2158 * @hw: pointer to the HW structure
2159 * @offset: register offset to write to
2160 * @data: data to write to register at offset
2161 *
2162 * Writes data to MDI control register in the PHY at offset.
2163 **/
e1000_write_phy_reg_82580(struct e1000_hw * hw,u32 offset,u16 data)2164 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2165 {
2166 s32 ret_val;
2167
2168 DEBUGFUNC("e1000_write_phy_reg_82580");
2169
2170 ret_val = hw->phy.ops.acquire(hw);
2171 if (ret_val)
2172 goto out;
2173
2174 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2175
2176 hw->phy.ops.release(hw);
2177
2178 out:
2179 return ret_val;
2180 }
2181
2182 /**
2183 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2184 * @hw: pointer to the HW structure
2185 *
2186 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2187 * the values found in the EEPROM. This addresses an issue in which these
2188 * bits are not restored from EEPROM after reset.
2189 **/
e1000_reset_mdicnfg_82580(struct e1000_hw * hw)2190 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2191 {
2192 s32 ret_val = E1000_SUCCESS;
2193 u32 mdicnfg;
2194 u16 nvm_data = 0;
2195
2196 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2197
2198 if (hw->mac.type != e1000_82580)
2199 goto out;
2200 if (!e1000_sgmii_active_82575(hw))
2201 goto out;
2202
2203 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2204 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2205 &nvm_data);
2206 if (ret_val) {
2207 DEBUGOUT("NVM Read Error\n");
2208 goto out;
2209 }
2210
2211 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2212 if (nvm_data & NVM_WORD24_EXT_MDIO)
2213 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2214 if (nvm_data & NVM_WORD24_COM_MDIO)
2215 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2216 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2217 out:
2218 return ret_val;
2219 }
2220
2221 /**
2222 * e1000_reset_hw_82580 - Reset hardware
2223 * @hw: pointer to the HW structure
2224 *
2225 * This resets function or entire device (all ports, etc.)
2226 * to a known state.
2227 **/
e1000_reset_hw_82580(struct e1000_hw * hw)2228 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2229 {
2230 s32 ret_val = E1000_SUCCESS;
2231 /* BH SW mailbox bit in SW_FW_SYNC */
2232 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2233 u32 ctrl, status;
2234 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2235
2236 DEBUGFUNC("e1000_reset_hw_82580");
2237
2238 hw->dev_spec._82575.global_device_reset = false;
2239
2240 /* 82580 does not reliably do global_device_reset due to hw errata */
2241 if (hw->mac.type == e1000_82580)
2242 global_device_reset = false;
2243
2244 /* Get current control state. */
2245 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2246
2247 /*
2248 * Prevent the PCI-E bus from sticking if there is no TLP connection
2249 * on the last TLP read/write transaction when MAC is reset.
2250 */
2251 ret_val = e1000_disable_pcie_master_generic(hw);
2252 if (ret_val)
2253 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2254
2255 DEBUGOUT("Masking off all interrupts\n");
2256 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2257 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2258 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2259 E1000_WRITE_FLUSH(hw);
2260
2261 msec_delay(10);
2262
2263 /* Determine whether or not a global dev reset is requested */
2264 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2265 swmbsw_mask))
2266 global_device_reset = false;
2267
2268 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2269 E1000_STAT_DEV_RST_SET))
2270 ctrl |= E1000_CTRL_DEV_RST;
2271 else
2272 ctrl |= E1000_CTRL_RST;
2273
2274 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2275
2276 switch (hw->device_id) {
2277 case E1000_DEV_ID_DH89XXCC_SGMII:
2278 break;
2279 default:
2280 E1000_WRITE_FLUSH(hw);
2281 break;
2282 }
2283
2284 /* Add delay to insure DEV_RST or RST has time to complete */
2285 msec_delay(5);
2286
2287 ret_val = e1000_get_auto_rd_done_generic(hw);
2288 if (ret_val) {
2289 /*
2290 * When auto config read does not complete, do not
2291 * return with an error. This can happen in situations
2292 * where there is no eeprom and prevents getting link.
2293 */
2294 DEBUGOUT("Auto Read Done did not complete\n");
2295 }
2296
2297 /* clear global device reset status bit */
2298 status = E1000_READ_REG(hw, E1000_STATUS);
2299 E1000_WRITE_REG(hw, E1000_STATUS,
2300 status | E1000_STAT_DEV_RST_SET);
2301
2302 /* Clear any pending interrupt events. */
2303 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2304 E1000_READ_REG(hw, E1000_ICR);
2305
2306 ret_val = e1000_reset_mdicnfg_82580(hw);
2307 if (ret_val)
2308 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2309
2310 /* Install any alternate MAC address into RAR0 */
2311 ret_val = e1000_check_alt_mac_addr_generic(hw);
2312
2313 /* Release semaphore */
2314 if (global_device_reset)
2315 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2316
2317 return ret_val;
2318 }
2319
2320 /**
2321 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2322 * @data: data received by reading RXPBS register
2323 *
2324 * The 82580 uses a table based approach for packet buffer allocation sizes.
2325 * This function converts the retrieved value into the correct table value
2326 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2327 * 0x0 36 72 144 1 2 4 8 16
2328 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2329 */
e1000_rxpbs_adjust_82580(u32 data)2330 u16 e1000_rxpbs_adjust_82580(u32 data)
2331 {
2332 u16 ret_val = 0;
2333
2334 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2335 ret_val = e1000_82580_rxpbs_table[data];
2336
2337 return ret_val;
2338 }
2339
2340 /**
2341 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2342 * checksum
2343 * @hw: pointer to the HW structure
2344 * @offset: offset in words of the checksum protected region
2345 *
2346 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2347 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2348 **/
e1000_validate_nvm_checksum_with_offset(struct e1000_hw * hw,u16 offset)2349 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2350 {
2351 s32 ret_val = E1000_SUCCESS;
2352 u16 checksum = 0;
2353 u16 i, nvm_data;
2354
2355 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2356
2357 for (i = offset; i < (u16)((NVM_CHECKSUM_REG + offset) + 1); i++) {
2358 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2359 if (ret_val) {
2360 DEBUGOUT("NVM Read Error\n");
2361 goto out;
2362 }
2363 checksum += nvm_data;
2364 }
2365
2366 if (checksum != (u16) NVM_SUM) {
2367 DEBUGOUT("NVM Checksum Invalid\n");
2368 ret_val = -E1000_ERR_NVM;
2369 goto out;
2370 }
2371
2372 out:
2373 return ret_val;
2374 }
2375
2376 /**
2377 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2378 * checksum
2379 * @hw: pointer to the HW structure
2380 * @offset: offset in words of the checksum protected region
2381 *
2382 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2383 * up to the checksum. Then calculates the EEPROM checksum and writes the
2384 * value to the EEPROM.
2385 **/
e1000_update_nvm_checksum_with_offset(struct e1000_hw * hw,u16 offset)2386 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2387 {
2388 s32 ret_val;
2389 u16 checksum = 0;
2390 u16 i, nvm_data;
2391
2392 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2393
2394 for (i = offset; i < (u16)(NVM_CHECKSUM_REG + offset); i++) {
2395 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2396 if (ret_val) {
2397 DEBUGOUT("NVM Read Error while updating checksum.\n");
2398 goto out;
2399 }
2400 checksum += nvm_data;
2401 }
2402 checksum = (u16) NVM_SUM - checksum;
2403 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2404 &checksum);
2405 if (ret_val)
2406 DEBUGOUT("NVM Write Error while updating checksum.\n");
2407
2408 out:
2409 return ret_val;
2410 }
2411
2412 /**
2413 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2414 * @hw: pointer to the HW structure
2415 *
2416 * Calculates the EEPROM section checksum by reading/adding each word of
2417 * the EEPROM and then verifies that the sum of the EEPROM is
2418 * equal to 0xBABA.
2419 **/
e1000_validate_nvm_checksum_82580(struct e1000_hw * hw)2420 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2421 {
2422 s32 ret_val;
2423 u16 eeprom_regions_count = 1;
2424 u16 j, nvm_data;
2425 u16 nvm_offset;
2426
2427 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2428
2429 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2430 if (ret_val) {
2431 DEBUGOUT("NVM Read Error\n");
2432 goto out;
2433 }
2434
2435 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2436 /* if checksums compatibility bit is set validate checksums
2437 * for all 4 ports. */
2438 eeprom_regions_count = 4;
2439 }
2440
2441 for (j = 0; j < eeprom_regions_count; j++) {
2442 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2443 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2444 nvm_offset);
2445 if (ret_val != E1000_SUCCESS)
2446 goto out;
2447 }
2448
2449 out:
2450 return ret_val;
2451 }
2452
2453 /**
2454 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2455 * @hw: pointer to the HW structure
2456 *
2457 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2458 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2459 * checksum and writes the value to the EEPROM.
2460 **/
e1000_update_nvm_checksum_82580(struct e1000_hw * hw)2461 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2462 {
2463 s32 ret_val;
2464 u16 j, nvm_data;
2465 u16 nvm_offset;
2466
2467 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2468
2469 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2470 if (ret_val) {
2471 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2472 goto out;
2473 }
2474
2475 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2476 /* set compatibility bit to validate checksums appropriately */
2477 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2478 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2479 &nvm_data);
2480 if (ret_val) {
2481 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2482 goto out;
2483 }
2484 }
2485
2486 for (j = 0; j < 4; j++) {
2487 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2488 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2489 if (ret_val)
2490 goto out;
2491 }
2492
2493 out:
2494 return ret_val;
2495 }
2496
2497 /**
2498 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2499 * @hw: pointer to the HW structure
2500 *
2501 * Calculates the EEPROM section checksum by reading/adding each word of
2502 * the EEPROM and then verifies that the sum of the EEPROM is
2503 * equal to 0xBABA.
2504 **/
e1000_validate_nvm_checksum_i350(struct e1000_hw * hw)2505 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2506 {
2507 s32 ret_val = E1000_SUCCESS;
2508 u16 j;
2509 u16 nvm_offset;
2510
2511 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2512
2513 for (j = 0; j < 4; j++) {
2514 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2515 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2516 nvm_offset);
2517 if (ret_val != E1000_SUCCESS)
2518 goto out;
2519 }
2520
2521 out:
2522 return ret_val;
2523 }
2524
2525 /**
2526 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2527 * @hw: pointer to the HW structure
2528 *
2529 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2530 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2531 * checksum and writes the value to the EEPROM.
2532 **/
e1000_update_nvm_checksum_i350(struct e1000_hw * hw)2533 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2534 {
2535 s32 ret_val = E1000_SUCCESS;
2536 u16 j;
2537 u16 nvm_offset;
2538
2539 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2540
2541 for (j = 0; j < 4; j++) {
2542 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2543 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2544 if (ret_val != E1000_SUCCESS)
2545 goto out;
2546 }
2547
2548 out:
2549 return ret_val;
2550 }
2551
2552 /**
2553 * __e1000_access_emi_reg - Read/write EMI register
2554 * @hw: pointer to the HW structure
2555 * @address: EMI address to program
2556 * @data: pointer to value to read/write from/to the EMI address
2557 * @read: boolean flag to indicate read or write
2558 **/
__e1000_access_emi_reg(struct e1000_hw * hw,u16 address,u16 * data,bool read)2559 static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2560 u16 *data, bool read)
2561 {
2562 s32 ret_val;
2563
2564 DEBUGFUNC("__e1000_access_emi_reg");
2565
2566 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2567 if (ret_val)
2568 return ret_val;
2569
2570 if (read)
2571 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2572 else
2573 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2574
2575 return ret_val;
2576 }
2577
2578 /**
2579 * e1000_read_emi_reg - Read Extended Management Interface register
2580 * @hw: pointer to the HW structure
2581 * @addr: EMI address to program
2582 * @data: value to be read from the EMI address
2583 **/
e1000_read_emi_reg(struct e1000_hw * hw,u16 addr,u16 * data)2584 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2585 {
2586 DEBUGFUNC("e1000_read_emi_reg");
2587
2588 return __e1000_access_emi_reg(hw, addr, data, true);
2589 }
2590
2591 /**
2592 * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2593 * @hw: pointer to the HW structure
2594 *
2595 * Initialize Marvell 1512 to work correctly with Avoton.
2596 **/
e1000_initialize_M88E1512_phy(struct e1000_hw * hw)2597 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2598 {
2599 struct e1000_phy_info *phy = &hw->phy;
2600 s32 ret_val = E1000_SUCCESS;
2601
2602 DEBUGFUNC("e1000_initialize_M88E1512_phy");
2603
2604 /* Check if this is correct PHY. */
2605 if (phy->id != M88E1512_E_PHY_ID)
2606 goto out;
2607
2608 /* Switch to PHY page 0xFF. */
2609 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2610 if (ret_val)
2611 goto out;
2612
2613 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2614 if (ret_val)
2615 goto out;
2616
2617 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2618 if (ret_val)
2619 goto out;
2620
2621 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2622 if (ret_val)
2623 goto out;
2624
2625 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2626 if (ret_val)
2627 goto out;
2628
2629 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2630 if (ret_val)
2631 goto out;
2632
2633 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2634 if (ret_val)
2635 goto out;
2636
2637 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2638 if (ret_val)
2639 goto out;
2640
2641 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2642 if (ret_val)
2643 goto out;
2644
2645 /* Switch to PHY page 0xFB. */
2646 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2647 if (ret_val)
2648 goto out;
2649
2650 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2651 if (ret_val)
2652 goto out;
2653
2654 /* Switch to PHY page 0x12. */
2655 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2656 if (ret_val)
2657 goto out;
2658
2659 /* Change mode to SGMII-to-Copper */
2660 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2661 if (ret_val)
2662 goto out;
2663
2664 /* Return the PHY to page 0. */
2665 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2666 if (ret_val)
2667 goto out;
2668
2669 ret_val = phy->ops.commit(hw);
2670 if (ret_val) {
2671 DEBUGOUT("Error committing the PHY changes\n");
2672 return ret_val;
2673 }
2674
2675 msec_delay(1000);
2676 out:
2677 return ret_val;
2678 }
2679
2680 /**
2681 * e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
2682 * @hw: pointer to the HW structure
2683 *
2684 * Initialize Marvell 1543 to work correctly with Avoton.
2685 **/
e1000_initialize_M88E1543_phy(struct e1000_hw * hw)2686 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
2687 {
2688 struct e1000_phy_info *phy = &hw->phy;
2689 s32 ret_val = E1000_SUCCESS;
2690
2691 DEBUGFUNC("e1000_initialize_M88E1543_phy");
2692
2693 /* Check if this is correct PHY. */
2694 if (phy->id != M88E1543_E_PHY_ID)
2695 goto out;
2696
2697 /* Switch to PHY page 0xFF. */
2698 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2699 if (ret_val)
2700 goto out;
2701
2702 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2703 if (ret_val)
2704 goto out;
2705
2706 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2707 if (ret_val)
2708 goto out;
2709
2710 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2711 if (ret_val)
2712 goto out;
2713
2714 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2715 if (ret_val)
2716 goto out;
2717
2718 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2719 if (ret_val)
2720 goto out;
2721
2722 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2723 if (ret_val)
2724 goto out;
2725
2726 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2727 if (ret_val)
2728 goto out;
2729
2730 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2731 if (ret_val)
2732 goto out;
2733
2734 /* Switch to PHY page 0xFB. */
2735 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2736 if (ret_val)
2737 goto out;
2738
2739 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2740 if (ret_val)
2741 goto out;
2742
2743 /* Switch to PHY page 0x12. */
2744 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2745 if (ret_val)
2746 goto out;
2747
2748 /* Change mode to SGMII-to-Copper */
2749 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2750 if (ret_val)
2751 goto out;
2752
2753 /* Switch to PHY page 1. */
2754 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2755 if (ret_val)
2756 goto out;
2757
2758 /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */
2759 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2760 if (ret_val)
2761 goto out;
2762
2763 /* Return the PHY to page 0. */
2764 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2765 if (ret_val)
2766 goto out;
2767
2768 ret_val = phy->ops.commit(hw);
2769 if (ret_val) {
2770 DEBUGOUT("Error committing the PHY changes\n");
2771 return ret_val;
2772 }
2773
2774 msec_delay(1000);
2775 out:
2776 return ret_val;
2777 }
2778
2779 /**
2780 * e1000_set_eee_i350 - Enable/disable EEE support
2781 * @hw: pointer to the HW structure
2782 * @adv1G: boolean flag enabling 1G EEE advertisement
2783 * @adv100M: boolean flag enabling 100M EEE advertisement
2784 *
2785 * Enable/disable EEE based on setting in dev_spec structure.
2786 *
2787 **/
e1000_set_eee_i350(struct e1000_hw * hw,bool adv1G,bool adv100M)2788 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2789 {
2790 u32 ipcnfg, eeer;
2791
2792 DEBUGFUNC("e1000_set_eee_i350");
2793
2794 if ((hw->mac.type < e1000_i350) ||
2795 (hw->phy.media_type != e1000_media_type_copper))
2796 goto out;
2797 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2798 eeer = E1000_READ_REG(hw, E1000_EEER);
2799
2800 /* enable or disable per user setting */
2801 if (!(hw->dev_spec._82575.eee_disable)) {
2802 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2803
2804 if (adv100M)
2805 ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2806 else
2807 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2808
2809 if (adv1G)
2810 ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2811 else
2812 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2813
2814 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2815 E1000_EEER_LPI_FC);
2816
2817 /* This bit should not be set in normal operation. */
2818 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2819 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2820 } else {
2821 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2822 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2823 E1000_EEER_LPI_FC);
2824 }
2825 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2826 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2827 E1000_READ_REG(hw, E1000_IPCNFG);
2828 E1000_READ_REG(hw, E1000_EEER);
2829 out:
2830
2831 return E1000_SUCCESS;
2832 }
2833
2834 /**
2835 * e1000_set_eee_i354 - Enable/disable EEE support
2836 * @hw: pointer to the HW structure
2837 * @adv1G: boolean flag enabling 1G EEE advertisement
2838 * @adv100M: boolean flag enabling 100M EEE advertisement
2839 *
2840 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2841 *
2842 **/
e1000_set_eee_i354(struct e1000_hw * hw,bool adv1G,bool adv100M)2843 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2844 {
2845 struct e1000_phy_info *phy = &hw->phy;
2846 s32 ret_val = E1000_SUCCESS;
2847 u16 phy_data;
2848
2849 DEBUGFUNC("e1000_set_eee_i354");
2850
2851 if ((hw->phy.media_type != e1000_media_type_copper) ||
2852 ((phy->id != M88E1543_E_PHY_ID) &&
2853 (phy->id != M88E1512_E_PHY_ID)))
2854 goto out;
2855
2856 if (!hw->dev_spec._82575.eee_disable) {
2857 /* Switch to PHY page 18. */
2858 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2859 if (ret_val)
2860 goto out;
2861
2862 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2863 &phy_data);
2864 if (ret_val)
2865 goto out;
2866
2867 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2868 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2869 phy_data);
2870 if (ret_val)
2871 goto out;
2872
2873 /* Return the PHY to page 0. */
2874 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2875 if (ret_val)
2876 goto out;
2877
2878 /* Turn on EEE advertisement. */
2879 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2880 E1000_EEE_ADV_DEV_I354,
2881 &phy_data);
2882 if (ret_val)
2883 goto out;
2884
2885 if (adv100M)
2886 phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2887 else
2888 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2889
2890 if (adv1G)
2891 phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2892 else
2893 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2894
2895 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2896 E1000_EEE_ADV_DEV_I354,
2897 phy_data);
2898 } else {
2899 /* Turn off EEE advertisement. */
2900 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2901 E1000_EEE_ADV_DEV_I354,
2902 &phy_data);
2903 if (ret_val)
2904 goto out;
2905
2906 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2907 E1000_EEE_ADV_1000_SUPPORTED);
2908 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2909 E1000_EEE_ADV_DEV_I354,
2910 phy_data);
2911 }
2912
2913 out:
2914 return ret_val;
2915 }
2916
2917 /**
2918 * e1000_get_eee_status_i354 - Get EEE status
2919 * @hw: pointer to the HW structure
2920 * @status: EEE status
2921 *
2922 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2923 * been received.
2924 **/
e1000_get_eee_status_i354(struct e1000_hw * hw,bool * status)2925 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2926 {
2927 struct e1000_phy_info *phy = &hw->phy;
2928 s32 ret_val = E1000_SUCCESS;
2929 u16 phy_data;
2930
2931 DEBUGFUNC("e1000_get_eee_status_i354");
2932
2933 /* Check if EEE is supported on this device. */
2934 if ((hw->phy.media_type != e1000_media_type_copper) ||
2935 ((phy->id != M88E1543_E_PHY_ID) &&
2936 (phy->id != M88E1512_E_PHY_ID)))
2937 goto out;
2938
2939 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2940 E1000_PCS_STATUS_DEV_I354,
2941 &phy_data);
2942 if (ret_val)
2943 goto out;
2944
2945 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2946 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2947
2948 out:
2949 return ret_val;
2950 }
2951
2952 /* Due to a hw errata, if the host tries to configure the VFTA register
2953 * while performing queries from the BMC or DMA, then the VFTA in some
2954 * cases won't be written.
2955 */
2956
2957 /**
2958 * e1000_clear_vfta_i350 - Clear VLAN filter table
2959 * @hw: pointer to the HW structure
2960 *
2961 * Clears the register array which contains the VLAN filter table by
2962 * setting all the values to 0.
2963 **/
e1000_clear_vfta_i350(struct e1000_hw * hw)2964 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2965 {
2966 u32 offset;
2967 int i;
2968
2969 DEBUGFUNC("e1000_clear_vfta_350");
2970
2971 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2972 for (i = 0; i < 10; i++)
2973 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2974
2975 E1000_WRITE_FLUSH(hw);
2976 }
2977 }
2978
2979 /**
2980 * e1000_write_vfta_i350 - Write value to VLAN filter table
2981 * @hw: pointer to the HW structure
2982 * @offset: register offset in VLAN filter table
2983 * @value: register value written to VLAN filter table
2984 *
2985 * Writes value at the given offset in the register array which stores
2986 * the VLAN filter table.
2987 **/
e1000_write_vfta_i350(struct e1000_hw * hw,u32 offset,u32 value)2988 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2989 {
2990 int i;
2991
2992 DEBUGFUNC("e1000_write_vfta_350");
2993
2994 for (i = 0; i < 10; i++)
2995 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2996
2997 E1000_WRITE_FLUSH(hw);
2998 }
2999
3000
3001 /**
3002 * e1000_set_i2c_bb - Enable I2C bit-bang
3003 * @hw: pointer to the HW structure
3004 *
3005 * Enable I2C bit-bang interface
3006 *
3007 **/
e1000_set_i2c_bb(struct e1000_hw * hw)3008 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3009 {
3010 s32 ret_val = E1000_SUCCESS;
3011 u32 ctrl_ext, i2cparams;
3012
3013 DEBUGFUNC("e1000_set_i2c_bb");
3014
3015 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3016 ctrl_ext |= E1000_CTRL_I2C_ENA;
3017 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3018 E1000_WRITE_FLUSH(hw);
3019
3020 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3021 i2cparams |= E1000_I2CBB_EN;
3022 i2cparams |= E1000_I2C_DATA_OE_N;
3023 i2cparams |= E1000_I2C_CLK_OE_N;
3024 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3025 E1000_WRITE_FLUSH(hw);
3026
3027 return ret_val;
3028 }
3029
3030 /**
3031 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3032 * @hw: pointer to hardware structure
3033 * @byte_offset: byte offset to read
3034 * @dev_addr: device address
3035 * @data: value read
3036 *
3037 * Performs byte read operation over I2C interface at
3038 * a specified device address.
3039 **/
e1000_read_i2c_byte_generic(struct e1000_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)3040 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3041 u8 dev_addr, u8 *data)
3042 {
3043 s32 status = E1000_SUCCESS;
3044 u32 max_retry = 10;
3045 u32 retry = 1;
3046 u16 swfw_mask = 0;
3047
3048 bool nack = true;
3049
3050 DEBUGFUNC("e1000_read_i2c_byte_generic");
3051
3052 swfw_mask = E1000_SWFW_PHY0_SM;
3053
3054 do {
3055 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3056 != E1000_SUCCESS) {
3057 status = E1000_ERR_SWFW_SYNC;
3058 goto read_byte_out;
3059 }
3060
3061 e1000_i2c_start(hw);
3062
3063 /* Device Address and write indication */
3064 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3065 if (status != E1000_SUCCESS)
3066 goto fail;
3067
3068 status = e1000_get_i2c_ack(hw);
3069 if (status != E1000_SUCCESS)
3070 goto fail;
3071
3072 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3073 if (status != E1000_SUCCESS)
3074 goto fail;
3075
3076 status = e1000_get_i2c_ack(hw);
3077 if (status != E1000_SUCCESS)
3078 goto fail;
3079
3080 e1000_i2c_start(hw);
3081
3082 /* Device Address and read indication */
3083 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3084 if (status != E1000_SUCCESS)
3085 goto fail;
3086
3087 status = e1000_get_i2c_ack(hw);
3088 if (status != E1000_SUCCESS)
3089 goto fail;
3090
3091 e1000_clock_in_i2c_byte(hw, data);
3092
3093 status = e1000_clock_out_i2c_bit(hw, nack);
3094 if (status != E1000_SUCCESS)
3095 goto fail;
3096
3097 e1000_i2c_stop(hw);
3098 break;
3099
3100 fail:
3101 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3102 msec_delay(100);
3103 e1000_i2c_bus_clear(hw);
3104 retry++;
3105 if (retry < max_retry)
3106 DEBUGOUT("I2C byte read error - Retrying.\n");
3107 else
3108 DEBUGOUT("I2C byte read error.\n");
3109
3110 } while (retry < max_retry);
3111
3112 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3113
3114 read_byte_out:
3115
3116 return status;
3117 }
3118
3119 /**
3120 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3121 * @hw: pointer to hardware structure
3122 * @byte_offset: byte offset to write
3123 * @dev_addr: device address
3124 * @data: value to write
3125 *
3126 * Performs byte write operation over I2C interface at
3127 * a specified device address.
3128 **/
e1000_write_i2c_byte_generic(struct e1000_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)3129 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3130 u8 dev_addr, u8 data)
3131 {
3132 s32 status = E1000_SUCCESS;
3133 u32 max_retry = 1;
3134 u32 retry = 0;
3135 u16 swfw_mask = 0;
3136
3137 DEBUGFUNC("e1000_write_i2c_byte_generic");
3138
3139 swfw_mask = E1000_SWFW_PHY0_SM;
3140
3141 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3142 status = E1000_ERR_SWFW_SYNC;
3143 goto write_byte_out;
3144 }
3145
3146 do {
3147 e1000_i2c_start(hw);
3148
3149 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3150 if (status != E1000_SUCCESS)
3151 goto fail;
3152
3153 status = e1000_get_i2c_ack(hw);
3154 if (status != E1000_SUCCESS)
3155 goto fail;
3156
3157 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3158 if (status != E1000_SUCCESS)
3159 goto fail;
3160
3161 status = e1000_get_i2c_ack(hw);
3162 if (status != E1000_SUCCESS)
3163 goto fail;
3164
3165 status = e1000_clock_out_i2c_byte(hw, data);
3166 if (status != E1000_SUCCESS)
3167 goto fail;
3168
3169 status = e1000_get_i2c_ack(hw);
3170 if (status != E1000_SUCCESS)
3171 goto fail;
3172
3173 e1000_i2c_stop(hw);
3174 break;
3175
3176 fail:
3177 e1000_i2c_bus_clear(hw);
3178 retry++;
3179 if (retry < max_retry)
3180 DEBUGOUT("I2C byte write error - Retrying.\n");
3181 else
3182 DEBUGOUT("I2C byte write error.\n");
3183 } while (retry < max_retry);
3184
3185 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3186
3187 write_byte_out:
3188
3189 return status;
3190 }
3191
3192 /**
3193 * e1000_i2c_start - Sets I2C start condition
3194 * @hw: pointer to hardware structure
3195 *
3196 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3197 **/
e1000_i2c_start(struct e1000_hw * hw)3198 static void e1000_i2c_start(struct e1000_hw *hw)
3199 {
3200 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3201
3202 DEBUGFUNC("e1000_i2c_start");
3203
3204 /* Start condition must begin with data and clock high */
3205 e1000_set_i2c_data(hw, &i2cctl, 1);
3206 e1000_raise_i2c_clk(hw, &i2cctl);
3207
3208 /* Setup time for start condition (4.7us) */
3209 usec_delay(E1000_I2C_T_SU_STA);
3210
3211 e1000_set_i2c_data(hw, &i2cctl, 0);
3212
3213 /* Hold time for start condition (4us) */
3214 usec_delay(E1000_I2C_T_HD_STA);
3215
3216 e1000_lower_i2c_clk(hw, &i2cctl);
3217
3218 /* Minimum low period of clock is 4.7 us */
3219 usec_delay(E1000_I2C_T_LOW);
3220
3221 }
3222
3223 /**
3224 * e1000_i2c_stop - Sets I2C stop condition
3225 * @hw: pointer to hardware structure
3226 *
3227 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3228 **/
e1000_i2c_stop(struct e1000_hw * hw)3229 static void e1000_i2c_stop(struct e1000_hw *hw)
3230 {
3231 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3232
3233 DEBUGFUNC("e1000_i2c_stop");
3234
3235 /* Stop condition must begin with data low and clock high */
3236 e1000_set_i2c_data(hw, &i2cctl, 0);
3237 e1000_raise_i2c_clk(hw, &i2cctl);
3238
3239 /* Setup time for stop condition (4us) */
3240 usec_delay(E1000_I2C_T_SU_STO);
3241
3242 e1000_set_i2c_data(hw, &i2cctl, 1);
3243
3244 /* bus free time between stop and start (4.7us)*/
3245 usec_delay(E1000_I2C_T_BUF);
3246 }
3247
3248 /**
3249 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3250 * @hw: pointer to hardware structure
3251 * @data: data byte to clock in
3252 *
3253 * Clocks in one byte data via I2C data/clock
3254 **/
e1000_clock_in_i2c_byte(struct e1000_hw * hw,u8 * data)3255 static void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3256 {
3257 s32 i;
3258 bool bit = 0;
3259
3260 DEBUGFUNC("e1000_clock_in_i2c_byte");
3261
3262 *data = 0;
3263 for (i = 7; i >= 0; i--) {
3264 e1000_clock_in_i2c_bit(hw, &bit);
3265 *data |= bit << i;
3266 }
3267 }
3268
3269 /**
3270 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3271 * @hw: pointer to hardware structure
3272 * @data: data byte clocked out
3273 *
3274 * Clocks out one byte data via I2C data/clock
3275 **/
e1000_clock_out_i2c_byte(struct e1000_hw * hw,u8 data)3276 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3277 {
3278 s32 status = E1000_SUCCESS;
3279 s32 i;
3280 u32 i2cctl;
3281 bool bit = 0;
3282
3283 DEBUGFUNC("e1000_clock_out_i2c_byte");
3284
3285 for (i = 7; i >= 0; i--) {
3286 bit = (data >> i) & 0x1;
3287 status = e1000_clock_out_i2c_bit(hw, bit);
3288
3289 if (status != E1000_SUCCESS)
3290 break;
3291 }
3292
3293 /* Release SDA line (set high) */
3294 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3295
3296 i2cctl |= E1000_I2C_DATA_OE_N;
3297 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3298 E1000_WRITE_FLUSH(hw);
3299
3300 return status;
3301 }
3302
3303 /**
3304 * e1000_get_i2c_ack - Polls for I2C ACK
3305 * @hw: pointer to hardware structure
3306 *
3307 * Clocks in/out one bit via I2C data/clock
3308 **/
e1000_get_i2c_ack(struct e1000_hw * hw)3309 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3310 {
3311 s32 status = E1000_SUCCESS;
3312 u32 i = 0;
3313 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3314 u32 timeout = 10;
3315 bool ack = true;
3316
3317 DEBUGFUNC("e1000_get_i2c_ack");
3318
3319 e1000_raise_i2c_clk(hw, &i2cctl);
3320
3321 /* Minimum high period of clock is 4us */
3322 usec_delay(E1000_I2C_T_HIGH);
3323
3324 /* Wait until SCL returns high */
3325 for (i = 0; i < timeout; i++) {
3326 usec_delay(1);
3327 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3328 if (i2cctl & E1000_I2C_CLK_IN)
3329 break;
3330 }
3331 if (!(i2cctl & E1000_I2C_CLK_IN))
3332 return E1000_ERR_I2C;
3333
3334 ack = e1000_get_i2c_data(&i2cctl);
3335 if (ack) {
3336 DEBUGOUT("I2C ack was not received.\n");
3337 status = E1000_ERR_I2C;
3338 }
3339
3340 e1000_lower_i2c_clk(hw, &i2cctl);
3341
3342 /* Minimum low period of clock is 4.7 us */
3343 usec_delay(E1000_I2C_T_LOW);
3344
3345 return status;
3346 }
3347
3348 /**
3349 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3350 * @hw: pointer to hardware structure
3351 * @data: read data value
3352 *
3353 * Clocks in one bit via I2C data/clock
3354 **/
e1000_clock_in_i2c_bit(struct e1000_hw * hw,bool * data)3355 static void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3356 {
3357 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3358
3359 DEBUGFUNC("e1000_clock_in_i2c_bit");
3360
3361 e1000_raise_i2c_clk(hw, &i2cctl);
3362
3363 /* Minimum high period of clock is 4us */
3364 usec_delay(E1000_I2C_T_HIGH);
3365
3366 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3367 *data = e1000_get_i2c_data(&i2cctl);
3368
3369 e1000_lower_i2c_clk(hw, &i2cctl);
3370
3371 /* Minimum low period of clock is 4.7 us */
3372 usec_delay(E1000_I2C_T_LOW);
3373 }
3374
3375 /**
3376 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3377 * @hw: pointer to hardware structure
3378 * @data: data value to write
3379 *
3380 * Clocks out one bit via I2C data/clock
3381 **/
e1000_clock_out_i2c_bit(struct e1000_hw * hw,bool data)3382 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3383 {
3384 s32 status;
3385 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3386
3387 DEBUGFUNC("e1000_clock_out_i2c_bit");
3388
3389 status = e1000_set_i2c_data(hw, &i2cctl, data);
3390 if (status == E1000_SUCCESS) {
3391 e1000_raise_i2c_clk(hw, &i2cctl);
3392
3393 /* Minimum high period of clock is 4us */
3394 usec_delay(E1000_I2C_T_HIGH);
3395
3396 e1000_lower_i2c_clk(hw, &i2cctl);
3397
3398 /* Minimum low period of clock is 4.7 us.
3399 * This also takes care of the data hold time.
3400 */
3401 usec_delay(E1000_I2C_T_LOW);
3402 } else {
3403 status = E1000_ERR_I2C;
3404 DEBUGOUT1("I2C data was not set to %X\n", data);
3405 }
3406
3407 return status;
3408 }
3409 /**
3410 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3411 * @hw: pointer to hardware structure
3412 * @i2cctl: Current value of I2CCTL register
3413 *
3414 * Raises the I2C clock line '0'->'1'
3415 **/
e1000_raise_i2c_clk(struct e1000_hw * hw,u32 * i2cctl)3416 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3417 {
3418 DEBUGFUNC("e1000_raise_i2c_clk");
3419
3420 *i2cctl |= E1000_I2C_CLK_OUT;
3421 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3422 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3423 E1000_WRITE_FLUSH(hw);
3424
3425 /* SCL rise time (1000ns) */
3426 usec_delay(E1000_I2C_T_RISE);
3427 }
3428
3429 /**
3430 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3431 * @hw: pointer to hardware structure
3432 * @i2cctl: Current value of I2CCTL register
3433 *
3434 * Lowers the I2C clock line '1'->'0'
3435 **/
e1000_lower_i2c_clk(struct e1000_hw * hw,u32 * i2cctl)3436 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3437 {
3438
3439 DEBUGFUNC("e1000_lower_i2c_clk");
3440
3441 *i2cctl &= ~E1000_I2C_CLK_OUT;
3442 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3443 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3444 E1000_WRITE_FLUSH(hw);
3445
3446 /* SCL fall time (300ns) */
3447 usec_delay(E1000_I2C_T_FALL);
3448 }
3449
3450 /**
3451 * e1000_set_i2c_data - Sets the I2C data bit
3452 * @hw: pointer to hardware structure
3453 * @i2cctl: Current value of I2CCTL register
3454 * @data: I2C data value (0 or 1) to set
3455 *
3456 * Sets the I2C data bit
3457 **/
e1000_set_i2c_data(struct e1000_hw * hw,u32 * i2cctl,bool data)3458 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3459 {
3460 s32 status = E1000_SUCCESS;
3461
3462 DEBUGFUNC("e1000_set_i2c_data");
3463
3464 if (data)
3465 *i2cctl |= E1000_I2C_DATA_OUT;
3466 else
3467 *i2cctl &= ~E1000_I2C_DATA_OUT;
3468
3469 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3470 *i2cctl |= E1000_I2C_CLK_OE_N;
3471 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3472 E1000_WRITE_FLUSH(hw);
3473
3474 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3475 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3476
3477 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3478 if (data != e1000_get_i2c_data(i2cctl)) {
3479 status = E1000_ERR_I2C;
3480 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3481 }
3482
3483 return status;
3484 }
3485
3486 /**
3487 * e1000_get_i2c_data - Reads the I2C SDA data bit
3488 * @i2cctl: Current value of I2CCTL register
3489 *
3490 * Returns the I2C data bit value
3491 **/
e1000_get_i2c_data(u32 * i2cctl)3492 static bool e1000_get_i2c_data(u32 *i2cctl)
3493 {
3494 bool data;
3495
3496 DEBUGFUNC("e1000_get_i2c_data");
3497
3498 if (*i2cctl & E1000_I2C_DATA_IN)
3499 data = 1;
3500 else
3501 data = 0;
3502
3503 return data;
3504 }
3505
3506 /**
3507 * e1000_i2c_bus_clear - Clears the I2C bus
3508 * @hw: pointer to hardware structure
3509 *
3510 * Clears the I2C bus by sending nine clock pulses.
3511 * Used when data line is stuck low.
3512 **/
e1000_i2c_bus_clear(struct e1000_hw * hw)3513 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3514 {
3515 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3516 u32 i;
3517
3518 DEBUGFUNC("e1000_i2c_bus_clear");
3519
3520 e1000_i2c_start(hw);
3521
3522 e1000_set_i2c_data(hw, &i2cctl, 1);
3523
3524 for (i = 0; i < 9; i++) {
3525 e1000_raise_i2c_clk(hw, &i2cctl);
3526
3527 /* Min high period of clock is 4us */
3528 usec_delay(E1000_I2C_T_HIGH);
3529
3530 e1000_lower_i2c_clk(hw, &i2cctl);
3531
3532 /* Min low period of clock is 4.7us*/
3533 usec_delay(E1000_I2C_T_LOW);
3534 }
3535
3536 e1000_i2c_start(hw);
3537
3538 /* Put the i2c bus back to default state */
3539 e1000_i2c_stop(hw);
3540 }
3541