1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34
35 /*
36 * 82542 Gigabit Ethernet Controller
37 */
38
39 #include "e1000_api.h"
40
41 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw);
42 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw);
43 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw);
44 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw);
45 static s32 e1000_reset_hw_82542(struct e1000_hw *hw);
46 static s32 e1000_init_hw_82542(struct e1000_hw *hw);
47 static s32 e1000_setup_link_82542(struct e1000_hw *hw);
48 static s32 e1000_led_on_82542(struct e1000_hw *hw);
49 static s32 e1000_led_off_82542(struct e1000_hw *hw);
50 static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
51 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
52 static s32 e1000_read_mac_addr_82542(struct e1000_hw *hw);
53
54 /**
55 * e1000_init_phy_params_82542 - Init PHY func ptrs.
56 * @hw: pointer to the HW structure
57 **/
e1000_init_phy_params_82542(struct e1000_hw * hw)58 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
59 {
60 struct e1000_phy_info *phy = &hw->phy;
61 s32 ret_val = E1000_SUCCESS;
62
63 DEBUGFUNC("e1000_init_phy_params_82542");
64
65 phy->type = e1000_phy_none;
66
67 return ret_val;
68 }
69
70 /**
71 * e1000_init_nvm_params_82542 - Init NVM func ptrs.
72 * @hw: pointer to the HW structure
73 **/
e1000_init_nvm_params_82542(struct e1000_hw * hw)74 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
75 {
76 struct e1000_nvm_info *nvm = &hw->nvm;
77
78 DEBUGFUNC("e1000_init_nvm_params_82542");
79
80 nvm->address_bits = 6;
81 nvm->delay_usec = 50;
82 nvm->opcode_bits = 3;
83 nvm->type = e1000_nvm_eeprom_microwire;
84 nvm->word_size = 64;
85
86 /* Function Pointers */
87 nvm->ops.read = e1000_read_nvm_microwire;
88 nvm->ops.release = e1000_stop_nvm;
89 nvm->ops.write = e1000_write_nvm_microwire;
90 nvm->ops.update = e1000_update_nvm_checksum_generic;
91 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
92
93 return E1000_SUCCESS;
94 }
95
96 /**
97 * e1000_init_mac_params_82542 - Init MAC func ptrs.
98 * @hw: pointer to the HW structure
99 **/
e1000_init_mac_params_82542(struct e1000_hw * hw)100 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
101 {
102 struct e1000_mac_info *mac = &hw->mac;
103
104 DEBUGFUNC("e1000_init_mac_params_82542");
105
106 /* Set media type */
107 hw->phy.media_type = e1000_media_type_fiber;
108
109 /* Set mta register count */
110 mac->mta_reg_count = 128;
111 /* Set rar entry count */
112 mac->rar_entry_count = E1000_RAR_ENTRIES;
113
114 /* Function pointers */
115
116 /* bus type/speed/width */
117 mac->ops.get_bus_info = e1000_get_bus_info_82542;
118 /* function id */
119 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
120 /* reset */
121 mac->ops.reset_hw = e1000_reset_hw_82542;
122 /* hw initialization */
123 mac->ops.init_hw = e1000_init_hw_82542;
124 /* link setup */
125 mac->ops.setup_link = e1000_setup_link_82542;
126 /* phy/fiber/serdes setup */
127 mac->ops.setup_physical_interface =
128 e1000_setup_fiber_serdes_link_generic;
129 /* check for link */
130 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
131 /* multicast address update */
132 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
133 /* writing VFTA */
134 mac->ops.write_vfta = e1000_write_vfta_generic;
135 /* clearing VFTA */
136 mac->ops.clear_vfta = e1000_clear_vfta_generic;
137 /* read mac address */
138 mac->ops.read_mac_addr = e1000_read_mac_addr_82542;
139 /* set RAR */
140 mac->ops.rar_set = e1000_rar_set_82542;
141 /* turn on/off LED */
142 mac->ops.led_on = e1000_led_on_82542;
143 mac->ops.led_off = e1000_led_off_82542;
144 /* clear hardware counters */
145 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
146 /* link info */
147 mac->ops.get_link_up_info =
148 e1000_get_speed_and_duplex_fiber_serdes_generic;
149
150 return E1000_SUCCESS;
151 }
152
153 /**
154 * e1000_init_function_pointers_82542 - Init func ptrs.
155 * @hw: pointer to the HW structure
156 *
157 * Called to initialize all function pointers and parameters.
158 **/
e1000_init_function_pointers_82542(struct e1000_hw * hw)159 void e1000_init_function_pointers_82542(struct e1000_hw *hw)
160 {
161 DEBUGFUNC("e1000_init_function_pointers_82542");
162
163 hw->mac.ops.init_params = e1000_init_mac_params_82542;
164 hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
165 hw->phy.ops.init_params = e1000_init_phy_params_82542;
166 }
167
168 /**
169 * e1000_get_bus_info_82542 - Obtain bus information for adapter
170 * @hw: pointer to the HW structure
171 *
172 * This will obtain information about the HW bus for which the
173 * adapter is attached and stores it in the hw structure.
174 **/
e1000_get_bus_info_82542(struct e1000_hw * hw)175 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
176 {
177 DEBUGFUNC("e1000_get_bus_info_82542");
178
179 hw->bus.type = e1000_bus_type_pci;
180 hw->bus.speed = e1000_bus_speed_unknown;
181 hw->bus.width = e1000_bus_width_unknown;
182
183 return E1000_SUCCESS;
184 }
185
186 /**
187 * e1000_reset_hw_82542 - Reset hardware
188 * @hw: pointer to the HW structure
189 *
190 * This resets the hardware into a known state.
191 **/
e1000_reset_hw_82542(struct e1000_hw * hw)192 static s32 e1000_reset_hw_82542(struct e1000_hw *hw)
193 {
194 struct e1000_bus_info *bus = &hw->bus;
195 s32 ret_val = E1000_SUCCESS;
196 u32 ctrl;
197
198 DEBUGFUNC("e1000_reset_hw_82542");
199
200 if (hw->revision_id == E1000_REVISION_2) {
201 DEBUGOUT("Disabling MWI on 82542 rev 2\n");
202 e1000_pci_clear_mwi(hw);
203 }
204
205 DEBUGOUT("Masking off all interrupts\n");
206 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
207
208 E1000_WRITE_REG(hw, E1000_RCTL, 0);
209 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
210 E1000_WRITE_FLUSH(hw);
211
212 /*
213 * Delay to allow any outstanding PCI transactions to complete before
214 * resetting the device
215 */
216 msec_delay(10);
217
218 ctrl = E1000_READ_REG(hw, E1000_CTRL);
219
220 DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n");
221 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
222
223 hw->nvm.ops.reload(hw);
224 msec_delay(2);
225
226 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
227 E1000_READ_REG(hw, E1000_ICR);
228
229 if (hw->revision_id == E1000_REVISION_2) {
230 if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
231 e1000_pci_set_mwi(hw);
232 }
233
234 return ret_val;
235 }
236
237 /**
238 * e1000_init_hw_82542 - Initialize hardware
239 * @hw: pointer to the HW structure
240 *
241 * This inits the hardware readying it for operation.
242 **/
e1000_init_hw_82542(struct e1000_hw * hw)243 static s32 e1000_init_hw_82542(struct e1000_hw *hw)
244 {
245 struct e1000_mac_info *mac = &hw->mac;
246 struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
247 s32 ret_val = E1000_SUCCESS;
248 u32 ctrl;
249 u16 i;
250
251 DEBUGFUNC("e1000_init_hw_82542");
252
253 /* Disabling VLAN filtering */
254 E1000_WRITE_REG(hw, E1000_VET, 0);
255 mac->ops.clear_vfta(hw);
256
257 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
258 if (hw->revision_id == E1000_REVISION_2) {
259 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
260 e1000_pci_clear_mwi(hw);
261 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
262 E1000_WRITE_FLUSH(hw);
263 msec_delay(5);
264 }
265
266 /* Setup the receive address. */
267 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
268
269 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
270 if (hw->revision_id == E1000_REVISION_2) {
271 E1000_WRITE_REG(hw, E1000_RCTL, 0);
272 E1000_WRITE_FLUSH(hw);
273 msec_delay(1);
274 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
275 e1000_pci_set_mwi(hw);
276 }
277
278 /* Zero out the Multicast HASH table */
279 DEBUGOUT("Zeroing the MTA\n");
280 for (i = 0; i < mac->mta_reg_count; i++)
281 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
282
283 /*
284 * Set the PCI priority bit correctly in the CTRL register. This
285 * determines if the adapter gives priority to receives, or if it
286 * gives equal priority to transmits and receives.
287 */
288 if (dev_spec->dma_fairness) {
289 ctrl = E1000_READ_REG(hw, E1000_CTRL);
290 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
291 }
292
293 /* Setup link and flow control */
294 ret_val = e1000_setup_link_82542(hw);
295
296 /*
297 * Clear all of the statistics registers (clear on read). It is
298 * important that we do this after we have tried to establish link
299 * because the symbol error count will increment wildly if there
300 * is no link.
301 */
302 e1000_clear_hw_cntrs_82542(hw);
303
304 return ret_val;
305 }
306
307 /**
308 * e1000_setup_link_82542 - Setup flow control and link settings
309 * @hw: pointer to the HW structure
310 *
311 * Determines which flow control settings to use, then configures flow
312 * control. Calls the appropriate media-specific link configuration
313 * function. Assuming the adapter has a valid link partner, a valid link
314 * should be established. Assumes the hardware has previously been reset
315 * and the transmitter and receiver are not enabled.
316 **/
e1000_setup_link_82542(struct e1000_hw * hw)317 static s32 e1000_setup_link_82542(struct e1000_hw *hw)
318 {
319 struct e1000_mac_info *mac = &hw->mac;
320 s32 ret_val = E1000_SUCCESS;
321
322 DEBUGFUNC("e1000_setup_link_82542");
323
324 if (hw->fc.requested_mode == e1000_fc_default) {
325 ret_val = e1000_set_default_fc_generic(hw);
326 if (ret_val)
327 goto out;
328 }
329
330 /* 82542 rev 2.0 cannot transmit PAUSE frames. */
331 if (hw->revision_id == E1000_REVISION_2) {
332 switch (hw->fc.requested_mode) {
333 case e1000_fc_tx_pause:
334 hw->fc.requested_mode = e1000_fc_none;
335 break;
336 case e1000_fc_full:
337 hw->fc.requested_mode = e1000_fc_rx_pause;
338 break;
339 default:
340 break;
341 }
342 }
343
344 /* Early transmit reporting is incompatible with receiving PAUSE. */
345 if (mac->report_tx_early) {
346 switch (hw->fc.requested_mode) {
347 case e1000_fc_rx_pause:
348 hw->fc.requested_mode = e1000_fc_none;
349 break;
350 case e1000_fc_full:
351 hw->fc.requested_mode = e1000_fc_tx_pause;
352 break;
353 default:
354 break;
355 }
356 }
357
358 /*
359 * Save off the requested flow control mode for use later. Depending
360 * on the link partner's capabilities, we may or may not use this mode.
361 */
362 hw->fc.current_mode = hw->fc.requested_mode;
363
364 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
365 hw->fc.current_mode);
366
367 /* Call the necessary subroutine to configure the link. */
368 ret_val = mac->ops.setup_physical_interface(hw);
369 if (ret_val)
370 goto out;
371
372 /*
373 * Initialize the flow control address, type, and PAUSE timer
374 * registers to their default values. This is done even if flow
375 * control is disabled, because it does not hurt anything to
376 * initialize these registers.
377 */
378 DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
379
380 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
381 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
382 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
383
384 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
385
386 ret_val = e1000_set_fc_watermarks_generic(hw);
387
388 out:
389 return ret_val;
390 }
391
392 /**
393 * e1000_led_on_82542 - Turn on SW controllable LED
394 * @hw: pointer to the HW structure
395 *
396 * Turns the SW defined LED on.
397 **/
e1000_led_on_82542(struct e1000_hw * hw)398 static s32 e1000_led_on_82542(struct e1000_hw *hw)
399 {
400 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
401
402 DEBUGFUNC("e1000_led_on_82542");
403
404 ctrl |= E1000_CTRL_SWDPIN0;
405 ctrl |= E1000_CTRL_SWDPIO0;
406 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
407
408 return E1000_SUCCESS;
409 }
410
411 /**
412 * e1000_led_off_82542 - Turn off SW controllable LED
413 * @hw: pointer to the HW structure
414 *
415 * Turns the SW defined LED off.
416 **/
e1000_led_off_82542(struct e1000_hw * hw)417 static s32 e1000_led_off_82542(struct e1000_hw *hw)
418 {
419 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
420
421 DEBUGFUNC("e1000_led_off_82542");
422
423 ctrl &= ~E1000_CTRL_SWDPIN0;
424 ctrl |= E1000_CTRL_SWDPIO0;
425 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
426
427 return E1000_SUCCESS;
428 }
429
430 /**
431 * e1000_rar_set_82542 - Set receive address register
432 * @hw: pointer to the HW structure
433 * @addr: pointer to the receive address
434 * @index: receive address array register
435 *
436 * Sets the receive address array register at index to the address passed
437 * in by addr.
438 **/
e1000_rar_set_82542(struct e1000_hw * hw,u8 * addr,u32 index)439 static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
440 {
441 u32 rar_low, rar_high;
442
443 DEBUGFUNC("e1000_rar_set_82542");
444
445 /*
446 * HW expects these in little endian so we reverse the byte order
447 * from network order (big endian) to little endian
448 */
449 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
450 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
451
452 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
453
454 /* If MAC address zero, no need to set the AV bit */
455 if (rar_low || rar_high)
456 rar_high |= E1000_RAH_AV;
457
458 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
459 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
460
461 return E1000_SUCCESS;
462 }
463
464 /**
465 * e1000_translate_register_82542 - Translate the proper register offset
466 * @reg: e1000 register to be read
467 *
468 * Registers in 82542 are located in different offsets than other adapters
469 * even though they function in the same manner. This function takes in
470 * the name of the register to read and returns the correct offset for
471 * 82542 silicon.
472 **/
e1000_translate_register_82542(u32 reg)473 u32 e1000_translate_register_82542(u32 reg)
474 {
475 /*
476 * Some of the 82542 registers are located at different
477 * offsets than they are in newer adapters.
478 * Despite the difference in location, the registers
479 * function in the same manner.
480 */
481 switch (reg) {
482 case E1000_RA:
483 reg = 0x00040;
484 break;
485 case E1000_RDTR:
486 reg = 0x00108;
487 break;
488 case E1000_RDBAL(0):
489 reg = 0x00110;
490 break;
491 case E1000_RDBAH(0):
492 reg = 0x00114;
493 break;
494 case E1000_RDLEN(0):
495 reg = 0x00118;
496 break;
497 case E1000_RDH(0):
498 reg = 0x00120;
499 break;
500 case E1000_RDT(0):
501 reg = 0x00128;
502 break;
503 case E1000_RDBAL(1):
504 reg = 0x00138;
505 break;
506 case E1000_RDBAH(1):
507 reg = 0x0013C;
508 break;
509 case E1000_RDLEN(1):
510 reg = 0x00140;
511 break;
512 case E1000_RDH(1):
513 reg = 0x00148;
514 break;
515 case E1000_RDT(1):
516 reg = 0x00150;
517 break;
518 case E1000_FCRTH:
519 reg = 0x00160;
520 break;
521 case E1000_FCRTL:
522 reg = 0x00168;
523 break;
524 case E1000_MTA:
525 reg = 0x00200;
526 break;
527 case E1000_TDBAL(0):
528 reg = 0x00420;
529 break;
530 case E1000_TDBAH(0):
531 reg = 0x00424;
532 break;
533 case E1000_TDLEN(0):
534 reg = 0x00428;
535 break;
536 case E1000_TDH(0):
537 reg = 0x00430;
538 break;
539 case E1000_TDT(0):
540 reg = 0x00438;
541 break;
542 case E1000_TIDV:
543 reg = 0x00440;
544 break;
545 case E1000_VFTA:
546 reg = 0x00600;
547 break;
548 case E1000_TDFH:
549 reg = 0x08010;
550 break;
551 case E1000_TDFT:
552 reg = 0x08018;
553 break;
554 default:
555 break;
556 }
557
558 return reg;
559 }
560
561 /**
562 * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters
563 * @hw: pointer to the HW structure
564 *
565 * Clears the hardware counters by reading the counter registers.
566 **/
e1000_clear_hw_cntrs_82542(struct e1000_hw * hw)567 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
568 {
569 DEBUGFUNC("e1000_clear_hw_cntrs_82542");
570
571 e1000_clear_hw_cntrs_base_generic(hw);
572
573 E1000_READ_REG(hw, E1000_PRC64);
574 E1000_READ_REG(hw, E1000_PRC127);
575 E1000_READ_REG(hw, E1000_PRC255);
576 E1000_READ_REG(hw, E1000_PRC511);
577 E1000_READ_REG(hw, E1000_PRC1023);
578 E1000_READ_REG(hw, E1000_PRC1522);
579 E1000_READ_REG(hw, E1000_PTC64);
580 E1000_READ_REG(hw, E1000_PTC127);
581 E1000_READ_REG(hw, E1000_PTC255);
582 E1000_READ_REG(hw, E1000_PTC511);
583 E1000_READ_REG(hw, E1000_PTC1023);
584 E1000_READ_REG(hw, E1000_PTC1522);
585 }
586
587 /**
588 * e1000_read_mac_addr_82542 - Read device MAC address
589 * @hw: pointer to the HW structure
590 *
591 * Reads the device MAC address from the EEPROM and stores the value.
592 **/
e1000_read_mac_addr_82542(struct e1000_hw * hw)593 s32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
594 {
595 s32 ret_val = E1000_SUCCESS;
596 u16 offset, nvm_data, i;
597
598 DEBUGFUNC("e1000_read_mac_addr");
599
600 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
601 offset = i >> 1;
602 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
603 if (ret_val) {
604 DEBUGOUT("NVM Read Error\n");
605 goto out;
606 }
607 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
608 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
609 }
610
611 for (i = 0; i < ETHER_ADDR_LEN; i++)
612 hw->mac.addr[i] = hw->mac.perm_addr[i];
613
614 out:
615 return ret_val;
616 }
617